Micro-led wafer bonding method
By combining dry etching and photoelectrochemical etching technologies, the problems of difficult etching depth control, non-uniformity, and thermal damage in Micro-LED wafer bonding have been solved, achieving high-precision etching and improved stability, and reducing production costs.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- SHANGHAI UNIV
- Filing Date
- 2025-01-20
- Publication Date
- 2026-07-23
AI Technical Summary
In the process of Micro-LED wafer bonding, traditional dry etching has problems such as difficulty in controlling etching depth, non-uniformity and thermal damage, which affect the display effect and device stability.
By combining dry etching and photoelectrochemical etching techniques, preliminary etching is first performed to form independent Micro-LED pixels, and then photoelectrochemical etching is used to repair the sidewalls of the pixels, achieving fine etching with low temperature and low damage.
Improve etching precision, reduce pixel damage, increase production efficiency, avoid thermal damage, enhance pixel isolation and wafer bonding stability, and reduce costs.
Smart Images
Figure CN2025073173_23072026_PF_FP_ABST
Abstract
Description
A Micro-LED Wafer Bonding Method Technical Field
[0001] This invention relates to the field of display technology, and in particular to a method for bonding Micro-LED wafers. Background Technology
[0002] Compared to traditional LCD display technology, micro-LED array display technology achieves deeper blacks, higher color saturation, and superior display effects because each Micro-LED pixel is an independent light-emitting unit capable of emitting its own light without relying on a backlight. Due to the extremely small size of each Micro-LED pixel, the manufacturing process demands higher requirements for precise isolation and efficient integration between pixels, especially in high-density integration applications.
[0003] In the fabrication of micro-LED arrays, wafer bonding is commonly used to integrate multiple small-sized Micro-LED chips onto a large-sized substrate, significantly improving yield, reducing the scrap rate of individual chips, and lowering production costs. To the inventor's knowledge, dry etching methods (such as ICP etching and inductively coupled plasma etching) are commonly used in wafer bonding. However, dry etching often suffers from difficulties in controlling etching depth and uneven processing. Especially in large-area wafer bonding, traditional dry etching can easily lead to crosstalk and damage between pixels, affecting display performance and the long-term stability of the device. Furthermore, after dry etching, thermal annealing is required for repair, which can easily cause thermal damage. Summary of the Invention
[0004] The purpose of this invention is to solve the above-mentioned technical problems and provide a Micro-LED wafer bonding method. Based on the traditional dry etching method, it adds photoelectrochemical etching technology that can perform fine etching under low temperature and low damage conditions. By using photoelectrochemical etching to repair and correct the sidewalls of Micro-LED pixels, it can avoid the problems of difficulty in depth control, excessive damage, non-uniformity and thermal damage that may occur when using the dry etching method throughout the process.
[0005] To achieve the above objectives, the present invention provides the following solution: The present invention discloses a Micro-LED wafer bonding method, comprising the following steps:
[0006] Step 1: Prepare an epitaxial wafer and a driving substrate. The epitaxial wafer includes a substrate layer and a pixel layer. The pixel layer includes a P-polarity surface and an N-polarity surface. The N-polarity surface is attached to the substrate layer and faces away from the substrate layer.
[0007] Step 2: Deposit a metal layer on the P-electrode surface of the pixel layer as a p-electrode, and deposit a bonding layer on the driving substrate. The bonding layer includes a leveling region and a bonding region for electrical connection with the metal layer. The bonding regions are arranged in the leveling region. At least the bonding region is made of metal.
[0008] Step 3: Bond the metal layer to the bonding layer, and then peel off the substrate layer;
[0009] Step 4: Individual Micro-LED pixels are etched on the pixel layer using dry etching;
[0010] Step 5: Deposit metallic Ti as a hard mask on the N-electrode surface of the Micro-LED pixel, and repair the sidewalls of the Micro-LED pixel by photoelectrochemical etching;
[0011] Step 6: Remove the metal Ti and deposit the first passivation layer, which covers the Micro-LED pixel and the metal layer;
[0012] Step 7: Form a first via on the first passivation layer in the region between the Micro-LED pixels;
[0013] Step 8: Etch away the metal material in the bonding layer using dry etching;
[0014] Step 9: Deposit a second passivation layer, the second passivation layer covering the first via, and open a second via on the second passivation layer on the N-electrode surface of the Micro-LED pixel;
[0015] Step 10: Evaporate an interconnect layer, the interconnect layer covering the second passivation layer and the second via, the interconnect layer being interconnected with the driving substrate as an n-electrode.
[0016] The present invention achieves the following technical effects compared to the prior art:
[0017] In this invention's Micro-LED wafer bonding method, photoelectrochemical etching technology is added to the traditional dry etching process. First, dry etching is used for preliminary etching to form independent Micro-LED pixels. Then, photoelectrochemical etching is used to repair and correct the sidewalls of the Micro-LED pixels. Photoelectrochemical etching can perform fine etching under low temperature and low damage conditions, avoiding the excessive damage or non-uniformity problems that may occur in traditional etching methods. Compared with traditional dry etching, photoelectrochemical etching can not only improve etching accuracy and effectively achieve pixel isolation, but also reduce etching damage to materials and complete etching in a shorter time, improving production efficiency. Moreover, photoelectrochemical etching is performed at a lower temperature, which can also avoid thermal damage that may occur during traditional etching. Attached Figure Description
[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 is a schematic diagram of the overall process in a Micro-LED wafer bonding method according to one or more embodiments;
[0020] Figure 2 is a cross-sectional schematic diagram of the wafer bonding process in a Micro-LED wafer bonding method according to one or more embodiments;
[0021] Figure 3 is a cross-sectional schematic diagram of the dry etching process in a Micro-LED wafer bonding method according to one or more embodiments;
[0022] Figure 4 is a cross-sectional schematic diagram of the Ti deposition process in a Micro-LED wafer bonding method according to one or more embodiments;
[0023] Figure 5 is a cross-sectional schematic diagram of the photoelectrochemical etching process in a Micro-LED wafer bonding method according to one or more embodiments;
[0024] Figure 6 is a cross-sectional schematic diagram of the Ti removal process in a Micro-LED wafer bonding method according to one or more embodiments;
[0025] Figure 7 is a cross-sectional schematic diagram of the first passivation process in a Micro-LED wafer bonding method according to one or more embodiments;
[0026] Figure 8 is a cross-sectional schematic diagram of the first opening process in a Micro-LED wafer bonding method according to one or more embodiments;
[0027] Figure 9 is a cross-sectional schematic diagram of the metal layer etching process in a Micro-LED wafer bonding method according to one or more embodiments;
[0028] Figure 10 is a cross-sectional schematic diagram of the second passivation process in a Micro-LED wafer bonding method according to one or more embodiments;
[0029] Figure 11 is a cross-sectional schematic diagram of the second opening process in a Micro-LED wafer bonding method according to one or more embodiments;
[0030] Figure 12 is a cross-sectional schematic diagram of the interconnect layer deposition process in a Micro-LED wafer bonding method according to one or more embodiments;
[0031] Figure 13 is a top view of Figure 7;
[0032] Figure 14 is a top view of Figure 8;
[0033] Figure 15 is a top view of Figure 11.
[0034] Explanation of reference numerals in the attached figures: 1. Substrate layer; 2. N-GaN layer; 3. MQW layer; 4. P-GaN layer; 5. Metal layer; 6. Leveling area; 7. Bonding area; 8. Driving substrate; 9. Metal Ti; 10. First passivation layer; 11. First via; 12. Second passivation layer; 13. Second via; 14. Interconnect layer. Detailed Implementation
[0035] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0036] This embodiment provides a Micro-LED wafer bonding method, as shown in Figures 1 to 15, including the following steps:
[0037] Step 1: Prepare an epitaxial wafer and a driving substrate 8. The epitaxial wafer includes a substrate layer 1 and a pixel layer. The pixel layer includes a P-side and an N-side. The N-side is attached to the substrate layer 1, and the P-side is away from the substrate layer 1.
[0038] Step 2: A metal layer 5 is deposited on the P-electrode surface of the pixel layer as the p-electrode. A bonding layer is deposited on the driving substrate 8. The bonding layer includes a leveling region 6 and a bonding region 7. The bonding region 7 is used for electrical connection with the metal layer 5. The bonding region 7 is arranged within the leveling region 6. At least the bonding region 7 is made of metal, that is, the leveling region 6 can also be made of metal or non-metal. Since the p-electrode and the bonding region 7 are connected surface to surface, the leveling region 6 is designed to ensure the flatness of the bonding layer.
[0039] Step 3: Bond the metal layer 5 to the bonding layer, and then peel off the substrate layer 1;
[0040] Step 4: Using dry etching, individual Micro-LED pixels are etched on the pixel layer. This is the initial etching step.
[0041] Step 5: Deposit Ti9 metal as a hard mask on the N-electrode surface of the Micro-LED pixel, and repair the sidewalls of the Micro-LED pixel by photoelectrochemical etching;
[0042] Step 6: Remove the metal Ti9, deposit the first passivation layer 10 by vapor deposition, and the first passivation layer 10 covers the Micro-LED pixel and the metal layer 5;
[0043] Step 7: Form a first via 11 on the first passivation layer 10 in the region between Micro-LED pixels;
[0044] Step 8: Use dry etching to etch away the metal material in the bonding layer. If the leveling area 6 is metal, then both the leveling area 6 and the bonding area 7 will be etched away. If the leveling area 6 is non-metallic, then only the bonding area 7 will be etched away.
[0045] Step 9: Deposit a second passivation layer 12, which covers the first passivation layer 10 and the first via 11. A second via 13 is formed on the second passivation layer 12 on the N-side of the Micro-LED pixel.
[0046] Step 10: Evaporate interconnect layer 14, interconnect layer 14 covers second passivation layer 12 and second via 13, interconnect layer 14 is interconnected with driving substrate 8 as n electrode.
[0047] This Micro-LED wafer bonding method first uses dry etching for initial etching, creating individual Micro-LED pixels. Then, photoelectrochemical etching technology is used to repair and correct these pixels. Photoelectrochemical etching is a high-precision etching method that combines the advantages of light and electrochemical reactions. It achieves more uniform and precise etching, accurately controlling etching depth and pixel isolation, reducing sidewall damage, minimizing non-radiative recombination on the Micro-LED chip sidewalls, effectively improving electrical isolation between pixels, and enhancing wafer bonding stability. It avoids problems such as difficulty in controlling etching depth and uneven processing. Furthermore, it can be performed at lower temperatures, avoiding potential thermal damage and further improving the yield and productivity of the entire manufacturing process. Its low-damage characteristics and short processing time optimize the production process and reduce manufacturing costs.
[0048] Note: Micro-LED stands for Micro-Light Emitting Diode.
[0049] In one embodiment, as shown in Figures 1 to 15, the pixel layer includes an N-GaN layer 2, an MQW layer 3, and a P-GaN layer 4 sequentially disposed. The N-GaN layer 2 is bonded to the substrate layer 1, and the P-GaN layer 4 is disposed away from the substrate layer 1. Note: GaN stands for gallium nitride. The N-GaN layer refers to the gallium nitride layer at the N-end, and the P-GaN layer refers to the gallium nitride layer at the P-end. MQW stands for multiple quantum well.
[0050] In one embodiment, as shown in Figures 1 to 15, the substrate 1 is made of silicon or sapphire.
[0051] In one embodiment, as shown in Figures 1 to 15, the leveling area 6 is made of metal, adhesive, or oxide. If the leveling area 6 is made of metal, then in step 8, both the leveling area 6 and the bonding area 7 are etched away. When the leveling area 6 is metal, it can be the same metal as the bonding area 7. When the leveling area 6 is made of adhesive or oxide, it is considered a mixed bond, such as a mixed bond of PI (polyimide) / metal or SiO2 / Cu.
[0052] In one embodiment, as shown in Figures 1 to 15, step 6 employs a wet method to remove metallic Ti9.
[0053] In one embodiment, as shown in Figures 1 to 15, both the first passivation layer 10 and the second passivation layer 12 are formed by silicon oxide deposition.
[0054] In one embodiment, as shown in Figures 1 to 15, in step 7, the first through hole 11 is etched by photolithography.
[0055] In one embodiment, as shown in Figures 1 to 15, in step 8, the second through hole 13 is etched by photolithography.
[0056] In one embodiment, as shown in Figures 1 to 15, the dry etching in step 4 uses ICP etching, and the dry etching in step 8 uses IBE etching.
[0057] Note: ICP etching (Inductively Coupled Plasma Etching) is a process that uses a high-frequency electromagnetic field to excite gas to generate plasma, thereby removing materials through physical bombardment and chemical reactions. Its basic principle is to generate plasma by exciting gas with a radio frequency power supply in a vacuum low-pressure environment. Ions and active particles in the plasma bombard the material surface and undergo chemical reactions under the influence of an electric field, thus removing the material.
[0058] IBE (Ion Beam Etching) is a physical etching method that uses a high-energy ion beam to precisely and directionally bombard the surface of a material, thereby removing the material. IBE etching is highly directional, enabling fine machining of material surfaces.
[0059] In one embodiment, as shown in Figures 1 to 15, the interconnect layer 14 is a metal mesh or an ITO thin film.
[0060] Note: IBE (Ion Beam Etching) is a physical etching method that uses a high-energy ion beam to precisely and directionally bombard the surface of a material, thereby removing the material. IBE etching is highly directional, enabling fine machining of material surfaces.
[0061] In one embodiment, as shown in Figures 1 to 15, the interconnect layer 14 is a metal mesh or an ITO thin film. Note: ITO stands for indium tin oxide.
[0062] In one implementation, as shown in Figures 1 to 15, before step S1, the following steps are included, which mainly involve machine learning:
[0063] Step 1: Collect key data during the chip bonding process, including four main input parameters: pressure, temperature, duration, and warpage level, as well as the corresponding output parameters: bonding force and yield;
[0064] Step 2: Clean the data and use mean imputation or interpolation based on similar samples to handle missing values;
[0065] Step 3: Standardize the input features, such as using Z-score standardization;
[0066] Step 4: Train the preprocessed data using a Gaussian process regression model;
[0067] Step 5: Select an appropriate kernel function to capture the correlation between input parameters and provide the confidence interval of the prediction results;
[0068] Step 6: Evaluate model performance using cross-validation;
[0069] Step 7: Optimize the hyperparameters of the kernel function by maximizing the marginal likelihood function;
[0070] Step 8: Use evaluation metrics such as mean squared error (MSE), mean absolute error (MAE), and coefficient of determination (R2) to comprehensively measure the predictive performance of the Gaussian process regression model;
[0071] Step 9: Using the trained Gaussian process regression model, combined with the Bayesian optimization algorithm, find the combination of input parameters that maximizes the bonding yield;
[0072] Step 10: Determine the combination of input parameters that maximizes bonding yield to optimize the production process.
[0073] Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of this invention. Furthermore, those skilled in the art will recognize that, based on the ideas of this invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this invention.
Claims
1. A method for bonding Micro-LED wafers, characterized in that, Includes the following steps: Step 1: Prepare an epitaxial wafer and a driving substrate. The epitaxial wafer includes a substrate layer and a pixel layer. The pixel layer includes a P-polarity surface and an N-polarity surface. The N-polarity surface is attached to the substrate layer and faces away from the substrate layer. Step 2: Deposit a metal layer on the P-electrode surface of the pixel layer as a p-electrode, and deposit a bonding layer on the driving substrate. The bonding layer includes a leveling region and a bonding region for electrical connection with the metal layer. The bonding regions are arranged in the leveling region. At least the bonding region is made of metal. Step 3: Bond the metal layer to the bonding layer, and then peel off the substrate layer; Step 4: Individual Micro-LED pixels are etched on the pixel layer using dry etching; Step 5: Deposit metallic Ti as a hard mask on the N-electrode surface of the Micro-LED pixel, and repair the sidewalls of the Micro-LED pixel by photoelectrochemical etching; Step 6: Remove the metal Ti and deposit the first passivation layer, which covers the Micro-LED pixel and the metal layer; Step 7: Form a first via on the first passivation layer in the region between the Micro-LED pixels; Step 8: Etch away the metal material in the bonding layer using dry etching; Step 9: Deposit a second passivation layer, the second passivation layer covering the first via, and open a second via on the second passivation layer on the N-electrode surface of the Micro-LED pixel; Step 10: Evaporate an interconnect layer, the interconnect layer covering the second passivation layer and the second via, the interconnect layer being interconnected with the driving substrate as an n-electrode.
2. The Micro-LED wafer bonding method according to claim 1, characterized in that, The pixel layer includes an N-GaN layer, an MQW layer, and a P-GaN layer arranged sequentially. The N-GaN layer is attached to the substrate layer, and the P-GaN layer is away from the substrate layer.
3. The Micro-LED wafer bonding method according to claim 1 or 2, characterized in that, The substrate is made of silicon or sapphire.
4. The Micro-LED wafer bonding method according to claim 1, characterized in that, The leveling area is made of metal, adhesive, or oxide materials.
5. The Micro-LED wafer bonding method according to claim 1, characterized in that, In step 6, a wet process is used to remove metallic Ti.
6. The Micro-LED wafer bonding method according to claim 1, characterized in that, Both the first and second passivation layers are formed by silicon oxide deposition.
7. The Micro-LED wafer bonding method according to claim 1, characterized in that, In step 7, the first through hole is etched by photolithography.
8. The Micro-LED wafer bonding method according to claim 1, characterized in that, In step 8, the second through hole is etched by photolithography.
9. The Micro-LED wafer bonding method according to claim 1 or 8, characterized in that, The dry etching in step 4 uses ICP etching, and the dry etching in step 8 uses IBE etching.
10. The Micro-LED wafer bonding method according to claim 1, characterized in that, The interconnect layer is a metal mesh or an ITO thin film.