Low-power MCU power management unit implemented by using asynchronous circuit
By using an asynchronous circuit design, the MCU power management unit achieves isolation and clock control through delay chains and flip-flops, solving the problems of dynamic power consumption and wake-up response time in low-power mode and realizing the effects of low power consumption and fast wake-up.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- JIANGSU HUACHUANG MICROSYSTEM CO LTD
- Filing Date
- 2025-01-20
- Publication Date
- 2026-07-23
AI Technical Summary
Existing MCU power management units suffer from high dynamic power consumption and long wake-up response time in low-power mode, and cannot completely shut down the clock source, affecting the chip's low power consumption and wake-up efficiency.
An asynchronous circuit design is adopted, using delay chains and flip-flops to achieve isolation control, regulated power supply control and HSI clock control. Timing control is completed asynchronously, reducing dynamic power consumption and shortening wake-up response time.
It achieves low-power mode without clock operation, reduces dynamic power consumption, shortens wake-up response time, has a simple circuit structure, supports hardware control of HSI clock source and avoids circuit error wake-up.
Smart Images
Figure CN2025073227_23072026_PF_FP_ABST
Abstract
Description
A low-power MCU power management unit implemented using asynchronous circuitry Technical Field
[0001] This invention relates to the field of chip design, and more specifically to a low-power MCU power management unit implemented using asynchronous circuitry. Background Technology
[0002] With the continuous development of IoT technology, MCUs are playing an increasingly important role. A key metric for MCUs is power consumption. Reducing MCU power consumption not only extends the operating time of IoT systems in battery-powered environments but also lowers the MCU chip's operating temperature, thus extending its lifespan. Currently, the main low-power approach involves dividing the chip into multiple power domains and shutting down the MCU's internal clock and power supply as much as possible when the CPU is not operating. This is typically achieved through a power management unit (PMU) in conjunction with clock, reset, isolation units, and power switches to control the MCU's low power consumption. In existing solutions, the PMU is usually implemented based on a state machine, controlling the circuit by transitioning to different states. This approach typically has two drawbacks. First, state machines are sequential circuits that require a clock to operate. A state machine-based PMU generates significant dynamic power consumption during operation, and even in low-power mode, it cannot completely shut down the clock source; otherwise, the PMU would be unable to perform a wake-up operation. Second, even if an asynchronous wake-up circuit can shut down the clock source in low-power mode, the PMU still needs to wait for the clock to recover before it can start operating, thus increasing the recovery time during chip wake-up. Summary of the Invention
[0003] The present invention aims to address the shortcomings of existing MCU power management unit implementation technologies by providing an asynchronous circuit-implemented power management unit to effectively reduce power consumption and area cost, while shortening the response time for waking up from low-power mode.
[0004] This invention provides the following technical solution:
[0005] This invention provides a low-power MCU power management unit, or PMU, implemented using asynchronous circuitry. The MCU includes an LDO, HSI, ISO, VCORE field, and HSION register. The output signal of the VCORE field is passed through ISO before being output to other modules.
[0006] The PMU includes an isolation control module, a power-on control module, and a delayed wake-up module;
[0007] Among them, the isolation control module outputs Iso_on to the ISO as the ISO's enable signal;
[0008] The isolation control module is configured as follows:
[0009] When Por_rstn_dly is in the power-on reset state or Iso_clamp is in the active state, Iso_on is set to the active state; where Por_rstn_dly is Por_rstn released after a delay, and Por_rstn is the power-on reset signal; Iso_clamp is the signal obtained after Standby_en is delayed by a delay chain, and Standby_en is the low-power mode switching enable signal;
[0010] When the first condition changes from an unsatisfied state to a satisfied state, after a delay chain, Iso_on is set to an invalid state. The content of the first condition is that Por_rstn_dly is in a reset release state and Standby_rstn is in an invalid state; where Standby_rstn is the VCORE field reset signal. When Standby_rstn is valid, the VCORE field is reset.
[0011] Among them, the power-on control module outputs Ldo_on to the LDO as the LDO enable signal;
[0012] The power-on control module is configured as follows:
[0013] When Por_rstn_dly is in power-on reset state or the wake-up condition is met, Ldo_on is set to the active state; where the wake-up condition includes the wake-up flag signal Stdby_wkup_src being active, and Ldo_on_dly being Ldo_on after the delay chain.
[0014] When Iso_on_dly changes from invalid to valid, Ldo_on is set to invalid; where Iso_on_dly is the Iso_on after the delay chain.
[0015] The delayed wake-up module outputs Standby_rstn;
[0016] The delayed wake-up module is configured as follows:
[0017] When Por_rstn_dly is in power-on reset state, Standby_rstn is set to invalid state;
[0018] When the wake-up condition changes from not being met to being met, Standby_rstn is set to an active state; if the preset wake-up time is delayed, Standby_rstn is set to an inactive state.
[0019] The core circuit of this invention uses only a few delay chains to complete all timing control, without relying on a clock, thus reducing the dynamic power consumption of the PMU and making it simpler in structure than a PMU implemented with a state machine. Compared to a PMU implemented with a state machine, which needs to wait for the clock to stabilize before starting to work, this invention starts working as soon as the wake-up flag is valid, effectively shortening the chip's wake-up response time.
[0020] Furthermore, when both the LDO and HSION registers send valid enable signals to the HSI, the HSI is turned on; otherwise, the HSI is turned off. The LDO sends a valid enable signal to the HSI after the output voltage reaches the threshold and remains there for a preset time.
[0021] The external wiring of the PMU is configured as follows:
[0022] When Por_rstn_dly is in power-on reset state or Standby_rstn is in active state, the VCORE field is reset and the HSION register is reset, so that the enable signal sent by the HSION register to HSI is enabled.
[0023] This solution indirectly controls the HSI clock source enable by controlling the LDO enable and Standby_rstn, thus enabling hardware control of the HSI without affecting software control of the HSI.
[0024] Furthermore, the delayed wake-up module uses the clock signal Hsi_clk generated by HSI for timing when the preset wake-up time is delayed.
[0025] This scheme uses the clock signal Hsi_clk for timing, thus ensuring that the VCORE domain is released and reset after the HSI clock stabilizes.
[0026] Furthermore, the wake-up condition also includes Ldo_on_dly being in an invalid state.
[0027] This solution disables the wake-up flag signal before the power-off process ends (when Ldo_on_dly has not yet become invalid) to prevent the circuit from being woken up incorrectly.
[0028] Furthermore, the isolation control module includes a DFF trigger ISO_ON and a delay chain;
[0029] The data input terminal D of ISO_ON is always 1, and the positive output terminal Q is connected to Iso_on;
[0030] Delay Standby_en using a delay chain to obtain Iso_clamp. Perform a logical OR operation between Iso_clamp and the inverted Por_rstn_dly, and then connect it to the high-level active reset input of ISO_ON.
[0031] After Por_rstn_dly and Standby_rstn perform a logical AND operation, the result is delayed by a delay chain and then connected to the rising edge trigger clock input of ISO_ON.
[0032] Iso_on and Standby_rstn are active low, Standby_en is active high, Por_rstn_dly is low during power-on reset and high during reset release; Iso_on is set to 0 when ISO_ON is reset.
[0033] Furthermore, the power-on control module includes a DFF trigger LDO_ON and a delay chain;
[0034] The data input terminal D of LDO_ON is always 1, and the inverting output terminal QN is connected to LDO_ON;
[0035] After delaying Iso_on using a delay chain, it is connected to the falling edge trigger clock input of LDO_ON;
[0036] After delaying Ldo_on using a delay chain, we get Ldo_on_dly. After inverting Ldo_on_dly, we perform a logical AND operation with Stdby_wkup_src to get Ldo_on_set. After inverting Ldo_on_set, we perform a logical AND operation with Por_rstn_dly and then connect it to the low-level active reset input of LDO_ON.
[0037] Among them, Ldo_on and Stdby_wkup_src are active high, and Iso_on is active low; Por_rstn_dly is low in the power-on reset state and high in the reset release state; Ldo_on is set to 1 when LDO_ON is reset;
[0038] Furthermore, the delayed wake-up module includes a DFF trigger LDO_HSI_ON, a counter Standby_rstn_cnt, a comparator, and a delay chain;
[0039] The data input D of LDO_HSI_ON is always 1. Its positive output Q is connected to Ldo_hsi_on, and its inverted output QN is connected to Standby_rstn. The result of a logical AND operation between the inverted Ldo_on_dly and Stdby_wkup_src is connected to the rising edge trigger input of LDO_HSI_ON, where Ldo_on_dly is the delayed Ldo_on after a delay chain. After synchronization, Ldo_hsi_on is input to the enable input of Standby_rstn_cnt. The clock signal Hsi_clk generated by HSI is connected to the rising edge trigger clock input of Standby_rstn_cnt. The count value H generated by Standby_rstn_cnt... `si_cnt` is connected to the input of the comparator, and the output of the comparator is connected to the `Hsi_stable` signal. When `Hsi_cnt` equals the set threshold `n`, `Hsi_stable` is set to 1; otherwise, `Hsi_stable` is set to 0. After delaying `Hsi_stable` using a delay chain, `Hsi_stable_dly` is obtained. After inverting `Hsi_stable_dly`, a logical AND operation is performed with `Por_rstn_dly` to obtain `Ldo_hsi_on_rstn`. `Ldo_hsi_on_rstn` is input to the active-low reset input of the `LDO_HSI_ON` flip-flop, and `Ldo_hsi_on_rstn` is also input to the active-low reset input of `Standby_rstn_cnt`.
[0040] Standby_rstn is active low, while Ldo_hsi_on, Ldo_on, and Stdby_wkup_src are active high. Por_rstn_dly is low during power-on reset and high during reset release. When LDO_HSI_ON is reset, Ldo_hsi_on is set to 0 and Standby_rstn is set to 1.
[0041] Beneficial Effects: This invention asynchronously implements isolation unit control, regulated power supply control, HSI clock control, and VCORE domain reset control through flip-flops and a series of delay chains. Compared to a PMU implemented based on a state machine, this invention is a fully asynchronous design, requiring no clock during operation, reducing the dynamic power consumption of the PMU, and saving the power required to maintain clock operation in low-power mode. Unlike a state machine-implemented PMU that needs to wait for the clock to stabilize before starting work, this invention starts working immediately after the wake-up flag is valid, effectively shortening the chip's wake-up response time. From a circuit scale perspective, the core circuit of this invention uses only 3 flip-flops, 1 counter, and several delay chains to complete all timing control, making it simpler than a state machine-implemented PMU circuit structure. This invention can reset and release the VCORE domain during wake-up and automatically reset the internal counter after wake-up, without requiring software reset. This invention indirectly controls the HSI clock source enable by controlling the LDO enable and Standby_rstn, achieving hardware control of the HSI without affecting software control of the HSI. Finally, this invention can shield the wake-up flag signal before the power-off process ends, thus preventing the circuit from being woken up incorrectly. Attached Figure Description
[0042] Figure 1 is a structural diagram of one embodiment of the power management unit in this invention;
[0043] Figure 2 is a structural diagram of one embodiment of the peripheral circuit of the power management unit in this invention;
[0044] Figure 3 is a timing control diagram of the power management unit in an embodiment of the present invention; Detailed Implementation
[0045] To make the objectives, features, and advantages of this invention more apparent and understandable, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described below are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.
[0046] A low-power MCU power management unit, or PMU for short, is implemented using asynchronous circuitry. The MCU includes an LDO (linear regulated power supply), an HSI (high-speed internal oscillator), an ISO (isolation unit), a VCORE domain, and an HSION register. The output signal of the VCORE domain is output to other modules after passing through the ISO. The HSI is enabled when both the LDO and the HSION register send valid enable signals to the HSI; otherwise, the HSI is disabled. The LDO sends a valid enable signal to the HSI after its output voltage reaches a threshold and remains there for a preset time.
[0047] The PMU includes an isolation control module, a power-on control module, and a delayed wake-up module;
[0048] Among them, the isolation control module outputs Iso_on to the ISO as the ISO's enable signal;
[0049] The isolation control module is configured as follows:
[0050] When Por_rstn_dly is in the power-on reset state or Iso_clamp is in the active state, Iso_on is set to the active state; where Por_rstn_dly is Por_rstn released after a delay, and Por_rstn is the power-on reset signal; Iso_clamp is the signal obtained after Standby_en is delayed by a delay chain, and Standby_en is the low-power mode switching enable signal;
[0051] When the first condition changes from an unsatisfied state to a satisfied state, after a delay chain, Iso_on is set to an invalid state. The content of the first condition is that Por_rstn_dly is in a reset release state and Standby_rstn is in an invalid state; where Standby_rstn is the VCORE field reset signal. When Standby_rstn is valid, the VCORE field is reset.
[0052] Among them, the power-on control module outputs Ldo_on to the LDO as the LDO enable signal;
[0053] The power-on control module is configured as follows:
[0054] When Por_rstn_dly is in power-on reset state or the wake-up condition is met, Ldo_on is set to the active state; wherein, the wake-up condition includes the wake-up flag signal Stdby_wkup_src being active and Ldo_on_dly being inactive, where Ldo_on_dly is Ldo_on after the delay chain;
[0055] When Iso_on_dly changes from invalid to valid, Ldo_on is set to invalid; where Iso_on_dly is the Iso_on after the delay chain.
[0056] The delayed wake-up module outputs Standby_rstn;
[0057] The delayed wake-up module is configured as follows:
[0058] When Por_rstn_dly is in power-on reset state, Standby_rstn is set to invalid state;
[0059] When the wake-up condition changes from not being met to being met, Standby_rstn is set to an active state; when the preset wake-up time is delayed, Standby_rstn is set to an inactive state.
[0060] The external wiring of the PMU is configured as follows:
[0061] When Por_rstn_dly is in power-on reset state or Standby_rstn is in active state, the VCORE field is reset and the HSION register is reset, so that the enable signal sent by the HSION register to HSI is enabled.
[0062] The following describes a more specific implementation:
[0063] The PMU is located in the 3.3V digital normally open power domain of the MCU, which is powered by the chip's power supply pin and remains powered when entering low-power mode.
[0064] The VCORE domain is located in the 1.1V digital power-down domain and contains the MCU core, bus, and various 1.1V digital peripherals. It is powered off when the chip enters low-power mode.
[0065] The circuit architecture of the PMU is shown in Figure 1. It consists of three DFF flip-flops (ISO_ON, LDO_ON, LDO_HSI_ON), one counter (Standby_rstn_cnt), one digital comparator (COMP), five delay chains, and several logic gates and synchronizers. The PMU performs asynchronous power-on and power-off timing control through the five delay chains, without requiring a clock. The counter uses the clock signal Hsi_clk to count, and releases and resets the VCORE field after the HSI clock stabilizes.
[0066] When the chip enters low-power mode, the PMU controls the ISO enable signal Iso_on and the LDO enable signal Ldo_on to be set to 0. When exiting low-power mode, it controls Ldo_on to be set to 1, controls the VCORE domain reset signal Standby_rstn to be set to 0 and then set to 1 after a period of time, and finally controls Iso_on to be set to 1 to release the isolation of the VCORE domain.
[0067] The Iso_on is an ISO enable signal that is active low. When Iso_on is 0, all output signals of the VCORE domain are isolated. When Iso_on is 1, the isolation of the VCORE domain is released.
[0068] The Ldo_on is a high-level active LDO enable signal. When Ldo_on is 1, it enables the LDO to restore power to the VCORE domain. When Ldo_on is 0, it disables the LDO to power down the VCORE domain.
[0069] Standby_rstn is a low-level active VCORE field reset signal. When Standby_rstn is 0, the VCORE field is reset; when Standby_rstn is 1, the VCORE field reset is released.
[0070] The circuit connection of the PMU is shown in Figure 1. Por_rstn_dly and Standby_rstn are combined to obtain Iso_release_in. Iso_release_in is delayed by a set of delay chains to obtain Iso_release, which is then connected to the rising edge trigger clock input of the ISO_ON flip-flop. The Standby_en signal is delayed by a set of delay chains to obtain Iso_clamp. Iso_clamp and the inverted Por_rstn_dly are ORed to obtain Iso_on_rst. Iso_on_rst is connected to the high-level active reset input of the ISO_ON flip-flop. The data input D of the ISO_ON flip-flop is always 1, and its positive output Q is connected to Iso_on. Iso_on is delayed by a set of delay chains to obtain Iso_on_dly, which is input to the falling edge trigger clock input of the LDO_ON flip-flop. The data input D of the LDO_ON is always 1, and its inverted output QN is connected to LDO_on to control the enable of the 1.1V regulated power supply. Ldo_on is passed through a delay chain to obtain Ldo_on_dly. Ldo_on_dly is inverted and then ANDed with the wake-up flag signal Stdby_wkup_src to obtain Ldo_on_set. Ldo_on_set is inverted and then ANDed with Por_rstn_dly to obtain the low-level active reset input signal Ldo_on_rstn of the LDO_ON flip-flop. Ldo_on_set is also connected to the rising edge trigger clock input of the LDO_HSI_ON flip-flop, and the data input D of the LDO_HSI_ON flip-flop is always 1. The positive output Q of the LDO_HSI_ON flip-flop is connected to Ldo_Hsi_on. Ldo_Hsi_on is synchronized to the HSI clock through two stages of synchronizers and then used as the enable signal for the Standby_rstn_cnt counter. The inverted output QN of LDO_HSI_ON is connected to the Standby_rstn signal, which resets the VCORE field when it is 0. The rising edge trigger clock input of the Standby_rstn_cnt counter is connected to Hsi_clk. It starts counting up on Hsi_clk when the enable signal EN of the Standby_rstn_cnt counter is 1. The count value Hsi_cnt output by Standby_rstn_cnt is connected to the input of a comparator, and the output of the comparator is connected to the Hsi_stable signal. When Hsi_cnt equals the set threshold n, Hsi_stable is set to 1; otherwise, Hsi_stable is 0.Hsi_stable is delayed by a set of delay chains to obtain Hsi_stable_dly. Hsi_stable_dly is inverted and ANDed with Por_rstn_dly to obtain Ldo_hsi_on_rstn. Ldo_hsi_on_rstn is input to the active-low reset input of the LDO_HSI_ON flip-flop, and Ldo_hsi_on_rstn is also input to the active-low reset input of Standby_rstn_cnt.
[0071] The peripheral circuit of the PMU is shown in Figure 2. Por_rstn_dly and Standby_rstn are connected to the HSION register and the low-level active reset input of the VCORE domain. The output of the HSION register is Hsi_on, with a reset value of 1, indicating an active state. The HSION register can be configured via software. Ldo_on is connected to the enable input of the regulated power supply LDO. When the LDO's output voltage reaches a threshold of 10µs, the LDO sends an enable signal VCORE_OK_HV to the HSI, setting it to 1, indicating an active state. VCORE_OK_HV and Hsi_on are ANDed to obtain En_hsi, which is then input to the enable input of the HSI clock source. When En_hsi is 1, the HSI starts working and outputs the clock Hsi_clk; otherwise, the clock output is disabled. When the Standby_en signal output from the VCORE domain is 1, it indicates that the PMU is enabled to enter low-power mode. The VCORE domain output signal is output to other modules after passing through the ISO isolation unit. The isolation unit is active when Iso_on is low. The APB bus output from the VCORE domain is connected to the HSION register after passing through ISO, and is used to configure the HSION register.
[0072] As shown in Figure 3, the control flow of the PMU in this implementation use case is described as follows:
[0073] 1) Por_rstn_dly is Por_rstn released after a clock delay of Hsi_clk. Por_rstn is the power-on reset signal. When Por_rstn_dly is in the power-on reset state, it defaults to a low level and resets all flip-flops and counters of the PMU, where Iso_on and Hsi_cnt are reset to 0, Ldo_on and Standby_rstn are reset to 1, enabling LDO output and isolating the VCORE domain.
[0074] 2) After the LDO output voltage reaches the threshold of 10us, VCORE_OK_HV is set to 1, enabling the HSI oscillator to generate a clock.
[0075] The AND operation between Por_rstn_dly and Standby_rstn is used to obtain Iso_release_in. Por_rstn_dly is reset to a high level, which sets Iso_release_in to 1.
[0076] 3) Iso_release_in generates Iso_release through a delay chain. The rising edge of Iso_release triggers Iso_on to be set to 1, and ISO changes from being enabled at power-on to being disabled.
[0077] 4) When entering low power mode, the low power mode switching enable signal Standby_en is set to 1. After a delay chain, Iso_clamp is set to 1. When Iso_clamp is high, Iso_on is set to 0. Enabling ISO also clamps Standby_en to 0.
[0078] Meanwhile, since the PMU does not depend on the clock signal, HSI is turned off by configuring the HSION register via ISO through the APB bus before the Standby_en is issued in the VCORE domain.
[0079] 5) After the delay chain, Iso_on sets Iso_on_dly to 0. The falling edge of Iso_on_dly triggers LDO_ON to output Ldo_on to 0, and LDO is turned off, completing the entire power-down process.
[0080] 6) When exiting low-power mode, the input wake-up flag signal Stdby_wkup_src is set to 1. Ldo_on_dly is generated by Ldo_on through a delay chain, and the wake-up condition is only met when it is 0. When Ldo_on_dly is 0 and Stdby_wkup_src is 1, Ldo_on_set is set to 1.
[0081] 7) Setting Ldo_on_set to 1 resets the LDO_ON flip-flop, setting Ldo_on to 1 and enabling LDO. Once the LDO output is valid, VCORE_OK_HV is set to 1.
[0082] Simultaneously, the rising edge of Ldo_on_set triggers Ldo_Hsi_on to be set to 1, enabling the counter to count Hsi_clk; the rising edge of Ldo_on_set triggers the LDO_HSI_ON inverting output terminal Standby_rstn to be set to 0, resetting the VCORE domain register and simultaneously resetting the HSION register, causing Hsi_on to be set to 1, at which point the HSI oscillator generates a clock.
[0083] 8) When the Hsi_cnt count value reaches the comparator threshold, Hsi_stable is set to 1, and the LDO_HSI_ON flip-flop and counter are reset.
[0084] 9) Resetting the LDO_HSI_ON trigger sets Ldo_Hsi_on to 0 to stop counting and simultaneously sets Standby_rstn to 1 to release the VCORE field reset.
[0085] 10) Iso_release_in changes with Standby_rstn. When Standby_rstn is released, Iso_release_in will generate a rising edge.
[0086] 11) After the rising edge of Iso_release_in is delayed, the rising edge of Iso_release is generated, triggering Iso_on to be set to 1, thus completing the entire low-power wake-up process.
[0087] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A low-power MCU power management unit, or PMU for short, implemented using asynchronous circuitry, wherein the MCU includes an LDO, HSI, ISO, VCORE domain, and HSION register; the output signal of the VCORE domain is output to other modules after passing through ISO. Its features are, The PMU includes an isolation control module, a power-on control module, and a delayed wake-up module; Among them, the isolation control module outputs Iso_on to the ISO as the ISO's enable signal; The isolation control module is configured as follows: When Por_rstn_dly is in the power-on reset state or Iso_clamp is in the active state, Iso_on is set to the active state; where Por_rstn_dly is Por_rstn released after a delay, and Por_rstn is the power-on reset signal; Iso_clamp is the signal obtained after Standby_en is delayed by a delay chain, and Standby_en is the low-power mode switching enable signal; When the first condition changes from an unsatisfied state to a satisfied state, after a delay chain, Iso_on is set to an invalid state. The content of the first condition is that Por_rstn_dly is in a reset release state and Standby_rstn is in an invalid state; where Standby_rstn is the VCORE field reset signal. When Standby_rstn is valid, the VCORE field is reset. Among them, the power-on control module outputs Ldo_on to the LDO as the LDO enable signal; The power-on control module is configured as follows: When Por_rstn_dly is in power-on reset state or the wake-up condition is met, Ldo_on is set to the active state; where the wake-up condition includes the wake-up flag signal Stdby_wkup_src being active, and Ldo_on_dly being Ldo_on after the delay chain. When Iso_on_dly changes from invalid to valid, Ldo_on is set to invalid; where Iso_on_dly is the Iso_on after the delay chain. The delayed wake-up module outputs Standby_rstn; The delayed wake-up module is configured as follows: When Por_rstn_dly is in power-on reset state, Standby_rstn is set to invalid state; When the wake-up condition changes from not being met to being met, Standby_rstn is set to an active state; if the preset wake-up time is delayed, Standby_rstn is set to an inactive state.
2. A low-power MCU power management unit (PMU) implemented using asynchronous circuitry as described in claim 1, characterized in that: HSI is enabled when both the LDO and HSION registers send valid enable signals to HSI; otherwise, HSI is disabled. The LDO sends a valid enable signal to HSI after the output voltage reaches the threshold and remains so for a preset time. The external wiring of the PMU is configured as follows: When Por_rstn_dly is in power-on reset state or Standby_rstn is in active state, the VCORE field is reset and the HSION register is reset, so that the enable signal sent by the HSION register to HSI is enabled.
3. A low-power MCU power management unit (PMU) implemented using asynchronous circuitry as described in claim 1, characterized in that: The delayed wake-up module uses the clock signal Hsi_clk generated by HSI to keep track of the time when the preset wake-up time is delayed.
4. A low-power MCU power management unit (PMU) implemented using asynchronous circuits according to claim 1, wherein the wake-up condition further includes Ldo_on_dly being in an invalid state.
5. A low-power MCU power management unit implemented using asynchronous circuits as described in claim 1, abbreviated as PMU, characterized in that the isolation control module includes a DFF flip-flop ISO_ON and a delay chain; The data input terminal D of ISO_ON is always 1, and the positive output terminal Q is connected to Iso_on; Delay Standby_en using a delay chain to obtain Iso_clamp. Perform a logical OR operation between Iso_clamp and the inverted Por_rstn_dly, and then connect it to the high-level active reset input of ISO_ON. After Por_rstn_dly and Standby_rstn perform a logical AND operation, the result is delayed by a delay chain and then connected to the rising edge trigger clock input of ISO_ON. Iso_on and Standby_rstn are active low, Standby_en is active high, Por_rstn_dly is low during power-on reset and high during reset release; Iso_on is set to 0 when ISO_ON is reset.
6. A low-power MCU power management unit implemented using asynchronous circuits as described in claim 1, abbreviated as PMU, characterized in that the power-on control module includes a DFF flip-flop LDO_ON and a delay chain; The data input terminal D of LDO_ON is always 1, and the inverting output terminal QN is connected to LDO_ON; After delaying Iso_on using a delay chain, it is connected to the falling edge trigger clock input of LDO_ON; After delaying Ldo_on using a delay chain, we get Ldo_on_dly. After inverting Ldo_on_dly, we perform a logical AND operation with Stdby_wkup_src to get Ldo_on_set. After inverting Ldo_on_set, we perform a logical AND operation with Por_rstn_dly and then connect it to the low-level active reset input of LDO_ON. in, Ldo_on and Stdby_wkup_src are active high, while Iso_on is active low; Por_rstn_dly is low on power-on reset and high on reset release; LDO_ON is set to 1 during LDO_ON reset.
7. A low-power MCU power management unit (PMU) implemented using asynchronous circuits according to claim 1, characterized in that the delayed wake-up module includes a DFF flip-flop LDO_HSI_ON, a counter Standby_rstn_cnt, a comparator, and a delay chain; The data input D of LDO_HSI_ON is always 1. Its positive output Q is connected to Ldo_hsi_on, and its inverted output QN is connected to Standby_rstn. The result of a logical AND operation between the inverted Ldo_on_dly and Stdby_wkup_src is connected to the rising edge trigger input of LDO_HSI_ON, where Ldo_on_dly is the delayed Ldo_on after a delay chain. After synchronization, Ldo_hsi_on is input to the enable input of Standby_rstn_cnt. The clock signal Hsi_clk generated by HSI is connected to the rising edge trigger clock input of Standby_rstn_cnt. The count value H generated by Standby_rstn_cnt... `si_cnt` is connected to the input of the comparator, and the output of the comparator is connected to the `Hsi_stable` signal. When `Hsi_cnt` equals the set threshold `n`, `Hsi_stable` is set to 1; otherwise, `Hsi_stable` is set to 0. After delaying `Hsi_stable` using a delay chain, `Hsi_stable_dly` is obtained. After inverting `Hsi_stable_dly`, a logical AND operation is performed with `Por_rstn_dly` to obtain `Ldo_hsi_on_rstn`. `Ldo_hsi_on_rstn` is input to the active-low reset input of the `LDO_HSI_ON` flip-flop, and `Ldo_hsi_on_rstn` is also input to the active-low reset input of `Standby_rstn_cnt`. Standby_rstn is active low, while Ldo_hsi_on, Ldo_on, and Stdby_wkup_src are active high. Por_rstn_dly is low during power-on reset and high during reset release. When LDO_HSI_ON is reset, Ldo_hsi_on is set to 0 and Standby_rstn is set to 1.