Array substrate and electronic paper display panel

Abstract

An array substrate, comprising a substrate, a first conductive layer, a semiconductor layer, a second conductive layer, a pixel electrode layer, and a thin-film transistor. The first conductive layer comprises a plurality of first signal lines and a first conductive pattern. The semiconductor layer comprises a plurality of semiconductor patterns, each semiconductor pattern comprising a channel structure and a first portion and a second portion located on two sides of the channel structure. The second conductive layer comprises a plurality of second signal lines, a gate electrically connected to the second signal lines, a first electrode, a second electrode, and a second conductive pattern. The first electrode is electrically connected to the first signal lines and the first portions, and the second electrode is electrically connected to both the first conductive pattern and the second portions. The orthographic projection of the second conductive pattern on the substrate at least partially overlaps the orthographic projection of the first conductive pattern on the substrate, and a first capacitor is formed between the second conductive pattern and the first conductive pattern. The pixel electrode layer comprises a pixel electrode, and the pixel electrode is electrically connected to the second electrode. The thin-film transistor comprises a gate, a semiconductor pattern, a first electrode, and a second electrode.

Description

Array substrate and electronic paper display panel Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to an array substrate and an electronic paper display panel. Background Technology

[0002] Electrophoretic displays offer advantages such as low power consumption, portability, eye protection, and the ability to update display content at any time, leading to their increasing application in various fields including education, healthcare, and daily reading. For example, an electrophoretic display device can be electronic paper, an ultra-thin and ultra-light display device whose display effect closely resembles that of natural paper. As a reading device, electronic paper can reduce reading fatigue and is therefore widely used in the reading field. Summary of the Invention

[0003] On one hand, an array substrate is provided. The array substrate includes a substrate, a first conductive layer, a semiconductor layer, a second conductive layer, and a pixel electrode layer. The first conductive layer is located on one side of the substrate and includes multiple first signal lines and a first conductive pattern. The semiconductor layer is located on the side of the first conductive layer away from the substrate and includes multiple semiconductor patterns. The semiconductor pattern includes a channel structure and a first portion and a second portion located on both sides of the channel structure. The second conductive layer is located on the side of the semiconductor layer away from the substrate and includes multiple second signal lines, a gate electrically connected to the second signal lines, a first electrode, a second electrode, and a second conductive pattern. The first electrode is electrically connected to the first signal lines and the first portion, respectively, and the second electrode is electrically connected to the first conductive pattern and the second portion, respectively. The orthographic projection of the second conductive pattern on the substrate at least partially overlaps with the orthographic projection of the first conductive pattern on the substrate, and forms a first capacitance between the second conductive pattern and the first conductive pattern. The pixel electrode layer is located on the side of the second conductive layer away from the substrate and includes a pixel electrode, which is electrically connected to the second electrode. The array substrate further includes a thin-film transistor, which includes the gate, the semiconductor pattern, the first electrode, and the second electrode.

[0004] In some embodiments, the orthogonal projection of the second electrode on the substrate does not coincide with the orthogonal projection of the gate on the substrate, nor with the orthogonal projection of the second signal line on the substrate.

[0005] In some embodiments, the array substrate further includes a third conductive layer. The third conductive layer is located between the second conductive layer and the pixel electrode layer, and includes a third conductive pattern. The orthographic projection of the third conductive pattern on the substrate at least partially coincides with the orthographic projection of the pixel electrode on the substrate, and forms a second capacitance between the third conductive pattern and the pixel electrode.

[0006] In some embodiments, the third conductive layer further includes a transition block, which is electrically connected to the second electrode and the pixel electrode, respectively.

[0007] In some embodiments, the array substrate further includes a first insulating layer, a planarization layer, and a second insulating layer. The first insulating layer is located between the second conductive layer and the third conductive layer. The planarization layer is located between the first insulating layer and the third conductive layer. The second insulating layer is located between the third conductive layer and the pixel electrode layer. The array substrate further includes a second via, a first via, and a third via. The first via penetrates the first insulating layer and exposes at least a portion of the second conductive pattern. The second via penetrates the planarization layer and exposes at least a portion of the first via. The third via penetrates the second insulating layer and exposes at least a portion of the adapter block. The adapter block is electrically connected to the second conductive pattern through the second via and the first via, and the pixel electrode is electrically connected to the adapter block through the third via.

[0008] In some embodiments, the orthographic projection of the second via on the substrate covers the orthographic projection of the first via on the substrate; and / or, the orthographic projection of the third via on the substrate at least partially overlaps with the orthographic projection of the second via on the substrate.

[0009] The second conductive layer further includes a first connecting line located between two adjacent second conductive patterns along a first direction and electrically connected to the two second conductive patterns. The third conductive layer further includes a second connecting line located between two adjacent third conductive patterns along a second direction and electrically connected to the two third conductive patterns. The first direction is the extension direction of the second signal line, and the second direction is the extension direction of the first signal line. The array substrate includes a display area and a peripheral area surrounding the display area. The second conductive pattern and the third conductive pattern are configured to transmit the same voltage signal, and the second conductive pattern and the third conductive pattern are electrically connected in the peripheral area.

[0010] In some embodiments, the array substrate further includes a first insulating layer and a planarization layer. The first insulating layer is located between the second conductive layer and the third conductive layer. The planarization layer is located between the second insulating layer and the third conductive layer. The fourth via penetrates the first insulating layer and exposes at least a portion of the second conductive pattern; the fifth via penetrates the planarization layer and exposes at least a portion of the fourth via. The third conductive pattern is electrically connected to the second conductive pattern through the fifth via and the fourth via.

[0011] In some embodiments, the array substrate includes a plurality of sub-pixels arranged in an array. Each sub-pixel includes a thin-film transistor and a pixel electrode electrically connected to the thin-film transistor. The plurality of sub-pixels are arranged in rows along a first direction and in columns along a second direction. A plurality of second signal lines are arranged at intervals along the second direction, with two rows of sub-pixels between adjacent two second signal lines. A second signal line is electrically connected to the thin-film transistors of two adjacent rows of sub-pixels along the second direction.

[0012] In some embodiments, two first signal lines are included between two adjacent columns of the sub-pixels. Two thin-film transistors of two adjacent sub-pixels along the second direction are respectively electrically connected to the two first signal lines located adjacent to each sub-pixel along the first direction.

[0013] In some embodiments, the orthographic projection of the second conductive pattern on the substrate is located between the orthographic projections of two adjacent second signal lines on the substrate, and coincides with the orthographic projection portions of the two first conductive patterns on the substrate, forming the first capacitor with the two first conductive patterns respectively. And / or, the orthographic projection of the third conductive pattern on the substrate is located between the orthographic projections of two adjacent second signal lines on the substrate, and coincides with the orthographic projection portions of the two pixel electrodes on the substrate, forming the second capacitor with the two pixel electrodes respectively.

[0014] In some embodiments, the array substrate includes a plurality of sub-pixels arranged in an array. Each sub-pixel includes a thin-film transistor and a pixel electrode electrically connected to the thin-film transistor. The plurality of sub-pixels are arranged in rows along a first direction and in columns along a second direction. A plurality of second signal lines are arranged at intervals along the second direction, with a row of sub-pixels between two adjacent second signal lines, and one second signal line electrically connected to the thin-film transistor of a row of sub-pixels. A first signal line is included between two adjacent columns of sub-pixels, and the thin-film transistor of a column of sub-pixels is electrically connected to one first signal line.

[0015] In some embodiments, the orthographic projection of the first portion on the substrate coincides with the orthographic projection of the first signal line on the substrate, and the portion of the orthographic projection of the first portion on the substrate and the orthographic projection of the first signal line on the substrate that coincide has a dimension greater than or equal to 2 μm along a first target direction, the first target direction being perpendicular to the edge of the semiconductor pattern near the first signal line. And / or, the orthographic projection of the second portion on the substrate coincides with the orthographic projection of the first conductive pattern on the substrate, and the portion of the orthographic projection of the second portion on the substrate and the orthographic projection of the first conductive pattern on the substrate that coincide has a dimension greater than or equal to 2 μm along a second target direction; the second target direction being perpendicular to the edge of the semiconductor pattern near the first conductive pattern.

[0016] In some embodiments, the array substrate further includes a third insulating layer, a sixth via, and a seventh via. The third insulating layer is located between the first conductive layer and the semiconductor layer. The sixth via penetrates at least the third insulating layer and exposes at least a portion of the first signal line; the seventh via penetrates at least the third insulating layer and exposes at least a portion of the first conductive pattern. The portion of the first signal line within the sixth via has a dimension greater than or equal to 3 μm along the first target direction. The portion of the first conductive pattern exposed by the seventh via has a dimension greater than or equal to 3 μm along the second target direction.

[0017] In some embodiments, the portion of the first electrode that contacts the first part has a dimension greater than or equal to 4 μm along the first target direction. And / or, the portion of the second electrode that contacts the second part has a dimension greater than or equal to 4 μm along the second target direction.

[0018] On the other hand, an electronic paper display panel is also provided, the electronic paper display panel including the array substrate described in any of the above embodiments. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0020] Figure 1 is a structural diagram of an electronic paper display panel according to some embodiments;

[0021] Figure 2 is a planar structural diagram of an array substrate according to some embodiments;

[0022] Figure 3 is a cross-sectional view along section line AA in Figure 2;

[0023] Figure 4 is a structural diagram of a first conductive layer, a semiconductor layer, and a second conductive layer according to some embodiments;

[0024] Figure 5 is a structural diagram of the first conductive layer and semiconductor pattern of a thin-film transistor according to some embodiments;

[0025] Figure 6 is a structural diagram of the semiconductor pattern and the second conductive layer of a thin-film transistor according to some embodiments;

[0026] Figure 7 is another planar structure diagram of the array substrate according to some embodiments;

[0027] Figure 8 is a cross-sectional view along section line BB in Figure 7;

[0028] Figure 9 is a structural diagram of the second via and the first via according to some embodiments;

[0029] Figure 10 is a structural diagram of the third via and the second via according to some embodiments;

[0030] Figure 11 is a planar structural diagram of an array substrate according to some embodiments;

[0031] Figure 12 is a structural diagram of a second conductive pattern and a third conductive pattern according to some embodiments;

[0032] Figure 13 is a structural diagram of the third conductive layer according to some embodiments;

[0033] Figure 14 is a cross-sectional structural diagram of an array substrate according to some embodiments;

[0034] Figure 15 is a structural diagram of the third conductive layer and the pixel electrode layer according to some embodiments;

[0035] Figure 16 is another planar structure diagram of an array substrate according to some embodiments. Detailed Implementation

[0036] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0037] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0038] In this disclosure, terms such as “down,” “below,” “above,” and “up” are used to explain the relationships between components shown in the accompanying drawings. The terms may be relative concepts and described based on the directions shown in the drawings, or based on the sequence of process steps, but are not limited thereto.

[0039] The term "relative" means that the first element can be directly or indirectly relative to the second element. In the case where the third element is between the first and second elements, although they are still relative to each other, the first and second elements can be understood as being indirectly relative to each other.

[0040] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0041] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium.

[0042] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0043] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0044] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0045] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0046] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0047] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0048] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0049] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0050] Embodiments of this disclosure provide a display device, wherein the display device 1000 is a product having an image display function. Exemplarily, the display device 1000 may be any device that displays either moving (e.g., video) or fixed (e.g., still image) content, and whether it is text or an image.

[0051] For example, the display device 1000 can be any product or component with display function, such as electronic paper, television, laptop computer, tablet computer, personal digital assistant (PDA), mobile phone, watch, clock, calculator, GPS receiver / navigator, camera, display of camera view (e.g., display of rearview camera in vehicle), wearable device, augmented reality (AR) device, virtual reality (VR) device, mixed reality (MR) device, in-vehicle display, flying display, etc.

[0052] In some embodiments, from the perspective of the light emission type of the display device 1000, the display device 1000 may be a liquid crystal display (LCD) or an electrophoretic display device. In one example, the display device provided in the embodiments of this disclosure may be an electrophoretic display device, for example, the display device may be electronic paper.

[0053] In some embodiments, referring to FIG1, the display device 1000 includes an electronic paper display panel 1100 and a driving circuit board (not shown in the figure). The driving circuit board may include, for example, a timing controller (TCON), a power management chip (DC / DC), and an adjustable resistor voltage divider circuit (generating Vcom), etc. Of course, the driving circuit board may also include other circuit structures, which will not be listed here. The driving circuit board is electrically connected to the electronic paper display panel 1100 and is used to transmit control signals to the electronic paper display panel 1100 to drive the electronic paper display panel 1100 to achieve image display. In addition, the display device 1000 may also include, but is not limited to, a touch structure, enabling the display device 1000 to realize touch and other functions, which will not be listed here.

[0054] In some embodiments, the electronic paper display panel 1100 may include an array substrate 100.

[0055] Referring, exemplarily, continuing to refer to FIG1, when the display device 1000 is an electrophoretic display device, the electronic paper display panel 1100 may include an array substrate 100, a cover plate 200 disposed opposite to the array substrate 100, and an electrophoretic layer 300 located between the array substrate 100 and the cover plate 200. Alternatively, exemplarily, when the display device 1000 is a liquid crystal display device, the electronic paper display panel 1100 may include an array substrate and a color filter substrate disposed opposite to each other, and a liquid crystal layer located between the array substrate and the color filter substrate. The embodiments of this disclosure will now be described exemplarily using an electrophoretic display device as an example. As shown in FIG1, the array substrate 100 may include a substrate 101 and a pixel electrode 41 disposed on the substrate 101, the pixel electrode 41 being disposed toward the cover plate 200. The cover plate 200 may include a substrate 201 and a common electrode 202 disposed on the substrate 201, the common electrode 202 being disposed toward the array substrate 100. The pixel electrode 41 and the common electrode 202 are at least partially disposed opposite to each other. The electrophoretic layer 300 may include multiple electrophoretic capsules 301. Each electrophoretic capsule 301 may include a capsule body, an electrophoretic liquid, and charged particles located within the capsule body. The charged particles may include at least two of black particles, white particles, and colored particles. The colored particles include, but are not limited to, yellow particles, cyan particles, red particles, blue particles, and gray particles. When a voltage is applied to the pixel electrode 41 in the array substrate 100, a voltage difference is formed between the pixel electrode 41 and the common electrode 202. Under the action of this voltage difference, the charged particles in the electrophoretic capsules 301 will move in the electrophoretic liquid to realize the display of the electronic paper.

[0056] For example, when a positive voltage is applied to the common electrode 202 and a negative voltage is applied to the pixel electrode 41, an electric field is generated between the common electrode 202 and the pixel electrode 41. Under the influence of this electric field, white particles accumulate on the side of the common electrode 202 (the side of the cover plate 200), while black particles accumulate on the side of the pixel electrode 41 (the side of the array substrate 100). At this time, under the reflection of natural light, the electronic paper display panel displays a white image. Conversely, when a negative voltage is applied to the common electrode 202 and a positive voltage is applied to the pixel electrode 41, black particles accumulate on the side of the common electrode 202 (the side of the cover plate 200), while white particles accumulate on the side of the pixel electrode 41 (the side of the array substrate 100). At this time, under the reflection of natural light, the electronic paper display panel displays a black image. Thus, the electronic paper display panel can perform different controls on each sub-pixel to achieve the display of text and images.

[0057] In some embodiments, at least one of the white and black particles in each display unit (subpixel) can be replaced with other reflective particles of different colors. For example, the white particles can be replaced with particles that can reflect various colors such as red, green, and blue, thereby enabling the electronic paper display to achieve color display under the above control.

[0058] The array substrate may also include data lines and thin-film transistors (TFTs). The data lines are electrically connected to one of the source and drain terminals of the TFTs. The TFTs can control the conduction or cutoff between the data lines and the pixel electrodes to control the transmission of data signals from the data lines to the pixel electrodes. In related technologies, TFTs typically employ a bottom-gate structure, meaning the gate of the TFT is located below the semiconductor layer. In this case, the gate of the TFT usually has a portion opposite to the source and drain, and the gate forms parasitic capacitances with the source and drain, respectively. As electronic paper display panels develop towards higher PPI, the number of sub-pixels on the array substrate increases, and the total parasitic capacitance formed between the data lines and the TFTs (one of the source and drain) also increases, resulting in a higher load on the data lines. This is detrimental to data signal transmission on the data lines and also hinders the reduction of power consumption of the array substrate. Furthermore, as electronic paper display panels develop towards higher PPI, the area of ​​each sub-pixel (including but not limited to pixel electrodes and common electrodes) on the array substrate 100 is becoming smaller. Correspondingly, the capacitance of the storage capacitor formed by the pixel electrodes and other conductive structures on the array substrate is also decreasing, which is detrimental to maintaining the voltage on the pixel electrodes. At lower refresh rates, the voltage on the pixel electrodes may decay, causing changes in the position of charged particles in the electrophoretic capsule 301, thereby affecting the display quality of the electronic paper display panel. To drive electronic paper for full-color display, a higher driving voltage is required, such as VGH≥28V, VGL≤-28V.

[0059] To address at least one of the aforementioned technical problems, referring to Figures 2, 3, and 4, embodiments of this disclosure provide an array substrate 100. The array substrate 100 includes a substrate 101, a first conductive layer 10, a semiconductor layer 50, a second conductive layer 20, a pixel electrode layer 40, and a thin-film transistor T. The first conductive layer 10 is located on one side of the substrate 101, the semiconductor layer 50 is located on the side of the first conductive layer 10 away from the substrate 101, the second conductive layer 20 is located on the side of the semiconductor layer 50 away from the substrate 101, and the pixel electrode layer 40 is located on the side of the second conductive layer 20 away from the substrate 101. That is, the first conductive layer 10, the semiconductor layer 50, the second conductive layer 20, and the pixel electrode layer 40 are sequentially arranged along a direction away from the substrate 101.

[0060] Referring to Figure 4, the first conductive layer 10 includes multiple first signal lines 11 and multiple first conductive patterns 12 (only one first signal line 11 and one first conductive pattern 12 are shown exemplary in Figure 4). Exemplarily, the first signal lines 11 can be data signal lines, in which case the first signal lines 11 can be configured to transmit data signals. Exemplarily, there is a gap between the first signal lines 11 and the first conductive patterns 12. The multiple first signal lines 11 can be distributed at intervals along a first direction X, and all the multiple first signal lines 11 extend along a second direction Y, where the first direction X intersects the second direction Y; for example, the first direction X and the second direction Y are perpendicular to each other.

[0061] Referring again to Figures 3 and 4, the semiconductor layer 50 includes a plurality of semiconductor patterns 51. The material of the semiconductor layer 50 may include polycrystalline silicon, amorphous silicon, and oxide semiconductors; embodiments of this disclosure do not specifically limit the material of the semiconductor layer 50. Furthermore, the semiconductor patterns 51 may include a channel structure 511 and a first portion 512 and a second portion 513 located on both sides of the channel structure 511. The channel structure 511 refers to the undoped portion of the semiconductor pattern 51 used to form a channel for a thin-film transistor T, which retains semiconductor properties. The first portion 512 and the second portion 513 refer to two portions separated by the channel structure 511, and the first portion 512 and the second portion 513 can be used to form the source region and drain region of the thin-film transistor T, respectively. Furthermore, at least a portion of the first portion 512 and at least a portion of the second portion 513 may undergo a conductor-forming process to form a conductor, thereby reducing the resistance of the first and second portions. The conductor-enhancing process can be achieved by injecting plasma (such as plasma containing at least one of the elements selected from helium, oxygen, nitrogen, chlorine, hydrogen, boron, and phosphorus) into the semiconductor material using dry etching equipment or ion implantation equipment, or by using ion doping process to dope any one or more of the above elements into the semiconductor material to achieve conductor-enhancing.

[0062] For example, the material of the semiconductor layer 50 may include metal oxide materials and / or metal oxide nitride materials. The metal oxide materials include, but are not limited to, one or more of the following: indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium-free metal oxide (In-free OS), rare earth doped oxide (Ln-OS), zinc oxide (ZnO), gallium oxide (GaO), indium oxide (InO), HfInZnO (HIZO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, and Cd-Sn-O.

[0063] Metallic nitride materials include, but are not limited to, zinc nitride, indium nitride, gallium nitride, tin nitride, cadmium nitride, aluminum nitride, germanium nitride, titanium nitride, silicon nitride, or combinations thereof.

[0064] The material of the semiconductor layer 50 can be amorphous, partially crystalline, single-crystal or polycrystalline, and can also be a single-layer or multi-layer structure.

[0065] In some embodiments, referring to FIG3 and FIG4, the first conductive layer 10 may further include a light-shielding pattern 13. The orthographic projection of the light-shielding pattern 13 on the substrate 101 can cover the orthographic projection of the channel structure 511 on the substrate 101. In this way, the light-shielding pattern 13 can block the light emitted from one side of the substrate 101 to the channel structure 511, reducing the risk of light leakage current generated by the thin film transistor T.

[0066] Referring again to Figures 3 and 4, the second conductive layer 20 includes multiple second signal lines 21, a gate 22 electrically connected to the second signal lines 21, a first electrode 23, a second electrode 24, and a second conductive pattern 25. The multiple second signal lines 21 can be spaced apart along two directions Y, and all of the multiple second signal lines 21 extend along a first direction X. The second signal lines 21 can be scan signal lines. The first electrode 23 is electrically connected to the first signal line 11 and the first part 512, respectively, and the second electrode 24 is electrically connected to the first conductive pattern 12 and the second part 513, respectively. In some embodiments, the light-shielding pattern 13 can be in a floating state, or it can be electrically connected to the second signal line 21 or the gate 22. When the light-shielding pattern 13 is in a floating state, and when the thin-film transistor T is operating, the light-shielding pattern 13 has no electrical signal. When the light-shielding pattern 13 is electrically connected to the second signal line 21 or the gate 22, and when the thin-film transistor T is operating, the voltage on the light-shielding pattern 13 is the same as the voltage on the second signal line 21.

[0067] The thin-film transistor T includes a gate 22, a semiconductor pattern 51, a first electrode 23, and a second electrode 24. That is, the thin-film transistor T can form a top-gate transistor. Moreover, the first electrode 23, the second signal line 21, and the gate 22 are all located in the same film layer. There are gaps between the first electrode 23 and the gate 22, and between the first electrode 23 and the second signal line 21. The orthographic projections of the first electrode 23 and the gate 22 on the substrate 101, and the orthographic projections of the first electrode 23 and the second signal line 21 on the substrate 101 do not coincide. Therefore, the parasitic capacitance formed between the first electrode 23 and the gate 22, and between the first electrode 23 and the second signal line 21, can be reduced. The first signal line 11 is connected to the first electrode 23, which can further reduce the parasitic capacitance formed between the first signal line 11 and the second signal line 21 and the gate 22, reduce the load on the first signal line 11, thereby facilitating the transmission of data signals on the first signal line 11 and reducing the power consumption of the array substrate.

[0068] As shown in Figures 2 and 3, the orthographic projection of the second conductive pattern 25 on the substrate 101 at least partially overlaps with the orthographic projection of the first conductive pattern 12 on the substrate 101, and a first capacitor is formed between the second conductive pattern 25 and the first conductive pattern 12. The pixel electrode layer 40 includes a pixel electrode 41, which is electrically connected to the second electrode 24. In the case that the array substrate 100 does not include other conductive layers, the pixel electrode 41 can also form a third capacitor with the second conductive pattern 25. The voltage on the pixel electrode 41 is the same as that on the first conductive pattern 12. In this way, the first capacitor and the third capacitor are connected in parallel, which helps to increase the total capacitance of the storage capacitor (including the first capacitor and the third capacitor) formed by the pixel electrode 41, thereby improving the voltage holding capability on the pixel electrode 41, ensuring that the position of the charged particles in the electrophoretic capsule 301 remains relatively stable within one frame, and thus improving the display quality of the electronic paper display panel.

[0069] In some embodiments, the array substrate 100 further includes an insulating layer located between adjacent conductive layers to prevent short circuits between adjacent conductive layers. Referring to FIG3, the array substrate 100 may further include a third insulating layer 61, a gate insulating layer 62, a first insulating layer 63, and a planarization layer 64. The third insulating layer 61 is located between the first conductive layer 10 and the semiconductor layer 50, the gate insulating layer 62 is located between the semiconductor layer 50 and the second conductive layer 20, and the first insulating layer 63 and the planarization layer 64 are located between the second conductive layer 20 and the pixel electrode layer 40. The planarization layer 64 is located between the first insulating layer 63 and the pixel electrode layer 40, that is, the first insulating layer 63 is closer to the substrate 101 than the planarization layer 64.

[0070] The array substrate 100 may further include a sixth via V6 and a seventh via V7. The sixth via V6 penetrates at least the third insulating layer 61. For example, the sixth via V6 sequentially penetrates the gate insulating layer 62 and the third insulating layer 61, and exposes a portion of the first signal line 11. The first electrode 23 is at least partially located within the sixth via V6, and the first electrode 23 is electrically connected to the first signal line 11 through the sixth via V6. The seventh via V7 penetrates at least the third insulating layer 61. For example, the seventh via V7 sequentially penetrates the gate insulating layer 62 and the third insulating layer 61, and exposes a portion of the first conductive pattern 12. The second electrode 24 is at least partially located within the seventh via V7, and is electrically connected to the first conductive pattern 12 and the semiconductor pattern 51 through the seventh via V7.

[0071] In some embodiments, referring to Figures 4 and 5, the orthographic projection of the first part 512 on the substrate 101 partially overlaps with the orthographic projection of the first signal line 11 on the substrate 101, and the portion of the first part 512 and the first signal line 11 overlapping on the substrate 101 has a dimension D1 greater than or equal to 2 μm along the first target direction M1. That is, the width D1 of the overlapping portion of the first part 512 and the first signal line 11 on the substrate 101 is greater than or equal to 2 μm. This avoids the formation of a deep hole in the sixth via V6 between the first part 512 and the first signal line 11, reducing the risk of the first electrode 23 breaking at the sidewall of the sixth via V6. Exemplarily, D1 can be 2 μm, 2.5 μm, 3 μm, or 4 μm, etc., and the embodiments of this disclosure will not list them all.

[0072] In this case, the first target direction M1 is perpendicular to the edge of the first part 512 near the first signal line 11. For example, as shown in FIG5, when the semiconductor pattern 51 extends along the first direction X, the edge of the first part 512 near the first signal line 11 extends along the second direction Y, and the first target direction M1 intersects or is perpendicular to the second direction Y. At this time, the first target direction M1 is also parallel to the first direction X.

[0073] Referring again to Figures 4 and 5, the orthographic projection of the second part 513 on the substrate 101 partially overlaps with the orthographic projection of the first conductive pattern 12 on the substrate 101, and the dimension D2 of the overlapping portion of the second part 513 and the first conductive pattern 12 on the substrate 101 along the second target direction M2 is greater than or equal to 2 μm. That is, the width D2 of the overlapping portion of the second part 513 and the first conductive pattern 12 on the substrate 101 is greater than or equal to 2 μm. This avoids the formation of a deep hole in the seventh via V7 between the second part 513 and the first conductive pattern 12, reducing the risk of the second electrode 24 breaking at the sidewall of the seventh via V7. Exemplarily, D2 can be 2 μm, 3 μm, 3.5 μm, or 4 μm, etc., and the embodiments of this disclosure will not list them all.

[0074] In this case, the second target direction M2 is perpendicular to the edge of the second part 513 near the first conductive pattern 12. For example, as shown in FIG5, when the semiconductor pattern 51 extends along the first direction X, the second part 513 extends along the second direction Y near the edge of the first conductive pattern 12, and the second target direction M2 intersects or is perpendicular to the second direction Y. At this time, the second target direction M2 is also parallel to the first direction X.

[0075] In some embodiments, referring to FIG5, the portion of the first signal line 11 exposed by the sixth via V6 has a dimension D3 greater than or equal to 3 μm along the first target direction M1. This is beneficial for increasing the contact area between the first electrode 23 and the first signal line 11, and reducing the contact resistance between the first electrode 23 and the first signal line 11. Exemplarily, the dimension D3 of the portion of the first signal line 11 exposed by the sixth via V6 along the first target direction M1 can be 3 μm, 3.5 μm, 4 μm, or 5 μm, etc., and the embodiments of this disclosure will not be listed one by one.

[0076] Referring again to Figure 5, the portion of the first conductive pattern 12 exposed by the seventh via V7 has a dimension D4 greater than or equal to 3 μm along the second target direction M2. This helps to increase the contact area between the second electrode 24 and the first conductive pattern 12, and reduce the contact resistance between the second electrode 24 and the first conductive pattern 12. Exemplarily, the portion D4 of the first conductive pattern 12 exposed by the seventh via V7 along the second target direction M2 can be 3 μm, 3.5 μm, 4 μm, 4.5 μm, or 5 μm, etc., and the embodiments of this disclosure will not be listed one by one.

[0077] In some embodiments, referring to FIG6, the dimension D5 of the portion of the first electrode 23 that contacts the first part 512 along the first target direction M1 is greater than or equal to 4 μm. This helps to increase the contact area between the first electrode 23 and the first part 512, ensuring that the first electrode 23 and the first part 512 can overlap. Exemplarily, the dimension D5 of the portion of the first electrode 23 that contacts the first part 512 along the first target direction M1 can be 4 μm, 4.5 μm, 5 μm, or 6 μm, etc., and the embodiments of this disclosure will not be exemplified one by one.

[0078] Referring again to Figure 6, the dimension D6 of the portion of the second electrode 24 that contacts the second part 513 along the second target direction M2 is greater than or equal to 4 μm. This helps to increase the contact area between the second electrode 24 and the second part 513, ensuring that the second electrode 24 and the second part 513 can overlap. For example, the dimension D6 of the portion of the second electrode 24 that contacts the second part 513 along the second target direction M2 can be 4 μm, 5 μm, 5.5 μm, or 6 μm, etc., and the embodiments of this disclosure will not be exemplified one by one.

[0079] In some embodiments, referring to Figures 7 and 8, the array substrate 100 further includes a third conductive layer 30, which is located between the second conductive layer 20 and the pixel electrode layer 40. The third conductive layer 30 includes a third conductive pattern 31, the orthographic projection of the third conductive pattern 31 on the substrate 101 at least partially coincides with the orthographic projection of the pixel electrode 41 on the substrate 101, and forms a second capacitor between the third conductive pattern 31 and the pixel electrode 41. The interval between the pixel electrode 41 and the third conductive pattern 31 is smaller than the interval between the pixel electrode 41 and the second conductive pattern 25. Thus, the capacitance value of the second capacitor formed between the pixel electrode 41 and the third conductive pattern 31 can be greater than the capacitance value of the third capacitor formed between the pixel electrode 41 and the second conductive pattern 25. By setting the third conductive layer 30 and the third conductive pattern 31, it is beneficial to increase the total capacitance value of the storage capacitor (first capacitor and second capacitor) formed by the pixel electrode 41, which is beneficial to further improve the voltage holding capability on the pixel electrode 41, ensure that the position of the charged particles in the electrophoretic capsule 301 remains relatively stable within one frame, and improve the display quality of the electronic paper display panel.

[0080] In some embodiments, referring to Figures 7 and 8, the third conductive layer 30 further includes a transition block 32, which is electrically connected to both the second electrode 24 and the pixel electrode 41. That is, the pixel electrode 41 is electrically connected to the second electrode 24 via the transition block 32. Compared to the pixel electrode 41 being directly electrically connected to the second electrode 24, providing the transition block 32 can reduce the depth of the connection via between the pixel electrode 41 and the second conductive pattern 25, thereby reducing the difficulty of connecting the pixel electrode 41 and the second conductive pattern 25 and reducing the risk of a short circuit at the connection via between the pixel electrode 41 and the second conductive pattern 25.

[0081] As shown in Figures 7 and 8, the array substrate further includes a first conductive layer 10, a semiconductor layer 50, and a second conductive layer 20. The structure of the first conductive layer 10, the semiconductor layer 50, and the second conductive layer 20 is the same as that of the first conductive layer 10, the semiconductor layer 50, and the second conductive layer 20 in the embodiments shown in Figures 2 and 3, and will not be described again here.

[0082] In some embodiments, at least two of the first conductive layer 10, the second conductive layer 20, the third conductive layer 30, and the pixel electrode layer 40 are made of a metallic conductive material. The metallic conductive material has a low resistance and is advantageous for reducing the thickness of the at least two conductive layers made of metallic conductive material.

[0083] The aforementioned conductive metallic materials may include one or more of titanium, aluminum, copper, molybdenum, niobium, nickel, and their alloys, or the conductive metallic materials may also be metallic multilayer structures. Exemplarily, the metallic multilayer structures may be titanium-aluminum-titanium (Ti / Al / Ti) multilayer structures, molybdenum-aluminum (Mo / Al) multilayer structures, molybdenum-aluminum-molybdenum (Mo / Al / Mo) multilayer structures, molybdenum-niobium-titanium (MoNb / Ti) multilayer structures, molybdenum-niobium-titanium-copper (MoNb / Ti / Cu) multilayer structures, molybdenum-niobium-copper (MoNb / Cu) multilayer structures, molybdenum-nickel-titanium-copper (MTD / Cu) multilayer structures, and molybdenum-niobium-copper-molybdenum-titanium-nickel (MoNb) multilayer structures. The following are some of the following stacked structures: (Cu / MTD) stacked structure, (MTD / Cu / MTD) stacked structure, (MoTi / Cu) stacked structure, (MoTi / Cu / MTD) stacked structure, (MoTi / Cu / MTD) stacked structure, (MoTi / Cu / MoTi) stacked structure, (MoTi / Cu / MoTi) stacked structure, (MoNb-Copper-MoNb) stacked structure, and (AlNb-MoNd) stacked structure, or combinations thereof.

[0084] In one embodiment, the materials of the first conductive layer 10 and the second conductive layer 20 may include metallic conductive materials, which is beneficial for reducing the resistivity of the first conductive layer 10 and the second conductive layer 20, and thus for reducing the resistance and linewidth of the first signal line 11 and the second signal line 21. The metallic conductive materials are described above and will not be repeated here.

[0085] The material of the third conductive layer 30 may include a metallic conductive material or a transparent conductive material. For example, the material of the third conductive layer 30 may include the aforementioned metallic conductive material.

[0086] When the material of the first conductive layer 10 includes a metallic conductive material, the thickness of the first conductive layer 10 can be [missing information]. For example, when the material of the first conductive layer 10 includes a single metal material, the thickness of the first conductive layer 10 can be [missing information]. When the material of the first conductive layer 10 is a metal stack structure, the total thickness of each stack of the first conductive layer 10 can be... For example, the thickness of the first conductive layer 10 can be or For example, the thickness of the first conductive layer 10 can be or And so on, which will not be listed one by one here.

[0087] Similar to the first conductive layer 10, when the materials of the second conductive layer 20 and the third conductive layer 30 include metallic conductive materials, the thickness of the second conductive layer 20 can be [missing information]. And / or, the thickness of the third conductive layer 30 can be For example, the thickness of the second conductive layer 20 can be or The thickness of the third conductive layer 30 can be... or And so on, which will not be listed one by one here.

[0088] The pixel electrode layer 40 is made of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO). These transparent conductive materials exhibit good stability and are not prone to oxidation, which helps to improve the stability of the pixel electrode layer 40.

[0089] When the material of the pixel electrode layer 40 includes a transparent conductive material (such as ITO), the thickness of the pixel electrode layer 40 can be For example, the thickness of the pixel electrode layer 40 can be or For example, the thickness of the pixel electrode layer 40 can be or

[0090] The array substrate 100 also includes an insulating layer located between adjacent conductive layers. Referring to FIG5, the array substrate 100 may further include a third insulating layer 61, a gate insulating layer 62, a first insulating layer 63, a planarization layer 64, and a second insulating layer 65. The third insulating layer 61 is located between the first conductive layer 10 and the semiconductor layer 50, the gate insulating layer 62 is located between the semiconductor layer 50 and the second conductive layer 20, the first insulating layer 63 and the planarization layer 64 are located between the second conductive layer 20 and the pixel electrode layer 40, and the planarization layer 64 is located between the first insulating layer 63 and the pixel electrode layer 40, that is, the first insulating layer 63 is closer to the substrate 101 than the planarization layer 64, and the second insulating layer 65 is located between the third conductive layer 30 and the pixel electrode layer 40.

[0091] In some embodiments, referring to Figures 8 and 9, the array substrate 100 further includes a first via V1, a second via V2, and a third via V3. The first via V1 penetrates the first insulating layer 63 and exposes at least a portion of the second electrode 24. The second via V2 penetrates the planarization layer 64 and exposes at least a portion of the first via V1, thus also exposing at least a portion of the second electrode 24. The adapter block 32 is electrically connected to the second conductive pattern 25 sequentially through the second via V2 and the first via V1. The third via V3 penetrates the second insulating layer 65, and the pixel electrode 41 can be electrically connected to the adapter block 32 through the third via V3.

[0092] In some embodiments, the orthographic projection of the second via V2 on the substrate 101 covers the orthographic projection of the first via V1 on the substrate 101, and the second via V2 and the first via V1 form a via. Referring to Figures 8 and 10, the orthographic projection of the third via V3 on the substrate 101 at least partially overlaps with the orthographic projection of the second via V2 on the substrate 101. This helps to reduce the area occupied by the third via V3 and the second via V2, thereby providing more space for the pixel electrode 41 and the third conductive pattern 31. That is, it helps to increase the area of ​​the pixel electrode 41 and the third conductive pattern 31, thereby increasing the capacitance of the second capacitor formed between the pixel electrode 41 and the third conductive pattern 31, and increasing the total capacitance of the storage capacitor (including the first capacitor and the third capacitor) formed by the pixel electrode 41.

[0093] In some embodiments, the orthogonal projection of the third conductive pattern 31 onto the substrate 101 can cover the orthogonal projection of the channel structure 511 onto the substrate 101. In this way, the third conductive pattern 31 can shield the semiconductor pattern 51, reduce the impact of the voltage on the pixel electrode 41 on the switching characteristics of the thin film transistor T, and thereby reduce the risk of leakage current in the thin film transistor T.

[0094] In some embodiments, referring to Figures 11 and 12, the second conductive layer 20 further includes a first connecting line 26. The first connecting line 26 is located between two adjacent second conductive patterns 25 along the first direction X and is electrically connected to the two second conductive patterns 25. Thus, applying a voltage signal to one of the second conductive patterns 25 or to one of the first connecting lines 26 allows the same voltage signal to be applied to a row of second conductive patterns 25 simultaneously, which is beneficial for transmitting voltage signals to the second conductive patterns 25. The first direction is the extension direction of the second signal line 21.

[0095] For example, the array substrate 100 includes a display area AA and a peripheral area BB surrounding the display area AA. A first connecting line 26 is provided between any two adjacent second conductive patterns 25 along the first direction X. In this way, a row of second conductive patterns 25 can be interconnected into a whole through the first connecting line 26 (hereinafter referred to as the first capacitor plate). For example, if the first capacitor plate extends along the first direction X to the peripheral area BB of the array substrate 100, applying a voltage signal to the first capacitor plate in the peripheral area BB will apply the same voltage signal to all the second conductive patterns 25 in that row, thereby facilitating the transmission of voltage signals to the second conductive patterns 25 located in the display area AA.

[0096] Referring to Figures 12 and 13, the third conductive layer 30 further includes a second connecting line 33. The second connecting line 33 is located between two adjacent third conductive patterns 31 along the second direction Y and is electrically connected to the two third conductive patterns 31. In this way, applying a voltage signal to one of the third conductive patterns 31 or to one of the second connecting lines 33 can simultaneously apply the same voltage signal to a row of third conductive patterns 31, which is beneficial for transmitting voltage signals to the third conductive patterns 31. Here, the second direction is the extension direction of the first signal line 11.

[0097] For example, a second connecting line 33 is provided between any two adjacent third conductive patterns 31 along the second direction Y. In this way, a column of third conductive patterns 31 can be connected to each other as a whole (hereinafter referred to as the second capacitor plate) through the second connecting line 33. For example, the second capacitor plate extends along the second direction Y to the peripheral area BB of the array substrate. Only one voltage signal needs to be applied to the second capacitor plate in the peripheral area BB to apply the same voltage signal to all the third conductive patterns 31 in the column, which is beneficial to transmitting voltage signals to the third conductive patterns 31 located in the display area AA.

[0098] In some embodiments, referring to Figures 8 and 12, the second conductive pattern 25 and the third conductive pattern 31 are configured to transmit the same voltage signal, and the second conductive pattern 25 and the third conductive pattern 31 are electrically connected in the peripheral area BB. Exemplarily, in the display area AA, the second conductive pattern 25 and the third conductive pattern 31 are not connected. For example, no vias for connecting the second conductive pattern 25 and the third conductive pattern 31 are provided in the first insulating layer 63 and the planarization layer 64. The second conductive pattern 25 and the third conductive pattern 31 are only electrically connected in the peripheral area BB. This improves the flatness of the third conductive pattern 31 and the pixel electrode 41 in the display area AA, and improves the uniformity of the electric field formed between the pixel electrode 41 and the common electrode, thereby improving the display quality of the electronic paper display panel.

[0099] For example, as shown in FIG12, the peripheral area BB may include a signal bus 102. The signal bus 102 is at least partially arranged around the display area AA (e.g., completely around the display area AA). The first capacitor plate formed by the second conductive pattern 25 and the first connecting line 26 is electrically connected to the signal bus 102 at both ends along the first direction X. The second capacitor plate formed by the third conductive pattern 31 and the second connecting line 33 is electrically connected to the signal bus 102 at both ends along the second direction Y. In this way, the first capacitor plate and the second capacitor plate are arranged in parallel, which helps to reduce the voltage drop on the first capacitor plate and the second capacitor plate and improve the voltage uniformity of the second conductive pattern 25 and the third conductive pattern 31 at different positions. Moreover, in the embodiments of this disclosure, the extension directions of the first capacitor plate and the second capacitor plate intersect each other. The orthographic projection of the first capacitor plate on the substrate 101 and the orthographic projection of the second capacitor plate on the substrate 101 intersect each other to form a mesh structure, which helps to improve the voltage uniformity of the second conductive pattern 25 and the third conductive pattern 31.

[0100] In some embodiments, referring to FIG14, the array substrate 100 further includes a first insulating layer 63 and a planarization layer 64. The positions of the first insulating layer 63 and the planarization layer 64 are described above and will not be repeated here. The array substrate 100 may also include a fourth via V4 and a fifth via V5. The fourth via V4 penetrates the first insulating layer 63 and exposes at least a portion of the second conductive pattern 25. The fifth via V5 penetrates the planarization layer 64 and exposes at least a portion of the fourth via V4. The third conductive pattern 31 is electrically connected to the second conductive pattern 25 through the fifth via V5 and the fourth via V1, thereby further improving the voltage uniformity of the second conductive pattern 25 and the third conductive pattern 31.

[0101] In some embodiments, referring to FIG11, the array substrate 100 may include a plurality of sub-pixels P arranged in an array. Each sub-pixel P includes a thin-film transistor T and a pixel electrode 41 electrically connected to the thin-film transistor T. In addition, the sub-pixel P may also include a first conductive pattern 12 electrically connected to the thin-film transistor T. The plurality of sub-pixels P are arranged in rows along a first direction X and in columns along a second direction Y.

[0102] In some embodiments, referring to FIG11, multiple second signal lines 21 are arranged at intervals along the second direction Y, and two rows of sub-pixels P are included between two adjacent second signal lines 21. One second signal line 21 is electrically connected to the thin-film transistors T of the two adjacent rows of sub-pixels P along the second direction Y; that is, two adjacent rows of sub-pixels P share one second signal line 21. As the PPI of the display panel increases, the number of rows of sub-pixels P on the array substrate 100 increases. Sharing one second signal line 21 between two adjacent rows of sub-pixels P is beneficial to increasing the time length for the second signal line 21 to output the scan signal within one frame, thereby increasing the conduction time of the thin-film transistors T of the sub-pixels P. This is beneficial to fully writing the data signal on the first signal line 11 into the pixel electrode 41, improving the charging effect of the pixel electrode 41, and improving the display quality of the electronic paper display panel.

[0103] Referring again to Figure 12, two first signal lines 11 are included between two adjacent columns of sub-pixels P, or in other words, two first signal lines 11 are provided for each column of sub-pixels P. The two thin-film transistors T of two adjacent sub-pixels P along the second direction Y are electrically connected to the two first signal lines 11 located adjacent to each other along the first direction X of the sub-pixels P, respectively. That is, two adjacent sub-pixels in a column are electrically connected to the two first signal lines 11 on both sides of that column. In this way, two thin-film transistors T in the same column, electrically connected to the same second signal line 21, can transmit data signals through the two first signal lines 11 respectively, allowing each sub-pixel P to be independently controlled.

[0104] In some embodiments, as shown in FIG11, the orthographic projection of the second conductive pattern 25 on the substrate 101 is located between the orthographic projections of two adjacent second signal lines 21 on the substrate 101, and coincides with the orthographic projections of the two first conductive patterns 12 on the substrate 101, forming a first capacitance with each of the two first conductive patterns 12. In this way, the size of the second conductive pattern 25 along the second direction Y can be increased, and compared to setting one second conductive pattern 25 for each sub-pixel P, the number of second conductive patterns 25 can be reduced by half, thereby reducing the number of first connecting lines 26, reducing the facing area between the second conductive layer 20 (first connecting lines 26) and the first signal line 11, reducing the parasitic capacitance formed between the first signal line 11 and the second conductive layer 20 (first connecting lines 26), which is beneficial to reducing the load on the first signal line 11.

[0105] Referring to Figures 13 and 15, the orthographic projection of the third conductive pattern 31 on the substrate 101 is located between the orthographic projections of two adjacent second signal lines 21 on the substrate 101, and coincides with the orthographic projection portions of the two pixel electrodes 41 on the substrate 101, forming second capacitors with the two pixel electrodes 41 respectively. In this way, the size of the third conductive pattern 31 along the second direction Y can be increased. Compared to setting one third conductive pattern 31 for each sub-pixel P, the number of third conductive patterns 31 can be reduced by half, which is beneficial to simplifying the pattern of the third conductive layer 30.

[0106] Referring again to FIG11, in some embodiments, two thin-film transistors T that are adjacent along the second direction Y and electrically connected to the same second signal line 21 are staggered along the first direction X. This facilitates the electrical connection of the two thin-film transistors T to the two first signal lines 11 on both sides. For example, as shown in FIG11, two thin-film transistors that are electrically connected to the second signal line 21 on the upper side and adjacent along the second direction Y are staggered in the first direction X. The thin-film transistor T on the upper side is electrically connected to the first signal line 11 on the left side, and the thin-film transistor T on the lower side is electrically connected to the first signal line 11 on the right side. In addition, the gates 22 of the two thin-film transistors T are completely staggered in the first direction X, and the semiconductor patterns 51 of the two thin-film transistors T are partially staggered.

[0107] In some embodiments, referring to FIG16, a plurality of second signal lines 21 are arranged at intervals along a second direction Y. A row of sub-pixels P is included between two adjacent rows of second signal lines 21, and a second signal line 21 is electrically connected to a thin-film transistor T of a row of sub-pixels P. A first signal line 11 is included between two adjacent columns of sub-pixels P, and a thin-film transistor P of a column of sub-pixels P is electrically connected to a first signal line 11. This helps to reduce the number of first signal lines 11 in the array substrate 100, thereby reducing the number of data signals output by the source driver chip, reducing the cost of the source driver chip, and reducing the manufacturing cost of the electronic paper display panel.

[0108] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An array substrate, comprising: Substrate; The first conductive layer, located on one side of the substrate, includes multiple first signal lines and a first conductive pattern; A semiconductor layer, located on the side of the first conductive layer away from the substrate, includes multiple semiconductor patterns; the semiconductor patterns include a channel structure and a first portion and a second portion located on both sides of the channel structure; The second conductive layer, located on the side of the semiconductor layer away from the substrate, includes multiple second signal lines, a gate electrically connected to the second signal lines, a first electrode, a second electrode, and a second conductive pattern; the first electrode is electrically connected to the first signal line and the first part, the second electrode is electrically connected to the first conductive pattern and the second part, and the orthographic projection of the second conductive pattern on the substrate at least partially overlaps with the orthographic projection of the first conductive pattern on the substrate, and a first capacitance is formed between the second conductive pattern and the first conductive pattern; A pixel electrode layer, located on the side of the second conductive layer away from the substrate, includes a pixel electrode, which is electrically connected to the second electrode. The array substrate further includes a thin-film transistor, which includes the gate, the semiconductor pattern, the first electrode, and the second electrode.

2. The array substrate according to claim 1, further comprising: A third conductive layer is located between the second conductive layer and the pixel electrode layer, and includes a third conductive pattern. The orthographic projection of the third conductive pattern on the substrate at least partially overlaps with the orthographic projection of the pixel electrode on the substrate, and forms a second capacitor between the third conductive pattern and the pixel electrode.

3. The array substrate according to claim 2, wherein, The third conductive layer further includes a transition block, which is electrically connected to the second electrode and the pixel electrode, respectively.

4. The array substrate according to claim 3, further comprising: A first insulating layer is located between the second conductive layer and the third conductive layer; A first via penetrates the first insulating layer and exposes at least a portion of the second conductive pattern; A planarization layer is located between the first insulating layer and the third conductive layer; A second via penetrates the planarization layer and exposes at least a portion of the first via; The second insulating layer is located between the third conductive layer and the pixel electrode layer; A third via penetrates the second insulating layer and exposes at least a portion of the adapter block; The adapter block is electrically connected to the second conductive pattern through the second via and the first via, and the pixel electrode is electrically connected to the adapter block through the third via.

5. The array substrate according to claim 4, wherein, The orthographic projection of the second via on the substrate covers the orthographic projection of the first via on the substrate; And / or, the orthographic projection of the third via on the substrate at least partially overlaps with the orthographic projection of the second via on the substrate.

6. The array substrate according to any one of claims 2 to 5, wherein, The second conductive layer further includes a first connecting line, which is located between two adjacent second conductive patterns along a first direction and is electrically connected to the two second conductive patterns; the first direction is the extension direction of the second signal line; The third conductive layer further includes a second connecting line, which is located between two adjacent third conductive patterns along a second direction and is electrically connected to the two third conductive patterns; the second direction is the extension direction of the first signal line. The array substrate includes a display area and a peripheral area surrounding the display area, the second conductive pattern and the third conductive pattern are configured to transmit the same voltage signal, and the second conductive pattern and the third conductive pattern are electrically connected in the peripheral area.

7. The array substrate according to any one of claims 2 to 6, further comprising: A first insulating layer is located between the second conductive layer and the third conductive layer; A fourth via penetrates the first insulating layer and exposes at least a portion of the second conductive pattern; A planarization layer is located between the second insulating layer and the third conductive layer; A fifth via penetrates the planarization layer and exposes at least a portion of the fourth via; The third conductive pattern is electrically connected to the second conductive pattern through the fifth via and the fourth via.

8. The array substrate according to any one of claims 1 to 7, wherein, The array substrate includes a plurality of sub-pixels arranged in an array. Each sub-pixel includes a thin-film transistor and a pixel electrode electrically connected to the thin-film transistor. The plurality of sub-pixels are arranged in a row along a first direction and in a column along a second direction. Multiple second signal lines are arranged at intervals along the second direction, and two rows of sub-pixels are included between two adjacent second signal lines. A second signal line is electrically connected to the thin-film transistors of two adjacent rows of sub-pixels along the second direction.

9. The array substrate according to claim 8, wherein, Two first signal lines are included between two adjacent columns of sub-pixels; The two thin-film transistors of two adjacent sub-pixels along the second direction are respectively electrically connected to two first signal lines located adjacent to the sub-pixels along the first direction.

10. The array substrate according to claim 8 or 9, wherein, The orthographic projection of the second conductive pattern on the substrate is located between the orthographic projections of two adjacent second signal lines on the substrate, and coincides with the orthographic projection portions of the two first conductive patterns on the substrate, forming the first capacitor with the two first conductive patterns respectively; And / or, The orthographic projection of the third conductive pattern on the substrate is located between the orthographic projections of two adjacent second signal lines on the substrate, and coincides with the orthographic projection portions of the two pixel electrodes on the substrate, forming the second capacitor with the two pixel electrodes respectively.

11. The array substrate according to any one of claims 8 to 10, wherein, Two thin-film transistors that are adjacent along the second direction and electrically connected to the same second signal line are staggered along the first direction.

12. The array substrate according to any one of claims 1 to 7, wherein, The array substrate includes a plurality of sub-pixels arranged in an array. Each sub-pixel includes a thin-film transistor and a pixel electrode electrically connected to the thin-film transistor. The plurality of sub-pixels are arranged in a row along a first direction and in a column along a second direction. Multiple second signal lines are arranged at intervals along the second direction, and a row of sub-pixels is included between two adjacent second signal lines. One second signal line is electrically connected to the thin-film transistor of the row of sub-pixels. A first signal line is included between two adjacent columns of the sub-pixels, and the thin-film transistor of one column of the sub-pixels is electrically connected to the first signal line.

13. The array substrate according to any one of claims 1 to 12, wherein, The orthographic projection of the first part on the substrate coincides with the orthographic projection of the first signal line on the substrate, and the portion of the orthographic projection of the first part on the substrate and the orthographic projection of the first signal line on the substrate that coincide with each other has a size greater than or equal to 2μm along the first target direction, and the first target direction is perpendicular to the edge of the first part near the first signal line. And / or, The orthographic projection of the second part on the substrate coincides with the orthographic projection of the first conductive pattern on the substrate, and the portion of the orthographic projection of the second part on the substrate and the orthographic projection of the first conductive pattern on the substrate that coincide with each other has a size greater than or equal to 2 μm along the second target direction; the second target direction is perpendicular to the edge of the semiconductor pattern near the first conductive pattern.

14. The array substrate according to claim 13, further comprising: A third insulating layer is located between the first conductive layer and the semiconductor layer; The sixth via penetrates at least the third insulating layer and exposes at least a portion of the first signal line; The seventh via penetrates at least the third insulating layer and exposes at least a portion of the first conductive pattern; Wherein, the portion of the first signal line exposed by the sixth via has a dimension greater than or equal to 3 μm along the first target direction; The portion of the first conductive pattern exposed by the seventh via has a dimension greater than or equal to 3 μm along the second target direction.

15. The array substrate according to claim 13 or 14, wherein, The portion of the first electrode that contacts the first part has a dimension greater than or equal to 4 μm along the first target direction; and / or, the portion of the second electrode that contacts the second part has a dimension greater than or equal to 4 μm along the second target direction.

16. An electronic paper display panel, comprising an array substrate as claimed in any one of claims 1 to 15.

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