Electrostatic protection device, display substrate and display device

Abstract

An electrostatic protection device, a display substrate and a display device. The electrostatic protection device comprises a transistor group (81), a diode group (82), and a trigger resistor (83). The transistor group (81) includes a plurality of transistors connected in parallel, and the diode group (82) includes a plurality of diodes connected in parallel. The trigger resistor (83) is arranged on one side of the transistor group (81) in a first direction, and the diode group (82) is arranged on one side of the transistor group (81) in a second direction. The electrostatic protection device further comprises a first P-type doped guard ring (91P). The first P-type doped guard ring (91P) is annular and is connected to a second power line. The transistor group (81) and the trigger resistor (83) are arranged in a space surrounded by the first P-type doped guard ring (91P).

Description

Electrostatic discharge protection device, display substrate and display device Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and in particular to an electrostatic discharge protection device, a display substrate, and a display device. Background Technology

[0002] Micro-OLED (Micro Organic Light-Emitting Diode) is a type of microdisplay that has emerged in recent years, with silicon-based OLED being one example. Silicon-based OLED is a novel display technology that combines semiconductor manufacturing processes with OLED display technology, using wafers as a substrate to fabricate OLED devices. Because it combines the advantages of both semiconductor manufacturing processes and OLED display technology, silicon-based OLED not only boasts a high pixel density (Pixels Per Inch, PPI), but also offers advantages such as high brightness, low power consumption, high response speed, wide color gamut, and high thermal stability. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] On one hand, this disclosure provides an electrostatic discharge (ESD) protection device, including a transistor group, a diode group, and a trigger resistor. The transistor group includes multiple transistors connected in parallel, and the diode group includes multiple diodes connected in parallel. The first terminal of each transistor and the first end of the trigger resistor are connected to a second power line. The second end of the trigger resistor is connected to the gate electrode of the transistor. The second terminal of each transistor and the first terminal of each diode are connected to a ground line. The second terminal of each diode is connected to a first power line. The trigger resistor is disposed on one side of the transistor group in a first direction, and the diode group is disposed on one side of the transistor group in a second direction, wherein the first direction and the second direction intersect. The ESD protection device further includes a first P-type doped protective ring. The first P-type doped protective ring is ring-shaped and connected to the second power line. The transistor group and the trigger resistor are disposed within the space surrounded by the first P-type doped protective ring.

[0005] In an exemplary embodiment, the first P-type doped guard ring includes at least a first doped sub-ring and a second doped sub-ring. The first doped sub-ring and the second doped sub-ring are ring-shaped. The second doped sub-ring is disposed on one side of the first doped sub-ring in the first direction and is connected to the first doped sub-ring. The transistor group is disposed within the space surrounded by the first doped sub-ring, and the trigger resistor is disposed within the space surrounded by the second doped sub-ring.

[0006] In an exemplary embodiment, the protective frame of the first doped sub-ring near the second doped sub-ring and the protective frame of the second doped sub-ring near the first doped sub-ring are the same protective frame.

[0007] In an exemplary embodiment, the plurality of transistors are arranged sequentially along the first direction, and at least one of the transistors includes at least a gate electrode, the gate electrode including at least a first sub-gate, a second sub-gate, and a sub-gate connecting strip; the first sub-gate and the second sub-gate are strip-shaped extending along the second direction and are spaced apart in the first direction, the sub-gate connecting strip is strip-shaped extending along the first direction and is connected to the ends of the first sub-gate and the second sub-gate on the opposite side of the second direction, forming an "n" shape; the first sub-gate or the second sub-gate has a sub-gate width, and there is a sub-gate spacing between the first sub-gate and the second sub-gate, the ratio of the sub-gate width to the sub-gate spacing is 0.2 to 0.3, and the sub-gate width and the sub-gate spacing are dimensions in the first direction.

[0008] In an exemplary embodiment, the transistor group further includes a gate connection line, the gate connection line being a straight line or a broken line extending along the first direction, the gate connection line being connected to the ends of the first sub-gate and the second sub-gate on the second direction side respectively, and the first sub-gate, the second sub-gate, the sub-gate connection strip and the gate connection line forming an annular hollow structure.

[0009] In an exemplary embodiment, in the second direction, the edge of the trigger resistor on the second direction side is flush with the gate connection line.

[0010] In an exemplary embodiment, the trigger resistor and the transistor group have a first device spacing, the ratio of the first device spacing to the sub-gate spacing is 1.0 to 2.0, and the first device spacing is the dimension in the first direction.

[0011] In an exemplary embodiment, a second device spacing is provided between the transistor group and the diode group, the second device spacing being greater than the first device spacing, and the second device spacing being a dimension in the second direction.

[0012] In an exemplary embodiment, the electrostatic discharge protection device further includes a first N-type doped protective ring, which is ring-shaped and connected to the first power line. The first P-type doped protective ring is disposed within the space surrounded by the first N-type doped protective ring.

[0013] In an exemplary embodiment, the electrostatic discharge protection device further includes a second P-type doped protective ring, which is ring-shaped, disposed on one side of the first P-type doped protective ring in the second direction, and connected to the grounding wire. The diode group is disposed within the space surrounded by the second P-type doped protective ring.

[0014] In an exemplary embodiment, the electrostatic discharge protection device further includes a second N-type doped protective ring, which is ring-shaped and connected to the first power line. The second P-type doped protective ring is disposed within the space surrounded by the second N-type doped protective ring.

[0015] In an exemplary embodiment, in the second direction, at least three protective frames are provided between the transistor group and the diode group, and the three protective frames are respectively a protective frame in the first P-type doped protective ring, a protective frame in the second P-type doped protective ring, and a protective frame in the second N-type doped protective ring.

[0016] In an exemplary embodiment, the electrostatic discharge protection device further includes a first N-type doped protective ring and a second N-type doped protective ring. The first N-type doped protective ring is ring-shaped and connected to the first power line. The first P-type doped protective ring is disposed within the space surrounded by the first N-type doped protective ring. The second N-type doped protective ring is ring-shaped and connected to the first power line. The second P-type doped protective ring is disposed within the space surrounded by the second N-type doped protective ring. The second N-type doped protective ring is disposed on one side of the first N-type doped protective ring in the second direction and is connected to the first N-type doped protective ring.

[0017] In an exemplary embodiment, the protective frame of the first N-type doped protective ring near the second N-type doped protective ring and the protective frame of the second N-type doped protective ring near the first N-type doped protective ring are the same protective frame.

[0018] In an exemplary embodiment, at least one of the diodes includes at least a first active region and a second active region; the first active region is in the shape of a strip extending along the first direction and is connected to the ground line, and a plurality of the first active regions form an n1*n2 first active array; the second active region is in the shape of a ring surrounding the first active region and is connected to the first power line, and a plurality of the second active regions form an n1*n2 second active array; at least one of the transistors includes at least m1 third active layers, the m1 third active layers are an interconnected integral structure, and m1, n1, and n2 are positive integers greater than 1.

[0019] In an exemplary embodiment, the annular second active region includes at least two first active frames and two second active frames. The first active frames are strip-shaped extending along the first direction, and the second active frames are strip-shaped extending along the second direction. The first active frames and the second active frames are connected in sequence. The plurality of first active frames include at least one first width frame and at least one second width frame. The first width frame has a first active width, and the second width frame has a second active width. The first active width is greater than the second active width, and the first active width and the second active width are dimensions in the second direction.

[0020] In an exemplary embodiment, the second active array has an array centerline, which is a straight line that bisects the second active array in the second direction and extends along the first direction; the orthographic projection of the first width frame on the plane of the electrostatic discharge device at least partially overlaps with the orthographic projection of the array centerline on the plane of the electrostatic discharge device, and the orthographic projection of the second width frame on the plane of the electrostatic discharge device does not overlap with the orthographic projection of the array centerline on the plane of the electrostatic discharge device.

[0021] On the other hand, embodiments of this disclosure provide a display substrate, including a display area and a non-display area; the display area includes a plurality of sub-pixels, at least one sub-pixel includes a pixel driving circuit and a light-emitting device connected to the pixel driving circuit, and the non-display area includes at least one of the aforementioned electrostatic discharge protection devices.

[0022] In another aspect, embodiments of this disclosure provide a display device including the aforementioned display substrate.

[0023] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects will become clear. Attached Figure Description

[0024] The accompanying drawings are provided to illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure, but do not constitute a limitation on the technical solutions of this disclosure. The shape and size of each component in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0025] Figure 1 is a schematic diagram of a silicon-based OLED display device;

[0026] Figure 2 is a schematic diagram of the planar structure of the display area in a silicon-based OLED display device;

[0027] Figure 3 is a schematic cross-sectional view of the display area in a silicon-based OLED display device;

[0028] Figure 4 is an equivalent circuit diagram of an electrostatic protection device according to an exemplary embodiment of the present disclosure;

[0029] Figure 5 is a structural schematic diagram of an electrostatic protection device according to an exemplary embodiment of the present disclosure;

[0030] Figure 6 is a schematic diagram showing the N-well region and P-well region patterns formed according to an embodiment of the present disclosure;

[0031] Figures 7A and 7B are schematic diagrams of the active region pattern formed according to the embodiments of this disclosure;

[0032] Figures 8A and 8B are schematic diagrams of the gate conductive layer pattern formed according to an embodiment of the present disclosure;

[0033] Figures 9A and 9B are schematic diagrams of the N-type doped region pattern formed according to the embodiments of this disclosure;

[0034] Figures 10A and 10B are schematic diagrams of the P-type doped region pattern formed according to the embodiments of this disclosure;

[0035] Figure 11 is a schematic diagram of the second insulating layer pattern after it is formed according to an embodiment of the present disclosure;

[0036] Figures 12A and 12B are schematic diagrams after the first conductive layer pattern is formed according to an embodiment of the present disclosure;

[0037] Figure 13 is a schematic diagram of the third insulating layer pattern after it is formed according to an embodiment of the present disclosure;

[0038] Figures 14A and 14B are schematic diagrams of the second conductive layer pattern after it is formed according to an embodiment of the present disclosure;

[0039] Figure 15 is a schematic diagram of the fourth insulating layer pattern formed according to an embodiment of the present disclosure;

[0040] Figures 16A and 16B are schematic diagrams of the formation of the third conductive layer pattern according to an embodiment of the present disclosure;

[0041] Figure 17 is a schematic diagram of the fifth insulating layer pattern after it is formed according to an embodiment of the present disclosure;

[0042] Figures 18A and 18B are schematic diagrams of the fourth conductive layer pattern formed according to an embodiment of this disclosure. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0044] The scale of the accompanying drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display device and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The accompanying drawings described in this disclosure are only structural schematic diagrams, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0045] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0046] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0047] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0048] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0049] In this specification, to distinguish the two terminals of a transistor other than the gate electrode, one terminal is directly described as the first terminal and the other as the second terminal. The first terminal can be the drain electrode and the second terminal can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0050] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0051] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0052] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0053] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple structures in a same-layer arrangement may be made of the same material, while the final materials may be the same or different.

[0054] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0055] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0056] Figure 1 is a schematic diagram of a silicon-based OLED display device. As shown in Figure 1, the silicon-based OLED display device may include a display area and a non-display area. The display area may include multiple scan signal lines, multiple data signal lines, and multiple sub-pixels Pxij forming multiple pixel rows and multiple pixel columns. The multiple scan signal lines are respectively arranged in the multiple pixel rows, and the multiple data signal lines are respectively arranged in the multiple pixel columns. Each sub-pixel Pxij may include at least a pixel driving circuit and a light-emitting device. The pixel driving circuit is configured to provide the current required for light emission to the connected light-emitting device. The pixel driving circuit of each sub-pixel Pxij may be connected to the scan signal line of the corresponding pixel row and the data signal line of the corresponding pixel column. The sub-pixel Pxij may refer to the sub-pixel of the i-th pixel row and the j-th pixel column. The pixel driving circuit of the sub-pixel Pxij is connected to the i-th scan signal line and the j-th data signal line, respectively. i and j can be natural numbers. The non-display area may include a display driver integrated circuit (DDIC), a gate driver (GD), and a source driver (SD). The display driver circuit may include at least a timing controller (TCON), configured to generate timing signals required by the gate driver, such as a start signal (STV) and a clock signal (CKV), and send these timing signals to the gate driver. The gate driver is connected to multiple scan signal lines in the display area and is configured to provide the required timing signals to the connected pixel driver circuits to achieve progressive scan functionality. The source driver is connected to multiple data signal lines in the display area and is configured to provide the required data signals to the connected pixel driver circuits to achieve switching and control of the display screen. In an exemplary embodiment, the pixel array may be disposed on a display substrate.

[0057] In one exemplary embodiment, the silicon-based OLED display device can be a one-chip display architecture, integrating gate driving devices, data driving devices, clock control units, image processing units, and memory units onto the same chip. The one-chip architecture chip includes both digital and analog parts, belonging to mixed-signal chips.

[0058] In another exemplary embodiment, the silicon-based OLED display device may be a two-chip display architecture, in which the gate driving device and the data driving device are integrated in the display substrate, and the clock control unit, the image processing unit, the mobile industry processor interface (MIPI) and the memory unit are integrated in one chip, which is bonded to the display substrate through a COC process.

[0059] Figure 2 is a schematic diagram of the planar structure of a display area in a display substrate. As shown in Figure 2, on a plane parallel to the display substrate, the display area may include multiple pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each of the three sub-pixels may include a pixel driving circuit and a light-emitting device. The pixel driving circuit in the sub-pixel is connected to the scan signal line and the data signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scan signal line and output a corresponding current to the display light-emitting device. The light-emitting device in the sub-pixel is connected to the pixel driving circuit of the sub-pixel and is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0060] In an exemplary embodiment, the first sub-pixel P1 may be a red (R) sub-pixel that emits red light, the second sub-pixel P2 may be a green (G) sub-pixel that emits green light, and the third sub-pixel P3 may be a blue (B) sub-pixel that emits blue light.

[0061] In exemplary embodiments, the shape of a sub-pixel can be any one or more of a triangle, square, rectangle, rhombus, trapezoid, parallelogram, pentagon, hexagon, and other polygons. Three sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a triangular pattern, etc., and this disclosure does not limit the arrangement. In other possible embodiments, a pixel unit may include four sub-pixels, and this disclosure does not limit the arrangement.

[0062] Figure 3 is a schematic cross-sectional view of the display area in a display substrate, illustrating a structure that achieves full color using a white light + color filter approach. As shown in Figure 3, in the direction perpendicular to the display substrate, the display substrate may include: a silicon substrate 200, a driving circuit layer 201 disposed on the silicon substrate 200, a light-emitting structure layer 202 disposed on the side of the driving circuit layer 201 away from the silicon substrate 200, a first encapsulation layer 203 disposed on the side of the light-emitting structure layer 202 away from the silicon substrate 200, a color filter structure layer 204 disposed on the side of the first encapsulation layer 203 away from the silicon substrate 200, a second encapsulation layer 205 disposed on the side of the color filter structure layer 204 away from the silicon substrate 200, and a cover plate layer 206 disposed on the side of the second encapsulation layer 205 away from the silicon substrate 200. In some possible implementations, the display substrate may also include other film layers, which are not limited herein.

[0063] In an exemplary embodiment, the silicon substrate 200 can be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. The driving circuit layer 201 can be fabricated on the silicon substrate 200 using silicon semiconductor processes. The driving circuit layer 201 can include multiple circuit units, each of which can include at least a pixel driving circuit. The pixel driving circuit is connected to the scan signal line and data signal line, respectively. The pixel driving circuit can include multiple transistors and storage capacitors; only one transistor is shown as an example in Figure 3. The transistor can include a gate electrode, a source electrode, and a drain electrode. The gate electrode, source electrode, and drain electrode can be connected to corresponding connection electrodes via tungsten-filled vias (i.e., tungsten vias, W-vias), and can be connected to other electrical structures (such as traces) via the connection electrodes.

[0064] In an exemplary embodiment, the light-emitting structure layer 202 may include multiple light-emitting devices. Each light-emitting device may include at least an anode, an organic light-emitting layer, and a cathode. The anode is connected to the drain electrode of a transistor via a connecting electrode. The organic light-emitting layer is connected to the anode, the cathode is connected to the organic light-emitting layer, and the cathode is connected to a second power line. The organic light-emitting layer emits light under the drive of the anode and cathode. In an exemplary embodiment, the organic light-emitting layer may include a light-emitting layer (EML), and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, for a light-emitting device emitting white light, the organic light-emitting layers of all sub-pixels may be a common layer connected together.

[0065] In an exemplary embodiment, the first encapsulation layer 203 and the second encapsulation layer 205 can employ thin film encapsulation (TFE) to prevent external moisture from entering the light-emitting structure layer. The color filter structure layer 204 can include at least a red filter unit, a blue filter unit, and a green filter unit. The red filter unit is located in the red sub-pixel and filters the white light emitted by the light-emitting device into red light. The blue filter unit is located in the blue sub-pixel and filters the white light emitted by the light-emitting device into blue light. The green filter unit is located in the green sub-pixel and filters the white light emitted by the light-emitting device into green light. The cover plate layer 206 can be made of glass or a flexible plastic such as colorless polyimide.

[0066] In the manufacturing of silicon-based OLED displays, the display substrate can suffer irreversible damage due to two electrostatic discharge (ESD) methods: Charged Device Mode (CDM) and Machine Model (MM). This primarily manifests as breakdown of transistor gate electrodes and melting of metal traces due to high current, leading to defects such as black screens and abnormal display. Furthermore, when personnel touch the display substrate, it can suffer irreversible damage due to ESD via Human Body Mode (HBM). Therefore, ESD protection devices are crucial throughout the entire lifecycle of silicon-based OLED displays, significantly contributing to improved product yield and reliability.

[0067] In silicon-based OLED display devices, electrostatic discharge (ESD) protection devices are primarily used to protect power and signals. The power and signals of the display substrate mainly originate from the driver board (FPC / PCB), display driver circuit (DDIC), and test. Power and signals from the driver board are received by the driver board pads, power and signals from the display driver circuit are received by the display driver circuit pads, and power and signals used for testing are received by the test pads. The display driver circuit pads mainly include gate drive signal pads and data signal pads, and the number of data signal pads is large (generally greater than 1000). Each data signal pad requires a corresponding ESD protection device.

[0068] An exemplary embodiment of this disclosure provides an electrostatic discharge (ESD) protection device, including a transistor group, a diode group, and a trigger resistor. The transistor group includes a plurality of transistors connected in parallel, and the diode group includes a plurality of diodes connected in parallel. The first terminal of each transistor and the first terminal of the trigger resistor are connected to a second power supply line. The second terminal of the trigger resistor is connected to the gate electrode of the transistor. The second terminal of each transistor and the first terminal of each diode are connected to a ground line. The second terminal of each diode is connected to a first power supply line. The trigger resistor is disposed on one side of the transistor group in a first direction, and the diode group is disposed on one side of the transistor group in a second direction, wherein the first direction and the second direction intersect. The ESD protection device further includes a first P-type doped protective ring. The first P-type doped protective ring is ring-shaped and connected to the second power supply line. The transistor group and the trigger resistor are disposed within the space surrounded by the first P-type doped protective ring.

[0069] In an exemplary embodiment, the first P-type doped guard ring includes at least a first doped sub-ring and a second doped sub-ring. The first doped sub-ring and the second doped sub-ring are ring-shaped. The second doped sub-ring is disposed on one side of the first doped sub-ring in the first direction and is connected to the first doped sub-ring. The transistor group is disposed within the space surrounded by the first doped sub-ring, and the trigger resistor is disposed within the space surrounded by the second doped sub-ring.

[0070] In an exemplary embodiment, the electrostatic discharge protection device further includes a first N-type doped protective ring, which is ring-shaped and connected to the first power line. The first P-type doped protective ring is disposed within the space surrounded by the first N-type doped protective ring.

[0071] In an exemplary embodiment, the electrostatic discharge protection device further includes a second P-type doped protective ring, which is ring-shaped, disposed on one side of the first P-type doped protective ring in the second direction, and connected to the grounding wire. The diode group is disposed within the space surrounded by the second P-type doped protective ring.

[0072] In an exemplary embodiment, the electrostatic discharge protection device further includes a second N-type doped protective ring, which is ring-shaped and connected to the first power line. The second P-type doped protective ring is disposed within the space surrounded by the second N-type doped protective ring.

[0073] In an exemplary embodiment, in the second direction, at least three protective frames are provided between the transistor group and the diode group, and the three protective frames are respectively a protective frame in the first P-type doped protective ring, a protective frame in the second P-type doped protective ring, and a protective frame in the second N-type doped protective ring.

[0074] The technical solution of the electrostatic discharge protection device disclosed herein is illustrated below through exemplary embodiments.

[0075] Figure 4 is an equivalent circuit diagram of an electrostatic discharge (ESD) protection device according to an exemplary embodiment of this disclosure. In an exemplary embodiment, the ESD protection device can be disposed in a non-display area for protecting the driver board pads, display driver circuit pads, and test pads by means of voltage triggering. As shown in Figure 4, the ESD protection device may include at least a first circuit C1 and a second circuit C2. The first circuit is configured to discharge the electrostatic current between the second power line VSS and the ground line GND, and the second circuit is configured to discharge the electrostatic current between the first power line VDD and the ground line GND, forming an ESD protection device with positive voltage (VDD) / ground (GND) / negative voltage (VSS) power rails.

[0076] In an exemplary embodiment, the first circuit C1 may include an N-type transistor NT and a trigger resistor R. The N-type transistor NT is a gate-coupled N-type transistor (GCNMOS). The first terminal of the trigger resistor R and the first electrode of the N-type transistor NT are connected to the second power supply line VSS, the second terminal of the trigger resistor R is connected to the gate electrode of the N-type transistor NT, and the second electrode of the N-type transistor NT is connected to the ground line GND. When an electrostatic discharge event occurs on the second power supply line VSS, current is discharged to the ground line GND through the parasitic transistor of the N-type transistor NT. The trigger resistor R is a high-resistance polysilicon resistor (rhrpo), which can further reduce the trigger voltage.

[0077] In an exemplary embodiment, the second circuit C2 may include an N-type diode ND, with its first terminal connected to the ground line GND and its second terminal connected to the first power line VDD. When an electrostatic discharge event occurs on the first power line VDD, current is discharged to the ground line GND through the N-type diode ND.

[0078] Figure 5 is a schematic diagram of an electrostatic discharge (ESD) protection device according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, the display substrate may include at least a display area and a non-display area. The display area may include multiple sub-pixels forming multiple pixel rows and multiple pixel columns. At least one sub-pixel includes a pixel driving circuit and a light-emitting device connected to the pixel driving circuit. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit. The non-display area may include at least multiple pads and multiple ESD protection devices. The multiple pads may include driver board pads, display driving circuit pads, and test pads. The ESD protection devices are configured to protect the driver board pads, display driving circuit pads, and test pads by voltage triggering.

[0079] As shown in Figure 5, the electrostatic discharge (ESD) protection device may include a transistor group 81, a diode group 82, and a trigger resistor 83 disposed on a silicon substrate. The trigger resistor 83 may be disposed on one side of the transistor group 81 in a first direction X, and the diode group 82 may be disposed on one side of the transistor group 81 in a second direction Y, wherein the first direction X and the second direction Y intersect.

[0080] In an exemplary embodiment, transistor group 81 may include 14 transistors NT connected in parallel, which may be arranged sequentially in the first direction X, and transistors NT are N-type transistors. Diode group 82 may include 56 diodes ND connected in parallel, which may be arranged in an array, including 14 diode rows and 4 diode columns, and diodes ND are N-type diodes.

[0081] In some possible implementations, transistor group 81 may include m1 transistors NT connected in parallel, and P-type diode group may include n1 diode rows and n2 diode columns. m1, n1, and n2 can be positive integers greater than 1, which are not limited herein.

[0082] In an exemplary embodiment, the trigger resistor 83 and 14 transistors NT can form the first circuit of the electrostatic discharge (ESD) protection device. The width-to-length ratio (W / L) of the 14 transistors NT connected in parallel is 14 times that of a single transistor, which can meet the requirements for ESD current discharge. The 56 diodes ND can form the second circuit of the ESD protection device, forming a 14x4 array in parallel, which can also meet the requirements for ESD current discharge.

[0083] In an exemplary embodiment, the first terminal of trigger resistor 83 and the first electrode of transistor NT are connected to the second power supply line, the second terminal of trigger resistor 84 is connected to the gate electrode of transistor NT, and the second electrode of transistor NT is connected to the ground line. The first electrode of diode ND is connected to the ground line, and the second electrode of diode ND is connected to the first power supply line.

[0084] In an exemplary embodiment, at least one transistor NT may include at least a gate electrode 31, which may include at least a first sub-gate 31-1, a second sub-gate 31-2, and a sub-gate connecting strip 31-3. The first sub-gate 31-1 and the second sub-gate 31-2 may be strip-shaped extending along the second direction Y and spaced apart in the first direction X. The sub-gate connecting strip 31-3 may be strip-shaped extending along the first direction X and may be disposed on the opposite side of the first sub-gate 31-1 and the second sub-gate 31-2 in the second direction Y, and connected to the ends of the first sub-gate 31-1 and the second sub-gate 31-2 on the opposite side of the second direction Y, respectively, forming an "n" shape.

[0085] In an exemplary embodiment, the first sub-gate 31-1 or the second sub-gate 31-2 may have a sub-gate width L1, and a sub-gate pitch L2 may be present between the first sub-gate 31-1 and the second sub-gate 31-2. The ratio of the sub-gate width L1 to the sub-gate pitch L2 may be 0.2 to 0.3, which can ensure that the transistor has a large aspect ratio (W / L). The sub-gate width L1 may be the distance between the edge of the first sub-gate 31-1 near the second sub-gate 31-2 and the edge of the first sub-gate 31-1 away from the second sub-gate 31-2, or the sub-gate width L1 may be the distance between the edge of the second sub-gate 31-2 near the first sub-gate 31-1 and the edge of the second sub-gate 31-2 away from the first sub-gate 31-1. The sub-gate pitch L2 may be the distance between the edge of the first sub-gate 31-1 near the second sub-gate 31-2 and the edge of the second sub-gate 31-2 near the first sub-gate 31-1. The sub-gate width L1 and the sub-gate pitch L2 may be dimensions in the first direction X.

[0086] In an exemplary embodiment, the transistor group 81 may further include a gate connection line 32. The gate connection line 32 may be a straight line or a zigzag line extending along the first direction X, and may be disposed on one side of the 14 first gate electrodes 31 in the second direction Y (the side away from the sub-gate connection strip 31-3), and connected to each of the 14 first gate electrodes 31. The first sub-gate 31-1, the second sub-gate 31-2, the sub-gate connection strip 31-3, and the gate connection line 32 may form an annular hollow structure. In an exemplary embodiment, the gate connection line 32 may serve as the input terminal of the gate electrode of the transistor, and is configured to be connected to the second terminal of the trigger resistor via a subsequently formed connection electrode.

[0087] In an exemplary embodiment, in the second direction Y, the edge of the trigger resistor 83 on the second direction Y side can be substantially flush with the gate connection line 32.

[0088] In an exemplary embodiment, a first device spacing S1 may be present between the trigger resistor 83 and the transistor group 81, and the ratio of the first device spacing S1 to the sub-gate spacing L2 may be 1.0 to 2.0. The first device spacing S1 may be the minimum distance between the edge of the trigger resistor 83 near the transistor group 81 and the edge of the first gate electrode 31 in the transistor group 81 near the trigger resistor 83, and may be a dimension in the first direction X.

[0089] In an exemplary embodiment, at least one diode may include a first active region 11 and a second active region 12. The first active region 11 may be a strip extending along a first direction X, and 56 first active regions 11 may form a 14*4 first active array. The second active region 12 may be annular (e.g., a rectangular ring) and may surround the first active region 11; 56 second active regions 12 may form a 14*4 second active array. At least one transistor NT may also include at least a third active region 13, which may be a strip extending along a second direction Y, and 14 third active regions 13 may be an integrally connected structure.

[0090] In an exemplary embodiment, a second device spacing S2 may be present between the transistor group 81 and the diode group 82, and the second device spacing S2 may be greater than the first device spacing S1. The second device spacing S2 may be the minimum distance between the edge of the third active region 13 in the transistor group near the diode group and the edge of the second active region 12 in the diode group near the transistor group, and may be a dimension in the second direction Y.

[0091] In an exemplary embodiment, the annular second active region 12 may include at least two first active frames 12-1 and two second active frames 12-2. The shape of the first active frame 12-1 may be a strip extending along the first direction X, and the shape of the second active frame 12-2 may be a strip extending along the second direction Y. The first active frames 12-1 and the second active frames 12-2 are connected end to end in sequence to form a rectangular annular second active region 12.

[0092] In an exemplary embodiment, the plurality of first active frames 12-1 may include at least one first width frame and at least one second width frame. The first width frame may have a first active width A1, and the second width frame may have a second active width A2. The first active width A1 may be greater than the second active width A2. The first active width A1 and the second active width A2 may be the distance between the edges of the first active frame 12-1 on both sides in the second direction Y, and may be a dimension in the second direction Y.

[0093] In an exemplary embodiment, the second active array may have an array centerline O1, which may be a straight line that bisects the second active array in the second direction Y and extends along the first direction X. The orthographic projection of the first width frame on the silicon substrate at least partially overlaps with the orthographic projection of the array centerline O1 on the silicon substrate, while the orthographic projection of the second width frame on the silicon substrate does not overlap with the orthographic projection of the array centerline O1 on the silicon substrate. That is, the width of the first active frame 12-1 located at halfway point in the second active array is greater than the width of the first active frame 12-1 located at other positions.

[0094] In an exemplary embodiment, the electrostatic discharge (ESD) protection device may further include a first P-type doped protective ring 91P and a second P-type doped protective ring 92P. The first P-type doped protective ring 91P and the second P-type doped protective ring 92P may be annular (e.g., rectangular ring). The first P-type doped protective ring 91P is connected to a second power supply line, and the second P-type doped protective ring 92P is connected to a grounding line. The second P-type doped protective ring 92P may be disposed on one side of the first P-type doped protective ring 91P in the second direction Y. The transistor group 81 and the trigger resistor 83 may be disposed within the space surrounded by the first P-type doped protective ring 91P, and the diode group 82 may be disposed within the space surrounded by the second P-type doped protective ring 92P.

[0095] In an exemplary embodiment, the first P-type doped guard ring 91P may include at least a first doped sub-ring 91A and a second doped sub-ring 91B. The first doped sub-ring 91A and the second doped sub-ring 91B are annular (e.g., rectangular rings). The second doped sub-ring 91B may be disposed on one side of the first doped sub-ring 91A in the first direction X, and the first doped sub-ring 91A and the second doped sub-ring 91B are interconnected. The transistor group 81 may be disposed within the space surrounded by the first doped sub-ring 91A, and the trigger resistor 83 may be disposed within the space surrounded by the second doped sub-ring 91B.

[0096] In an exemplary embodiment, the protective frame of the first doped sub-ring 91A near the second doped sub-ring 91B and the protective frame of the second doped sub-ring 91B near the first doped sub-ring 91A can be the same protective frame.

[0097] In an exemplary embodiment, the electrostatic discharge (ESD) protection device may further include a first N-type doped protective ring 91N and a second N-type doped protective ring 92N. The first N-type doped protective ring 91N and the second N-type doped protective ring 92N are annular (e.g., rectangular rings). The second N-type doped protective ring 92N may be disposed on one side of the first N-type doped protective ring 91N in the second direction Y, and both the first N-type doped protective ring 91N and the second N-type doped protective ring 92N are connected to the first power line. A first P-type doped protective ring 91P may be disposed within the space surrounded by the first N-type doped protective ring 91N, and the second P-type doped protective ring 92P may be disposed within the space surrounded by the second N-type doped protective ring 92N.

[0098] In an exemplary embodiment, the first N-type doped protective ring 91N and the second N-type doped protective ring 92N can be connected to each other, and the protective frame of the first N-type doped protective ring 91N near the second N-type doped protective ring 92N and the protective frame of the second N-type doped protective ring 92N near the first N-type doped protective ring 91N can be the same protective frame.

[0099] In an exemplary embodiment, at least three protective frames may be provided between the transistor group 81 and the diode group 82 in the second direction Y. The three protective frames may be the protective frame of the first P-type doped protective ring 91P that is close to the second P-type doped protective ring 92P, the protective frame of the second P-type doped protective ring 92P that is close to the first P-type doped protective ring 91P, and the protective frame shared by the first N-type doped protective ring 91N and the second N-type doped protective ring 92N.

[0100] The following is an illustrative description of the fabrication process of an electrostatic discharge (ESD) protection device. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as depositing a film, coating the film with photoresist, mask exposure, development, etching, and photoresist stripping; for organic materials, processes include coating the organic material, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display device. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0101] In an exemplary embodiment, the process of preparing an electrostatic protection device may include the following steps.

[0102] (1) An N-well region, a P-well region, and an active area pattern are sequentially formed on a silicon substrate. In an exemplary embodiment, forming the N-well and P-well region patterns may include: providing a P-type silicon substrate; forming a photoresist pattern including an opening region by coating photoresist on the P-type silicon substrate, exposure, and development; removing the photoresist in the opening region to expose the surface of the P-type silicon substrate; implanting n-type dopant ions into the opening region by ion implantation; stripping off the remaining photoresist; and forming an N-well (N-type well, abbreviated as NW) region pattern and a P-well (P-type well, abbreviated as PW) region pattern on the P-type silicon substrate, as shown in FIG6. Subsequently, an active area (AA) pattern is formed on the silicon substrate with the aforementioned patterns, as shown in FIG7A and FIG7B, FIG7B being a schematic diagram of the active area in FIG7A.

[0103] In an exemplary embodiment, the silicon substrate may be a P-type silicon substrate, which may serve as the channel region of an N-type transistor.

[0104] The N-well region pattern may include at least an N-well region 10, a first annular region 10A, and a second annular region 10B. The P-well region pattern may be located outside the N-well region pattern. The N-well region 10 may be rectangular in shape to save space occupied by the electrostatic discharge (ESD) protection device. The N-well region 10 is configured to form an N-type diode. The first annular region 10A and the second annular region 10B may be annular (e.g., rectangular rings). The second annular region 10B may be located on one side of the first annular region 10A in the second direction Y, and the second annular region 10B may surround the N-well region 10. The P-well region surrounded by the first annular region 10A is configured to form an N-type transistor. The first annular region 10A and the second annular region 10B are configured to isolate this ESD protection device from other ESD protection devices to prevent latch-up caused by silicon substrate bias due to ESD discharge spike current.

[0105] In an exemplary embodiment, the first annular region 10A and the second annular region 10B can be connected to each other. The border of the first annular region 10A near the second annular region 10B and the border of the second annular region 10B near the first annular region 10A can be the same border, that is, the first annular region 10A and the second annular region 10B can share the same border.

[0106] In some possible implementations, a deep N-type well (DNW) region can also be formed on the P-type silicon substrate. This DNW region is configured to electrically isolate different regions, and this disclosure is not limited thereto. Since electrostatic discharge (ESD) protection devices are used to protect against positive and negative voltage inputs, when protecting against negative voltage inputs, the DNW region can be used to isolate the P-type silicon substrate. This not only prevents short circuits between forward biases or different voltages but also effectively limits the current flow path, thereby reducing leakage current and energy loss.

[0107] In an exemplary embodiment, the active region pattern may include at least a first active group, a second active group, and a third active group.

[0108] In an exemplary embodiment, the first active group may include 56 first active regions 11, the second active group may include 56 second active regions 12, and the third active group may include 14 third active regions 13.

[0109] In an exemplary embodiment, the 56 first active regions 11 can be located within the area of ​​the N-well region 10. The shape of the first active regions 11 can be a strip extending along the first direction X. The 56 first active regions 11 form 14 active rows and 4 active columns, forming a 14*4 first active array. Each active row in the first active array includes 4 first active regions 11 arranged sequentially along the first direction X, and the 14 active rows are arranged sequentially along the second direction Y. Each active column in the first active array includes 14 first active regions 11 arranged sequentially along the second direction Y, and the 4 active columns are arranged sequentially along the first direction X.

[0110] In an exemplary embodiment, the 56 second active regions 12 can be located within the area of ​​the N-well region 10. The shape of the second active regions 12 can be annular (such as a rectangular ring), and they can be disposed outside each first active region 11 and surround the first active region 11. The 56 second active regions 12 can form a 14*4 second active array. Each active row in the second active array includes 4 second active regions 12 arranged sequentially along the first direction X, and the 14 active rows are arranged sequentially along the second direction Y. Each active column in the second active array includes 14 second active regions 12 arranged sequentially along the second direction Y, and the 4 active columns are arranged sequentially along the first direction X.

[0111] In an exemplary embodiment, adjacent second active regions 12 in the first direction X can be connected to each other, and adjacent second active regions 12 in the second direction Y can be connected to each other. The 56 second active regions 12 connected to each other form a grid structure.

[0112] In an exemplary embodiment, the annular second active region 12 may include at least two first active frames 12-1 and two second active frames 12-2. The shape of the first active frame 12-1 may be a strip extending along the first direction X, and the shape of the second active frame 12-2 may be a strip extending along the second direction Y. The first active frames 12-1 and the second active frames 12-2 are connected end to end in sequence to form a rectangular annular second active region 12.

[0113] In an exemplary embodiment, two adjacent second active regions 12 in the first direction X can share the same second active frame 12-2, and two adjacent second active regions 12 in the second direction Y can share the same first active frame 12-1.

[0114] In an exemplary embodiment, the plurality of first active frames 12-1 in the second active group may include at least one first width frame and at least one second width frame. The first width frame may have a first active width A1, and the second width frame may have a second active width A2. The first active width A1 may be greater than the second active width A2. The first active width A1 and the second active width A2 may be the distance between the edges of the first active frame 12-1 on both sides in the second direction Y, and may be a dimension in the second direction Y.

[0115] In an exemplary embodiment, the second active array formed by the 56 second active regions 12 may have an array center line O1, which may be a straight line that bisects the second active array in the second direction Y and extends along the first direction X. The orthographic projection of the first width frame on the silicon substrate at least partially overlaps with the orthographic projection of the array center line O1 on the silicon substrate, while the orthographic projection of the second width frame on the silicon substrate does not overlap with the orthographic projection of the array center line O1 on the silicon substrate. That is, the width of the first active frame 12-1 located at halfway point in the second active array (array center line O1) is greater than the width of the first active frame 12-1 located at other positions.

[0116] In an exemplary embodiment, the diode serves as a discharge device, and the second active region 12 is configured to be connected to the subsequently formed ground wire. This disclosure can effectively improve the discharge current capability at the location by setting a wider active frame at half of the second active array, thereby improving the discharge current capability of the entire diode group.

[0117] In an exemplary embodiment, the 14 third active regions 13 may be located within the range of the P-well region. The shape of the third active region 13 may be a strip shape extending along the second direction Y. The 14 third active regions 13 may be arranged sequentially in the first direction X.

[0118] In an exemplary embodiment, the 14 third active regions 13 can be connected in sequence to form an active block that is interconnected into a single structure.

[0119] In an exemplary embodiment, a second device spacing S2 may be present between the transistor group and the diode group. The second device spacing S2 may be the minimum distance between the edge of the third active region 13 in the transistor group near the diode group and the edge of the second active region 12 in the diode group near the transistor group, and may be a dimension in the second direction Y.

[0120] In some possible implementations, the plurality of first active regions 11 in the first active group can form an n1*n2 first active array, the plurality of second active regions 12 in the second active group can form an n1*n2 second active array, and the third active group can include m1 third active layers, the m1 third active layers can be an interconnected integral structure, and m1, n1 and n2 can be positive integers greater than 1.

[0121] In an exemplary embodiment, the active region pattern may further include a first active ring 21, a second active ring 22, a third active ring 23, and a fourth active ring 24.

[0122] In an exemplary embodiment, the first active ring 21 may include a first active sub-ring 21A and a second active sub-ring 21B. The first active sub-ring 21A may be annular (e.g., rectangular) in shape, and may be disposed outside and surrounding the 14 third active regions 13. The first active sub-ring 21A is configured as a protective structure for the transistor group. The second active sub-ring 21B may also be annular (e.g., rectangular) in shape, and may be disposed on one side of the first active sub-ring 21A in the first direction X. The second active sub-ring 21B and the first active sub-ring 21A are interconnected, and the second active sub-ring 21B is configured as a protective structure for the trigger resistor.

[0123] In an exemplary embodiment, the active frame of the first active sub-ring 21A near the second active sub-ring 21B and the active frame of the second active sub-ring 21B near the first active sub-ring 21A can be the same active frame, that is, the first active sub-ring 21A and the second active sub-ring 21B can share the same active frame extending along the second direction Y.

[0124] In an exemplary embodiment, the second active ring 22 can be annular (e.g., rectangular ring). The second active ring 22 can be disposed on one side of the first active ring 21 in the second direction Y, and the first active ring 21 and the second active ring 22 are isolated from each other. The second active ring 22 can be disposed outside the 56 second active regions 12 and surround the 56 second active regions 12. The second active ring 22 is configured as a protective structure for the 56 diodes.

[0125] In an exemplary embodiment, the first active sub-ring 21A and the second active sub-ring 21B can isolate the transistor group and the trigger resistor, and the first active ring 21 and the second active ring 22 can isolate the first circuit C1 and the second circuit C2, which can effectively prevent electrostatic discharge spike current between circuits.

[0126] In an exemplary embodiment, the third active ring 23 may be ring-shaped (such as a rectangular ring), and may be disposed outside the first active sub-ring 21A and the second active sub-ring 21B, and surround the first active sub-ring 21A and the second active sub-ring 21B. The third active ring 23 is configured as a protective structure for the first circuit C1.

[0127] In an exemplary embodiment, the fourth active ring 24 may be ring-shaped (e.g., a rectangular ring), and may be disposed on one side of the third active ring 23 in the second direction Y, with the third active ring 23 and the fourth active ring 24 interconnected. The fourth active ring 24 may be disposed outside the second active ring 22 and surround the second active ring 22, and the fourth active ring 24 is configured as a protective structure for the second circuit C2.

[0128] In an exemplary embodiment, the active frame of the third active ring 23 near the fourth active ring 24 and the active frame of the fourth active ring 24 near the third active ring 23 can be the same active frame, that is, the third active ring 23 and the fourth active ring 24 can share the same active frame extending along the first direction X.

[0129] In an exemplary embodiment, at least three active frame borders may be provided between the transistor group and the diode group in the second direction Y. The three active frame borders may be the active frame border of the first active ring 21 that is close to the second active ring 22, the active frame border of the second active ring 22 that is close to the first active ring 21, and the active frame border shared by the third active ring 23 and the fourth active ring 24.

[0130] In an exemplary embodiment, the third active ring 23 and the fourth active ring 24 can not only isolate the first circuit C1 and the second circuit C2, but also isolate this electrostatic discharge protection device from other electrostatic discharge protection devices, effectively shielding the electrostatic discharge spike current between electrostatic discharge protection devices.

[0131] The exemplary embodiment of this disclosure first uses an inner active guard ring to isolate the first circuit and the second circuit, and then uses an outer active guard ring to isolate this electrostatic discharge protection device from other electrostatic discharge protection devices, which can effectively prevent latch-up effect caused by silicon substrate bias due to electrostatic discharge spike current.

[0132] (2) Forming a gate conductive layer pattern. In an exemplary embodiment, forming a gate conductive layer pattern may include: sequentially depositing a first insulating film and a polysilicon film on a silicon substrate on which the aforementioned pattern is formed; firstly, patterning the polysilicon film using a patterning process to form a first insulating layer covering the silicon substrate and a polysilicon layer disposed on the first insulating layer; and then doping the polysilicon layer to form a gate conductive layer pattern, as shown in Figures 8A and 8B, where Figure 8B is a schematic diagram of the gate conductive layer in Figure 8A.

[0133] In an exemplary embodiment, the gate conductive layer pattern may include at least a gate electrode group, a gate connection line 32, and a trigger resistor 83.

[0134] In an exemplary embodiment, the gate electrode group may include 14 first gate electrodes 31 arranged sequentially in the first direction X. The shape of the first gate electrode 31 may be "n" shaped, and the orthographic projection of the first gate electrode 31 on the silicon substrate at least partially overlaps with the orthographic projection of the third active region 13 on the silicon substrate. The first gate electrode 31 may serve as the gate electrode of a transistor.

[0135] In an exemplary embodiment, at least one first gate electrode 31 may include at least a first sub-gate 31-1, a second sub-gate 31-2, and a sub-gate connecting strip 31-3. The first sub-gate 31-1 and the second sub-gate 31-2 may be strip-shaped extending along the second direction Y, and may be spaced apart in the first direction X. The sub-gate connecting strip 31-3 may be strip-shaped extending along the first direction X, and may be disposed on the opposite side of the first sub-gate 31-1 and the second sub-gate 31-2 in the second direction Y, and respectively connected to the ends of the first sub-gate 31-1 and the second sub-gate 31-2 on the opposite side of the second direction Y, forming an "n" shape.

[0136] In an exemplary embodiment, the first sub-gate 31-1 or the second sub-gate 31-2 may have a sub-gate width L1, and a sub-gate pitch L2 may be present between the first sub-gate 31-1 and the second sub-gate 31-2. The ratio of the sub-gate width L1 to the sub-gate pitch L2 may be 0.2 to 0.3, which can ensure that the transistor has a large aspect ratio (W / L). The sub-gate width L1 may be the distance between the edge of the first sub-gate 31-1 near the second sub-gate 31-2 and the edge of the first sub-gate 31-1 away from the second sub-gate 31-2, or the sub-gate width L1 may be the distance between the edge of the second sub-gate 31-2 near the first sub-gate 31-1 and the edge of the second sub-gate 31-2 away from the first sub-gate 31-1. The sub-gate pitch L2 may be the distance between the edge of the first sub-gate 31-1 near the second sub-gate 31-2 and the edge of the second sub-gate 31-2 near the first sub-gate 31-1. The sub-gate width L1 and the sub-gate pitch L2 may be dimensions in the first direction X.

[0137] In an exemplary embodiment, the gate connection line 32 can be a straight line or a broken line extending along the first direction X, and can be disposed on one side of the 14 first gate electrodes 31 in the second direction Y, and connected to the 14 first gate electrodes 31 respectively. In an exemplary embodiment, the gate connection line 32 can serve as the gate electrode input terminal of the transistor, and is configured to be connected to the second terminal of the trigger resistor through a subsequently formed connection electrode.

[0138] In an exemplary embodiment, the gate connection line 32 being connected to 14 first gate electrodes 31 means that the gate connection line 32 is connected to the ends of multiple first sub-gates 31-1 and multiple second sub-gates 31-2 on the Y side of the second direction, so that multiple first sub-gates 31-1, multiple second sub-gates 31-2, multiple sub-gate connecting strips 31-3 and gate connection line 32 form multiple annular hollow structures.

[0139] In an exemplary embodiment, the gate connection line 32 and the 14 first gate electrodes 31 can be an integral structure that is interconnected, and the integral structure is located in the space surrounded by the first active sub-ring 21A.

[0140] In an exemplary embodiment, the trigger resistor 83 may be a strip extending along the second direction Y, and may be located within the space surrounded by the second active sub-ring 21B. In the first direction X, the trigger resistor 83 may be disposed on one side of the transistor group in the first direction X, and in the second direction Y, the edge of the trigger resistor 83 on the second direction Y side may be substantially flush with the gate connection line 32.

[0141] In an exemplary embodiment, a first device spacing S1 may be present between the trigger resistor 83 and the gate electrode group, and the ratio of the first device spacing S1 to the sub-gate spacing L2 may be 1.0 to 2.0. The first device spacing S1 may be the minimum distance between the edge of the trigger resistor 83 near the gate electrode group and the edge of the first gate electrode 31 in the gate electrode group near the trigger resistor 83, and may be a dimension in the first direction X. In an exemplary embodiment, the edge of the first gate electrode 31 in the gate electrode group near the trigger resistor 83 may serve as the edge of the transistor group, thus the first device spacing S1 is present between the trigger resistor 83 and the transistor group.

[0142] In an exemplary embodiment, the first device spacing S1 may be smaller than the second device spacing S2.

[0143] This disclosure, by placing the trigger resistor 83 close to the gate connection line 32, facilitates the connection between the gate connection line 32 and the trigger resistor 83 using a shorter connection electrode, thus reducing the area occupied by the trigger device while ensuring the accuracy of the trigger resistor. By setting the spacing between the transistor group and the diode group to be greater than the spacing between the transistor group and the trigger resistor, mutual interference between the transistor group and the diode group can be reduced, improving anti-interference capability.

[0144] (3) Forming an N-type doped (SN) region pattern. In an exemplary embodiment, forming an N-type doped region pattern may include: coating a photoresist on a silicon substrate on which the aforementioned pattern is formed, forming a plurality of opening regions by exposure and development, removing the photoresist in the plurality of opening regions, and forming an N-type doped pattern in the opening regions by a doping process, as shown in Figures 9A and 9B, where Figure 9B is a schematic diagram of the N-type doped pattern in Figure 9A.

[0145] In an exemplary embodiment, the N-type doped region pattern may include at least a first N-type doped region 41N, a second N-type doped region 42N, a third N-type doped region 43N, and a fourth N-type doped region 44N.

[0146] In an exemplary embodiment, the first N-type doped region 41N can be rectangular in shape, and the orthographic projection of the first N-type doped region 41N on the silicon substrate at least partially overlaps with the orthographic projection of the 14 third active regions 13 on the silicon substrate, forming 14 N-type doped third active regions 13.

[0147] In an exemplary embodiment, the orthogonal projection of the first N-type doped region 41N onto the silicon substrate may include the orthogonal projections of 14 third active regions 13 onto the silicon substrate.

[0148] In an exemplary embodiment, the second N-type doped region 42N can be a grid-like structure. The orthogonal projection of the second N-type doped region 42N on the silicon substrate at least partially overlaps with the orthogonal projection of the grid-like second active region 12 on the silicon substrate, forming 56 N-type doped second active regions 12. The N-type doped second active regions 12 can serve as the N-type junction region of a diode.

[0149] In an exemplary embodiment, the orthogonal projection of the second N-type doped region 42N onto the silicon substrate may include the orthogonal projections of 56 second active regions 12 onto the silicon substrate.

[0150] In an exemplary embodiment, the third N-type doped region 43N can be ring-shaped (e.g., a rectangular ring). The orthographic projection of the third N-type doped region 43N onto the silicon substrate at least partially overlaps with the orthographic projection of the third active ring 23 onto the silicon substrate. Therefore, the third active ring 23 is an N-type doped ring, which can reduce contact resistance and improve current discharge capability. In an exemplary embodiment, the N-type doped third active ring 23 can serve as the first N-type doped guard ring of this disclosure.

[0151] In an exemplary embodiment, the orthogonal projection of the third N-type doped region 43N onto the silicon substrate may include the orthogonal projection of the third active ring 23 onto the silicon substrate.

[0152] In an exemplary embodiment, the fourth N-type doped region 44N can be annular (e.g., a rectangular ring) and can be disposed on one side of the third N-type doped region 43N in the second direction Y. The orthographic projection of the fourth N-type doped region 44N on the silicon substrate at least partially overlaps with the orthographic projection of the fourth active ring 24 on the silicon substrate. Therefore, the fourth active ring 24 is an N-type doped ring, which can reduce contact resistance and improve current discharge capability. In an exemplary embodiment, the N-type doped fourth active ring 24 can serve as the second N-type doped guard ring of this disclosure.

[0153] In an exemplary embodiment, the orthogonal projection of the fourth N-type doped region 44N onto the silicon substrate may include the orthogonal projection of the fourth active ring 24 onto the silicon substrate.

[0154] In an exemplary embodiment, the third N-type doped region 43N and the fourth N-type doped region 44N can be interconnected. The doping border of the third N-type doped region 43N near the fourth N-type doped region 44N and the doping border of the fourth N-type doped region 44N near the third N-type doped region 43N can be the same doping border, that is, the third N-type doped region 43N and the fourth N-type doped region 44N can share the same doping border extending along the first direction X.

[0155] (4) Forming a P-type doped (SP) region pattern. In an exemplary embodiment, forming a P-type doped region pattern may include: coating a photoresist on a silicon substrate on which the aforementioned pattern is formed, forming a plurality of opening regions by exposure and development, removing the photoresist in the plurality of opening regions, and forming a P-type doped region pattern in the opening regions by a doping process, as shown in Figures 10A and 10B, where Figure 10B is a schematic diagram of the P-type doped region in Figure 10A.

[0156] In an exemplary embodiment, the P-type doped pattern may be located outside the N-type doped pattern, meaning that the P-type doped region and the N-type doped region are complementary patterns. The P-type doped pattern may include at least a first P-type doped region 41N, a second P-type doped region 42P, a third P-type doped region 43P, and a fourth P-type doped region 44P.

[0157] In an exemplary embodiment, the shape of the first P-type doped region 41N can be a strip shape extending along the first direction X. The orthogonal projections of the 56 first P-type doped regions 41N on the silicon substrate at least partially overlap with the orthogonal projections of the 56 first active regions 11 on the silicon substrate, forming 56 P-type doped first active regions 11. The P-type doped first active regions 11 can serve as the P-type junction region of a diode.

[0158] In an exemplary embodiment, the orthogonal projection of the first P-type doped region 41N onto the silicon substrate may include the orthogonal projection of the first active region 11 onto the silicon substrate.

[0159] In an exemplary embodiment, the shape of the second P-type doped region 42P can be block-shaped (such as rectangular), and the two second P-type doped regions 42P can be arranged sequentially along the second direction Y. The orthogonal projection of the two second P-type doped regions 42P on the silicon substrate and the orthogonal projection of the trigger resistor 83 on the silicon substrate at least partially overlap, forming two trigger resistor doped regions that can serve as polysilicon trigger resistors (rhrpo).

[0160] In an exemplary embodiment, the third P-type doped region 43P may include a first doped sub-region 43A and a second doped sub-region 43B. The first doped sub-region 43A may be annular (e.g., a rectangular ring). The orthographic projection of the first doped sub-region 43A onto the silicon substrate at least partially overlaps with the orthographic projection of the first active sub-ring 21A onto the silicon substrate. Therefore, the first active sub-ring 21A is a P-type doped ring, which can reduce contact trigger resistance and improve current discharge capability. The second doped sub-region 43B may be annular (e.g., a rectangular ring). The orthographic projection of the second doped sub-region 43B onto the silicon substrate at least partially overlaps with the orthographic projection of the second active sub-ring 21B onto the silicon substrate. Therefore, the second active sub-ring 21B is a P-type doped ring, which can reduce contact resistance and improve current discharge capability. The first active sub-ring 21A doped with P-type can be used as the first doped sub-ring 91A of this disclosure, the second active sub-ring 21B doped with P-type can be used as the second doped sub-ring 91B of this disclosure, and the first active ring 21 doped with P-type can be used as the first P-type doped guard ring of this disclosure.

[0161] The exemplary embodiment of this disclosure first uses a P-type doped guard ring to isolate the first circuit and the second circuit, and then uses an N-type doped guard ring to isolate this electrostatic discharge protection device from other electrostatic discharge protection devices, which can effectively prevent latch-up effect caused by silicon substrate bias due to electrostatic discharge spike current.

[0162] (5) Forming a second insulating layer pattern. In an exemplary embodiment, forming a second insulating layer pattern may include: depositing a second insulating film on a silicon substrate on which the aforementioned pattern is formed, and patterning the second insulating film by a patterning process to form a second insulating layer covering the gate conductive layer pattern, wherein a plurality of vias are provided on the second insulating layer, as shown in FIG11.

[0163] In an exemplary embodiment, the plurality of vias may include at least the first via V1 to the twelfth via V12.

[0164] In an exemplary embodiment, the orthogonal projection of the first via V1 onto the silicon substrate may be located within the range of the orthogonal projection of the N-type source region of the third active region 13 onto the silicon substrate. The first insulating layer and the second insulating layer within the first via V1 are etched away, exposing the surface of the N-type source region of the third active region 13. The first via V1 is configured to allow the subsequently formed first connection electrode to be connected to the N-type source region of the third active region 13 through the via.

[0165] In an exemplary embodiment, the orthogonal projection of the second via V2 onto the silicon substrate may be located within the orthogonal projection of the N-type drain region of the third active region 13 onto the silicon substrate. The first and second insulating layers within the second via V2 are etched away, exposing the surface of the N-type drain region of the third active region 13. The second via V2 is configured to allow a subsequently formed second connection electrode to be connected to the N-type drain region of the third active region 13 through the via.

[0166] In an exemplary embodiment, the orthogonal projection of the third via V3 onto the silicon substrate may be located within the range of the orthogonal projection of the first active region 11 onto the silicon substrate. The first and second insulating layers within the third via V3 are etched away, exposing the surface of the first active region 11. The third via V3 is configured to allow a subsequently formed third connection electrode to be connected to the first active region 11 through the via.

[0167] In an exemplary embodiment, the orthogonal projection of the fourth via V4 onto the silicon substrate may be located within the range of the orthogonal projection of the second active region 12 onto the silicon substrate. The first and second insulating layers within the fourth via V4 are etched away, exposing the surface of the second active region 12. The fourth via V4 is configured to allow a subsequently formed fourth connection electrode to be connected to the second active region 12 through the via.

[0168] In an exemplary embodiment, the orthogonal projection of the fifth via V5 onto the silicon substrate may be within the range of the orthogonal projection of the gate connection line 32 onto the silicon substrate. The second insulating layer within the fifth via V5 is etched away, exposing the surface of the gate connection line 32. The fifth via V5 is configured to allow the subsequently formed fifth connection electrode to be connected to the gate connection line 32 through the via.

[0169] In an exemplary embodiment, the orthogonal projection of the sixth via V6 onto the silicon substrate may be located within the range of the orthogonal projection of the first end of the trigger resistor 83 onto the silicon substrate. The second insulating layer within the sixth via V6 is etched away, exposing the surface of the trigger resistor 83. The sixth via V6 is configured to allow the subsequently formed sixth connection electrode to be connected to the first end of the trigger resistor 83 through the via.

[0170] In an exemplary embodiment, the orthogonal projection of the seventh via V7 onto the silicon substrate may be located within the range of the orthogonal projection of the second end of the trigger resistor 83 onto the silicon substrate. The second insulating layer within the seventh via V7 is etched away, exposing the surface of the trigger resistor 83. The seventh via V7 is configured to allow the subsequently formed seventh connection electrode to be connected to the second end of the trigger resistor 83 through the via.

[0171] In an exemplary embodiment, the orthogonal projection of the eighth via V8 onto the silicon substrate may be within the range of the orthogonal projection of the first active sub-ring 21A onto the silicon substrate. The second insulating layer within the eighth via V8 is etched away, exposing the surface of the first active sub-ring 21A. The eighth via V8 is configured to allow the subsequently formed first conductive ring to be connected to the first active sub-ring 21A through the via.

[0172] In an exemplary embodiment, the orthogonal projection of the ninth via V9 onto the silicon substrate may be within the range of the orthogonal projection of the second active sub-ring 21B onto the silicon substrate. The first and second insulating layers within the ninth via V9 are etched away, exposing the surface of the second active sub-ring 21B. The ninth via V9 is configured to allow the subsequently formed first conductive ring to be connected to the second active sub-ring 21B through the via.

[0173] In an exemplary embodiment, the orthogonal projection of the tenth via V10 onto the silicon substrate may be located within the range of the orthogonal projection of the second active ring 22 onto the silicon substrate. The first and second insulating layers within the tenth via V10 are etched away, exposing the surface of the second active ring 22. The tenth via V10 is configured to allow a subsequently formed second conductive ring to be connected to the second active ring 22 through the via.

[0174] In an exemplary embodiment, the orthographic projection of the eleventh via V11 onto the silicon substrate may be within the range of the orthographic projection of the third active ring 23 onto the silicon substrate. The first and second insulating layers within the eleventh via V11 are etched away, exposing the surface of the third active ring 23. The eleventh via V11 is configured to allow the subsequently formed third conductive ring to be connected to the third active ring 23 through the via.

[0175] In an exemplary embodiment, the orthogonal projection of the twelfth via V12 onto the silicon substrate may be within the range of the orthogonal projection of the fourth active ring 24 onto the silicon substrate. The first and second insulating layers within the twelfth via V12 are etched away, exposing the surface of the fourth active ring 24. The twelfth via V12 is configured to allow the subsequently formed fourth conductive ring to be connected to the fourth active ring 24 through the via.

[0176] In an exemplary embodiment, one or more of the first vias V1 to the twelfth vias V12 may be multiple to reduce contact resistance and increase connection reliability.

[0177] (6) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a first conductive thin film on a silicon substrate on which the aforementioned pattern is formed, patterning the first conductive thin film using a patterning process, and forming the first conductive layer pattern on a second insulating layer, as shown in Figures 12A and 12B, where Figure 12B is a schematic diagram of the first conductive layer in Figure 12A. In an exemplary embodiment, the first conductive layer may be referred to as a first metal layer.

[0178] In an exemplary embodiment, the first conductive layer pattern may include at least: a first connecting electrode 101 to a seventh connecting electrode 107.

[0179] In an exemplary embodiment, the first connection electrode 101 can be a strip extending along the second direction Y. Fifteen first connection electrodes 101 can be arranged sequentially in the first direction X. Each of the fifteen first connection electrodes 101 can be connected to an N-type source region of one of the fifteen third active regions 13 via a first via V1. In an exemplary embodiment, the fifteen first connection electrodes 101 can serve as the first electrode of a transistor.

[0180] In an exemplary embodiment, the second connection electrode 102 can be a strip shape extending along the second direction Y. Fourteen second connection electrodes 102 can be arranged sequentially in the first direction X. Each of the fourteen second connection electrodes 102 can be connected to the N-type drain regions of the fourteen third active regions 13 via a second via V2. In an exemplary embodiment, the fourteen second connection electrodes 102 can serve as the second electrode of a transistor.

[0181] In an exemplary embodiment, 15 first connecting electrodes 101 and 14 second connecting electrodes 102 may be alternately arranged in the first direction X. At least one first connecting electrode 101 may be arranged between two adjacent second connecting electrodes 102 in the first direction X, and at least one second connecting electrode 102 may be arranged between two adjacent first connecting electrodes 101 in the first direction X.

[0182] In an exemplary embodiment, the third connecting electrode 103 can be a strip extending along the first direction X. The 56 third connecting electrodes 103 form a 14*4 electrode array. Each of the 56 third connecting electrodes 103 can be connected to one of the 56 first active regions 11 via a third via V3. In another exemplary embodiment, the 56 third connecting electrodes 103 can serve as the first electrode of a diode.

[0183] In an exemplary embodiment, the fourth connecting electrode 104 can be annular (e.g., a rectangular ring) and can be disposed outside each third connecting electrode 103, surrounding the third connecting electrode 103. The 56 fourth connecting electrodes 104 can form a 14*4 electrode array. Adjacent fourth connecting electrodes 104 in the first direction X can be interconnected, and adjacent fourth connecting electrodes 104 in the second direction Y can be interconnected, forming a mesh structure with the 56 interconnected fourth connecting electrodes 104. The 56 fourth connecting electrodes 104 can be respectively connected to 56 second active regions 12 through fourth vias V4. In an exemplary embodiment, the 56 fourth connecting electrodes 104 can serve as the second electrode of a diode.

[0184] In an exemplary embodiment, the fifth connection electrode 105 may be a straight line or a broken line extending along the first direction X, and may be disposed on one side of the plurality of first connection electrodes 101 and the plurality of second connection electrodes 102 in the second direction Y. The fifth connection electrode 105 may be connected to the gate connection line 32 through the fifth via V5.

[0185] In an exemplary embodiment, the sixth connecting electrode 106 may be block-shaped (e.g., rectangular) and may be disposed on one side of the fifth connecting electrode 105 in the first direction X. The sixth connecting electrode 106 may be connected to the first end of the trigger resistor 83 through the sixth via V6.

[0186] In an exemplary embodiment, the seventh connecting electrode 107 may be block-shaped (e.g., rectangular) and may be disposed on one side of the fifth connecting electrode 105 in the first direction X. The seventh connecting electrode 107 may be connected to the second end of the trigger resistor 83 through the seventh via V7.

[0187] In an exemplary embodiment, the first conductive layer pattern may further include a first conductive ring 51, a second conductive ring 52, a third conductive ring 53, and a fourth conductive ring 54.

[0188] In an exemplary embodiment, the first conductive ring 51 may include a first conductive sub-ring 51A and a second conductive sub-ring 51B. The first conductive sub-ring 51A may be annular (e.g., rectangular) in shape, and may be disposed outside and around the plurality of first connecting electrodes 101 and second connecting electrodes 102. The first conductive sub-ring 51A may be connected to the first active sub-ring 21A via an eighth via V8, and is configured as a protective structure for 14 transistors. The second conductive sub-ring 51B may be annular (e.g., rectangular) in shape, and may be disposed on one side of the first conductive sub-ring 51A in the first direction X. The first conductive ring 51A and the second conductive ring 51B are interconnected, and the second conductive ring 51B may be connected to the second active sub-ring 21B via a ninth via V9. The second conductive ring 51B is configured as a protective structure for a trigger resistor.

[0189] In an exemplary embodiment, the conductive frame of the first conductive ring 51A near the second conductive ring 51B and the conductive frame of the second conductive ring 51B near the first conductive ring 51A can be the same conductive frame, that is, the first conductive ring 51A and the second conductive ring 51B can share the same conductive frame extending along the second direction Y.

[0190] In an exemplary embodiment, the conductive frame shared by the first conductive ring 51A and the second conductive ring 51B is also connected to the sixth connecting electrode 106, so that the first end of the trigger resistor 83 and the first conductive ring 51 have the same potential.

[0191] In an exemplary embodiment, the second conductive ring 52 can be annular (e.g., rectangular ring). The second conductive ring 52 can be disposed on one side of the first conductive sub-ring 51 in the second direction Y, and the first conductive sub-ring 51 and the second conductive ring 52 are isolated from each other. The second conductive ring 52 can be disposed outside and surrounding the plurality of third connecting electrodes 103 and the plurality of fourth connecting electrodes 104. The second conductive ring 52 can be connected to the second active ring 22 through the tenth via V10. The second conductive ring 52 is configured as a protective structure for 56 diodes.

[0192] In an exemplary embodiment, the first conductive ring 51A and the second conductive ring 51B can isolate the transistor group and the trigger resistor in the first circuit C1, and the first conductive ring 51 and the second conductive ring 52 can isolate the first circuit C1 and the second circuit C2, which can effectively prevent electrostatic discharge spike current between circuits.

[0193] In an exemplary embodiment, the third conductive ring 53 may be ring-shaped (such as a rectangular ring), may be disposed outside the first conductive sub-ring 51 and surround the first conductive sub-ring 51, and the third conductive ring 53 may be connected to the third active ring 23 through the eleventh via V11. The third conductive ring 53 is configured as a protective structure for the first circuit C1.

[0194] In an exemplary embodiment, the fourth conductive ring 54 can be annular (e.g., rectangular ring) in shape, and can be disposed on one side of the third conductive ring 53 in the second direction Y, with the third conductive ring 53 and the fourth conductive ring 54 interconnected. The fourth conductive ring 54 can be disposed outside the second conductive ring 52 and surround the second conductive ring 52. The fourth conductive ring 54 can be connected to the fourth active ring 24 through the twelfth via V12, and the fourth conductive ring 54 is configured as a protective structure for the second circuit C2.

[0195] In an exemplary embodiment, the third conductive ring 53 and the fourth conductive ring 54 can be interconnected. The conductive frame of the third conductive ring 53 near the fourth conductive ring 54 and the conductive frame of the fourth conductive ring 54 near the third conductive ring 53 can be the same conductive frame, that is, the third conductive ring 53 and the fourth conductive ring 54 can share the same conductive frame extending along the first direction X.

[0196] In an exemplary embodiment, at least three conductive borders may be provided between the transistor group and the diode group in the second direction Y. The three conductive borders may be the conductive border on the side of the first conductive ring 51 closer to the second conductive ring 52, the conductive border on the side of the second conductive ring 52 closer to the first conductive ring 51, and the conductive border shared by the third conductive ring 53 and the fourth conductive ring 54.

[0197] In an exemplary embodiment, the third conductive ring 53 and the fourth conductive ring 54 can isolate this electrostatic discharge protection device from other electrostatic discharge protection devices, and can effectively shield the electrostatic discharge spike current between electrostatic discharge protection devices.

[0198] (7) Forming a third insulating layer pattern. In an exemplary embodiment, forming a third insulating layer pattern may include: depositing a third insulating film on a silicon substrate on which the aforementioned pattern is formed, and patterning the third insulating film by a patterning process to form a third insulating layer covering the pattern of the first conductive layer, wherein a plurality of vias are provided on the third insulating layer, as shown in FIG13.

[0199] In an exemplary embodiment, the plurality of vias may include vias V21 to V35.

[0200] In an exemplary embodiment, the orthographic projection of the 21st via V21 onto the silicon substrate may be within the range of the orthographic projection of the first connection electrode 101 onto the silicon substrate. The third insulating layer within the 21st via V21 is etched away, exposing the surface of the first connection electrode 101. The 21st via V21 is configured to allow the subsequently formed 11th connection electrode to be connected to the first connection electrode 101 through the via.

[0201] In an exemplary embodiment, the orthogonal projection of the 22nd via V22 onto the silicon substrate may be within the range of the orthogonal projection of the second connection electrode 102 onto the silicon substrate. The third insulating layer within the 22nd via V22 is etched away, exposing the surface of the second connection electrode 102. The 22nd via V22 is configured to allow the subsequently formed 12th connection electrode to be connected to the second connection electrode 102 through the via.

[0202] In an exemplary embodiment, the orthogonal projection of the 23rd via V23 onto the silicon substrate may be located within the range of the orthogonal projection of the third connection electrode 103 onto the silicon substrate. The third insulating layer within the 23rd via V23 is etched away, exposing the surface of the third connection electrode 103. The 23rd via V23 is configured to allow the subsequently formed 13th connection electrode to be connected to the third connection electrode 103 through the via.

[0203] In an exemplary embodiment, the orthographic projection of the 24th via V24 onto the silicon substrate may be within the range of the orthographic projection of the fourth connection electrode 104 onto the silicon substrate. The third insulating layer within the 24th via V24 is etched away, exposing the surface of the fourth connection electrode 104. The 24th via V24 is configured to allow the subsequently formed 14th connection electrode to be connected to the fourth connection electrode 104 through the via.

[0204] In an exemplary embodiment, the orthographic projection of the 25th via V25 onto the silicon substrate may be within the range of the orthographic projection of the fifth connection electrode 105 onto the silicon substrate. The third insulating layer within the 25th via V25 is etched away, exposing the surface of the fifth connection electrode 105. The 25th via V25 is configured to allow the subsequently formed 15th connection electrode to be connected to the fifth connection electrode 105 through the via.

[0205] In an exemplary embodiment, the orthographic projection of the 26th via V26 onto the silicon substrate may be within the range of the orthographic projection of the 7th connection electrode 107 onto the silicon substrate. The third insulating layer within the 26th via V26 is etched away, exposing the surface of the 7th connection electrode 107. The 26th via V26 is configured to allow the subsequently formed 15th connection electrode to be connected to the 7th connection electrode 107 through the via.

[0206] In an exemplary embodiment, the orthogonal projection of the 27th via V27 onto the silicon substrate can be located within the range of the orthogonal projection of the conductive frame on the opposite side of the first conductive ring 51A in the first direction X onto the silicon substrate. The third insulating layer within the 27th via V27 is etched away, exposing the surface of the conductive frame on the opposite side of the first conductive ring 51A in the first direction X. The 27th via V27 is configured to allow the subsequently formed 16th connection electrode to be connected to the conductive frame on the opposite side of the first conductive ring 51A in the first direction X through the via.

[0207] In an exemplary embodiment, the orthographic projection of the 28th via V28 onto the silicon substrate can be located within the range of the orthographic projection of the conductive frame on the first direction X side of the first conductive ring 51A onto the silicon substrate. The third insulating layer within the 28th via V28 is etched away, exposing the surface of the conductive frame on the first direction X side of the first conductive ring 51A. The 28th via V28 is configured to allow the subsequently formed 16th connection electrode to be connected to the conductive frame on the first direction X side of the first conductive ring 51A through the via.

[0208] In an exemplary embodiment, the orthographic projection of the 29th via V29 onto the silicon substrate can be located within the range of the orthographic projection of the conductive frame on the first direction X side of the second conductive ring 51B onto the silicon substrate. The third insulating layer within the 29th via V29 is etched away, exposing the surface of the conductive frame on the first direction X side of the second conductive ring 51B. The 29th via V29 is configured to allow the subsequently formed 17th connection electrode to be connected to the conductive frame on the first direction X side of the second conductive ring 51B through the via.

[0209] In an exemplary embodiment, the orthogonal projection of the thirtieth via V30 onto the silicon substrate can be located within the range of the orthogonal projection of the frame on the opposite side of the second conductive ring 52 in the second direction Y onto the silicon substrate. The third insulating layer within the thirtieth via V30 is etched away, exposing the surface of the conductive frame on the opposite side of the second conductive ring 52 in the second direction Y. The thirtieth via V30 is configured to allow the subsequently formed eighteenth connection electrode to be connected to the conductive frame on the opposite side of the second conductive ring 52 in the second direction Y through the via.

[0210] In an exemplary embodiment, the orthographic projection of the 31st via V31 onto the silicon substrate can be located within the range of the orthographic projection of the conductive frame on the second Y side of the second conductive ring 52 onto the silicon substrate. The third insulating layer within the 31st via V31 is etched away, exposing the surface of the conductive frame on the second Y side of the second conductive ring 52. The 31st via V31 is configured to allow the subsequently formed 18th connection electrode to be connected to the conductive frame on the second Y side of the second conductive ring 52 through the via.

[0211] In an exemplary embodiment, the orthogonal projection of the 32nd via V32 onto the silicon substrate can be located within the range of the orthogonal projection of the conductive frame on the opposite side of the second direction Y of the fourth conductive ring 54 onto the silicon substrate. The third insulating layer within the 32nd via V32 is etched away, exposing the surface of the conductive frame on the opposite side of the second direction Y of the fourth conductive ring 54. The 32nd via V32 is configured to allow the subsequently formed 19th connection electrode to be connected to the conductive frame on the opposite side of the second direction Y of the fourth conductive ring 54 through the via.

[0212] In an exemplary embodiment, the orthographic projection of the 33rd via V33 onto the silicon substrate can be located within the range of the orthographic projection of the conductive frame on the second direction Y side of the fourth conductive ring 54 onto the silicon substrate. The third insulating layer within the 33rd via V33 is etched away, exposing the surface of the conductive frame on the second direction Y side of the fourth conductive ring 54. The 33rd via V33 is configured to allow the subsequently formed 19th connection electrode to be connected to the conductive frame on the second direction Y side of the fourth conductive ring 54 through the via.

[0213] In an exemplary embodiment, the orthogonal projection of the 34th via V34 onto the silicon substrate can be located within the range of the orthogonal projection of the conductive frame on the opposite side of the first direction X of the fourth conductive ring 54 onto the silicon substrate. The third insulating layer within the 34th via V34 is etched away, exposing the surface of the conductive frame on the opposite side of the first direction X of the fourth conductive ring 54. The 34th via V34 is configured to allow the subsequently formed 20th connection electrode to be connected to the conductive frame on the opposite side of the first direction X of the fourth conductive ring 54 through the via.

[0214] In an exemplary embodiment, the orthographic projection of the 35th via V35 onto the silicon substrate can be located within the range of the orthographic projection of the conductive frame on the first direction X side of the fourth conductive ring 54 onto the silicon substrate. The third insulating layer within the 35th via V35 is etched away, exposing the surface of the conductive frame on the first direction X side of the fourth conductive ring 54. The 35th via V35 is configured to allow the subsequently formed 20th connection electrode to be connected to the conductive frame on the first direction X side of the fourth conductive ring 54 through the via.

[0215] In an exemplary embodiment, one or more of the twenty-first vias V21 to the thirty-fifth via V35 may be multiple to reduce contact resistance and increase connection reliability.

[0216] (8) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: depositing a second conductive film on a silicon substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process, and forming the second conductive layer pattern on a third insulating layer, as shown in Figures 14A and 14B, where Figure 14B is a schematic diagram of the second conductive layer in Figure 14A. In an exemplary embodiment, the second conductive layer may be referred to as a second metal (Metal2) layer.

[0217] In an exemplary embodiment, the second conductive layer pattern may include at least: the eleventh connecting electrode 111 to the twentieth connecting electrode 120.

[0218] In an exemplary embodiment, the eleventh connecting electrode 111 can be a strip shape extending along the second direction Y. The 15 eleventh connecting electrodes 111 can be arranged sequentially in the first direction X. The 15 eleventh connecting electrodes 111 can be connected to the 15 first connecting electrodes 101 respectively through the twenty-first via V21.

[0219] In an exemplary embodiment, the twelfth connecting electrode 112 can be a strip shape extending along the second direction Y, and the 14 twelfth connecting electrodes 112 can be arranged sequentially in the first direction X. The 14 second connecting electrodes 112 can be respectively connected to the 14 second connecting electrodes 102 through the twelfth via V22.

[0220] In an exemplary embodiment, 15 eleventh connecting electrodes 111 and 14 twelfth connecting electrodes 112 may be alternately arranged in the first direction X. At least one eleventh connecting electrode 111 may be arranged between two adjacent twelfth connecting electrodes 112 in the first direction X, and at least one twelfth connecting electrode 112 may be arranged between two adjacent eleventh connecting electrodes 111 in the first direction X.

[0221] In an exemplary embodiment, the thirteenth connecting electrode 113 can be a strip shape extending along the first direction X. The 56 thirteenth connecting electrodes 113 form a 14*4 electrode array. The 56 thirteenth connecting electrodes 113 can be respectively connected to the 56 third connecting electrodes 103 through the twenty-third via V23.

[0222] In an exemplary embodiment, the fourteenth connecting electrode 114 can be annular (e.g., a rectangular ring) in shape, and can be disposed outside each thirteenth connecting electrode 113, surrounding the thirteenth connecting electrode 113. The 56 fourteenth connecting electrodes 114 can form a 14*4 electrode array. Adjacent fourteenth connecting electrodes 114 in the first direction X can be interconnected, and adjacent fourteenth connecting electrodes 114 in the second direction Y can be interconnected, forming a mesh structure with the 56 interconnected fourteenth connecting electrodes 114 forming a single integrated structure. The 56 fourteenth connecting electrodes 114 can be respectively connected to the 56 fourth connecting electrodes 104 through the twenty-fourth via V24.

[0223] In an exemplary embodiment, the fifteenth connecting electrode 115 can be a straight line or a broken line extending along the first direction X, and can be disposed on one side of the plurality of eleventh connecting electrodes 111 and the plurality of twelfth connecting electrodes 112 along the second direction Y. The fifteenth connecting electrode 115 can be connected to the fifth connecting electrode 105 through the twenty-fifth via V25, and to the seventh connecting electrode 107 through the twenty-sixth via V26. Since the seventh connecting electrode 107 is connected to the second end of the trigger resistor 83 through the via, the second end of the trigger resistor 83 and the fifteenth connecting electrode 115 have the same potential.

[0224] In an exemplary embodiment, the sixteenth connecting electrode 116 can be a strip shape extending along the second direction Y. Two sixteenth connecting electrodes 116 can be respectively disposed on both sides of a plurality of eleventh connecting electrodes 111 and a plurality of twelfth connecting electrodes 112 in the first direction X. One sixteenth connecting electrode 116 can be connected to the conductive frame on the opposite side of the first conductive ring 51A in the first direction X through the twenty-seventh through hole V27, and the other sixteenth connecting electrode 116 can be connected to the conductive frame on the first conductive ring 51A in the first direction X through the twenty-eighth through hole V28.

[0225] In an exemplary embodiment, the seventeenth connecting electrode 117 can be a strip extending along the second direction Y, and can be disposed on one side of the sixteenth connecting electrode 116 in the first direction X. The seventeenth connecting electrode 117 can be connected to the conductive frame of the second conductive ring 51B on the first direction X side through the twenty-ninth through-hole V29. Since the first conductive ring 51A and the second conductive ring 51B are interconnected, the sixteenth connecting electrode 116 and the seventeenth connecting electrode 117 have the same potential.

[0226] In an exemplary embodiment, the shape of the eighteenth connecting electrode 118 can be a straight line or a broken line extending along the first direction X. The two eighteenth connecting electrodes 118 can be respectively disposed on both sides of the plurality of thirteenth connecting electrodes 113 and the plurality of fourteenth connecting electrodes 114 in the second direction Y. One eighteenth connecting electrode 118 can be connected to the conductive frame on the opposite side of the second conductive ring 52 in the second direction Y through the thirtieth through hole V30, and the other eighteenth connecting electrode 118 can be connected to the conductive frame on the second conductive ring 52 in the second direction Y through the thirtieth through hole V31.

[0227] In an exemplary embodiment, the nineteenth connecting electrode 119 can be a straight line or a broken line extending along the first direction X. The two nineteenth connecting electrodes 119 can be respectively disposed on the side of the two eighteenth connecting electrodes 118 away from the plurality of fourteenth connecting electrodes 114. One nineteenth connecting electrode 119 can be connected to the conductive frame on the opposite side of the second direction Y of the fourth conductive ring 54 through the thirty-second through hole V32. The other nineteenth connecting electrode 119 can be connected to the conductive frame on the second direction Y side of the fourth conductive ring 54 through the thirty-third through hole V33.

[0228] In an exemplary embodiment, the twentieth connecting electrode 120 can be a strip shape extending along the second direction Y. The two twentieth connecting electrodes 120 can be respectively disposed on both sides of the plurality of thirteenth connecting electrodes 113 and the plurality of fourteenth connecting electrodes 114 in the first direction X. One twentieth connecting electrode 120 can be connected to the conductive frame on the opposite side of the first direction X of the fourth conductive ring 54 through the thirty-fourth through hole V34, and the other twentieth connecting electrode 120 can be connected to the conductive frame on the first direction X side of the fourth conductive ring 54 through the thirty-fifth through hole V35.

[0229] In an exemplary embodiment, the two twentieth connection electrodes 120 may be connected to a plurality of fourteenth connection electrodes 114, respectively.

[0230] In an exemplary embodiment, the plurality of fourteenth connecting electrodes 114 and the two twentieth connecting electrodes 120 may be an integral structure interconnected with each other.

[0231] In an exemplary embodiment, since the nineteenth connecting electrode 119 and the twentieth connecting electrode 120 are both connected to the fourth conductive ring 54 through vias, and the fourteenth connecting electrode 114 is connected to the twentieth connecting electrode 120, the fourteenth connecting electrode 114, the nineteenth connecting electrode 119 and the twentieth connecting electrode 120 have the same potential.

[0232] (9) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming a fourth insulating layer pattern may include: depositing a fourth insulating film on a silicon substrate on which the aforementioned pattern is formed, and patterning the fourth insulating film by a patterning process to form a fourth insulating layer covering the pattern of the second conductive layer, wherein a plurality of vias are provided on the fourth insulating layer, as shown in FIG15.

[0233] In an exemplary embodiment, the plurality of vias may include vias V41 to V48.

[0234] In an exemplary embodiment, the orthographic projection of the forty-first via V41 on the silicon substrate may be within the range of the orthographic projection of the eleventh connection electrode 111 on the silicon substrate. The fourth insulating layer in the forty-first via V41 is etched away, exposing the surface of the eleventh connection electrode 111. The forty-first via V41 is configured to allow the subsequently formed first connection line to be connected to the eleventh connection electrode 111 through the via.

[0235] In an exemplary embodiment, the orthogonal projection of the forty-second via V42 on the silicon substrate may be within the range of the orthogonal projection of the twelfth connecting electrode 112 on the silicon substrate. The fourth insulating layer within the forty-second via V42 is etched away, exposing the surface of the twelfth connecting electrode 112. The forty-second via V42 is configured to allow a subsequently formed second connecting line to be connected to the twelfth connecting electrode 112 through the via.

[0236] In an exemplary embodiment, the orthogonal projection of the forty-third via V43 onto the silicon substrate may be within the range of the orthogonal projection of the thirteenth connecting electrode 113 onto the silicon substrate. The fourth insulating layer within the forty-third via V43 is etched away, exposing the surface of the thirteenth connecting electrode 113. The forty-third via V43 is configured to allow a subsequently formed third connecting line to be connected to the thirteenth connecting electrode 113 through the via.

[0237] In an exemplary embodiment, the orthographic projection of the forty-fourth via V44 onto the silicon substrate may be within the range of the orthographic projection of the fourteenth connection electrode 114 onto the silicon substrate. The fourth insulating layer within the forty-fourth via V44 is etched away, exposing the surface of the fourteenth connection electrode 114. The forty-fourth via V44 is configured to allow the subsequently formed fourth connection line to be connected to the fourteenth connection electrode 114 through the via.

[0238] In an exemplary embodiment, the orthographic projection of the forty-fifth via V45 onto the silicon substrate may be within the range of the orthographic projection of the sixteenth connection electrode 116 onto the silicon substrate. The fourth insulating layer within the forty-fifth via V45 is etched away, exposing the surface of the sixteenth connection electrode 116. The forty-fifth via V45 is configured to allow a subsequently formed first connection line to be connected to the sixteenth connection electrode 116 through the via.

[0239] In an exemplary embodiment, the orthographic projection of the forty-sixth via V46 onto the silicon substrate may be within the range of the orthographic projection of the seventeenth connection electrode 117 onto the silicon substrate. The fourth insulating layer within the forty-sixth via V46 is etched away, exposing the surface of the seventeenth connection electrode 117. The forty-sixth via V46 is configured to allow a subsequently formed first connection line to be connected to the seventeenth connection electrode 117 through the via.

[0240] In an exemplary embodiment, the orthographic projection of the forty-seventh via V47 onto the silicon substrate may be within the range of the orthographic projection of the eighteenth connecting electrode 118 onto the silicon substrate. The fourth insulating layer within the forty-seventh via V47 is etched away, exposing the surface of the eighteenth connecting electrode 118. The forty-seventh via V47 is configured to allow a subsequently formed third connecting line to be connected to the eighteenth connecting electrode 118 through the via.

[0241] In an exemplary embodiment, the orthographic projection of the forty-eighth via V48 onto the silicon substrate may be within the range of the orthographic projection of the nineteenth connection electrode 119 onto the silicon substrate. The fourth insulating layer within the forty-eighth via V48 is etched away, exposing the surface of the nineteenth connection electrode 119. The forty-eighth via V48 is configured to allow the subsequently formed fourth connection line to be connected to the nineteenth connection electrode 119 through the via.

[0242] In an exemplary embodiment, one or more of the forty-first vias V41 to forty-eighth vias V48 may be multiple to reduce contact resistance and increase connection reliability.

[0243] (10) Forming a third conductive layer pattern. In an exemplary embodiment, forming a third conductive layer pattern may include: depositing a third conductive film on a silicon substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process, and forming the third conductive layer pattern on a fourth insulating layer, as shown in Figures 16A and 16B, where Figure 16B is a schematic diagram of the third conductive layer in Figure 16A. In an exemplary embodiment, the third conductive layer may be referred to as a third metal (Metal3) layer.

[0244] In an exemplary embodiment, the third conductive layer pattern may include at least: a first connecting line 61, a second connecting line 62, a third connecting line 63, and a fourth connecting line 64.

[0245] In an exemplary embodiment, the first connecting line 61 can be a strip shape extending along the first direction X. The first connecting line 61 is connected to 15 eleventh connecting electrodes 111 through the forty-first via V41, connected to 2 sixteenth connecting electrodes 116 through the forty-fifth via V45, and connected to the seventeenth connecting electrode 117 through the forty-sixth via V46.

[0246] In an exemplary embodiment, the second connecting line 62 may be a strip shape extending along the first direction X, and may be disposed on one side of the first connecting line 61 in the second direction Y. The second connecting line 62 may be connected to the 14 twelfth connecting electrodes 112 through the forty-second via V42.

[0247] In an exemplary embodiment, the third connecting line 63 can be a strip extending along the second direction Y. Eight third connecting lines 63 can be arranged sequentially in the first direction X, positioned on one side of the second connecting line 62 in the second direction Y, and all connected to the second connecting line 62. The eight third connecting lines 63 can be connected to 56 thirteenth connecting electrodes 113 respectively through the forty-third via V43, and can also be connected to two eighteenth connecting electrodes 118 respectively through the forty-seventh via V47.

[0248] In an exemplary embodiment, the fourth connecting line 64 can be a strip extending along the second direction Y. Eight fourth connecting lines 64 can be arranged sequentially in the first direction X, positioned on one side of the second connecting line 62 in the second direction Y, and all spaced a distance from the second connecting line 62. The eight fourth connecting lines 64 can be connected to 56 fourteenth connecting electrodes 114 via a forty-fourth via V44, and can also be connected to two nineteenth connecting electrodes 119 via a forty-eighth via V48.

[0249] In an exemplary embodiment, the third connecting line 63 is configured to connect to the subsequently formed grounding line, and the fourth connecting line 64 is configured to connect to the subsequently formed first power line. The third connecting line 63 and the fourth connecting line 64 can be alternately arranged in the first direction X to form a symmetrical arrangement structure of power lines and grounding lines. This not only ensures the wiring width of the electrostatic protection device, but also ensures uniform metal discharge, effectively improving the heat dissipation effect and maximizing the discharge area while keeping the area of ​​the electrostatic protection device as small as possible.

[0250] (11) Forming a fifth insulating layer pattern. In an exemplary embodiment, forming a fifth insulating layer pattern may include: depositing a fifth insulating film on a silicon substrate on which the aforementioned pattern is formed, and patterning the fifth insulating film by a patterning process to form a fifth insulating layer covering the pattern of the third conductive layer, wherein a plurality of vias are provided on the fifth insulating layer, as shown in FIG17.

[0251] In an exemplary embodiment, the plurality of vias may include vias V51 to V54.

[0252] In an exemplary embodiment, the orthographic projection of the 51st via V51 onto the silicon substrate may be within the range of the orthographic projection of the first connection line 61 onto the silicon substrate. The fifth insulating layer within the 51st via V51 is etched away, exposing the surface of the first connection line 61. The 51st via V51 is configured to allow a subsequently formed second power line to be connected to the first connection line 61 through the via.

[0253] In an exemplary embodiment, the orthographic projection of the 52nd via V52 onto the silicon substrate may be within the range of the orthographic projection of the second connection line 62 onto the silicon substrate. The fifth insulating layer within the 52nd via V52 is etched away, exposing the surface of the second connection line 62. The 52nd via V52 is configured to allow a subsequently formed first ground wire to be connected to the second connection line 62 through the via.

[0254] In an exemplary embodiment, the orthographic projection of the 53rd via V53 onto the silicon substrate may be within the range of the orthographic projection of the third connection line 63 onto the silicon substrate. The fifth insulating layer within the 53rd via V53 is etched away, exposing the surface of the third connection line 63. The 53rd via V53 is configured to allow a subsequently formed second grounding wire to be connected to the third connection line 63 through the via.

[0255] In an exemplary embodiment, the orthographic projection of the 54th via V54 onto the silicon substrate may be within the range of the orthographic projection of the fourth connection line 64 onto the silicon substrate. The fifth insulating layer within the 54th via V54 is etched away, exposing the surface of the fourth connection line 64. The 54th via V54 is configured to allow a subsequently formed first power line to be connected to the fourth connection line 64 through the via.

[0256] In an exemplary embodiment, one or more of the fifty-first vias V51 to the fifty-fourth via V54 may be multiple to reduce contact resistance and increase connection reliability.

[0257] (12) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming a fourth conductive layer pattern may include: depositing a fourth conductive thin film on a silicon substrate on which the aforementioned pattern is formed, patterning the fourth conductive thin film using a patterning process, and forming the fourth conductive layer pattern on a fifth insulating layer, as shown in Figures 18A and 18B, where Figure 18B is a schematic diagram of the fourth conductive layer in Figure 18A. In an exemplary embodiment, the fourth conductive layer may be referred to as a fourth metal layer (Metal4).

[0258] In an exemplary embodiment, the fourth conductive layer pattern may include at least: a first power line 71, a second power line 72, a first ground line 73, and a second ground line 74.

[0259] In an exemplary embodiment, the first power line 71 can be a strip extending along the first direction X. The first power line 71 can be connected to the fourth connecting line 64 through the fifty-fourth via V54, thus the fourth connecting line 64 has the potential of the first power line. Since the fourth connecting line 64 is connected to the fourteenth connecting electrode 114 and the nineteenth connecting electrode 119 through vias, the fourteenth connecting electrode 114 and the nineteenth connecting electrode 119 have the potential of the first power line. Since the fourteenth connecting electrode 114 is connected to the fourth connecting electrode 104 through a via, and the fourth connecting electrode 104 is connected to the second active region 12 through a via, the second electrode of the diode has the potential of the first power line. Since the nineteenth connecting electrode 119 is connected to the fourth conductive ring 54 through a via, and the fourth conductive ring 54 is connected to the third conductive ring 53, the third conductive ring 53 and the fourth conductive ring 54 have the potential of the first power line, which can isolate this electrostatic discharge protection device from other electrostatic discharge protection devices and effectively shield the electrostatic discharge spike current between electrostatic discharge protection devices.

[0260] In an exemplary embodiment, a plurality of first openings K1 may be provided on the first power line 71.

[0261] In an exemplary embodiment, the second power line 72 can be a strip extending along the first direction X. The second power line 72 can be connected to the first connecting line 61 through the fifty-first via V51, thus the first connecting line 61 has the potential of the second power line. Since the first connecting line 61 is connected to the eleventh connecting electrode 111, the sixteenth connecting electrode 116, and the seventeenth connecting electrode 117 through vias, the eleventh connecting electrode 111, the sixteenth connecting electrode 116, and the seventeenth connecting electrode 117 have the potential of the second power line. Since the eleventh connecting electrode 111 is connected to the first connecting electrode 101 through a via, and the first connecting electrode 101 is connected to the N-type source region of the third active region 13 through a via, the first electrode of the N-type transistor has the potential of the second power line. Since the sixteenth connecting electrode 116 is connected to the first conductive ring 51A through a via, and the seventeenth connecting electrode 117 is connected to the second conductive ring 51B through a via, the first conductive ring 51A and the second conductive ring 51B have the potential of the second power line. Since the second conductive electronic ring 51B is connected to the sixth connecting electrode 106, and the sixth connecting electrode 106 is connected to the first end of the trigger resistor 83 through a via, the first end of the trigger resistor 83 has the potential of the second power line.

[0262] In an exemplary embodiment, the first ground wire 73 can be a strip extending along the first direction X. The first ground wire 73 can be connected to the second connection wire 62 through the 52nd via V52, thus the second connection wire 62 has the potential of the ground wire. Since the second connection wire 62 is connected to the 12th connection electrode 112 through a via, the 12th connection electrode 112 is connected to the second connection electrode 102 through a via, and the second connection electrode 102 is connected to the N-type drain region of the third active region 13 through a via, the second electrode of the N-type transistor has the potential of the ground wire.

[0263] In an exemplary embodiment, the second grounding wire 74 can be a strip extending along the first direction X. The second grounding wire 74 can be connected to the third connecting wire 63 via the fifty-third via V53, thus the third connecting wire 63 has a grounding potential. Since the third connecting wire 63 is connected to the thirteenth connecting electrode 113 and the eighteenth connecting electrode 118 vias, the thirteenth connecting electrode 113 and the eighteenth connecting electrode 118 have grounding potentials. Since the thirteenth connecting electrode 113 is connected to the third connecting electrode 103 via a via, and the third connecting electrode 103 is connected to the first active region 11 via a via, the first electrode of the diode has a grounding potential. Since the eighteenth connecting electrode 118 is connected to the second conductive ring 52 via a via, the second conductive ring 52 has a grounding potential.

[0264] In an exemplary embodiment, a plurality of second openings K2 may be provided on the second grounding wire 74.

[0265] In an exemplary embodiment, the first grounding wire 73 may be disposed on one side of the second power line 72 in the second direction Y, the first power line 71 may be disposed on one side of the first grounding wire 73 in the second direction Y, and the second grounding wire 74 may be disposed on one side of the first power line 71 in the second direction Y. That is, the second power line 72, the first grounding wire 73, the first power line 71 and the second grounding wire 74 are arranged sequentially along the second direction Y.

[0266] In an exemplary embodiment, the first grounding wire 73 and the second grounding wire 74 have the same grounding potential and can be collectively referred to as grounding wires.

[0267] In an exemplary embodiment, the gate electrodes of 14 transistors are interconnected via gate connection line 32. The first electrode of each of the 14 transistors has the potential of the second power line, and the second electrode of each of the 14 transistors has the potential of the ground line. Thus, the 14 transistors are connected in parallel to form a transistor group. The width-to-length ratio of the transistor group is 14 times that of a single transistor, which can meet the requirements for electrostatic current discharge.

[0268] In an exemplary embodiment, the first terminals of all 56 diodes have the potential of the ground wire, and the second terminals of all 56 diodes have the potential of the first power line. This achieves parallel connection of the 56 diodes, forming a diode group that can meet the requirements for discharging electrostatic current.

[0269] In an exemplary embodiment, since the gate electrodes of the 14 transistors are interconnected through the gate connection line 32, the gate connection line 32 is connected to the fifth connection electrode 105 through a via, the fifth connection electrode 105 is connected to the seventh connection electrode 107 through the fifteenth connection electrode 115, and the seventh connection electrode 107 is connected to the second end of the trigger resistor 83 through a via, the connection between the gate electrodes of the 14 transistors and the second end of the trigger resistor 83 is realized.

[0270] In an exemplary embodiment, the first end of the trigger resistor 83 has the potential of the second power line, and the second end of the trigger resistor 83 has the potential of the gate electrode of the transistor.

[0271] This completes the fabrication of the electrostatic protection device of the exemplary embodiments of this disclosure.

[0272] In an exemplary embodiment, the first to fifth insulating layers can be silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON), etc., and can be a single-layer structure or a multi-layer composite structure. The first to fourth conductive layers can be made of metallic materials, such as silver (Ag), copper (Cu), aluminum (Al), or molybdenum (Mo), etc., or can be made of alloy materials composed of metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), etc. The alloy material can be a single-layer structure or a multi-layer composite structure, such as a composite structure composed of Mo, Cu, and Mo layers, etc. In an exemplary embodiment, the planar shape of the via can be rectangular, circular, or elliptical, etc., and the dimensions of multiple vias can be substantially the same or different; this disclosure does not limit this.

[0273] An exemplary embodiment of this disclosure provides an electrostatic discharge (ESD) protection device that can be installed in a non-display area to protect driver board pads, display driver circuit pads, and test pads via voltage triggering.

[0274] This disclosure isolates the transistors and diodes by setting a first P-type doped protective ring and a second P-type doped protective ring, placing the transistor group and trigger resistor within the space surrounded by the first P-type doped protective ring, and placing the diode group within the space surrounded by the second P-type doped protective ring. This not only effectively prevents crosstalk between the transistors and diodes and improves anti-interference capability, but also effectively prevents latch-up effect caused by silicon substrate bias due to electrostatic discharge spike current, thus avoiding failure of the electrostatic protection device.

[0275] This disclosure, by setting a first doped sub-ring and a second doped sub-ring, with the transistor group located within the space surrounded by the first doped sub-ring and the trigger resistor located within the space surrounded by the second doped sub-ring, separates the transistor and the trigger resistor, thereby further preventing the electrostatic discharge protection device from failing.

[0276] This disclosure, by setting a first N-type doped protective ring and a second N-type doped protective ring, with the first P-type doped protective ring disposed within the space surrounded by the first N-type doped protective ring and the second P-type doped protective ring disposed within the space surrounded by the second N-type doped protective ring, uses the P-type doped protective ring to isolate the transistor and diode, and uses the N-type doped protective ring to isolate this electrostatic discharge protection device from other electrostatic discharge protection devices, which can further effectively shield the electrostatic discharge spike current between electrostatic discharge protection devices.

[0277] By placing the trigger resistor close to the gate connection line, this disclosure facilitates the connection between the gate connection line and the trigger resistor using a shorter connection electrode, which helps reduce the area occupied by the trigger device while ensuring the accuracy of the trigger resistor.

[0278] This disclosure reduces mutual interference between transistor groups and diode groups and improves anti-interference capability by setting the spacing between transistor groups and diode groups to be greater than the spacing between transistor groups and trigger resistors.

[0279] This disclosure further reduces mutual interference between the transistor group and the diode group by setting at least three protective borders between them, thereby further improving the anti-interference capability.

[0280] This disclosure, by setting a symmetrical arrangement of power supply and grounding lines, not only ensures the width of the electrostatic discharge device's wiring but also ensures uniform metal discharge, effectively improving heat dissipation and maximizing the discharge area while keeping the electrostatic discharge device area as small as possible.

[0281] This disclosure optimizes the layout of the electrostatic discharge (ESD) protection device through the above-described structural design, optimizes the layout space, reduces the area occupied by the ESD protection device, and improves circuit quality and signal quality. It can be applied to various pad types, functions, pitches, voltage values, power-on times, and quantities in silicon-based OLEDs.

[0282] The preparation process disclosed herein can be achieved using mature preparation equipment, requires minimal process modification, has high compatibility, is simple to implement, is easy to carry out, has high production efficiency, low production cost, and high yield.

[0283] The structure and fabrication process of the electrostatic protection device of the exemplary embodiments disclosed herein are merely illustrative examples. The corresponding structure and the patterning process may be modified or increased or decreased according to the actual situation. This disclosure does not limit the scope of the invention.

[0284] An exemplary embodiment of this disclosure also provides a display substrate, which may include a display area and a non-display area. The display area may include a plurality of sub-pixels, at least one sub-pixel including a pixel driving circuit and a light-emitting device connected to the pixel driving circuit, and the non-display area may include at least one of the aforementioned electrostatic discharge protection devices.

[0285] This exemplary embodiment also provides a display device including the aforementioned display substrate. The display device of this disclosure can be used in virtual reality (VR) devices, augmented reality (AR) devices, extended reality (XR) devices, mixed reality (MR) devices, sights, rangefinders, etc.

[0286] While the embodiments disclosed herein are as described above, it should be noted that these embodiments are merely exemplary and not restrictive. Therefore, this disclosure is not limited to the specific content shown and described herein. Various modifications, substitutions, or omissions can be made to the form and details of the embodiments without departing from the scope of this disclosure.

Claims

1. An electrostatic discharge (ESD) protection device, comprising a transistor group, a diode group, and a trigger resistor, wherein the transistor group comprises a plurality of transistors connected in parallel, the diode group comprises a plurality of diodes connected in parallel, a first terminal of the transistor and a first terminal of the trigger resistor are connected to a second power supply line, a second terminal of the trigger resistor is connected to the gate electrode of the transistor, a second terminal of the transistor and a first terminal of the diode are connected to a ground line, a second terminal of the diode is connected to a first power supply line, the trigger resistor is disposed on one side of the transistor group in a first direction, the diode group is disposed on one side of the transistor group in a second direction, the first direction and the second direction intersect; the ESD protection device further comprises a first P-type doped protective ring, the first P-type doped protective ring being ring-shaped and connected to the second power supply line, and the transistor group and the trigger resistor being disposed within the space surrounded by the first P-type doped protective ring.

2. The electrostatic discharge protection device of claim 1, wherein, The first P-type doped guard ring includes at least a first doped sub-ring and a second doped sub-ring. The first doped sub-ring and the second doped sub-ring are ring-shaped. The second doped sub-ring is disposed on one side of the first doped sub-ring in the first direction and is connected to the first doped sub-ring. The transistor group is disposed in the space surrounded by the first doped sub-ring, and the trigger resistor is disposed in the space surrounded by the second doped sub-ring.

3. The electrostatic discharge protection device of claim 2, wherein, The protective frame on the side of the first doped sub-ring close to the second doped sub-ring and the protective frame on the side of the second doped sub-ring close to the first doped sub-ring are the same protective frame.

4. The electrostatic discharge protection device of claim 1, wherein, The plurality of transistors are arranged sequentially along the first direction, and at least one of the transistors includes at least a gate electrode, the gate electrode including at least a first sub-gate, a second sub-gate, and a sub-gate connecting strip; the first sub-gate and the second sub-gate are strip-shaped extending along the second direction and are spaced apart in the first direction, the sub-gate connecting strip is strip-shaped extending along the first direction and is connected to the ends of the first sub-gate and the second sub-gate on the opposite side of the second direction, forming an "n" shape; the first sub-gate or the second sub-gate has a sub-gate width, and there is a sub-gate spacing between the first sub-gate and the second sub-gate, the ratio of the sub-gate width to the sub-gate spacing is 0.2 to 0.3, and the sub-gate width and the sub-gate spacing are dimensions in the first direction.

5. The electrostatic discharge protection device of claim 4, wherein, The transistor group further includes a gate connection line, which is a straight line or a broken line extending along the first direction. The gate connection line is connected to the end of the first sub-gate and the second sub-gate on the second direction side, respectively. The first sub-gate, the second sub-gate, the sub-gate connection strip and the gate connection line form an annular hollow structure.

6. The electrostatic discharge protection device of claim 5, wherein, In the second direction, the edge of the trigger resistor on the second direction side is flush with the gate connection line.

7. The electrostatic discharge protection device of claim 4, wherein, The trigger resistor and the transistor group have a first device spacing, the ratio of the first device spacing to the sub-gate spacing is 1.0 to 2.0, and the first device spacing is the dimension in the first direction.

8. The electrostatic discharge protection device of claim 7, wherein, The transistor group and the diode group have a second device spacing, which is greater than the first device spacing, and the second device spacing is a dimension in the second direction.

9. The electrostatic discharge protection device of claim 1, wherein, The electrostatic discharge protection device further includes a first N-type doped protective ring, which is ring-shaped and connected to the first power line. The first P-type doped protective ring is disposed within the space surrounded by the first N-type doped protective ring.

10. The electrostatic discharge protection device of claim 1, wherein, The electrostatic discharge protection device further includes a second P-type doped protective ring, which is ring-shaped and disposed on one side of the first P-type doped protective ring in the second direction, and is connected to the grounding wire. The diode group is disposed within the space surrounded by the second P-type doped protective ring.

11. The electrostatic discharge protection device of claim 10, wherein, The electrostatic discharge protection device further includes a second N-type doped protective ring, which is ring-shaped and connected to the first power line. The second P-type doped protective ring is disposed within the space surrounded by the second N-type doped protective ring.

12. The electrostatic discharge protection device of claim 11, wherein, In the second direction, at least three protective frames are provided between the transistor group and the diode group. The three protective frames are one of the protective frames in the first P-type doped protective ring, one of the protective frames in the second P-type doped protective ring, and one of the protective frames in the second N-type doped protective ring.

13. The electrostatic discharge protection device of claim 10, wherein, The electrostatic discharge protection device further includes a first N-type doped protective ring and a second N-type doped protective ring. The first N-type doped protective ring is ring-shaped and connected to the first power line. The first P-type doped protective ring is disposed within the space surrounded by the first N-type doped protective ring. The second N-type doped protective ring is ring-shaped and connected to the first power line. The second P-type doped protective ring is disposed within the space surrounded by the second N-type doped protective ring. The second N-type doped protective ring is disposed on one side of the first N-type doped protective ring in the second direction and is connected to the first N-type doped protective ring.

14. The electrostatic discharge protection device of claim 13, wherein, The protective frame of the first N-type doped protective ring near the second N-type doped protective ring and the protective frame of the second N-type doped protective ring near the first N-type doped protective ring are the same protective frame.

15. The electrostatic discharge protection device of any one of claims 1 to 14, wherein, At least one of the diodes includes at least a first active region and a second active region; the first active region is in the shape of a strip extending along the first direction and is connected to the ground line, and a plurality of the first active regions form an n1*n2 first active array; the second active region is in the shape of a ring surrounding the first active region and is connected to the first power line, and a plurality of the second active regions form an n1*n2 second active array; at least one of the transistors includes at least m1 third active layers, the m1 third active layers are an interconnected integral structure, and m1, n1, and n2 are positive integers greater than 1.

16. The electrostatic discharge protection device of claim 15, wherein, The annular second active region includes at least two first active frames and two second active frames. The first active frames are strip-shaped extending along the first direction, and the second active frames are strip-shaped extending along the second direction. The first active frames and the second active frames are connected in sequence. The plurality of first active frames include at least one first width frame and at least one second width frame. The first width frame has a first active width, and the second width frame has a second active width. The first active width is greater than the second active width, and the first active width and the second active width are dimensions in the second direction.

17. The electrostatic discharge protection device of claim 16, wherein, The second active array has an array centerline, which is a straight line that bisects the second active array in the second direction and extends along the first direction; the orthographic projection of the first width frame on the plane of the electrostatic discharge device at least partially overlaps with the orthographic projection of the array centerline on the plane of the electrostatic discharge device, and the orthographic projection of the second width frame on the plane of the electrostatic discharge device does not overlap with the orthographic projection of the array centerline on the plane of the electrostatic discharge device.

18. A display substrate, comprising a display area and a non-display area; the display area comprising a plurality of sub-pixels, at least one sub-pixel comprising a pixel driving circuit and a light-emitting device connected to the pixel driving circuit, the non-display area comprising at least one electrostatic discharge protection device as described in any one of claims 1 to 17.

19. A display device comprising the display substrate as claimed in claim 18.

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