Electrostatic protection device, display substrate and display device

Abstract

An electrostatic protection device, a display substrate and a display device. The electrostatic protection device comprises a P-type transistor group (81), an N-type transistor group (82), and a resistor array (85). The P-type transistor group (81) includes a plurality of first P-type transistors (PT1) connected in parallel and a plurality of second P-type transistors (PT2) connected in parallel. The N-type transistor group (82) includes a plurality of first N-type transistors (NT1) connected in parallel and a plurality of second N-type transistors (NT2) connected in parallel. The resistor array (85) includes at least a plurality of second resistors (40B) connected in parallel and a plurality of third resistors (40C) connected in parallel. The P-type transistor group (81) and the N-type transistor group (82) are respectively arranged on two sides of the resistor array (85) in a second direction.

Description

Electrostatic discharge protection device, display substrate and display device Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and in particular to an electrostatic discharge protection device, a display substrate, and a display device. Background Technology

[0002] Micro-OLED (Micro Organic Light-Emitting Diode) is a type of microdisplay that has emerged in recent years, with silicon-based OLED being one example. Silicon-based OLED is a novel display technology that combines semiconductor manufacturing processes with OLED display technology, using wafers as a substrate to fabricate OLED devices. Because it combines the advantages of both semiconductor manufacturing processes and OLED display technology, silicon-based OLED not only boasts a high pixel density (Pixels Per Inch, PPI), but also offers advantages such as high brightness, low power consumption, high response speed, wide color gamut, and high thermal stability. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] On one hand, this disclosure provides an electrostatic discharge (ESD) protection device, including a P-type transistor group, an N-type transistor group, and a resistor array. The P-type transistor group includes a plurality of first P-type transistors and a plurality of second P-type transistors connected in parallel. The N-type transistor group includes a plurality of first N-type transistors and a plurality of second N-type transistors connected in parallel. The resistor array includes a plurality of resistors, at least including a plurality of second resistors and a plurality of third resistors connected in parallel. The gate electrodes of the first P-type transistors and the gate electrodes of the first N-type transistors are connected. The first terminals of the first P-type transistors and the second P-type transistors are connected to a first power supply line. The first terminals of the first N-type transistors and the second N-type transistors are connected to a first power supply line. The first terminal is connected to the ground wire. The second terminals of the first P-type transistor, the second terminals of the first N-type transistor, the gate electrode of the second P-type transistor, and the gate electrode of the second N-type transistor are connected. The second terminal of the second P-type transistor is connected to the output terminal through the second resistor, and the second terminal of the second N-type transistor is connected to the output terminal through the third resistor. The plurality of first P-type transistors and the plurality of second P-type transistors are arranged sequentially in the first direction. The plurality of first N-type transistors and the plurality of second N-type transistors are arranged sequentially in the first direction. The P-type transistor group and the N-type transistor group are respectively disposed on both sides of the resistor array in the second direction. The first direction and the second direction intersect.

[0005] In an exemplary embodiment, at least one of the resistors has a first spacing with the gate electrode of at least one first P-type transistor or the gate electrode of at least one second P-type transistor, and at least one of the resistors has a second spacing with the gate electrode of at least one first N-type transistor or the gate electrode of at least one second N-type transistor, wherein the first spacing is greater than the second spacing, and the first spacing and the second spacing are dimensions in the second direction.

[0006] In an exemplary embodiment, the plurality of second resistors are divided into m1 first subgroups, each first subgroup including m2 second resistors arranged sequentially along the first direction, and the plurality of third resistors are divided into m1 second subgroups, each second subgroup including m2 third resistors arranged sequentially along the first direction. The first subgroups and the second subgroups are alternately arranged in the first direction, and m1 and m2 are positive integers greater than 1.

[0007] In an exemplary embodiment, the N-type transistor group further includes a ground transistor, and the plurality of resistors further include a first resistor. The first end of the first resistor is connected to the input terminal, and the second end of the first resistor is connected to the second electrode of the ground transistor, the gate electrode of the first P-type transistor, and the gate electrode of the first N-type transistor, respectively. The gate electrode of the ground transistor and the first electrode of the ground transistor are connected to the grounding wire. The plurality of first N-type transistors are disposed on one side of the ground transistor in the first direction, and the plurality of second N-type transistors are disposed on one side of the plurality of first N-type transistors in the first direction.

[0008] In an exemplary embodiment, the plurality of resistors further includes a plurality of fourth resistors, the first end of the fourth resistors and the second end of the fourth resistors being connected to the grounding wire.

[0009] In an exemplary embodiment, the plurality of fourth resistors are divided into a third subgroup and a fourth subgroup. The third subgroup includes n1 fourth resistors arranged sequentially along the first direction, and the second subgroup includes n2 fourth resistors arranged sequentially along the first direction, where n1 and n2 are positive integers greater than 1. The third subgroup is located on one side of the first resistor in the opposite direction to the first direction, and the fourth subgroup is located on one side of the first resistor in the first direction.

[0010] In an exemplary embodiment, the first end of the second resistor is connected to the second electrode of the second P-type transistor, the first end of the third resistor is connected to the second electrode of the second N-type transistor, the second end of the second resistor and the second end of the third resistor are connected to each other through an output node electrode, the gate electrode of the first P-type transistor and the gate electrode of the first N-type transistor are connected to each other through a first node electrode, a shielding opening is provided on the output node electrode, and the first node electrode is disposed in the shielding opening.

[0011] In an exemplary embodiment, the electrostatic discharge protection device includes multiple conductive layers, with the first node electrode and the output node electrode disposed in the same conductive layer.

[0012] In an exemplary embodiment, the electrostatic discharge protection device further includes a first conductive ring and a second conductive ring. The second conductive ring is disposed on one side of the first conductive ring in the second direction. The first conductive ring and the second conductive ring are ring-shaped. The first conductive ring is connected to the first power line, and the second conductive ring is connected to the grounding wire. The P-type transistor group is disposed in the space surrounded by the first conductive ring, and the N-type transistor group and the resistor array are disposed in the space surrounded by the second conductive ring.

[0013] In an exemplary embodiment, the second conductive ring includes a first conductive sub-ring and a second conductive sub-ring disposed on the side of the first conductive sub-ring close to the first conductive ring. The first conductive sub-ring and the second conductive sub-ring are ring-shaped. The N-type transistor group is disposed in the space surrounded by the first conductive sub-ring, and the resistor array is disposed in the space surrounded by the second conductive sub-ring.

[0014] In an exemplary embodiment, the first conductive sub-ring and the second conductive sub-ring are interconnected, and the conductive frame of the first conductive sub-ring near the second conductive sub-ring and the conductive frame of the second conductive sub-ring near the first conductive sub-ring are the same conductive frame.

[0015] In an exemplary embodiment, the electrostatic protection device further includes a fifth conductive ring, which is ring-shaped and connected to the first power line. The first conductive ring and the second conductive ring are disposed within the space surrounded by the fifth conductive ring.

[0016] In an exemplary embodiment, the electrostatic discharge protection device further includes a P-type diode group and an N-type diode group. The P-type diode group includes multiple P-type diodes connected in parallel, and the N-type diode group includes multiple N-type diodes connected in parallel. The first terminal of the N-type diode is connected to the grounding wire, and the second terminal of the P-type diode is connected to the first power supply line. The first terminals of the P-type diodes and the second terminals of the N-type diodes are connected to the output terminal. The P-type diode group is disposed on one side of the N-type transistor group in the second direction, and the N-type diode group is disposed on one side of the P-type diode group in the second direction.

[0017] In an exemplary embodiment, the output terminal is connected to the first terminal of the plurality of P-type diodes and the second terminal of the plurality of N-type diodes through multiple output traces. The first power line is connected to the second terminal of the plurality of P-type diodes through multiple power traces. The ground line is connected to the first terminal of the plurality of N-type diodes through multiple ground traces. The output traces, the power traces, and the ground traces are strip-shaped extending along the second direction. In the first direction, the power traces and the ground traces are arranged between two adjacent output traces. In the second direction, the ground trace is arranged on one side of the power trace in the second direction. The output traces, the power traces, and the ground traces form an interdigitated arrangement.

[0018] In an exemplary embodiment, the electrostatic discharge protection device further includes a third conductive ring and a fourth conductive ring. The fourth conductive ring is disposed on one side of the third conductive ring in the second direction. The third conductive ring and the fourth conductive ring are both ring-shaped and connected to the grounding wire. The P-type diode group is disposed within the space surrounded by the third conductive ring, and the N-type diode group is disposed within the space surrounded by the fourth conductive ring.

[0019] In an exemplary embodiment, the electrostatic discharge protection device further includes a conductive ring connecting wire, which is disposed between the P-type diode group and the N-type diode group. The conductive ring connecting wire is connected to the conductive frame of the third conductive ring near the fourth conductive ring and the conductive frame of the fourth conductive ring near the third conductive ring, respectively.

[0020] In an exemplary embodiment, the conductive border of the third conductive ring or the fourth conductive ring has a first width, the conductive ring connecting line has a second width, the ratio of the second width to the first width is greater than or equal to 3, and the first width and the second width are dimensions in the second direction.

[0021] In an exemplary embodiment, the electrostatic discharge protection device further includes a sixth conductive ring and a seventh conductive ring; the sixth conductive ring and the seventh conductive ring are ring-shaped and are both connected to the first power line; the third conductive ring is disposed within the space surrounded by the sixth conductive ring, and the fourth conductive ring is disposed within the space surrounded by the seventh conductive ring.

[0022] In an exemplary embodiment, the sixth conductive ring and the seventh conductive ring are interconnected, and the conductive frame of the sixth conductive ring near the seventh conductive ring and the conductive frame of the seventh conductive ring near the sixth conductive ring are the same conductive frame.

[0023] On the other hand, embodiments of this disclosure provide a display substrate, including a display area and a non-display area; the display area includes a plurality of sub-pixels, at least one sub-pixel includes a pixel driving circuit and a light-emitting device connected to the pixel driving circuit, and the non-display area includes at least one electrostatic discharge (ESD) protection device, the at least one ESD protection device including the aforementioned ESD protection device.

[0024] In another aspect, embodiments of this disclosure provide a display device including the aforementioned display substrate.

[0025] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects will become clear. Attached Figure Description

[0026] The accompanying drawings are provided to illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure, but do not constitute a limitation on the technical solutions of this disclosure. The shape and size of each component in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0027] Figure 1 is a schematic diagram of a silicon-based OLED display device;

[0028] Figure 2 is a schematic diagram of the planar structure of the display area in a silicon-based OLED display device;

[0029] Figure 3 is a schematic cross-sectional view of the display area in a silicon-based OLED display device;

[0030] Figure 4 is an equivalent circuit diagram of an electrostatic protection device according to an exemplary embodiment of the present disclosure;

[0031] Figure 5 is a structural schematic diagram of an electrostatic protection device according to an exemplary embodiment of the present disclosure;

[0032] Figure 6 is a schematic diagram showing the N-well region and P-well region patterns formed according to an embodiment of the present disclosure;

[0033] Figures 7A and 7B are schematic diagrams of the active region pattern formed according to the embodiments of this disclosure;

[0034] Figures 8A and 8B are schematic diagrams of the gate conductive layer pattern formed according to an embodiment of the present disclosure;

[0035] Figures 9A and 9B are schematic diagrams of the N-type doped region pattern formed according to the embodiments of this disclosure;

[0036] Figures 10A and 10B are schematic diagrams of the P-type doped region pattern formed according to the embodiments of this disclosure;

[0037] Figure 11 is a schematic diagram of the second insulating layer pattern after it is formed according to an embodiment of the present disclosure;

[0038] Figures 12A and 12B are schematic diagrams after the first conductive layer pattern is formed according to an embodiment of the present disclosure;

[0039] Figure 13 is a schematic diagram of the third insulating layer pattern after it is formed according to an embodiment of the present disclosure;

[0040] Figures 14A and 14B are schematic diagrams of the second conductive layer pattern after it is formed according to an embodiment of the present disclosure;

[0041] Figure 15 is a schematic diagram of the fourth insulating layer pattern formed according to an embodiment of the present disclosure;

[0042] Figures 16A and 16B are schematic diagrams of the formation of the third conductive layer pattern according to an embodiment of the present disclosure;

[0043] Figure 17 is a schematic diagram of the fifth insulating layer pattern after it is formed according to an embodiment of the present disclosure;

[0044] Figures 18A and 18B are schematic diagrams of the fourth conductive layer pattern formed according to an embodiment of this disclosure. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0046] The scale of the accompanying drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display device and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The accompanying drawings described in this disclosure are only structural schematic diagrams, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0047] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0048] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0049] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0050] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0051] In this specification, to distinguish the two terminals of a transistor other than the gate electrode, one terminal is directly described as the first terminal and the other as the second terminal. The first terminal can be the drain electrode and the second terminal can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0052] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0053] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0054] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0055] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple structures in a same-layer arrangement may be made of the same material, while the final materials may be the same or different.

[0056] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0057] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0058] Figure 1 is a schematic diagram of a silicon-based OLED display device. As shown in Figure 1, the silicon-based OLED display device may include a display area and a non-display area. The display area may include multiple scan signal lines, multiple data signal lines, and multiple sub-pixels Pxij forming multiple pixel rows and multiple pixel columns. The multiple scan signal lines are respectively arranged in the multiple pixel rows, and the multiple data signal lines are respectively arranged in the multiple pixel columns. Each sub-pixel Pxij may include at least a pixel driving circuit and a light-emitting device. The pixel driving circuit is configured to provide the current required for light emission to the connected light-emitting device. The pixel driving circuit of each sub-pixel Pxij may be connected to the scan signal line of the corresponding pixel row and the data signal line of the corresponding pixel column. The sub-pixel Pxij may refer to the sub-pixel of the i-th pixel row and the j-th pixel column. The pixel driving circuit of the sub-pixel Pxij is connected to the i-th scan signal line and the j-th data signal line, respectively. i and j can be natural numbers. The non-display area may include a display driver integrated circuit (DDIC), a gate driver (GD), and a source driver (SD). The display driver circuit may include at least a timing controller (TCON), configured to generate timing signals required by the gate driver, such as a start signal (STV) and a clock signal (CKV), and send these timing signals to the gate driver. The gate driver is connected to multiple scan signal lines in the display area and is configured to provide the required timing signals to the connected pixel driver circuits to achieve progressive scan functionality. The source driver is connected to multiple data signal lines in the display area and is configured to provide the required data signals to the connected pixel driver circuits to achieve switching and control of the display screen. In an exemplary embodiment, the pixel array may be disposed on a display substrate.

[0059] In one exemplary embodiment, the silicon-based OLED display device can be a one-chip display architecture, integrating gate driving devices, data driving devices, clock control units, image processing units, and memory units onto the same chip. The one-chip architecture chip includes both digital and analog parts, belonging to mixed-signal chips.

[0060] In another exemplary embodiment, the silicon-based OLED display device may be a two-chip display architecture, in which the gate driving device and the data driving device are integrated in the display substrate, and the clock control unit, the image processing unit, the mobile industry processor interface (MIPI) and the memory unit are integrated in one chip, which is bonded to the display substrate through a COC process.

[0061] Figure 2 is a schematic diagram of the planar structure of a display area in a display substrate. As shown in Figure 2, on a plane parallel to the display substrate, the display area may include multiple pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each of the three sub-pixels may include a pixel driving circuit and a light-emitting device. The pixel driving circuit in the sub-pixel is connected to the scan signal line and the data signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scan signal line and output a corresponding current to the display light-emitting device. The light-emitting device in the sub-pixel is connected to the pixel driving circuit of the sub-pixel and is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0062] In an exemplary embodiment, the first sub-pixel P1 may be a red (R) sub-pixel that emits red light, the second sub-pixel P2 may be a green (G) sub-pixel that emits green light, and the third sub-pixel P3 may be a blue (B) sub-pixel that emits blue light.

[0063] In exemplary embodiments, the shape of a sub-pixel can be any one or more of a triangle, square, rectangle, rhombus, trapezoid, parallelogram, pentagon, hexagon, and other polygons. Three sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a triangular pattern, etc., and this disclosure does not limit the arrangement. In other possible embodiments, a pixel unit may include four sub-pixels, and this disclosure does not limit the arrangement.

[0064] Figure 3 is a schematic cross-sectional view of the display area in a display substrate, illustrating a structure that achieves full color using a white light + color filter approach. As shown in Figure 3, in the direction perpendicular to the display substrate, the display substrate may include: a silicon substrate 200, a driving circuit layer 201 disposed on the silicon substrate 200, a light-emitting structure layer 202 disposed on the side of the driving circuit layer 201 away from the silicon substrate 200, a first encapsulation layer 203 disposed on the side of the light-emitting structure layer 202 away from the silicon substrate 200, a color filter structure layer 204 disposed on the side of the first encapsulation layer 203 away from the silicon substrate 200, a second encapsulation layer 205 disposed on the side of the color filter structure layer 204 away from the silicon substrate 200, and a cover plate layer 206 disposed on the side of the second encapsulation layer 205 away from the silicon substrate 200. In some possible implementations, the display substrate may also include other film layers, which are not limited herein.

[0065] In an exemplary embodiment, the silicon substrate 200 can be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. The driving circuit layer 201 can be fabricated on the silicon substrate 200 using silicon semiconductor processes. The driving circuit layer 201 can include multiple circuit units, each of which can include at least a pixel driving circuit. The pixel driving circuit is connected to the scan signal line and data signal line, respectively. The pixel driving circuit can include multiple transistors and storage capacitors; only one transistor is shown as an example in Figure 3. The transistor can include a gate electrode, a source electrode, and a drain electrode. The gate electrode, source electrode, and drain electrode can be connected to corresponding connection electrodes via tungsten-filled vias (i.e., tungsten vias, W-vias), and can be connected to other electrical structures (such as traces) via the connection electrodes.

[0066] In an exemplary embodiment, the light-emitting structure layer 202 may include multiple light-emitting devices. Each light-emitting device may include at least an anode, an organic light-emitting layer, and a cathode. The anode is connected to the drain electrode of a transistor via a connecting electrode. The organic light-emitting layer is connected to the anode, the cathode is connected to the organic light-emitting layer, and the cathode is connected to a second power line. The organic light-emitting layer emits light under the drive of the anode and cathode. In an exemplary embodiment, the organic light-emitting layer may include a light-emitting layer (EML), and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, for a light-emitting device emitting white light, the organic light-emitting layers of all sub-pixels may be a common layer connected together.

[0067] In an exemplary embodiment, the first encapsulation layer 203 and the second encapsulation layer 205 can employ thin film encapsulation (TFE) to prevent external moisture from entering the light-emitting structure layer. The color filter structure layer 204 can include at least a red filter unit, a blue filter unit, and a green filter unit. The red filter unit is located in the red sub-pixel and filters the white light emitted by the light-emitting device into red light. The blue filter unit is located in the blue sub-pixel and filters the white light emitted by the light-emitting device into blue light. The green filter unit is located in the green sub-pixel and filters the white light emitted by the light-emitting device into green light. The cover plate layer 206 can be made of glass or a flexible plastic such as colorless polyimide.

[0068] In the manufacturing of silicon-based OLED displays, the display substrate can suffer irreversible damage due to two electrostatic discharge (ESD) methods: Charged Device Mode (CDM) and Machine Model (MM). This primarily manifests as breakdown of transistor gate electrodes and melting of metal traces due to high current, leading to defects such as black screens and abnormal display. Furthermore, when personnel touch the display substrate, it can suffer irreversible damage due to ESD via Human Body Mode (HBM). Therefore, ESD protection devices are crucial throughout the entire lifecycle of silicon-based OLED displays, significantly contributing to improved product yield and reliability.

[0069] An exemplary embodiment of this disclosure provides an electrostatic discharge (ESD) protection device, including a P-type transistor group, an N-type transistor group, and a resistor array. The P-type transistor group includes a plurality of first P-type transistors and a plurality of second P-type transistors connected in parallel. The N-type transistor group includes a plurality of first N-type transistors and a plurality of second N-type transistors connected in parallel. The resistor array includes a plurality of resistors, including at least a plurality of second resistors and a plurality of third resistors connected in parallel. The gate electrodes of the first P-type transistors and the gate electrodes of the first N-type transistors are connected. The first terminals of the first P-type transistors and the first terminals of the second P-type transistors are connected to a first power supply line. The first terminals of the first N-type transistors and the second N-type transistors are connected to a first power supply line. The first terminal is connected to the ground wire. The second terminals of the first P-type transistor, the second terminals of the first N-type transistor, the gate electrode of the second P-type transistor, and the gate electrode of the second N-type transistor are connected. The second terminal of the second P-type transistor is connected to the output terminal through the second resistor, and the second terminal of the second N-type transistor is connected to the output terminal through the third resistor. The plurality of first P-type transistors and the plurality of second P-type transistors are arranged sequentially in the first direction. The plurality of first N-type transistors and the plurality of second N-type transistors are arranged sequentially in the first direction. The P-type transistor group and the N-type transistor group are respectively disposed on both sides of the resistor array in the second direction. The first direction and the second direction intersect.

[0070] In an exemplary embodiment, at least one of the resistors has a first spacing with the gate electrode of at least one first P-type transistor or the gate electrode of at least one second P-type transistor, and at least one of the resistors has a second spacing with the gate electrode of at least one first N-type transistor or the gate electrode of at least one second N-type transistor, wherein the first spacing is greater than the second spacing, and the first spacing and the second spacing are dimensions in the second direction.

[0071] In an exemplary embodiment, the plurality of second resistors are divided into m1 first subgroups, each first subgroup including m2 second resistors arranged sequentially along the first direction, and the plurality of third resistors are divided into m1 second subgroups, each second subgroup including m2 third resistors arranged sequentially along the first direction. The first subgroups and the second subgroups are alternately arranged in the first direction, and m1 and m2 are positive integers greater than 1.

[0072] In an exemplary embodiment, the plurality of resistors further includes a plurality of fourth resistors, the first end of the fourth resistors and the second end of the fourth resistors being connected to the grounding wire.

[0073] In an exemplary embodiment, the plurality of fourth resistors are divided into a third subgroup and a fourth subgroup. The third subgroup includes n1 fourth resistors arranged sequentially along the first direction, and the second subgroup includes n2 fourth resistors arranged sequentially along the first direction, where n1 and n2 are positive integers greater than 1. The third subgroup is located on one side of the first resistor in the opposite direction to the first direction, and the fourth subgroup is located on one side of the first resistor in the first direction.

[0074] In an exemplary embodiment, the electrostatic discharge protection device further includes a P-type diode group and an N-type diode group. The P-type diode group includes multiple P-type diodes connected in parallel, and the N-type diode group includes multiple N-type diodes connected in parallel. The first terminal of each N-type diode is connected to the grounding wire, and the second terminal of each P-type diode is connected to the first power supply line. The first terminals of both the P-type diodes and the N-type diodes are connected to the output terminal. The P-type diode group is disposed on one side of the N-type transistor group in the second direction, and the N-type diode group is disposed on one side of the P-type diode group in the second direction.

[0075] The technical solution of the electrostatic discharge protection device disclosed herein is illustrated below through exemplary embodiments.

[0076] Figure 4 is an equivalent circuit diagram of an electrostatic discharge (ESD) protection device according to an exemplary embodiment of this disclosure. In an exemplary embodiment, the ESD protection device can be disposed at the output port of the display driving circuit in a non-display area. It can not only discharge electrostatic current generated inside and outside the integrated circuit IC (IC), but also amplify the signal output by the IC. As shown in Figure 4, the ESD protection device may include at least a first circuit C1, a second circuit C2, and a third circuit C3. The first circuit C1 is configured to discharge electrostatic current generated inside the IC, the second circuit C2 is configured to discharge electrostatic current generated outside the IC, and the third circuit C3 is configured to amplify the signal output by the IC.

[0077] In an exemplary embodiment, the first circuit C1 may include at least a grounding transistor GT and a first resistor R1, forming a voltage-triggered CDM protection circuit that can serve as a CDM protection device. The first terminal of the first resistor R1 is connected to the input terminal IN of the electrostatic discharge protection device, and the second terminal of the first resistor R1 is connected to the second electrode (drain electrode) of the grounding transistor GT. The gate electrode and the first electrode (source electrode) of the grounding transistor GT are connected to the grounding line GND. The grounding transistor GT is a gate-grounded NMOS (GGNMOS). The first circuit C1 utilizes a substrate parasitic transistor to discharge electrostatic current.

[0078] In an exemplary embodiment, the second circuit C2 may include at least an N-type diode ND and a P-type diode PD, forming an HBM protection circuit and serving as an HBM protection device. The first terminal of the N-type diode ND is connected to the ground line GND, the second terminal of the N-type diode ND is connected to the first terminal of the P-type diode PD, and the second terminal of the P-type diode PD is connected to the first power line VDD. The second circuit C2 utilizes the forward conduction characteristic of the diode to discharge electrostatic current.

[0079] In an exemplary embodiment, the third circuit C3 may include at least a cascaded first inverter and a second inverter. The first inverter may include a first P-type transistor PT1 and a first N-type transistor NT1, and the second inverter may include a second P-type transistor PT2, a second N-type transistor NT2, a second resistor R2, and a third resistor R3. The gate electrodes of the first P-type transistor PT1 and the first N-type transistor NT1 are interconnected and connected to the second terminal of the first resistor R1. The first terminal of the first P-type transistor PT1 is connected to the first power supply line VDD. The first terminal of the first N-type transistor NT1 is connected to the ground line GND. The second terminals of the first P-type transistor PT1 and the first N-type transistor NT1 are connected to each other and to the gate electrodes of the second P-type transistor PT2 and the second N-type transistor NT2. The first terminal of the second P-type transistor PT2 is connected to the first power supply line VDD. The second terminal of the second P-type transistor PT2 is connected to the output terminal OUT of the electrostatic discharge protection device through the second resistor R2. The first terminal of the second N-type transistor NT2 is connected to the ground line GND. The second terminal of the second N-type transistor NT2 is connected to the output terminal OUT of the electrostatic discharge protection device through the third resistor R3.

[0080] In an exemplary embodiment, the first resistor R1, the second resistor R2, and the third resistor R3 may be non-silicide p+poly resistors (rpposab).

[0081] In an exemplary embodiment, the electrostatic discharge (ESD) protection device may include a first node N1, a second node N2, and a third node N3. The first node N1 may be connected to the second terminal of the first resistor R1, the second terminal of the grounding transistor GT, the gate electrode of the first P-type transistor PT1, and the gate electrode of the first N-type transistor NT1, respectively. The second node N2 may be connected to the second terminal of the first P-type transistor PT1, the second terminal of the first N-type transistor NT1, the gate electrode of the second P-type transistor PT2, and the gate electrode of the second N-type transistor NT2, respectively. The third node N3 (output node) may be connected to the second terminal of the second resistor R2, the second terminal of the third resistor R3, the first terminal of the P-type diode PD, and the second terminal of the N-type diode ND, respectively.

[0082] Figure 5 is a schematic diagram of an electrostatic discharge (ESD) protection device according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, the display substrate may include at least a display area and a non-display area. The display area may include multiple sub-pixels forming multiple pixel rows and multiple pixel columns. At least one sub-pixel includes a pixel driving circuit and a light-emitting device connected to the pixel driving circuit. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit. The non-display area may include at least an integrated circuit and multiple ESD protection devices. The ESD protection devices are configured to discharge electrostatic current generated inside and outside the integrated circuit and to amplify the signal output by the integrated circuit.

[0083] As shown in Figure 5, the electrostatic discharge protection device may include a P-type transistor group 81, an N-type transistor group 82, a P-type diode group 83, an N-type diode group 84, and a resistor array 85 disposed on a silicon substrate. The P-type transistor group 81 may include 10 first P-type transistors PT1 connected in parallel and 20 second P-type transistors PT2 connected in parallel. The N-type transistor group 82 may include a ground transistor GT, 10 first N-type transistors NT1 connected in parallel and 20 second N-type transistors NT2 connected in parallel. The P-type diode group 83 may include 24 P-type diodes PD connected in parallel. The N-type diode group 84 may include 24 N-type diodes ND connected in parallel. The resistor array 85 may include 25 resistors, which may include at least one first resistor 40A, eight second resistors 40B connected in parallel, eight third resistors 40C connected in parallel, and eight fourth resistors 40D connected in parallel.

[0084] In an exemplary embodiment, the 10 first P-type transistors PT1 and 20 second P-type transistors PT2 in the P-type transistor group 81 can be arranged sequentially in the first direction X. The ground transistor GT, 10 first N-type transistors NT1 and 20 second N-type transistors NT2 in the N-type transistor group 82 can be arranged sequentially in the first direction X. The 25 resistors in the resistor array 85 can be arranged sequentially in the first direction X. The resistor array 85 can be disposed on one side of the P-type transistor group 81 in the second direction Y, and the N-type transistor group 82 can be disposed on one side of the resistor array 85 in the second direction Y. That is, the P-type transistor group 81 and the N-type transistor group 82 are respectively disposed on both sides of the resistor array 85 in the second direction Y, and the resistor array 85 is disposed between the P-type transistor group 81 and the N-type transistor group 82, with the first direction X and the second direction Y intersecting.

[0085] In an exemplary embodiment, in the P-type transistor group 81, 20 second P-type transistors PT2 can be disposed on one side of 10 first P-type transistors PT1 in the first direction X. The 10 first P-type transistors PT1 can be arranged sequentially in the first direction X, and the P-type active regions of the 10 first P-type transistors PT1 can be an integral structure interconnected with each other. The 20 second P-type transistors PT2 can be divided into 4 P-type transistor groups arranged sequentially in the first direction X. Each P-type transistor group can include 5 second P-type transistors PT2 arranged sequentially in the first direction X, and the P-type active regions of the 5 second P-type transistors PT2 can be an integral structure interconnected with each other.

[0086] In an exemplary embodiment, the grounding transistor GT and the first resistor 40A can form the first circuit of the electrostatic discharge protection device, and the 24 P-type diodes PD and 24 N-type diodes ND connected in parallel can form the second circuit of the electrostatic discharge protection device.

[0087] In an exemplary embodiment, 10 first P-type transistors PT1 and 10 first N-type transistors NT1 connected in parallel can form the first inverter of the third circuit in the electrostatic discharge protection device, and the aspect ratio of the 10 parallel transistors is 10 times that of a single transistor. 20 second P-type transistors PT2, 20 second N-type transistors NT2, 8 second resistors 40B, and 8 third resistors 40C can form four second inverters of the third circuit in the electrostatic discharge protection device. Each second inverter may include 5 second P-type transistors PT2, 5 second N-type transistors NT2, 2 second resistors 40B, and 2 third resistors 40C connected in parallel.

[0088] In an exemplary embodiment, in the N-type transistor group 82, 10 first N-type transistors NT1 can be disposed on one side of the ground transistor GT in the first direction X, and 20 second N-type transistors NT2 can be disposed on one side of the 10 first N-type transistors NT1 in the first direction X. The 10 first N-type transistors NT1 can be arranged sequentially in the first direction X, and the N-type active regions of the 10 first N-type transistors NT1 can be an integral structure interconnected with each other. The 20 second N-type transistors NT2 can be divided into 4 N-type transistor groups arranged sequentially in the first direction X. Each N-type transistor group can include 5 second N-type transistors NT2 arranged sequentially in the first direction X, and the N-type active regions of the 5 second N-type transistors NT2 can be an integral structure interconnected with each other.

[0089] In an exemplary embodiment, a first spacing S1 may be present between the gate electrode of at least one first P-type transistor PT1 or at least one second P-type transistor PT2 in the P-type transistor group 81 and at least one resistor in the resistor array 85, and a second spacing S2 may be present between the gate electrode of at least one first N-type transistor NT1 or at least one second N-type transistor NT2 in the N-type transistor group 82 and at least one resistor in the resistor array 85. The first spacing S1 may be greater than the second spacing S2. The first spacing S1 may be the minimum distance between the edge of the resistor near the P-type transistor group 81 and the edge of the gate electrode of the first P-type transistor PT1 or the second P-type transistor PT2 near the resistor array 85. The second spacing S2 may be the minimum distance between the edge of the resistor near the N-type transistor group 82 and the edge of the gate electrode of the first N-type transistor NT1 or the second N-type transistor NT2 near the resistor array 85. The first spacing S1 and the second spacing S2 may be dimensions in the second direction Y.

[0090] In an exemplary embodiment, the 24 P-type diodes PD in the P-type diode group 83 can be arranged in an array, including 6 diode rows and 4 diode columns. The 24 P-type diodes PD in the N-type diode group 84 can also be arranged in an array, including 6 diode rows and 4 diode columns. The P-type diode group 83 can be disposed on one side of the N-type transistor group 82 in the second direction Y, and the N-type diode group 84 can be disposed on one side of the P-type diode group 83 in the second direction Y.

[0091] In some possible implementations, a P-type diode group may include m diode rows and n diode columns, where n and m are positive integers greater than 1, and are not limited herein.

[0092] In an exemplary embodiment, the eight second resistors 40B can be divided into four first subgroups, and the eight third resistors 40C can be divided into four second subgroups. The first subgroups and the second subgroups can be alternately arranged in the first direction X. Each first subgroup may include two second resistors 40B arranged sequentially in the first direction X, and each second subgroup may include two third resistors 40C arranged sequentially in the first direction X.

[0093] In some possible implementations, the plurality of second resistors can be divided into m1 first subgroups, each first subgroup including m2 second resistors arranged sequentially along the first direction X. The plurality of third resistors can be divided into m1 second subgroups, each second subgroup including m2 third resistors arranged sequentially along the first direction X. The first subgroups and the second subgroups can be alternately arranged in the first direction X. m1 and m2 can be positive integers greater than 1, which are not limited herein.

[0094] In an exemplary embodiment, the eight fourth resistors 40D can be divided into a third subgroup and a fourth subgroup. The third subgroup may include five fourth resistors 40D arranged sequentially in the first direction X, and the fourth subgroup may include three fourth resistors 40D arranged sequentially in the first direction X. The third subgroup may be located on the side opposite to the first resistor 40A in the first direction X, and the fourth subgroup may be located on the side of the first resistor 40A in the first direction X. The four first subgroups and four second subgroups may be located on the side of the fourth subgroup in the first direction X.

[0095] In some possible implementations, the third subgroup may include n1 fourth resistors arranged sequentially along the first direction X, and the fourth subgroup may include n2 fourth resistors arranged sequentially along the first direction X, where n1 and n2 are positive integers greater than 1, and are not limited herein.

[0096] In an exemplary embodiment, the first terminal of the first resistor 40A is connected to the input terminal of the electrostatic discharge (ESD) protection device. The second terminal of the first resistor 40A is connected to the second terminal of the grounding transistor GT, the gate electrode of the first P-type transistor PT1, and the gate electrode of the first N-type transistor NT1. The first terminal of the first P-type transistor PT1, the first terminal of the second P-type transistor PT2, and the second terminal of the P-type diode PD are connected to the first power supply line. The gate electrode of the grounding transistor GT, the first terminal of the grounding transistor GT, the first terminal of the first N-type transistor NT1, the first terminal of the second N-type transistor NT2, and the first terminal of the N-type diode ND are connected to the grounding line. The second terminals of the first P-type transistor PT1, the first terminal of the first N-type transistor NT1, the gate electrode of the second P-type transistor PT2, and the gate electrode of the second N-type transistor NT2 are interconnected. The second terminal of the second P-type transistor PT2 is connected to the first terminal of the second resistor 40B. The second terminal of the second N-type transistor NT2 is connected to the first terminal of the third resistor 40C. The second terminals of the second resistor 40B, the second terminal of the third resistor 40C, the first terminals of the P-type diode PD, and the second terminals of the N-type diode ND are connected to the output terminal of the ESD protection device.

[0097] In an exemplary embodiment, the first and second ends of the eight fourth resistors 40D are both connected to the ground wire.

[0098] In an exemplary embodiment, the electrostatic discharge (ESD) protection device may further include a first conductive ring 51 and a second conductive ring 52, wherein the second conductive ring 52 may be disposed on one side of the first conductive ring 51 in the second direction Y. The first conductive ring 51 and the second conductive ring 52 may be annular (e.g., rectangular ring). The first conductive ring 51 may be connected to a first power line, and the second conductive ring 52 may be connected to a grounding wire. A P-type transistor group 81 may be disposed within the space surrounded by the first conductive ring 51, and an N-type transistor group 82 and a resistor array 85 may be disposed within the space surrounded by the second conductive ring 52.

[0099] In an exemplary embodiment, the second conductive ring 52 may include a first conductive sub-ring 52A and a second conductive sub-ring 52B. The second conductive sub-ring 52B may be disposed on the side opposite to the second direction Y of the first conductive sub-ring 52A (the side closer to the first conductive ring 51). The first conductive sub-ring 52A and the second conductive sub-ring 52B may be annular (such as a rectangular ring) in shape and both are connected to the ground wire. The N-type transistor group 82 may be disposed within the space surrounded by the first conductive sub-ring 52A, and the resistor array 85 may be disposed within the space surrounded by the second conductive ring 52B.

[0100] In an exemplary embodiment, the first conductive sub-ring 52A and the second conductive sub-ring 52B can be interconnected. The conductive frame of the first conductive sub-ring 52A near the second conductive sub-ring 52B and the conductive frame of the second conductive sub-ring 52B near the first conductive sub-ring 52A can be the same conductive frame, that is, the first conductive sub-ring 52A and the second conductive sub-ring 52B can share the same conductive frame.

[0101] In an exemplary embodiment, the electrostatic discharge protection device may further include a third conductive ring 53 and a fourth conductive ring 54, wherein the fourth conductive ring 54 may be disposed on one side of the third conductive ring 53 in the second direction Y. The third conductive ring 53 and the fourth conductive ring 54 may be annular (e.g., rectangular ring) in shape and are both connected to a grounding wire. A P-type diode group 83 may be disposed within the space surrounded by the third conductive ring 53, and an N-type diode group 84 may be disposed within the space surrounded by the fourth conductive ring 54.

[0102] In an exemplary embodiment, the electrostatic discharge (ESD) protection device may further include a conductive ring connecting line 152, which may be a straight line extending along a first direction X. In the second direction Y, the conductive ring connecting line 152 may be disposed between the P-type diode group 83 and the N-type diode group 84. The conductive ring connecting line 152 may be connected, on one hand, to the conductive frame of the third conductive ring 53 near the fourth conductive ring 54, and on the other hand, to the conductive frame of the fourth conductive ring 54 near the third conductive ring 53.

[0103] In an exemplary embodiment, the conductive border of the third conductive ring 53 or the fourth conductive ring 54 may have a first width A1, and the conductive ring connecting line 152 may have a second width A2. The ratio of the second width A2 to the first width A1 may be greater than or equal to 3. The first width A1 may be the average width of the conductive border of the third conductive ring 53 on the side closer to the fourth conductive ring 54, the conductive border of the third conductive ring 53 on the side farther from the fourth conductive ring 54, the conductive border of the fourth conductive ring 54 on the side closer to the third conductive ring 53, or the conductive border of the fourth conductive ring 54 on the side farther from the third conductive ring 53. The second width A2 may be the average width of the conductive ring connecting line 152. The first width A1 and the second width A2 may be dimensions in the second direction Y.

[0104] In an exemplary embodiment, the electrostatic discharge (ESD) protection device may further include a fifth conductive ring 55, a sixth conductive ring 56, and a seventh conductive ring 57. The sixth conductive ring 56 may be disposed on one side of the fifth conductive ring 55 in the second direction Y, and the seventh conductive ring 57 may be disposed on one side of the sixth conductive ring 56 in the second direction Y. The fifth conductive ring 55, the sixth conductive ring 56, and the seventh conductive ring 57 are annular (e.g., rectangular rings) in shape and are all connected to the first power line. The first conductive ring 51 and the second conductive ring 52 may be disposed within the space surrounded by the fifth conductive ring 55, the third conductive ring 53 may be disposed within the space surrounded by the sixth conductive ring 56, and the fourth conductive ring 54 may be disposed within the space surrounded by the seventh conductive ring 57.

[0105] In an exemplary embodiment, the fifth conductive ring 55 and the sixth conductive ring 56 can be interconnected. The conductive frame of the fifth conductive ring 55 near the sixth conductive ring 56 and the conductive frame of the sixth conductive ring 56 near the fifth conductive ring 55 can be the same conductive frame, that is, the fifth conductive ring 55 and the sixth conductive ring 56 can share the same conductive frame.

[0106] In an exemplary embodiment, the sixth conductive ring 56 and the seventh conductive ring 57 can be interconnected. The conductive frame of the sixth conductive ring 56 near the seventh conductive ring 57 and the conductive frame of the seventh conductive ring 57 near the sixth conductive ring 56 can be the same conductive frame, that is, the sixth conductive ring 56 and the seventh conductive ring 57 can share the same conductive frame.

[0107] In an exemplary embodiment, the electrostatic discharge (ESD) protection device may further include multiple power supply lines 61, multiple grounding lines 62, and multiple output lines 63. The power supply lines 61, grounding lines 62, and output lines 63 may be strip-shaped extending along a second direction Y. The multiple power supply lines 61 may be arranged sequentially in a first direction X, the multiple grounding lines 62 may be arranged sequentially in a first direction X, and the multiple output lines 63 may be arranged sequentially in a first direction X. The first power supply line can be connected to the second terminal of multiple P-type diodes PD through the multiple power supply lines 61, the grounding line can be connected to the first terminal of multiple N-type diodes ND through the multiple grounding lines 62, and the output terminal can be connected to the first terminal of multiple P-type diodes PD and the second terminal of multiple N-type diodes ND through the multiple output lines 63.

[0108] In an exemplary embodiment, in the first direction X, the power supply trace 61 and the ground trace 62 can be arranged between two adjacent output traces 63, and in the second direction Y, the ground trace 62 can be arranged on one side of the power supply trace 61 in the second direction Y. The output trace 63 forms an interdigitated arrangement with the power supply trace 61 and the ground trace 62.

[0109] The following is an illustrative description of the fabrication process of an electrostatic discharge (ESD) protection device. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as depositing a film, coating the film with photoresist, mask exposure, development, etching, and photoresist stripping; for organic materials, processes include coating the organic material, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display device. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0110] In an exemplary embodiment, the process of preparing an electrostatic protection device may include the following steps.

[0111] (1) An N-well region, a P-well region, and an active area pattern are sequentially formed on a silicon substrate. In an exemplary embodiment, forming the N-well and P-well region patterns may include: providing a P-type silicon substrate; forming a photoresist pattern including an opening region by coating photoresist on the P-type silicon substrate, exposure, and development; removing the photoresist in the opening region to expose the surface of the P-type silicon substrate; implanting n-type dopant ions into the opening region by ion implantation; stripping off the remaining photoresist; and forming an N-well (N-type well, abbreviated as NW) region pattern and a P-well (P-type well, abbreviated as PW) region pattern on the P-type silicon substrate, as shown in FIG6. Subsequently, an active area (AA) pattern is formed on the silicon substrate with the aforementioned patterns, as shown in FIG7A and FIG7B, FIG7B being a schematic diagram of the active area in FIG7A.

[0112] In an exemplary embodiment, the silicon substrate may be a P-type silicon substrate, which may serve as the channel region of an N-type transistor.

[0113] In an exemplary embodiment, the N-well region pattern may include at least a first N-well region 10A, a second N-well region 10B, a first annular region 20A, a second annular region 20B, and a third annular region 20C, and the P-well region pattern may be located outside the N-well region pattern. The first N-well region 10A and the second N-well region 10B may be rectangular in shape, and the second N-well region 10B may be located on one side of the first N-well region 10A in the second direction Y, which can save the area occupied by the electrostatic discharge protection device.

[0114] In an exemplary embodiment, the first annular region 20A, the second annular region 20B, and the third annular region 20C can be annular (e.g., rectangular ring). The second annular region 20B can be disposed on one side of the first annular region 20A in the second direction Y, and the third annular region 20C can be disposed on one side of the second annular region 20B in the second direction Y. The first N-well region 10A can be disposed within and connected to the first annular region 20A, and the second N-well region 10B can be disposed within the second annular region 20B, surrounding the second N-well region 10B. The first annular region 20A, the second annular region 20B, and the third annular region 20C can form an annular region 20, configured to isolate this electrostatic discharge protection device from other electrostatic discharge protection devices, preventing latch-up caused by silicon substrate bias due to electrostatic discharge spike current.

[0115] In an exemplary embodiment, the first annular region 20A may be connected to the second annular region 20B, and the second annular region 20B may be connected to the third annular region 20C.

[0116] In an exemplary embodiment, the first N-well region 10A is configured to form a P-type transistor, the second N-well region 10B is configured to form a P-type diode, the first P-well region surrounded by the first annular region 20A is configured to form an N-type transistor, and the second P-well region surrounded by the third annular region 20C is configured to form an N-type diode.

[0117] In an exemplary embodiment, the active region pattern may include at least a transistor active group and a diode active group. The transistor active group may include a first P-type active group, a second P-type active group, a first N-type active group, a second N-type active group, and a ground active region 15, and the diode active group may include a third P-type active group, a fourth P-type active group, a third N-type active group, and a fourth N-type active group.

[0118] In an exemplary embodiment, the P-type first active group may include 10 first P-type active regions 11P, the P-type second active group may include 20 second P-type active regions 12P, the N-type first active group may include 10 first N-type active regions 11N, the N-type second active group may include 20 second N-type active regions 12N, the P-type third active group may include 24 third P-type active regions 13P, the P-type fourth active group may include 24 fourth P-type active regions 14P, the N-type third active group may include 24 third N-type active regions 13N, and the N-type fourth active group may include 24 fourth N-type active regions 14N.

[0119] In an exemplary embodiment, the 10 first P-type active regions 11P can be located within the range of the first N-well region 10A. The shape of the first P-type active regions 11P can be a strip shape extending along the second direction Y. The 10 first P-type active regions 11P can be arranged sequentially in the first direction X.

[0120] In an exemplary embodiment, 10 first P-type active regions 11P can be connected sequentially to form a first P-type active block that is interconnected into an integral structure.

[0121] In an exemplary embodiment, the 20 second P-type active regions 12P can be located within the range of the first N-well region 10A. The shape of the second P-type active regions 12P can be a strip shape extending along the second direction Y. The 20 second P-type active regions 12P can be arranged sequentially in the first direction X.

[0122] In an exemplary embodiment, the 20 second P-type active regions 12P can be divided into 4 groups. In each group, 5 second P-type active regions 12P arranged sequentially in the first direction X can be connected sequentially to form a second P-type active block that is interconnected into an integral structure. The 4 second P-type active blocks can be arranged sequentially in the first direction X.

[0123] In an exemplary embodiment, the 10 first N-type active regions 11N can be located within the range of the first P-well region. The shape of the first N-type active regions 11N can be a strip shape extending along the second direction Y. The 10 first N-type active regions 11N can be arranged sequentially in the first direction X.

[0124] In an exemplary embodiment, 10 first N-type active regions 11N can be connected sequentially to form a first N-type active block that is interconnected into an integral structure.

[0125] In an exemplary embodiment, the 20 second N-type active regions 12N can be located within the range of the first P-well region. The shape of the second N-type active regions 12N can be a strip shape extending along the second direction Y. The 20 second N-type active regions 12N can be arranged sequentially in the first direction X.

[0126] In an exemplary embodiment, the 20 second N-type active regions 12N can be divided into 4 groups. In each group, 5 second N-type active regions 12N arranged sequentially in the first direction X can be connected sequentially to form a second N-type active block that is interconnected into an integral structure. The 4 second N-type active blocks can be arranged sequentially in the first direction X.

[0127] In an exemplary embodiment, the grounded active region 15 may be located within the range of the first P-well region. The shape of the grounded active region 15 may be a strip shape extending along the second direction Y, and it may be located on the side of the first N-type active region 11N away from the second N-type active region 12N. That is, 10 first N-type active regions 11N may be located on the side of the grounded active region 15 in the first direction X, and 20 second N-type active regions 12N may be located on the side of the 10 first N-type active regions 11N in the first direction X.

[0128] In an exemplary embodiment, the 24 third P-type active regions 13P can be located within the area of ​​the second N-well region 10B. The third P-type active regions 13P are strip-shaped extending along the first direction X. The 24 third P-type active regions 13P form a 6*4 first active array including 6 active rows and 4 active columns. Each active row in the first active array includes 4 third P-type active regions 13P arranged sequentially in the first direction X, and the 6 active rows are arranged sequentially in the second direction Y. Each active column in the first active array includes 6 third P-type active regions 13P arranged sequentially in the second direction Y, and the 4 active columns are arranged sequentially in the first direction X.

[0129] In an exemplary embodiment, 24 fourth P-type active regions 14P can be located within the area of ​​the second N-well region 10B. The shape of the fourth P-type active regions 14P can be annular (such as a rectangular ring), and they can be disposed outside each third P-type active region 13P and surround the third P-type active region 13P. The 24 fourth P-type active regions 14P can form a 6*4 second active array including 6 active rows and 4 active columns. Each active row in the second active array includes 4 fourth P-type active regions 14P arranged sequentially in the first direction X, and the 6 active rows are arranged sequentially in the second direction Y. Each active column in the second active array includes 6 fourth P-type active regions 14P arranged sequentially in the second direction Y, and the 4 active columns are arranged sequentially in the first direction X.

[0130] In an exemplary embodiment, two adjacent fourth P-type active regions 14P in the first direction X can be connected to each other, and two adjacent fourth P-type active regions 14P in the second direction Y can be connected to each other. The 24 fourth P-type active regions 14P connected to each other form a grid structure.

[0131] In an exemplary embodiment, the 24 third-N type active regions 13N can be located within the area of ​​the second P-well region. The shape of the third-N type active regions 13N is a strip extending along the first direction X. The 24 third-N type active regions 13N form a 6*4 first active array including 6 active rows and 4 active columns. Each active row in the first active array includes 4 third-N type active regions 13N arranged sequentially in the first direction X, and the 6 active rows are arranged sequentially in the second direction Y. Each active column in the first active array includes 6 third-N type active regions 13N arranged sequentially in the second direction Y, and the 4 active columns are arranged sequentially in the first direction X.

[0132] In an exemplary embodiment, the 24 fourth N-type active regions 14N can be located within the area of ​​the second P-well region. The shape of the fourth N-type active regions 14N can be annular (such as a rectangular ring), and they can be disposed outside each third N-type active region 13N and surround the third N-type active region 13N. The 24 fourth N-type active regions 14N can form a 6*4 second active array including 6 active rows and 4 active columns. Each active row in the second active array includes 4 fourth N-type active regions 14N arranged sequentially in the first direction X, and the 6 active rows are arranged sequentially in the second direction Y. Each active column in the second active array includes 6 fourth N-type active regions 14N arranged sequentially in the second direction Y, and the 4 active columns are arranged sequentially in the first direction X.

[0133] In an exemplary embodiment, two adjacent fourth N-type active regions 14N in the first direction X can be connected to each other, and two adjacent fourth N-type active regions 14N in the second direction Y can be connected to each other. The 24 fourth N-type active regions 14N connected to each other form a grid structure.

[0134] In an exemplary embodiment, the active region pattern may further include a first active ring 21, a second active ring 22, a third active ring 23, a fourth active ring 24, a fifth active ring 25, a sixth active ring 26, and a seventh active ring 27.

[0135] In an exemplary embodiment, the first active ring 21 may be ring-shaped (such as a rectangular ring), and may be disposed outside the first P-type active group and the second P-type active group, and surround the first P-type active group and the second P-type active group. The first active ring 21 is configured as a protective structure for the P-type transistor.

[0136] In an exemplary embodiment, the second active ring 22 may be disposed on one side of the first active ring 21 in the second direction Y, and may include a first active sub-ring 22A and a second active sub-ring 22B. The first active sub-ring 22A may be annular (e.g., rectangular ring) in shape, and may be disposed outside the N-type first active group, the N-type second active group, and the grounded active region 15, and surround the N-type first active group, the N-type second active group, and the grounded active region 15. The first active sub-ring 22A is configured as a protective structure for the N-type transistor. The second active sub-ring 22B may be annular (e.g., rectangular ring) in shape, and may be disposed on the side of the first active sub-ring 22A close to the first active ring 21. The second active sub-ring 22B and the first active sub-ring 22A are interconnected, and the second active sub-ring 22B is configured as a protective structure for multiple resistors.

[0137] In an exemplary embodiment, the active frame of the first active sub-ring 22A near the second active sub-ring 22B and the active frame of the second active sub-ring 22B near the first active sub-ring 22A can be the same active frame, that is, the first active sub-ring 22A and the second active sub-ring 22B can share the same active frame extending along the first direction X.

[0138] In an exemplary embodiment, the first active sub-ring 22A and the second active sub-ring 22B can isolate the N-type transistor and the plurality of resistors, and the first active ring 21 and the second active ring 22 can isolate the P-type transistor and the N-type transistor.

[0139] In an exemplary embodiment, the third active ring 23 may be ring-shaped (such as a rectangular ring), and may be disposed outside the P-type third active group and the P-type fourth active group, and surround the P-type third active group and the P-type fourth active group. The third active ring 23 is configured as a protective structure for the P-type diode.

[0140] In an exemplary embodiment, the fourth active ring 24 may be ring-shaped (such as a rectangular ring), and may be disposed outside the N-type third active group and the N-type fourth active group, and surround the N-type third active group and the N-type fourth active group. The fourth active ring 24 is configured as a protective structure for the N-type diode.

[0141] In an exemplary embodiment, the third active ring 23 can be disposed on one side of the second active ring 22 in the second direction Y, and the fourth active ring 24 can be disposed on one side of the third active ring 23 in the second direction Y. The third active ring 23 and the fourth active ring 24 can isolate the P-type diode and the N-type diode, and can effectively shield the electrostatic discharge spike current between the P-type diode and the N-type diode.

[0142] In an exemplary embodiment, the fifth active ring 25 may be ring-shaped (such as a rectangular ring), and may be disposed outside the first active ring 21 and the second active ring 22, and surround the first active ring 21 and the second active ring 22. The fifth active ring 25 is configured as a protective structure for P-type transistors, N-type transistors and resistors.

[0143] In an exemplary embodiment, the sixth active ring 26 may be ring-shaped (such as a rectangular ring), and may be disposed outside the third active ring 23 and surround the third active ring 23. The sixth active ring 26 is configured as a protective structure for the P-type diode.

[0144] In an exemplary embodiment, the seventh active ring 27 may be annular (e.g., rectangular ring) in shape, and may be disposed outside the fourth active ring 24 and surround the fourth active ring 24. The seventh active ring 27 is configured as a protective structure for the N-type diode.

[0145] In an exemplary embodiment, the sixth active ring 26 may be disposed on one side of the fifth active ring 25 in the second direction Y, and the seventh active ring 27 may be disposed on one side of the sixth active ring 26 in the second direction Y. The fifth active ring 25 and the sixth active ring 26 may be interconnected, and the sixth active ring 26 and the seventh active ring 27 may be interconnected.

[0146] In an exemplary embodiment, the active frame of the fifth active ring 25 near the sixth active ring 26 and the active frame of the sixth active ring 26 near the fifth active ring 25 can be the same active frame, that is, the fifth active ring 25 and the sixth active ring 26 can share the same active frame extending along the first direction X.

[0147] In an exemplary embodiment, the active frame of the sixth active ring 26 near the seventh active ring 27 and the active frame of the seventh active ring 27 near the sixth active ring 26 can be the same active frame, that is, the sixth active ring 26 and the seventh active ring 27 can share the same active frame extending along the first direction X.

[0148] In an exemplary embodiment, the first active ring 21 may be located within the range of the N-well region, the second active ring 22, the third active ring 23 and the fourth active ring 24 may be located within the range of the P-well region, the fifth active ring 25 may be located within the range of the first annular region 20A, the sixth active ring 26 may be located within the range of the second annular region 20B, and the seventh active ring 27 may be located within the range of the third annular region 20C.

[0149] The exemplary embodiments disclosed herein first utilize multiple inner protective rings to isolate the P-type transistor, N-type transistor, P-type diode, N-type diode, and multiple resistors respectively, and then utilize multiple outer protective rings to isolate this electrostatic discharge protection device from other electrostatic discharge protection devices, which can effectively prevent latch-up effects caused by silicon substrate bias due to electrostatic discharge spike current.

[0150] (2) Forming a gate conductive layer pattern. In an exemplary embodiment, forming a gate conductive layer pattern may include: sequentially depositing a first insulating film and a polysilicon film on a silicon substrate on which the aforementioned pattern is formed; firstly, patterning the polysilicon film using a patterning process to form a first insulating layer covering the silicon substrate and a polysilicon layer disposed on the first insulating layer; and then doping the polysilicon layer to form a gate conductive layer pattern, as shown in Figures 8A and 8B, where Figure 8B is a schematic diagram of the gate conductive layer in Figure 8A.

[0151] In an exemplary embodiment, the gate conductive layer pattern may include at least a P-type gate electrode group, an N-type gate electrode group, and a resistor array. The P-type gate electrode group may include a first P-type gate electrode group and a second P-type gate electrode group, and the N-type gate electrode group may include a first N-type gate electrode group, an second N-type gate electrode group, and a ground gate electrode 35.

[0152] In an exemplary embodiment, the P-type first gate electrode group may include 10 first P-type gate electrodes 31P and 1 first P-type gate connection line 33P. The shape of the first P-type gate electrode 31P may be a strip extending along the second direction Y. The 10 first P-type gate electrodes 31P may be arranged sequentially in the first direction X. The orthographic projection of the first P-type gate electrode 31P on the silicon substrate at least partially overlaps with the orthographic projection of the first P-type active region 11P on the silicon substrate. The first P-type gate electrode 31P may serve as the gate electrode of the first P-type transistor. The shape of the first P-type gate connection line 33P may be a straight line or a broken line extending along the first direction X. It may be disposed on one side of the 10 first P-type gate electrodes 31P in the second direction Y and connected to the 10 first P-type gate electrodes 31P respectively.

[0153] In an exemplary embodiment, the 10 first P-type gate electrodes 31P and the 1 first P-type gate connection line 33P can be an integral structure that is interconnected and located within the space surrounded by the first active ring 21.

[0154] In an exemplary embodiment, the P-type second gate electrode group may include 20 second P-type gate electrodes 32P and 4 second P-type gate connection lines 34P. The shape of the second P-type gate electrodes 32P may be a strip shape extending along the second direction Y. The 20 second P-type gate electrodes 32P may be arranged sequentially in the first direction X. The orthographic projection of the second P-type gate electrodes 32P on the silicon substrate at least partially overlaps with the orthographic projection of the second P-type active region 12P on the silicon substrate. The second P-type gate electrodes 32P may serve as the gate electrodes of the second P-type transistor.

[0155] In an exemplary embodiment, the 20 second P-type gate electrodes 32P can be divided into 4 groups, each group including 5 second P-type gate electrodes 32P arranged sequentially in the first direction X. The shape of the second P-type gate connection line 34P can be a straight line or a broken line extending along the first direction X. The 4 second P-type gate connection lines 34P can be respectively disposed on one side of the 5 second P-type gate electrodes 32P in each group in the second direction Y, and each second P-type gate connection line 34P is respectively connected to the 5 second P-type gate electrodes 32P in each group.

[0156] In an exemplary embodiment, the five second P-type gate electrodes 32P and one second P-type gate connection line 34P in each group can be an integral structure that is interconnected, and all four groups are located within the space surrounded by the first active ring 21.

[0157] In an exemplary embodiment, the N-type first gate electrode group may include 10 first N-type gate electrodes 31N and 1 first N-type gate connection line 33N. The shape of the first N-type gate electrode 31N may be a strip extending along the second direction Y. The 10 first N-type gate electrodes 31N may be arranged sequentially in the first direction X. The orthographic projection of the first N-type gate electrode 31N on the silicon substrate at least partially overlaps with the orthographic projection of the first N-type active region 11N on the silicon substrate. The first N-type gate electrode 31N may serve as the gate electrode of the first N-type transistor. The shape of the first N-type gate connection line 33N may be a straight line or a broken line extending along the first direction X. It may be disposed on one side opposite to the second direction Y of the 10 first N-type gate electrodes 31N and connected to the 10 first N-type gate electrodes 31N respectively.

[0158] In an exemplary embodiment, the 10 first N-type gate electrodes 31N and the 1 first N-type gate connection line 33N can be an integral structure that is interconnected and located within the space surrounded by the first active sub-ring 22A.

[0159] In an exemplary embodiment, the N-type second gate electrode group may include 20 second N-type gate electrodes 32N and 4 second N-type gate connection lines 34N. The shape of the second N-type gate electrodes 32N may be a strip shape extending along the second direction Y. The 20 second N-type gate electrodes 32N may be arranged sequentially in the first direction X. The orthographic projection of the second N-type gate electrodes 32N on the silicon substrate at least partially overlaps with the orthographic projection of the second N-type active region 12N on the silicon substrate. The second N-type gate electrodes 32N may serve as the gate electrodes of the second N-type transistor.

[0160] In an exemplary embodiment, the 20 second N-type gate electrodes 32N can be divided into 4 groups, each group including 5 second N-type gate electrodes 32N arranged sequentially in the first direction X. The shape of the second N-type gate connection line 34N can be a straight line or a broken line extending along the first direction X. The 4 second N-type gate connection lines 34N can be respectively disposed on the opposite side of the second direction Y of the 5 second N-type gate electrodes 32N in each group, and each second N-type gate connection line 34N is connected to the 5 second N-type gate electrodes 32N in each group.

[0161] In an exemplary embodiment, the five second N-type gate electrodes 32N and one second N-type gate connection line 34N in each group can be an integral structure that is interconnected, and all four groups are located within the space surrounded by the first active sub-ring 22A.

[0162] In an exemplary embodiment, the ground gate electrode 35 is located within the space surrounded by the first active sub-ring 22A. The ground gate electrode 35 can be a strip shape extending along the second direction Y. The orthographic projection of the ground gate electrode 35 on the silicon substrate at least partially overlaps with the orthographic projection of the ground active region 15 on the silicon substrate. The ground gate electrode 35 can serve as the gate electrode of a ground transistor. The ground gate electrode 35 can be disposed on the side of the first N-type gate electrode 31N away from the second N-type gate electrode 32N, that is, 10 first N-type gate electrodes 31N can be disposed on the side of the ground gate electrode 35 in the first direction X, and 20 second N-type gate electrodes 32N can be disposed on the side of the 10 first N-type gate electrodes 31N in the first direction X.

[0163] In an exemplary embodiment, the resistor array may include at least 25 resistors arranged sequentially in the first direction X, and the resistors are polysilicon resistors. The 25 resistors may include one first resistor 40A, eight second resistors 40B, eight third resistors 40C, and eight fourth resistors 40D, and the resistor array is located within the space surrounded by the second active sub-ring 22B.

[0164] In an exemplary embodiment, in the second direction Y, the resistor array can be located between the P-type gate electrode group and the N-type gate electrode group; that is, the resistor array can be located between the first P-type gate electrode group and the first N-type gate electrode group, and between the second P-type gate electrode group and the second N-type gate electrode group. By placing the resistor array between the P-type gate electrode group and the N-type gate electrode group, this disclosure can effectively reduce the mutual influence between the P-type gate electrode and the N-type gate electrode, improve the operational reliability of the third circuit, and ensure the signal output quality of the third circuit.

[0165] In an exemplary embodiment, at least one first P-type gate electrode 31P or at least one second P-type gate electrode 32P in the P-type gate electrode group may have a first spacing S1 with at least one resistor in the resistor array, and at least one first N-type gate electrode 31N or at least one second N-type gate electrode 32N in the N-type gate electrode group may have a second spacing S2 with at least one resistor in the resistor array. The first spacing S1 may be greater than the second spacing S2. The first spacing S1 may be the minimum distance between the edge of the resistor near the P-type gate electrode group and the edge of the first P-type gate electrode 31P or the second P-type gate electrode 32P near the resistor array. The second spacing S2 may be the minimum distance between the edge of the resistor near the N-type gate electrode group and the edge of the first N-type gate electrode 31N or the second N-type gate electrode 32N near the resistor array. The first spacing S1 and the second spacing S2 may be dimensions in the second direction Y.

[0166] In an exemplary embodiment, the first resistor 40A, the second resistor 40B, the third resistor 40C, and the fourth resistor 40D can be block-shaped (e.g., rectangular), and the shapes and sizes of the multiple resistors can be substantially the same. In the first direction X, the spacing between two adjacent resistors can be substantially the same. In the second direction Y, the edges of the multiple resistors near the P-type gate electrode group can be substantially flush, and the edges of the multiple resistors near the N-type gate electrode group can be substantially flush.

[0167] In an exemplary embodiment, the eight second resistors 40B can be divided into four first subgroups. Each first subgroup includes two second resistors 40B arranged sequentially in the first direction X. The two second resistors 40B are configured to form a parallel structure, thus the eight second resistors 40B consist of four second resistors 40B connected in parallel in pairs. The eight third resistors 40C can be divided into four second subgroups. Each second subgroup includes two third resistors 40C arranged sequentially in the first direction X. The two third resistors 40C are configured to form a parallel structure, thus the eight third resistors 40C consist of four third resistors 40C connected in parallel in pairs.

[0168] In an exemplary embodiment, the four first subgroups and four second subgroups can be alternately arranged in the first direction X, that is, the arrangement of the eight second resistors 40B and the eight third resistors 40C is as follows: two second resistors 40B connected in parallel, two third resistors 40C connected in parallel, two second resistors 40B connected in parallel, two third resistors 40C connected in parallel, two second resistors 40B connected in parallel, two third resistors 40C connected in parallel, and two second resistors 40B and two third resistors 40C connected in parallel.

[0169] In an exemplary embodiment, since the second and third resistors are provided to increase the impedance of the path, ensuring that the electrostatic current is discharged from the N-type diode ND and the P-type diode PD, and preventing the electrostatic current from being discharged from the second N-type transistor NT2 and the second P-type transistor PT2, the resistance value of the second resistor is required to be equal to the resistance value of the third resistor, thus achieving impedance matching between the second resistor R2 and the third resistor. This disclosure effectively ensures impedance matching between the second resistor R2 and the third resistor by alternately arranging the second resistor 40B and the third resistor 40C.

[0170] In an exemplary embodiment, the eight fourth resistors 40D can be divided into a third subgroup and a fourth subgroup. The third subgroup may include five fourth resistors 40D arranged sequentially in the first direction X, and the fourth subgroup may include three fourth resistors 40D arranged sequentially in the first direction X. In the first direction X, the first resistor 40A may be disposed between the third and fourth subgroups.

[0171] In an exemplary embodiment, the third subgroup can be located on the side opposite to the first direction X of the first resistor 40A, the fourth subgroup can be located on the side of the first direction X of the first resistor 40A, and the four first subgroups and four second subgroups can be located on the side of the first direction X of the fourth subgroup.

[0172] In the exemplary embodiment, the resistance value accuracy of the first resistor is required to be relatively high, as the resistance value accuracy directly affects the trigger voltage of the grounding transistor. This disclosure effectively ensures the resistance value accuracy of the first resistor by providing a fourth resistor on both sides of the first resistor in the first direction X.

[0173] (3) Forming an N-type doped (SN) region pattern. In an exemplary embodiment, forming an N-type doped region pattern may include: coating a photoresist on a silicon substrate on which the aforementioned pattern is formed, forming a plurality of opening regions by exposure and development, removing the photoresist in the plurality of opening regions, and forming an N-type doped pattern in the opening regions by a doping process, as shown in Figures 9A and 9B, where Figure 9B is a schematic diagram of the N-type doped pattern in Figure 9A.

[0174] In an exemplary embodiment, the N-type doped region pattern may include at least a first N-type doped region 41N, a second N-type doped region 42N, a third N-type doped region 43N, a fourth N-type doped region 44N, a fifth N-type doped region 45N, a sixth N-type doped region 46N, and a seventh N-type doped region 47N.

[0175] In an exemplary embodiment, the first N-type doped region 41N may be rectangular in shape, and the orthographic projection of the first N-type doped region 41N on the silicon substrate at least partially overlaps with the orthographic projections of the 10 first N-type active regions 11N, the 20 second N-type active regions 12N, and the ground active region 15 on the silicon substrate.

[0176] In an exemplary embodiment, the orthogonal projection of the first N-type doped region 41N onto the silicon substrate may include the orthogonal projections of 10 first N-type active regions 11N, 20 second N-type active regions 12N, and the grounded active region 15 onto the silicon substrate.

[0177] In an exemplary embodiment, the second N-type doped region 42N can be a mesh structure. The orthogonal projection of the second N-type doped region 42N on the silicon substrate at least partially overlaps with the orthogonal projection of the 24 fourth P-type active regions 14P on the silicon substrate, forming 24 N-type doped fourth P-type active regions 14P. The N-type doped fourth P-type active regions 14P can serve as the N-type junction of a P-type diode.

[0178] In an exemplary embodiment, the orthogonal projection of the second N-type doped region 42N onto the silicon substrate may include the orthogonal projections of 24 fourth P-type active regions 14P onto the silicon substrate.

[0179] In an exemplary embodiment, the third N-type doped region 43N can be a doped array comprising 6 doped rows and 4 doped columns. The orthogonal projection of the third N-type doped region 43N on the silicon substrate at least partially overlaps with the orthogonal projections of the 24 third N-type active regions 13N on the silicon substrate, forming 24 N-type doped third N-type active regions 13N. The N-type doped third N-type active regions 13N can serve as the P-type junction of an N-type diode.

[0180] In an exemplary embodiment, the orthogonal projection of the third N-type doped region 43N onto the silicon substrate may include the orthogonal projections of 24 third N-type active regions 13N onto the silicon substrate.

[0181] In an exemplary embodiment, the fourth N-type doped region 44N can be ring-shaped (e.g., rectangular). The orthographic projection of the fourth N-type doped region 44N on the silicon substrate at least partially overlaps with the orthographic projection of the first active ring 21 on the silicon substrate. Therefore, the first active ring 21 is an N-type doped protective ring, which can reduce contact resistance and improve current discharge capability.

[0182] In an exemplary embodiment, the orthogonal projection of the fourth N-type doped region 44N onto the silicon substrate may include the orthogonal projection of the first active ring 21 onto the silicon substrate.

[0183] In an exemplary embodiment, the fifth N-type doped region 45N can be ring-shaped (e.g., rectangular). The orthographic projection of the fifth N-type doped region 45N on the silicon substrate at least partially overlaps with the orthographic projection of the fifth active ring 25 on the silicon substrate. Therefore, the fifth active ring 25 is an N-type doped protective ring, which can reduce contact resistance and improve current discharge capability.

[0184] In an exemplary embodiment, the orthogonal projection of the fifth N-type doped region 45N onto the silicon substrate may include the orthogonal projection of the fifth active ring 25 onto the silicon substrate.

[0185] In an exemplary embodiment, the sixth N-type doped region 46N can be ring-shaped (e.g., rectangular). The orthographic projection of the sixth N-type doped region 46N on the silicon substrate at least partially overlaps with the orthographic projection of the sixth active ring 26 on the silicon substrate. Therefore, the sixth active ring 26 is an N-type doped protective ring, which can reduce contact resistance and improve current discharge capability.

[0186] In an exemplary embodiment, the orthogonal projection of the sixth N-type doped region 46N onto the silicon substrate may include the orthogonal projection of the sixth active ring 26 onto the silicon substrate.

[0187] In an exemplary embodiment, the shape of the seventh N-type doped region 47N can be ring-shaped (such as rectangular). The orthographic projection of the seventh N-type doped region 47N on the silicon substrate at least partially overlaps with the orthographic projection of the seventh active ring 27 on the silicon substrate. Therefore, the seventh active ring 27 is an N-type doped protective ring, which can reduce contact resistance and improve current discharge capability.

[0188] In an exemplary embodiment, the orthogonal projection of the seventh N-type doped region 47N onto the silicon substrate may include the orthogonal projection of the seventh active ring 27 onto the silicon substrate.

[0189] In an exemplary embodiment, the fifth N-type doped region 45N and the sixth N-type doped region 46N can be interconnected, and the sixth N-type doped region 46N and the seventh N-type doped region 47N can be interconnected.

[0190] In an exemplary embodiment, the doping border of the fifth N-type doped region 45N near the sixth N-type doped region 46N and the doping border of the sixth N-type doped region 46N near the fifth N-type doped region 45N can be the same doping border, that is, the fifth N-type doped region 45N and the sixth N-type doped region 46N can share the same N-type doped border extending along the first direction X.

[0191] In an exemplary embodiment, the doping border of the sixth N-type doped region 46N near the seventh N-type doped region 47N and the doping border of the seventh N-type doped region 47N near the sixth N-type doped region 46N can be the same doping border, that is, the sixth N-type doped region 46N and the seventh N-type doped region 47N can share the same doping border extending along the first direction X.

[0192] (4) Forming a P-type doped (SP) region pattern. In an exemplary embodiment, forming a P-type doped region pattern may include: coating a photoresist on a silicon substrate on which the aforementioned pattern is formed, forming a plurality of opening regions by exposure and development, removing the photoresist in the plurality of opening regions, and forming a P-type doped region pattern in the opening regions by a doping process, as shown in Figures 10A and 10B, where Figure 10B is a schematic diagram of the P-type doped region in Figure 10A.

[0193] In an exemplary embodiment, the P-type doped pattern may be located outside the N-type doped pattern, meaning the P-type and N-type doped regions are complementary patterns. The P-type doped pattern may include at least a first P-type doped region 41P, a second P-type doped region 42P, a third P-type doped region 43P, a fourth P-type doped region 44P, a fifth P-type doped region 45P, a sixth P-type doped region 46P, and a seventh P-type doped region 47P.

[0194] In an exemplary embodiment, the first P-type doped region 41P can be rectangular in shape, and the orthographic projection of the first P-type doped region 41P on the silicon substrate at least partially overlaps with the orthographic projections of the 10 first P-type active regions 11P and the 20 second P-type active regions 12P on the silicon substrate.

[0195] In an exemplary embodiment, the orthogonal projection of the first P-type doped region 41P onto the silicon substrate may include the orthogonal projections of 10 first P-type active regions 11P and 20 second P-type active regions 12P onto the silicon substrate.

[0196] In an exemplary embodiment, the shape of the second P-type doped region 42P can be rectangular. The orthogonal projection of the second P-type doped region 42P on the silicon substrate at least partially overlaps with the orthogonal projections of the first resistor 40A to the fourth resistor 40D on the silicon substrate, forming a doped region of the polycrystalline silicon resistor.

[0197] In an exemplary embodiment, the orthogonal projection of the second P-type doped region 42P onto the silicon substrate may include the orthogonal projections of the first resistor 40A to the fourth resistor 40D onto the silicon substrate.

[0198] In an exemplary embodiment, the third P-type doped region 43P can be a doped array comprising 6 doped rows and 4 doped columns. The orthogonal projection of the third P-type doped region 43P on the silicon substrate at least partially overlaps with the orthogonal projections of the 24 third P-type active regions 13P on the silicon substrate, forming 24 P-type doped third P-type active regions 13P. The P-type doped third P-type active regions 13P can serve as the P-type junction of a P-type diode.

[0199] In an exemplary embodiment, the orthographic projection of the third P-type doped region 43P onto the silicon substrate may include the orthographic projections of 24 third P-type active regions 13P onto the silicon substrate.

[0200] In an exemplary embodiment, the fourth P-type doped region 44P can be a mesh structure. The orthogonal projection of the fourth P-type doped region 44P on the silicon substrate at least partially overlaps with the orthogonal projection of the 24 fourth N-type active regions 14N on the silicon substrate, forming 24 P-type doped fourth N-type active regions 14N. The P-type doped fourth N-type active regions 14N can serve as the N-type junction of an N-type diode.

[0201] In an exemplary embodiment, the orthogonal projection of the fourth P-type doped region 44P onto the silicon substrate may include the orthogonal projections of 24 fourth N-type active regions 14N onto the silicon substrate.

[0202] In an exemplary embodiment, the fifth P-type doped region 45P may include a first doped sub-ring 45A and a second doped sub-ring 45B. The first doped sub-ring 45A may be annular (e.g., rectangular), and its orthographic projection on the silicon substrate at least partially overlaps with the orthographic projection of the first active sub-ring 22A on the silicon substrate, thus the first active sub-ring 22A is a P-type doping protection ring. The second doped sub-ring 45B may be annular (e.g., rectangular), and its orthographic projection on the silicon substrate at least partially overlaps with the orthographic projection of the second active sub-ring 22B on the silicon substrate, thus the second active sub-ring 22B is a P-type doping protection ring.

[0203] In an exemplary embodiment, the doping border of the first doped sub-ring 45A near the second doped sub-ring 45B and the doping border of the second doped sub-ring 45B near the first doped sub-ring 45A can be the same doping border, that is, the first doped sub-ring 45A and the second doped sub-ring 45B can share the same doping border extending along the first direction X.

[0204] In an exemplary embodiment, the sixth P-type doped region 46P can be ring-shaped (e.g., rectangular). The orthographic projection of the sixth P-type doped region 46P on the silicon substrate at least partially overlaps with the orthographic projection of the third active ring 23 on the silicon substrate. Therefore, the third active ring 23 is a P-type doped protective ring, which can reduce contact resistance and improve current discharge capability.

[0205] In an exemplary embodiment, the orthogonal projection of the sixth P-type doped region 46P onto the silicon substrate may include the orthogonal projection of the third active ring 23 onto the silicon substrate.

[0206] In an exemplary embodiment, the shape of the seventh P-type doped region 47P can be ring-shaped (such as rectangular). The orthographic projection of the seventh P-type doped region 47P on the silicon substrate at least partially overlaps with the orthographic projection of the fourth active ring 24 on the silicon substrate. Therefore, the fourth active ring 24 is a P-type doped protective ring, which can reduce contact resistance and improve current discharge capability.

[0207] In an exemplary embodiment, the orthogonal projection of the seventh P-type doped region 47P onto the silicon substrate may include the orthogonal projection of the fourth active ring 24 onto the silicon substrate.

[0208] (5) Forming a second insulating layer pattern. In an exemplary embodiment, forming a second insulating layer pattern may include: depositing a second insulating film on a silicon substrate on which the aforementioned pattern is formed, and patterning the second insulating film by a patterning process to form a second insulating layer covering the gate conductive layer pattern, wherein a plurality of vias are provided on the second insulating layer, as shown in FIG11.

[0209] In an exemplary embodiment, the plurality of vias may include at least the first via V1 to the thirty-fourth via V34.

[0210] In an exemplary embodiment, the orthogonal projection of the first via V1 onto the silicon substrate may be located within the range of the orthogonal projection of the P-type source region of the first P-type active region 11P onto the silicon substrate. The first insulating layer and the second insulating layer within the first via V1 are etched away, exposing the surface of the P-type source region of the first P-type active region 11P. The first via V1 is configured to allow the subsequently formed first connection electrode to be connected to the P-type source region of the first P-type active region 11P through the via.

[0211] In an exemplary embodiment, the orthogonal projection of the second via V2 onto the silicon substrate may be within the range of the orthogonal projection of the P-type drain region of the first P-type active region 11P onto the silicon substrate. The first and second insulating layers within the second via V2 are etched away, exposing the surface. The second via V2 is configured to allow a subsequently formed second connection electrode to be connected to the P-type drain region of the first P-type active region 11P through the via.

[0212] In an exemplary embodiment, the orthogonal projection of the third via V3 onto the silicon substrate may be located within the range of the orthogonal projection of the P-type source region of the second P-type active region 12P onto the silicon substrate. The first and second insulating layers within the third via V3 are etched away, exposing the surface of the P-type source region of the second P-type active region 12P. The third via V3 is configured to allow the subsequently formed third connection electrode to be connected to the P-type source region of the second P-type active region 12P through the via.

[0213] In an exemplary embodiment, the orthogonal projection of the fourth via V4 onto the silicon substrate may be located within the orthogonal projection of the P-type drain region of the second P-type active region 12P onto the silicon substrate. The first and second insulating layers within the fourth via V4 are etched away, exposing the surface of the P-type drain region of the second P-type active region 12P. The fourth via V4 is configured to allow the subsequently formed fourth connection electrode to be connected to the P-type drain region of the second P-type active region 12P through the via.

[0214] In an exemplary embodiment, the orthogonal projection of the fifth via V5 onto the silicon substrate may be located within the range of the orthogonal projection of the N-type source region of the first N-type active region 11N onto the silicon substrate. The first and second insulating layers within the fifth via V5 are etched away, exposing the surface of the N-type source region of the first N-type active region 11N. The fifth via V5 is configured to allow the subsequently formed fifth connection electrode to be connected to the N-type source region of the first N-type active region 11N through the via.

[0215] In an exemplary embodiment, the orthogonal projection of the sixth via V6 onto the silicon substrate may be located within the range of the orthogonal projection of the N-type drain region of the first N-type active region 11N onto the silicon substrate. The first and second insulating layers within the sixth via V6 are etched away, exposing the surface of the N-type drain region of the first N-type active region 11N. The sixth via V6 is configured to allow the subsequently formed sixth connection electrode to be connected to the N-type drain region of the first N-type active region 11N through the via.

[0216] In an exemplary embodiment, the orthogonal projection of the seventh via V7 onto the silicon substrate may be located within the range of the orthogonal projection of the N-type source region of the second N-type active region 12N onto the silicon substrate. The first and second insulating layers within the seventh via V7 are etched away, exposing the surface of the N-type source region of the second N-type active region 12N. The seventh via V7 is configured to allow the subsequently formed seventh connection electrode to be connected to the N-type source region of the second N-type active region 12N through the via.

[0217] In an exemplary embodiment, the orthogonal projection of the eighth via V8 onto the silicon substrate may be located within the orthogonal projection of the N-type drain region of the second N-type active region 12N onto the silicon substrate. The first and second insulating layers within the eighth via V8 are etched away, exposing the surface of the N-type drain region of the second N-type active region 12N. The eighth via V8 is configured to allow the subsequently formed eighth connection electrode to be connected to the N-type drain region of the second N-type active region 12N through the via.

[0218] In an exemplary embodiment, the orthogonal projection of the ninth via V9 onto the silicon substrate may be within the range of the orthogonal projection of the source region of the ground active region 15 onto the silicon substrate. The first and second insulating layers within the ninth via V9 are etched away, exposing the surface of the source region of the ground active region 15. The ninth via V9 is configured to allow the subsequently formed ninth connection electrode to be connected to the source region of the ground active region 15 through the via.

[0219] In an exemplary embodiment, the orthographic projection of the tenth via V10 onto the silicon substrate may be located within the range of the orthographic projection of the drain region of the ground active region 15 onto the silicon substrate. The first and second insulating layers within the tenth via V10 are etched away, exposing the surface of the drain region of the ground active region 15. The tenth via V10 is configured to allow the subsequently formed tenth connection electrode to be connected to the drain region of the ground active region 15 through the via.

[0220] In an exemplary embodiment, the orthographic projection of the eleventh via V11 onto the silicon substrate may be located within the range of the orthographic projection of the first end of the first resistor 40A onto the silicon substrate. The second insulating layer within the eleventh via V11 is etched away, exposing the surface of the first end of the first resistor 40A. The eleventh via V11 is configured to allow the subsequently formed eleventh connection electrode to be connected to the first end of the first resistor 40A through the via.

[0221] In an exemplary embodiment, the orthogonal projection of the twelfth via V12 onto the silicon substrate may be located within the range of the orthogonal projection of the second end of the first resistor 40A onto the silicon substrate. The second insulating layer within the twelfth via V12 is etched away, exposing the surface of the second end of the first resistor 40A. The twelfth via V12 is configured to allow a subsequently formed twelfth connection electrode to be connected to the second end of the first resistor 40A through the via.

[0222] In an exemplary embodiment, the orthogonal projection of the thirteenth via V13 onto the silicon substrate may be located within the range of the orthogonal projection of the first end of the second resistor 40B onto the silicon substrate. The second insulating layer within the thirteenth via V13 is etched away, exposing the surface of the first end of the second resistor 40B. The thirteenth via V13 is configured to allow the subsequently formed thirteenth connection electrode to be connected to the first end of the second resistor 40B through the via.

[0223] In an exemplary embodiment, the orthogonal projection of the fourteenth via V14 onto the silicon substrate may be located within the range of the orthogonal projection of the second end of the second resistor 40B onto the silicon substrate. The second insulating layer within the fourteenth via V14 is etched away, exposing the surface of the second end of the second resistor 40B. The fourteenth via V14 is configured to allow the subsequently formed fourteenth connection electrode to be connected to the second end of the second resistor 40B through the via.

[0224] In an exemplary embodiment, the orthogonal projection of the fifteenth via V15 onto the silicon substrate may be located within the range of the orthogonal projection of the first end of the third resistor 40C onto the silicon substrate. The second insulating layer within the fifteenth via V15 is etched away, exposing the surface of the first end of the third resistor 40C. The fifteenth via V15 is configured to allow the subsequently formed fifteenth connection electrode to be connected to the first end of the third resistor 40C through the via.

[0225] In an exemplary embodiment, the orthogonal projection of the sixteenth via V16 onto the silicon substrate may be located within the range of the orthogonal projection of the second end of the third resistor 40C onto the silicon substrate. The second insulating layer within the sixteenth via V16 is etched away, exposing the surface of the second end of the third resistor 40C. The sixteenth via V16 is configured to allow the subsequently formed sixteenth connection electrode to be connected to the second end of the third resistor 40C through the via.

[0226] In an exemplary embodiment, the orthogonal projection of the seventeenth via V17 onto the silicon substrate may be located within the range of the orthogonal projection of the first end of the fourth resistor 40D onto the silicon substrate. The second insulating layer within the seventeenth via V17 is etched away, exposing the surface of the first end of the fourth resistor 40D. The seventeenth via V17 is configured to allow the subsequently formed seventeenth connection electrode to be connected to the first end of the fourth resistor 40D through the via.

[0227] In an exemplary embodiment, the orthogonal projection of the eighteenth via V18 onto the silicon substrate may be located within the range of the orthogonal projection of the second end of the fourth resistor 40D onto the silicon substrate. The second insulating layer within the eighteenth via V18 is etched away, exposing the surface of the second end of the fourth resistor 40D. The eighteenth via V18 is configured to allow the subsequently formed eighteenth connection electrode to be connected to the second end of the fourth resistor 40D through the via.

[0228] In an exemplary embodiment, the orthogonal projection of the nineteenth via V19 onto the silicon substrate may be within the range of the orthogonal projection of the first P-type gate connection line 33P onto the silicon substrate. The second insulating layer within the nineteenth via V19 is etched away, exposing the surface of the first P-type gate connection line 33P. The nineteenth via V19 is configured to allow the subsequently formed nineteenth connection electrode to be connected to the first P-type gate connection line 33P through the via.

[0229] In an exemplary embodiment, the orthogonal projection of the twentieth via V20 onto the silicon substrate may be located within the range of the orthogonal projection of the second P-type gate connection line 34P onto the silicon substrate. The second insulating layer within the twentieth via V20 is etched away, exposing the surface of the second P-type gate connection line 34P. The twentieth via V20 is configured to allow the subsequently formed twentieth connection electrode to be connected to the second P-type gate connection line 34P through the via.

[0230] In an exemplary embodiment, the orthogonal projection of the 21st via V21 onto the silicon substrate may be located within the range of the orthogonal projection of the first N-type gate connection line 33N onto the silicon substrate. The second insulating layer within the 21st via V21 is etched away, exposing the surface of the first N-type gate connection line 33N. The 21st via V21 is configured to allow the subsequently formed 21st connection electrode to be connected to the first N-type gate connection line 33N through the via.

[0231] In an exemplary embodiment, the orthogonal projection of the 22nd via V22 onto the silicon substrate may be within the range of the orthogonal projection of the second N-type gate connection line 34N onto the silicon substrate. The second insulating layer within the 22nd via V22 is etched away, exposing the surface of the second N-type gate connection line 34N. The 22nd via V22 is configured to allow the subsequently formed 22nd connection electrode to be connected to the second N-type gate connection line 34N through the via.

[0232] In an exemplary embodiment, the orthogonal projection of the 23rd via V23 onto the silicon substrate may be within the range of the orthogonal projection of the ground gate electrode 35 onto the silicon substrate. The second insulating layer within the 23rd via V23 is etched away, exposing the surface of the ground gate electrode 35. The 23rd via V23 is configured to allow the subsequently formed 23rd connection electrode to be connected to the ground gate electrode 35 through the via.

[0233] In an exemplary embodiment, the orthogonal projection of the 24th via V24 onto the silicon substrate may be located within the range of the orthogonal projection of the third P-type active region 13P onto the silicon substrate. The first and second insulating layers within the 24th via V24 are etched away, exposing the surface of the third P-type active region 13P. The 24th via V24 is configured to allow the subsequently formed 24th connection electrode to be connected to the third P-type active region 13P through the via.

[0234] In an exemplary embodiment, the orthogonal projection of the 25th via V25 onto the silicon substrate may be within the range of the orthogonal projection of the fourth P-type active region 14P onto the silicon substrate. The first and second insulating layers within the 25th via V25 are etched away, exposing the surface of the fourth P-type active region 14P. The 25th via V25 is configured to allow the subsequently formed 25th connection electrode to be connected to the fourth P-type active region 14P through the via.

[0235] In an exemplary embodiment, the orthogonal projection of the 26th via V26 onto the silicon substrate may be located within the range of the orthogonal projection of the third N-type active region 13N onto the silicon substrate. The first and second insulating layers within the 26th via V26 are etched away, exposing the surface of the third N-type active region 13N. The 26th via V26 is configured to allow the subsequently formed 26th connection electrode to be connected to the third N-type active region 13N through the via.

[0236] In an exemplary embodiment, the orthogonal projection of the 27th via V27 onto the silicon substrate may be within the range of the orthogonal projection of the fourth N-type active region 14N onto the silicon substrate. The first and second insulating layers within the 27th via V27 are etched away, exposing the surface of the fourth N-type active region 14N. The 27th via V27 is configured to allow the subsequently formed 27th connection electrode to be connected to the fourth N-type active region 14N through the via.

[0237] In an exemplary embodiment, the orthographic projection of the 28th via V28 onto the silicon substrate may be within the range of the orthographic projection of the first active ring 21 onto the silicon substrate. The first and second insulating layers within the 28th via V28 are etched away, exposing the surface of the first active ring 21. The 28th via V28 is configured to allow the subsequently formed first conductive ring to be connected to the first active ring 21 through the via.

[0238] In an exemplary embodiment, the orthographic projection of the 29th via V29 onto the silicon substrate may be within the range of the orthographic projection of the second active ring 22 onto the silicon substrate. The first and second insulating layers within the 29th via V29 are etched away, exposing the surface of the second active ring 22. The 29th via V29 is configured to allow a subsequently formed second conductive ring to be connected to the second active ring 22 through the via.

[0239] In an exemplary embodiment, the orthographic projection of the thirtieth via V30 onto the silicon substrate may be located within the range of the orthographic projection of the third active ring 23 onto the silicon substrate. The first and second insulating layers within the thirtieth via V30 are etched away, exposing the surface of the third active ring 23. The thirtieth via V30 is configured to allow the subsequently formed third conductive ring to be connected to the third active ring 23 through the via.

[0240] In an exemplary embodiment, the orthographic projection of the 31st via V31 onto the silicon substrate may be within the range of the orthographic projection of the fourth active ring 24 onto the silicon substrate. The first and second insulating layers within the 31st via V31 are etched away, exposing the surface of the fourth active ring 24. The 31st via V31 is configured to allow the subsequently formed fourth conductive ring to be connected to the fourth active ring 24 through the via.

[0241] In an exemplary embodiment, the orthogonal projection of the 32nd via V32 onto the silicon substrate may be located within the range of the orthogonal projection of the fifth active ring 25 onto the silicon substrate. The first and second insulating layers within the 32nd via V32 are etched away, exposing the surface of the fifth active ring 25. The 32nd via V32 is configured to allow the subsequently formed fifth conductive ring to be connected to the fifth active ring 25 through the via.

[0242] In an exemplary embodiment, the orthographic projection of the 33rd via V33 onto the silicon substrate may be within the range of the orthographic projection of the 6th active ring 26 onto the silicon substrate. The first and second insulating layers within the 33rd via V33 are etched away, exposing the surface of the 6th active ring 26. The 33rd via V33 is configured to allow the subsequently formed 6th conductive ring to be connected to the 6th active ring 26 through the via.

[0243] In an exemplary embodiment, the orthographic projection of the 34th via V34 onto the silicon substrate may be within the range of the orthographic projection of the 7th active ring 27 onto the silicon substrate. The first and second insulating layers within the 34th via V34 are etched away, exposing the surface of the 7th active ring 27. The 34th via V34 is configured to allow the subsequently formed 7th conductive ring to be connected to the 7th active ring 27 through the via.

[0244] In an exemplary embodiment, one or more of the first vias V1 to the thirty-fourth via V34 can be multiple to reduce contact resistance and increase connection reliability.

[0245] (6) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a first conductive thin film on a silicon substrate on which the aforementioned pattern is formed, patterning the first conductive thin film using a patterning process, and forming the first conductive layer pattern on a second insulating layer, as shown in Figures 12A and 12B, where Figure 12B is a schematic diagram of the first conductive layer in Figure 12A. In an exemplary embodiment, the first conductive layer may be referred to as a first metal layer.

[0246] In an exemplary embodiment, the first conductive layer pattern may include at least: a first connecting electrode 101 to a twenty-seventh connecting electrode 127.

[0247] In an exemplary embodiment, the first connection electrode 101 can be a strip extending along the second direction Y. Six first connection electrodes 101 can be arranged sequentially in the first direction X. Each of the six first connection electrodes 101 can be connected to the P-type source region of the first P-type active region 11P through a first via V1. In an exemplary embodiment, the first connection electrode 101 can serve as the first electrode of the first P-type transistor.

[0248] In an exemplary embodiment, the second connection electrode 102 can be a strip extending along the second direction Y. Five second connection electrodes 102 can be arranged sequentially in the first direction X. Each of the five second connection electrodes 102 can be connected to the P-type drain region of the first P-type active region 11P through a second via V2. In an exemplary embodiment, the second connection electrode 102 can serve as the second electrode of the first P-type transistor.

[0249] In an exemplary embodiment, six first connecting electrodes 101 and five second connecting electrodes 102 may be alternately arranged in the first direction X. At least one second connecting electrode 102 may be arranged between two adjacent first connecting electrodes 101 in the first direction X, and at least one first connecting electrode 101 may be arranged between two adjacent second connecting electrodes 102 in the first direction X.

[0250] In an exemplary embodiment, the third connection electrode 103 can be a strip extending along the second direction Y. Twelve third connection electrodes 103 can be arranged sequentially in the first direction X. Each of the twelve third connection electrodes 103 can be connected to the P-type source region of the second P-type active region 12P via a third via V3. In an exemplary embodiment, the third connection electrode 103 can serve as the first electrode of the second P-type transistor.

[0251] In an exemplary embodiment, the fourth connection electrode 104 can be a strip shape extending along the second direction Y. Twelve fourth connection electrodes 104 can be arranged sequentially in the first direction X. Each of the twelve fourth connection electrodes 104 can be connected to the P-type drain region of the second P-type active region 12P via a fourth via V4. In an exemplary embodiment, the fourth connection electrode 104 can serve as the second electrode of the second P-type transistor.

[0252] In an exemplary embodiment, 12 third connecting electrodes 103 and 12 fourth connecting electrodes 104 may be alternately arranged in the first direction X. At least one fourth connecting electrode 104 may be arranged between two adjacent third connecting electrodes 103 in the first direction X, and at least one third connecting electrode 103 may be arranged between two adjacent fourth connecting electrodes 104 in the first direction X.

[0253] In an exemplary embodiment, the fifth connection electrode 105 can be a strip extending along the second direction Y. Six fifth connection electrodes 105 can be arranged sequentially in the first direction X. Each of the six fifth connection electrodes 105 can be connected to the N-type source region of the first N-type active region 11N via a fifth via V5. In an exemplary embodiment, the fifth connection electrode 105 can serve as the first electrode of the first N-type transistor.

[0254] In an exemplary embodiment, the sixth connection electrode 106 can be a strip extending along the second direction Y. Five sixth connection electrodes 106 can be arranged sequentially in the first direction X. Each of the five sixth connection electrodes 106 can be connected to the N-type drain region of the first N-type active region 11N via a sixth via V6. In an exemplary embodiment, the sixth connection electrode 106 can serve as the second electrode of the first N-type transistor.

[0255] In an exemplary embodiment, six fifth connecting electrodes 105 and five sixth connecting electrodes 106 may be alternately arranged in the first direction X. At least one sixth connecting electrode 106 may be arranged between two adjacent fifth connecting electrodes 105 in the first direction X, and at least one fifth connecting electrode 105 may be arranged between two adjacent sixth connecting electrodes 106 in the first direction X.

[0256] In an exemplary embodiment, the seventh connection electrode 107 can be a strip extending along the second direction Y. Twelve seventh connection electrodes 107 can be arranged sequentially in the first direction X. Each of the twelve seventh connection electrodes 107 can be connected to the N-type source region of the second N-type active region 12N via a seventh via V7. In an exemplary embodiment, the seventh connection electrode 107 can serve as the first electrode of the second N-type transistor.

[0257] In an exemplary embodiment, the eighth connection electrode 108 can be a strip extending along the second direction Y. Twelve eighth connection electrodes 108 can be arranged sequentially in the first direction X. Each of the twelve eighth connection electrodes 108 can be connected to the N-type drain region of the second N-type active region 12N via an eighth via V8. In an exemplary embodiment, the eighth connection electrode 108 can serve as the second electrode of the second N-type transistor.

[0258] In an exemplary embodiment, 12 seventh connecting electrodes 107 and 12 eighth connecting electrodes 108 may be alternately arranged in the first direction X. At least one eighth connecting electrode 108 may be arranged between two adjacent seventh connecting electrodes 107 in the first direction X, and at least one seventh connecting electrode 107 may be arranged between two adjacent eighth connecting electrodes 108 in the first direction X.

[0259] In an exemplary embodiment, the ninth connection electrode 109 can be a strip shape extending along the second direction Y, and the ninth connection electrode 109 can be connected to the source region of the grounded active region 15 through the ninth via V9. In an exemplary embodiment, the ninth connection electrode 109 can serve as the first electrode of a grounded transistor.

[0260] In an exemplary embodiment, the tenth connection electrode 110 can be a strip shape extending along the second direction Y, and the tenth connection electrode 110 can be connected to the drain region of the grounded active region 15 through the tenth via V10. In an exemplary embodiment, the tenth connection electrode 110 can serve as the second electrode of a grounded transistor.

[0261] In an exemplary embodiment, the eleventh connecting electrode 111 can be block-shaped (such as rectangular), and the eleventh connecting electrode 111 can be connected to the first end of the first resistor 40A through the eleventh via V11.

[0262] In an exemplary embodiment, the twelfth connecting electrode 112 may be block-shaped (e.g., rectangular), and the twelfth connecting electrode 112 may be connected to the second end of the first resistor 40A through the twelfth via V12.

[0263] In an exemplary embodiment, the thirteenth connecting electrode 113 may be shaped as a strip extending along the first direction X, and each thirteenth connecting electrode 113 may be connected to the first end of the two second resistors 40B through the thirteenth via V13.

[0264] In an exemplary embodiment, the fourteenth connecting electrode 114 may be shaped as a strip extending along the first direction X, and each fourteenth connecting electrode 114 may be connected to the second end of the two second resistors 40B through the fourteenth via V14.

[0265] In an exemplary embodiment, since each thirteenth connecting electrode 113 is connected to the first end of the two second resistors 40B and each fourteenth connecting electrode 114 is connected to the second end of the two second resistors 40B, the two second resistors 40B are in parallel, and the eight second resistors 40B are four second resistors 40B connected in parallel in pairs.

[0266] In an exemplary embodiment, the fifteenth connecting electrode 115 may be shaped as a strip extending along the first direction X, and each fifteenth connecting electrode 115 may be connected to the first end of two third resistors 40C respectively through a fifteenth via V15.

[0267] In an exemplary embodiment, the sixteenth connecting electrode 116 may be shaped as a strip extending along the first direction X, and each sixteenth connecting electrode 116 may be connected to the second end of two third resistors 40C respectively through a sixteenth via V16.

[0268] In an exemplary embodiment, since each fifteenth connecting electrode 115 is connected to the first end of the two third resistors 40C and each sixteenth connecting electrode 116 is connected to the second end of the two third resistors 40C, the two third resistors 40C are in parallel, and the eight third resistors 40C are four third resistors 40C connected in parallel in pairs.

[0269] In an exemplary embodiment, the four thirteenth connecting electrodes 113 and the four fifteenth connecting electrodes 115 may be alternately arranged in the first direction X.

[0270] In an exemplary embodiment, the adjacent fourteenth connecting electrode 114 and sixteenth connecting electrode 116 can be an integral structure that is interconnected, thus realizing the interconnection between the second end of the second resistor 40B and the second end of the third resistor 40C. The four integrally structured fourteenth connecting electrode 114 and sixteenth connecting electrode 116 can be arranged sequentially in the first direction X.

[0271] In an exemplary embodiment, the shape of the seventeenth connecting electrode 117 can be extended along the first direction X into a strip shape, and can be respectively disposed on both sides of the eleventh connecting electrode 111. The seventeenth connecting electrode 117 located on the opposite side of the first direction X of the eleventh connecting electrode 111 can be connected to the first end of the five fourth resistors 40D through the seventeenth through hole V17, and the seventeenth connecting electrode 117 located on the first direction X side of the eleventh connecting electrode 111 can be connected to the first end of the three fourth resistors 40D through the seventeenth through hole V17.

[0272] In an exemplary embodiment, the shape of the eighteenth connecting electrode 118 can be a strip extending along the first direction X, and can be respectively disposed on both sides of the twelfth connecting electrode 112. The eighteenth connecting electrode 118 located on the opposite side of the first direction X of the twelfth connecting electrode 112 can be respectively connected to the second end of the five fourth resistors 40D through the eighteenth via V18, and the eighteenth connecting electrode 118 located on the first direction X side of the twelfth connecting electrode 112 can be respectively connected to the second end of the three fourth resistors 40D through the eighteenth via V18.

[0273] In an exemplary embodiment, the nineteenth connection electrode 119 may be shaped as a strip extending along the first direction X, and the nineteenth connection electrode 119 may be connected to the first P-type gate connection line 33P through the nineteenth via V19.

[0274] In an exemplary embodiment, the twentieth connection electrode 120 may be shaped as a strip extending along the first direction X, and the twentieth connection electrode 120 may be connected to the second P-type gate connection line 34P through the twentieth via V20.

[0275] In an exemplary embodiment, the shape of the twenty-first connecting electrode 121 can be a strip shape extending along the first direction X, and the twenty-first connecting electrode 121 can be connected to the first N-type gate connection line 33N through the twenty-first via V21.

[0276] In an exemplary embodiment, the shape of the second-second connecting electrode 122 can be a strip shape extending along the first direction X, and the second-second connecting electrode 122 can be connected to the second N-type gate connection line 34N through the second-second via V22.

[0277] In an exemplary embodiment, the shape of the second thirteenth connecting electrode 123 may be a strip shape extending along the first direction X, and the second thirteenth connecting electrode 123 may be connected to the ground grid electrode 35 through the second thirteenth via V23.

[0278] In an exemplary embodiment, the ninth connecting electrode 109 and the twenty-third connecting electrode 123 can be an integral structure interconnected with each other. Since the ninth connecting electrode 109 is connected to the source region of the grounded active region 15 and the twenty-third connecting electrode 123 is connected to the grounded gate electrode 35, the gate electrode and the first electrode of the grounded transistor GT are interconnected.

[0279] In an exemplary embodiment, the twenty-fourth connecting electrode 124 can be shaped as a strip extending along the first direction X. The 24 twenty-fourth connecting electrodes 124 form a 6*4 electrode array. Each of the 24 twenty-fourth connecting electrodes 124 can be connected to one of the 24 third P-type active regions 13P via a twenty-fourth via V24. In an exemplary embodiment, the twenty-fourth connecting electrode 124 can serve as the first electrode of a P-type diode.

[0280] In an exemplary embodiment, the twenty-fifth connecting electrode 125 can be ring-shaped, disposed outside each of the twenty-fourth connecting electrodes 124, and surrounding the twenty-fourth connecting electrodes 124. The 24 twenty-fifth connecting electrodes 125 can form a 6*4 electrode array. Adjacent twenty-fifth connecting electrodes 125 in the first direction X can be interconnected, and adjacent twenty-fifth connecting electrodes 125 in the second direction Y can be interconnected, forming a mesh structure with the 24 interconnected twenty-fifth connecting electrodes 125. The 24 twenty-fifth connecting electrodes 125 can be respectively connected to 24 fourth P-type active regions 14P through twenty-fifth vias V25. In an exemplary embodiment, the twenty-fifth connecting electrode 125 can serve as the second electrode of a P-type diode.

[0281] In an exemplary embodiment, the shape of the second sixteenth connecting electrode 126 can be a strip extending along the first direction X. The 24 second sixteenth connecting electrodes 126 form a 6*4 electrode array. Each of the 24 second sixteenth connecting electrodes 126 can be connected to one of the 24 third N-type active regions 13N via a second sixteenth via V26. In an exemplary embodiment, the second sixteenth connecting electrode 126 can serve as the second electrode of an N-type diode.

[0282] In an exemplary embodiment, the twenty-seventh connecting electrode 127 can be ring-shaped, disposed outside each twenty-sixth connecting electrode 126, and surrounding the twenty-sixth connecting electrode 126. The 24 twenty-seventh connecting electrodes 127 can form a 6*4 electrode array. Adjacent twenty-seventh connecting electrodes 127 in the first direction X can be interconnected, and adjacent twenty-seventh connecting electrodes 127 in the second direction Y can be interconnected, forming a mesh structure with the 24 interconnected twenty-seventh connecting electrodes 127. The 24 twenty-seventh connecting electrodes 127 can be respectively connected to 24 fourth N-type active regions 14N through twenty-seventh vias V27. In an exemplary embodiment, the twenty-seventh connecting electrode 127 can serve as the first electrode of an N-type diode.

[0283] In an exemplary embodiment, the first conductive layer pattern may further include a first conductive ring 51, a second conductive ring 52, a third conductive ring 53, a fourth conductive ring 54, a fifth conductive ring 55, a sixth conductive ring 56, and a seventh conductive ring 57.

[0284] In an exemplary embodiment, the first conductive ring 51 can be annular (such as a rectangular ring) in shape, and can be disposed outside the plurality of first connecting electrodes 101 to the plurality of fourth connecting electrodes 104 and surround the plurality of first connecting electrodes 101 to the plurality of fourth connecting electrodes 104. The first conductive ring 51 can be connected to the first active ring 21 through the twenty-eighth via V28 to form a protective structure for the P-type transistor.

[0285] In an exemplary embodiment, the first conductive ring 51 can be connected to multiple first connecting electrodes 101 and multiple third connecting electrodes 103 simultaneously, thereby enabling the first electrodes of multiple first P-type transistors PT1, the first electrodes of multiple second P-type transistors PT2, and the first conductive ring 51 to have the same potential.

[0286] In an exemplary embodiment, the first conductive ring 51, the plurality of first connecting electrodes 101 and the plurality of third connecting electrodes 103 may be an integral structure that is interconnected.

[0287] In an exemplary embodiment, the second conductive ring 52 may include a first conductive sub-ring 52A and a second conductive sub-ring 52B. The first conductive sub-ring 52A may be annular (e.g., rectangular) and may be disposed outside the plurality of fifth connecting electrodes 105 to tenth connecting electrodes 110, surrounding the plurality of fifth connecting electrodes 105 to tenth connecting electrodes 110 to form a protective structure for an N-type transistor. The second conductive sub-ring 52B may be annular (e.g., rectangular) and may be disposed outside the eleventh connecting electrodes 111 to eighteenth connecting electrodes 118, surrounding the eleventh connecting electrodes 111 to eighteenth connecting electrodes 118 to form a protective structure for a resistor array. The second conductive ring 52 may be connected to the second active ring 22 through a twenty-ninth via V29, forming a protective structure for the N-type transistor and resistor.

[0288] In an exemplary embodiment, the second conductive ring 52B can be disposed on the side opposite to the second direction Y of the first conductive ring 52A, that is, the second conductive ring 52B can be disposed on the side of the first conductive ring 52A close to the first conductive ring 51, and the first conductive ring 52A and the second conductive ring 52B are connected to each other.

[0289] In an exemplary embodiment, the conductive frame of the first conductive ring 52A near the second conductive ring 52B and the conductive frame of the second conductive ring 52B near the first conductive ring 52A can be the same conductive frame, that is, the first conductive ring 52A and the second conductive ring 52B can share the same conductive frame extending along the second direction Y.

[0290] In an exemplary embodiment, the first conductive ring 52A can be connected to multiple fifth connection electrodes 105, multiple seventh connection electrodes 107 and a ninth connection electrode 109 simultaneously, thereby enabling the gate electrode of the ground transistor GT, the first electrode of the ground transistor GT, the first electrode of multiple first N-type transistors NT1, the first electrode of multiple second N-type transistors NT2 and the second conductive ring 52 to have the same potential.

[0291] In an exemplary embodiment, the second conductive electronic ring 52B can be connected to multiple seventeenth connecting electrodes 117 and multiple eighteenth connecting electrodes 118 simultaneously via a connecting strip, thereby realizing the interconnection between the first end and the second end of the fourth resistor 40D.

[0292] In an exemplary embodiment, the second conductive ring 52, the plurality of fifth connecting electrodes 105, the plurality of seventh connecting electrodes 107, the plurality of seventeenth connecting electrodes 117, the plurality of eighteenth connecting electrodes 118, the ninth connecting electrode 109, and the twenty-third connecting electrode 123 can be an integral structure that is interconnected.

[0293] In an exemplary embodiment, the third conductive ring 53 can be ring-shaped (such as a rectangular ring), and can be disposed outside the plurality of twenty-fourth connecting electrodes 124 and the plurality of twenty-fifth connecting electrodes 125, and surround the plurality of twenty-fourth connecting electrodes 124 and the plurality of twenty-fifth connecting electrodes 125. The third conductive ring 53 can be connected to the third active ring 23 through the thirtieth via V30 to form a protective structure for the P-type diode.

[0294] In an exemplary embodiment, the fourth conductive ring 54 can be ring-shaped and can be disposed outside the plurality of twenty-sixth connecting electrodes 126 and the plurality of twenty-seventh connecting electrodes 127, and surround the plurality of twenty-sixth connecting electrodes 126 and the plurality of twenty-seventh connecting electrodes 127. The fourth conductive ring 54 can be connected to the fourth active ring 24 through the thirty-first via V31 to form a protective structure for an N-type diode.

[0295] In an exemplary embodiment, the fifth conductive ring 55 can be ring-shaped, and can be disposed outside the first conductive ring 51 and the second conductive ring 52, and surround the first conductive ring 51 and the second conductive ring 52. The fifth conductive ring 55 can be connected to the fifth active ring 25 through the thirty-second via V32.

[0296] In an exemplary embodiment, the sixth conductive ring 56 can be ring-shaped, can be disposed outside the third conductive ring 53 and surround the third conductive ring 53, and the sixth conductive ring 56 can be connected to the sixth active ring 26 through the thirty-third via V33.

[0297] In an exemplary embodiment, the seventh conductive ring 57 can be ring-shaped, can be disposed outside the fourth conductive ring 54 and surround the fourth conductive ring 54, and the seventh conductive ring 57 can be connected to the seventh active ring 27 through the thirty-fourth via V34.

[0298] In an exemplary embodiment, the sixth conductive ring 56 may be disposed on one side of the fifth conductive ring 55 in the second direction Y, and the seventh conductive ring 57 may be disposed on one side of the sixth conductive ring 56 in the second direction Y. The fifth conductive ring 55 and the sixth conductive ring 56 may be connected to each other, and the sixth conductive ring 56 and the seventh conductive ring 57 may be connected to each other.

[0299] In an exemplary embodiment, the conductive frame of the fifth conductive ring 55 near the sixth conductive ring 56 and the conductive frame of the sixth conductive ring 56 near the fifth conductive ring 55 can be the same conductive frame, that is, the fifth conductive ring 55 and the sixth conductive ring 56 can share the same conductive frame extending along the first direction X. Similarly, the conductive frame of the sixth conductive ring 56 near the seventh conductive ring 57 and the conductive frame of the seventh conductive ring 57 near the sixth conductive ring 56 can be the same conductive frame, that is, the sixth conductive ring 56 and the seventh conductive ring 57 can share the same conductive frame extending along the first direction X.

[0300] (7) Forming a third insulating layer pattern. In an exemplary embodiment, forming a third insulating layer pattern may include: depositing a third insulating film on a silicon substrate on which the aforementioned pattern is formed, and patterning the third insulating film by a patterning process to form a third insulating layer covering the pattern of the first conductive layer, wherein a plurality of vias are provided on the third insulating layer, as shown in FIG13.

[0301] In an exemplary embodiment, the plurality of vias may include vias V41 to V67.

[0302] In an exemplary embodiment, the orthographic projection of the forty-first via V41 on the silicon substrate may be located within the range of the orthographic projection of the first connection electrode 101 on the silicon substrate. The third insulating layer in the forty-first via V41 is etched away, exposing the surface of the first connection electrode 101. The forty-first via V41 is configured to allow the subsequently formed thirty-first connection electrode to be connected to the first connection electrode 101 through the via.

[0303] In an exemplary embodiment, the orthogonal projection of the forty-second via V42 on the silicon substrate may be located within the range of the orthogonal projection of the second connection electrode 102 on the silicon substrate. The third insulating layer within the forty-second via V42 is etched away, exposing the surface of the second connection electrode 102. The forty-second via V42 is configured to allow the subsequently formed thirty-second connection electrode to be connected to the second connection electrode 102 through the via.

[0304] In an exemplary embodiment, the orthogonal projection of the forty-third via V43 onto the silicon substrate may be located within the range of the orthogonal projection of the third connection electrode 103 onto the silicon substrate. The third insulating layer within the forty-third via V43 is etched away, exposing the surface of the third connection electrode 103. The forty-third via V43 is configured to allow the subsequently formed thirty-first connection electrode to be connected to the third connection electrode 103 through the via.

[0305] In an exemplary embodiment, the orthogonal projection of the forty-fourth via V44 onto the silicon substrate may be located within the range of the orthogonal projection of the fourth connection electrode 104 onto the silicon substrate. The third insulating layer within the forty-fourth via V44 is etched away, exposing the surface of the fourth connection electrode 104. The forty-fourth via V44 is configured to allow the subsequently formed thirty-third connection electrode to be connected to the fourth connection electrode 104 through the via.

[0306] In an exemplary embodiment, the orthogonal projection of the forty-fifth via V45 onto the silicon substrate may be within the range of the orthogonal projection of the fifth connection electrode 105 onto the silicon substrate. The third insulating layer within the forty-fifth via V45 is etched away, exposing the surface of the fifth connection electrode 105. The forty-fifth via V45 is configured to allow the subsequently formed thirty-fourth connection electrode to be connected to the fifth connection electrode 105 through the via.

[0307] In an exemplary embodiment, the orthogonal projection of the forty-sixth via V46 onto the silicon substrate may be within the range of the orthogonal projection of the sixth connection electrode 106 onto the silicon substrate. The third insulating layer within the forty-sixth via V46 is etched away, exposing the surface of the sixth connection electrode 106. The forty-sixth via V46 is configured to allow the subsequently formed thirty-fourth connection electrode to be connected to the sixth connection electrode 106 through the via.

[0308] In an exemplary embodiment, the orthographic projection of the forty-seventh via V47 onto the silicon substrate may be within the range of the orthographic projection of the seventh connection electrode 107 onto the silicon substrate. The third insulating layer within the forty-seventh via V47 is etched away, exposing the surface of the seventh connection electrode 107. The forty-seventh via V47 is configured to allow the subsequently formed thirty-fourth connection electrode to be connected to the seventh connection electrode 107 through the via.

[0309] In an exemplary embodiment, the orthographic projection of the forty-eighth via V48 onto the silicon substrate may be within the range of the orthographic projection of the eighth connection electrode 108 onto the silicon substrate. The third insulating layer within the forty-eighth via V48 is etched away, exposing the surface of the eighth connection electrode 108. The forty-eighth via V48 is configured to allow the subsequently formed thirty-fifth connection electrode to be connected to the eighth connection electrode 108 through the via.

[0310] In an exemplary embodiment, the orthogonal projection of the forty-ninth via V49 onto the silicon substrate may be within the range of the orthogonal projection of the ninth connection electrode 109 onto the silicon substrate. The third insulating layer within the forty-ninth via V49 is etched away, exposing the surface of the ninth connection electrode 109. The forty-ninth via V49 is configured to allow the subsequently formed thirty-fourth connection electrode to be connected to the ninth connection electrode 109 through the via.

[0311] In an exemplary embodiment, the orthographic projection of the fiftieth via V50 onto the silicon substrate may be within the range of the orthographic projection of the eleventh connection electrode 111 onto the silicon substrate. The third insulating layer within the fiftieth via V50 is etched away, exposing the surface of the eleventh connection electrode 111. The fiftieth via V50 is configured to allow the subsequently formed thirty-sixth connection electrode to be connected to the eleventh connection electrode 111 through the via.

[0312] In an exemplary embodiment, the orthographic projection of the 51st via V51 onto the silicon substrate may be within the range of the orthographic projection of the 12th connection electrode 112 onto the silicon substrate. The third insulating layer within the 51st via V51 is etched away, exposing the surface of the 12th connection electrode 112. The 51st via V51 is configured to allow the subsequently formed 37th connection electrode to be connected to the 12th connection electrode 112 through the via.

[0313] In an exemplary embodiment, the orthogonal projection of the 52nd via V52 onto the silicon substrate may be within the range of the orthogonal projection of the 13th connection electrode 113 onto the silicon substrate. The third insulating layer within the 52nd via V52 is etched away, exposing the surface of the 13th connection electrode 113. The 52nd via V52 is configured to allow the subsequently formed 39th connection electrode to be connected to the 13th connection electrode 113 through the via.

[0314] In an exemplary embodiment, the orthographic projection of the 53rd via V53 onto the silicon substrate may be located within the range of the orthographic projections of the 14th connection electrode 114 and the 16th connection electrode 116 of the integrated structure onto the silicon substrate. The third insulating layer within the 53rd via V53 is etched away, exposing the surfaces of the 14th connection electrode 114 and the 16th connection electrode 116 of the integrated structure. The 53rd via V53 is configured to allow the subsequently formed 41st connection electrode to be connected to the 14th connection electrode 114 and the 16th connection electrode 116 of the integrated structure through the via.

[0315] In an exemplary embodiment, the orthographic projection of the 54th via V54 onto the silicon substrate may be within the range of the orthographic projection of the 15th connection electrode 115 onto the silicon substrate. The third insulating layer within the 54th via V54 is etched away, exposing the surface of the 15th connection electrode 115. The 54th via V54 is configured to allow the subsequently formed 40th connection electrode to be connected to the 15th connection electrode 115 through the via.

[0316] In an exemplary embodiment, the orthographic projection of the 55th via V55 onto the silicon substrate may be within the range of the orthographic projection of the 19th connection electrode 119 onto the silicon substrate. The third insulating layer within the 55th via V55 is etched away, exposing the surface of the 19th connection electrode 119. The 55th via V55 is configured to allow the subsequently formed 42nd connection electrode to be connected to the 19th connection electrode 119 through the via.

[0317] In an exemplary embodiment, the orthogonal projection of the 56th via V56 onto the silicon substrate may be within the range of the orthogonal projection of the 20th connection electrode 120 onto the silicon substrate. The third insulating layer within the 56th via V56 is etched away, exposing the surface of the 20th connection electrode 120. The 56th via V56 is configured to allow the subsequently formed 43rd connection electrode to be connected to the 20th connection electrode 120 through the via.

[0318] In an exemplary embodiment, the orthographic projection of the 57th via V57 onto the silicon substrate may be within the range of the orthographic projection of the 21st connection electrode 121 onto the silicon substrate. The third insulating layer within the 57th via V57 is etched away, exposing the surface of the 21st connection electrode 121. The 57th via V57 is configured to allow the subsequently formed 44th connection electrode to be connected to the 21st connection electrode 121 through the via.

[0319] In an exemplary embodiment, the orthographic projection of the 58th via V58 onto the silicon substrate may be within the range of the orthographic projection of the 22nd connecting electrode 122 onto the silicon substrate. The third insulating layer within the 58th via V58 is etched away, exposing the surface of the 22nd connecting electrode 122. The 58th via V58 is configured to allow the subsequently formed 45th connecting electrode to be connected to the 22nd connecting electrode 122 through the via.

[0320] In an exemplary embodiment, the orthogonal projection of the 59th via V59 onto the silicon substrate may be within the range of the orthogonal projection of the 24th connection electrode 124 onto the silicon substrate. The third insulating layer within the 59th via V59 is etched away, exposing the surface of the 24th connection electrode 124. The 59th via V59 is configured to allow the subsequently formed 46th connection electrode to be connected to the 24th connection electrode 124 through the via.

[0321] In an exemplary embodiment, the orthographic projection of the sixtieth via V60 onto the silicon substrate may be within the range of the orthographic projection of the twenty-fifth connection electrode 125 onto the silicon substrate. The third insulating layer within the sixtieth via V60 is etched away, exposing the surface of the twenty-fifth connection electrode 125. The sixtieth via V60 is configured to allow the subsequently formed forty-seventh connection electrode to be connected to the twenty-fifth connection electrode 125 through the via.

[0322] In an exemplary embodiment, the orthographic projection of the sixty-first via V61 onto the silicon substrate may be within the range of the orthographic projection of the twenty-sixth connection electrode 126 onto the silicon substrate. The third insulating layer within the sixty-first via V61 is etched away, exposing the surface of the twenty-sixth connection electrode 126. The sixty-first via V61 is configured to allow the subsequently formed forty-eighth connection electrode to be connected to the twenty-sixth connection electrode 126 through the via.

[0323] In an exemplary embodiment, the orthogonal projection of the sixty-second via V62 onto the silicon substrate may be within the range of the orthogonal projection of the twenty-seventh connecting electrode 127 onto the silicon substrate. The third insulating layer within the sixty-second via V62 is etched away, exposing the surface of the twenty-seventh connecting electrode 127. The sixty-second via V62 is configured to allow the subsequently formed forty-ninth connecting electrode to be connected to the twenty-seventh connecting electrode 127 through the via.

[0324] In an exemplary embodiment, the orthographic projection of the sixty-third via V63 onto the silicon substrate can be located within the range of the orthographic projection of the conductive frame on the side of the first conductive ring 51 away from the second conductive ring 52 onto the silicon substrate. The third insulating layer within the sixty-third via V63 is etched away, exposing the surface of the conductive frame on the side of the first conductive ring 51 away from the second conductive ring 52. The sixty-third via V63 is configured to allow the subsequently formed thirty-first connection electrode to be connected to the conductive frame on the side of the first conductive ring 51 away from the second conductive ring 52 through the via.

[0325] In an exemplary embodiment, the orthographic projection of the sixty-fourth via V64 onto the silicon substrate may be located within the range of the orthographic projection of the conductive frame of the second conductive ring 52 on the side away from the first conductive ring 51 onto the silicon substrate. The third insulating layer within the sixty-fourth via V64 is etched away, exposing the surface of the conductive frame of the second conductive ring 52 on the side away from the first conductive ring 51. The sixty-fourth via V64 is configured to allow the subsequently formed thirty-fourth connection electrode to be connected to the conductive frame of the second conductive ring 52 on the side away from the first conductive ring 51 through the via.

[0326] In an exemplary embodiment, the orthographic projection of the sixty-fifth via V65 onto the silicon substrate may be located within the range of the orthographic projections of the two conductive frames of the sixth conductive ring 56 and the seventh conductive ring 57 that are far apart from each other onto the silicon substrate. The third insulating layer within the sixty-fifth via V65 is etched away, exposing the surfaces of the two conductive frames of the sixth conductive ring 56 and the seventh conductive ring 57 that are far apart from each other. The sixty-fifth via V65 is configured to allow the subsequently formed fifty-third or fifty-fourth connection electrode to be connected to the two conductive frames of the sixth conductive ring 56 and the seventh conductive ring 57 that are far apart from each other through the via.

[0327] In an exemplary embodiment, the orthographic projection of the sixty-sixth via V66 onto the silicon substrate can be located within the range of the orthographic projections of the two conductive frames on both sides of the third conductive ring 53 in the second direction Y onto the silicon substrate. The third insulating layer within the sixty-sixth via V66 is etched away, exposing the surfaces of the two conductive frames on both sides of the third conductive ring 53 in the second direction Y. The sixty-sixth via V66 is configured to allow the subsequently formed fiftieth or fifty-second connecting electrode to be connected to the two conductive frames on both sides of the third conductive ring 53 in the second direction Y through the via.

[0328] In an exemplary embodiment, the orthographic projection of the sixty-seventh via V67 onto the silicon substrate can be located within the range of the orthographic projections of the two conductive frames on both sides of the fourth conductive ring 54 in the second direction Y onto the silicon substrate. The third insulating layer within the sixty-seventh via V67 is etched away, exposing the surfaces of the two conductive frames on both sides of the fourth conductive ring 54 in the second direction Y. The sixty-seventh via V67 is configured to allow the subsequently formed fifty-first or fifty-second connecting electrode to be connected to the two conductive frames on both sides of the fourth conductive ring 54 in the second direction Y through the via.

[0329] In an exemplary embodiment, one or more of the forty-first vias V41 to the sixty-seventh via V67 may be multiple to reduce contact resistance and increase connection reliability.

[0330] (8) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: depositing a second conductive film on a silicon substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process, and forming the second conductive layer pattern on a third insulating layer, as shown in Figures 14A and 14B, where Figure 14B is a schematic diagram of the second conductive layer in Figure 14A. In an exemplary embodiment, the second conductive layer may be referred to as a second metal (Metal2) layer.

[0331] In an exemplary embodiment, the second conductive layer pattern may include at least: the thirty-first connecting electrode 131 to the fifty-fourth connecting electrode 154.

[0332] In an exemplary embodiment, the shape of the thirty-first connecting electrode 131 can be a strip shape extending along the first direction X. The thirty-first connecting electrode 131 can be connected to a plurality of first connecting electrodes 101 through the forty-first through hole V41, and can be connected to a plurality of third connecting electrodes 103 through the forty-third through hole V43. It can also be connected to the conductive frame of the first conductive ring 51 through the sixty-third through hole V63.

[0333] In an exemplary embodiment, the shape of the third second connecting electrode 132 may be a strip shape extending along the first direction X, and the third second connecting electrode 132 may be connected to a plurality of second connecting electrodes 102 through the fourth second via V42.

[0334] In an exemplary embodiment, the thirty-third connecting electrode 133 can be block-shaped (e.g., rectangular), and can be connected to multiple fourth connecting electrodes 104 via the forty-fourth via V44. In an exemplary embodiment, the four thirty-third connecting electrodes 133 can be arranged sequentially in the first direction X.

[0335] In an exemplary embodiment, the shape of the thirty-fourth connecting electrode 134 can be a strip shape extending along the first direction X. The thirty-fourth connecting electrode 134 can be connected to a plurality of fifth connecting electrodes 105 through the forty-fifth via V45, connected to a plurality of seventh connecting electrodes 107 through the forty-seventh via V47, connected to the ninth connecting electrode 109 through the forty-ninth via V49, and connected to the second conductive ring 52 through the sixty-fourth via V64. Thus, the interconnection between the first electrode of the first N-type transistor NT1, the first electrode of the second N-type transistor NT2, the gate electrode of the ground transistor GT, the first electrode of the ground transistor GT, and the second conductive ring 52 is realized.

[0336] In an exemplary embodiment, the shape of the thirty-fifth connecting electrode 135 may be a strip shape extending along the first direction X, and the thirty-fifth connecting electrode 135 may be connected to a plurality of sixth connecting electrodes 106 through the forty-sixth through-hole V46.

[0337] In an exemplary embodiment, the thirty-sixth connecting electrode 136 can be block-shaped (e.g., rectangular), and can be connected to multiple eighth connecting electrodes 108 via a forty-eighth via V48. In an exemplary embodiment, four thirty-sixth connecting electrodes 136 can be arranged sequentially in the first direction X.

[0338] In an exemplary embodiment, the shape of the thirty-seventh connecting electrode 137 can be block-shaped (such as rectangular), and the thirty-seventh connecting electrode 137 can be connected to the eleventh connecting electrode 111 through the fiftieth through-hole V50.

[0339] In an exemplary embodiment, the thirty-eighth connecting electrode 138 can be block-shaped (e.g., rectangular), and can be connected to the twelfth connecting electrode 112 via the fifty-first via V51. In another exemplary embodiment, the thirty-eighth connecting electrode 138 is configured to connect to the gate electrode of the first P-type transistor PT1 and the gate electrode of the first N-type transistor NT1 via a subsequently formed sixty-seventh connecting electrode, forming the first node N1 of the electrostatic discharge protection device. The thirty-eighth connecting electrode 138 can serve as the first node electrode of this disclosure.

[0340] In an exemplary embodiment, the shape of the thirty-ninth connecting electrode 139 can be block-shaped (such as rectangular), and the thirty-ninth connecting electrode 139 can be connected to the thirteenth connecting electrode 113 through the fifty-second via V52.

[0341] In an exemplary embodiment, the 40th connecting electrode 140 may be block-shaped (e.g., rectangular), and the 40th connecting electrode 140 may be connected to the 15th connecting electrode 115 through the 54th via V54.

[0342] In an exemplary embodiment, the four thirty-ninth connecting electrodes 139 and the four fortieth connecting electrodes 140 may be alternately arranged in the first direction X.

[0343] In an exemplary embodiment, the forty-first connecting electrode 141 can be a strip extending along the first direction X. The forty-first connecting electrode 141 can be connected to the fourteenth connecting electrodes 114 and the sixteenth connecting electrodes 116, which are integrally formed, via the fifty-third via V53. In another exemplary embodiment, the forty-first connecting electrode 141 is configured to be connected to the output terminal via a subsequently formed sixty-eighth connecting electrode. The forty-first connecting electrode 141 can serve as the output node electrode of this disclosure.

[0344] In an exemplary embodiment, a shielding opening K may be provided on the forty-first connecting electrode 141. The shape of the shielding opening K may be block-shaped (such as rectangular). The thirty-eighth connecting electrode 138 may be disposed within the shielding opening K, that is, the forty-first connecting electrode 141 surrounds the thirty-eighth connecting electrode 138, thus forming a structure in which the first node electrode is surrounded by the output node electrode. When an electrostatic event occurs, regardless of whether the electrostatic charge is positive or negative high voltage, the potential of the thirty-eighth connecting electrode 138 (first node N1) will cause the first inverter and the second inverter to conduct, and the output node electrode (third node N3) will be connected to the first power line or the ground line. That is, the output node electrode is at a constant potential. Therefore, the structure in which the output node electrode surrounds the first node electrode can effectively reduce the interference of electrostatic charge on the first node.

[0345] In an exemplary embodiment, the shape of the forty-second connecting electrode 142 may be a strip shape extending along the first direction X, and the forty-second connecting electrode 142 may be connected to the nineteenth connecting electrode 119 through the fifty-fifth through-hole V55.

[0346] In an exemplary embodiment, the shape of the forty-third connecting electrode 143 may be a strip shape extending along the first direction X, and the forty-third connecting electrode 143 may be connected to the twentieth connecting electrode 120 through the fifty-sixth through-hole V56.

[0347] In an exemplary embodiment, the shape of the forty-fourth connecting electrode 144 can be a strip shape extending along the first direction X, and the forty-fourth connecting electrode 144 can be connected to the twenty-first connecting electrode 121 through the fifty-seventh through-hole V57.

[0348] In an exemplary embodiment, the shape of the forty-fifth connecting electrode 145 may be a strip shape extending along the first direction X, and the forty-fifth connecting electrode 145 may be connected to the twenty-second connecting electrode 122 through the fifty-eighth via V58.

[0349] In an exemplary embodiment, the shape of the forty-sixth connecting electrode 146 can be a strip shape extending along the first direction X. The 24 forty-sixth connecting electrodes 146 form a 6*4 electrode array. The 24 forty-sixth connecting electrodes 146 can be respectively connected to the 24 twenty-fourth connecting electrodes 124 through the fifty-ninth via V59.

[0350] In an exemplary embodiment, the forty-seventh connecting electrode 147 can be ring-shaped, disposed outside each forty-sixth connecting electrode 146, and surrounding the forty-sixth connecting electrode 146. The 24 forty-seventh connecting electrodes 147 can form a 6*4 electrode array. Adjacent forty-seventh connecting electrodes 147 in the first direction X can be interconnected, and adjacent forty-seventh connecting electrodes 147 in the second direction Y can be interconnected, forming a mesh structure with the 24 interconnected forty-seventh connecting electrodes 147 forming a single integrated structure. The 24 forty-seventh connecting electrodes 147 can be respectively connected to the 24 twenty-fifth connecting electrodes 125 through the sixtieth via V60.

[0351] In an exemplary embodiment, the shape of the forty-eighth connecting electrode 148 can be a strip shape extending along the first direction X. The 24 forty-eighth connecting electrodes 148 form a 6*4 electrode array. The 24 forty-eighth connecting electrodes 148 can be respectively connected to the 24 twenty-sixth connecting electrodes 126 through the sixty-first via V61.

[0352] In an exemplary embodiment, the forty-ninth connecting electrode 149 can be ring-shaped, disposed outside each forty-eighth connecting electrode 148, and surrounding the forty-eighth connecting electrode 148. The 24 forty-ninth connecting electrodes 149 can form a 6*4 electrode array. Adjacent forty-ninth connecting electrodes 149 in the first direction X can be interconnected, and adjacent forty-ninth connecting electrodes 149 in the second direction Y can be interconnected, forming a mesh structure with the 24 interconnected forty-ninth connecting electrodes 149 forming a single integrated structure. The 24 forty-ninth connecting electrodes 149 can be respectively connected to the 24 twenty-seventh connecting electrodes 127 through the sixty-second via V62.

[0353] In an exemplary embodiment, the shape of the fiftieth connecting electrode 150 can be a straight line or a broken line extending along the first direction X, and it can be disposed on the side opposite to the second direction Y of the forty-seventh connecting electrode 147. The fiftieth connecting electrode 150 can be connected to the conductive frame on the side opposite to the second direction Y of the third conductive ring 53 through the sixty-sixth through hole V66.

[0354] In an exemplary embodiment, the shape of the fifty-first connecting electrode 151 can be a straight line or a broken line extending along the first direction X, and it can be disposed on one side of the forty-ninth connecting electrode 149 in the second direction Y. The fifty-first connecting electrode 151 can be connected to the conductive frame on the second direction Y side of the fourth conductive ring 54 through the sixty-seventh through hole V67.

[0355] In an exemplary embodiment, the shape of the fifty-second connecting electrode 152 can be a straight line or a broken line extending along the first direction X. It can be disposed between the forty-seventh connecting electrode 147 and the forty-ninth connecting electrode 149, that is, between the P-type diode and the N-type diode. The fifty-second connecting electrode 152 can be connected to the conductive frame of the third conductive ring 53 on the second direction Y side (near the fourth conductive ring 54) through the sixty-sixth via V66, and on the other hand, it can be connected to the conductive frame of the fourth conductive ring 54 on the opposite direction of the second direction Y (near the third conductive ring 53) through the sixty-seventh via V67, thus realizing the interconnection between the third conductive ring 53 and the fourth conductive ring 54. In an exemplary embodiment, the fifty-second connecting electrode 152 can serve as a conductive ring connecting line of this disclosure, which is configured to be connected to the subsequently formed grounding line.

[0356] In an exemplary embodiment, the conductive frame of the third conductive ring 53 or the fourth conductive ring 54 may have a first width A1, and the fifty-second connecting electrode 152 may have a second width A2. The ratio of the second width A2 to the first width A1 may be greater than or equal to 3, and the first width A1 and the second width A2 may be dimensions in the second direction Y. This disclosure, by providing a wider conductive ring connection line between the P-type diode and the N-type diode, and having the conductive ring connection line have a ground potential, can not only effectively prevent crosstalk between the P-type diode and the N-type diode, but also effectively increase the current discharge capability of the electrostatic discharge protection device.

[0357] In an exemplary embodiment, the shape of the fifty-third connecting electrode 153 can be a straight line or a broken line extending along the first direction X, and it can be disposed on the side of the fiftyth connecting electrode 150 away from the forty-seventh connecting electrode 147. The fifty-third connecting electrode 153 can be connected to the conductive frame of the sixth conductive ring 56 away from the seventh conductive ring 57 through the sixty-fifth through hole V65.

[0358] In an exemplary embodiment, the shape of the 54th connecting electrode 154 can be a straight line or a broken line extending along the first direction X, and it can be disposed on the side of the 51st connecting electrode 151 away from the 49th connecting electrode 149. The 54th connecting electrode 154 can be connected to the conductive frame of the 7th conductive ring 57 away from the 6th conductive ring 56 through the 65th through hole V65.

[0359] In an exemplary embodiment, since the sixth conductive ring 56 and the seventh conductive ring 57 are interconnected, the fifty-third connecting electrode 153 and the fifty-fourth connecting electrode 154 have the same potential.

[0360] (9) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming a fourth insulating layer pattern may include: depositing a fourth insulating film on a silicon substrate on which the aforementioned pattern is formed, and patterning the fourth insulating film by a patterning process to form a fourth insulating layer covering the pattern of the second conductive layer, wherein a plurality of vias are provided on the fourth insulating layer, as shown in FIG15.

[0361] In an exemplary embodiment, the plurality of vias may include via seventy-first V71 to via ninety-second V92.

[0362] In an exemplary embodiment, the orthogonal projection of the seventy-first via V71 onto the silicon substrate may be within the range of the orthogonal projection of the thirty-first connecting electrode 131 onto the silicon substrate. The fourth insulating layer within the seventy-first via V71 is etched away, exposing the surface of the thirty-first connecting electrode 131. The seventy-first via V71 is configured to allow the subsequently formed sixty-first connecting electrode to be connected to the thirty-first connecting electrode 131 through the via.

[0363] In an exemplary embodiment, the orthogonal projection of the 72nd via V72 onto the silicon substrate may be within the range of the orthogonal projection of the 32nd connection electrode 132 onto the silicon substrate. The fourth insulating layer within the 72nd via V72 is etched away, exposing the surface of the 32nd connection electrode 132. The 72nd via V72 is configured to allow the subsequently formed 62nd connection electrode to be connected to the 32nd connection electrode 132 through the via.

[0364] In an exemplary embodiment, the orthogonal projection of the seventy-third via V73 onto the silicon substrate may be within the range of the orthogonal projection of the thirty-third connecting electrode 133 onto the silicon substrate. The fourth insulating layer within the seventy-third via V73 is etched away, exposing the surface of the thirty-third connecting electrode 133. The seventy-third via V73 is configured to allow the subsequently formed sixty-third connecting electrode to be connected to the thirty-third connecting electrode 133 through the via.

[0365] In an exemplary embodiment, the orthogonal projection of the seventy-fourth via V74 onto the silicon substrate may be within the range of the orthogonal projection of the thirty-fourth connection electrode 134 onto the silicon substrate. The fourth insulating layer within the seventy-fourth via V74 is etched away, exposing the surface of the thirty-fourth connection electrode 134. The seventy-fourth via V74 is configured to allow the subsequently formed sixty-fourth connection electrode to be connected to the thirty-fourth connection electrode 134 through the via.

[0366] In an exemplary embodiment, the orthogonal projection of the 75th via V75 onto the silicon substrate may be within the range of the orthogonal projection of the 35th connection electrode 135 onto the silicon substrate. The fourth insulating layer within the 75th via V75 is etched away, exposing the surface of the 35th connection electrode 135. The 75th via V75 is configured to allow the subsequently formed 62nd connection electrode to be connected to the 35th connection electrode 135 through the via.

[0367] In an exemplary embodiment, the orthogonal projection of the seventy-sixth via V76 onto the silicon substrate may be within the range of the orthogonal projection of the thirty-sixth connection electrode 136 onto the silicon substrate. The fourth insulating layer within the seventy-sixth via V76 is etched away, exposing the surface of the thirty-sixth connection electrode 136. The seventy-sixth via V76 is configured to allow the subsequently formed sixty-fifth connection electrode to be connected to the thirty-sixth connection electrode 136 through the via.

[0368] In an exemplary embodiment, the orthogonal projection of the seventy-seventh via V77 onto the silicon substrate may be within the range of the orthogonal projection of the thirty-seventh connecting electrode 137 onto the silicon substrate. The fourth insulating layer within the seventy-seventh via V77 is etched away, exposing the surface of the thirty-seventh connecting electrode 137. The seventy-seventh via V77 is configured to allow the subsequently formed sixty-sixth connecting electrode to be connected to the thirty-seventh connecting electrode 137 through the via.

[0369] In an exemplary embodiment, the orthographic projection of the seventy-eighth via V78 on the silicon substrate may be within the range of the orthographic projection of the thirty-eighth connecting electrode 138 on the silicon substrate. The fourth insulating layer in the seventy-eighth via V78 is etched away, exposing the surface of the thirty-eighth connecting electrode 138. The seventy-eighth via V78 is configured to allow the subsequently formed sixty-seventh connecting electrode to be connected to the thirty-eighth connecting electrode 138 through the via.

[0370] In an exemplary embodiment, the orthographic projection of the seventy-ninth via V79 onto the silicon substrate may be within the range of the orthographic projection of the thirty-ninth connection electrode 139 onto the silicon substrate. The fourth insulating layer within the seventy-ninth via V79 is etched away, exposing the surface of the thirty-ninth connection electrode 139. The seventy-ninth via V79 is configured to allow the subsequently formed sixty-third connection electrode to be connected to the thirty-ninth connection electrode 139 through the via.

[0371] In an exemplary embodiment, the orthographic projection of the 80th via V80 onto the silicon substrate may be within the range of the orthographic projection of the 40th connection electrode 140 onto the silicon substrate. The fourth insulating layer within the 80th via V80 is etched away, exposing the surface of the 40th connection electrode 140. The 80th via V80 is configured to allow the subsequently formed 65th connection electrode to be connected to the 40th connection electrode 140 through the via.

[0372] In an exemplary embodiment, the orthogonal projection of the 81st via V81 onto the silicon substrate may fall within the range of the orthogonal projection of the 41st connection electrode 141 onto the silicon substrate. The fourth insulating layer within the 81st via V81 is etched away, exposing the surface of the 41st connection electrode 141. The 81st via V81 is configured to allow the subsequently formed 68th connection electrode to connect to the 41st connection electrode 141 through this via. The 81st via V81 on the 41st connection electrode 141 may include five sets of vias, which are arranged sequentially in the first direction.

[0373] In an exemplary embodiment, the orthogonal projection of the 82nd via V82 onto the silicon substrate may be within the range of the orthogonal projection of the 42nd connection electrode 142 onto the silicon substrate. The fourth insulating layer within the 82nd via V82 is etched away, exposing the surface of the 42nd connection electrode 142. The 82nd via V82 is configured to allow the subsequently formed 67th connection electrode to be connected to the 42nd connection electrode 142 through the via.

[0374] In an exemplary embodiment, the orthogonal projection of the 83rd via V83 onto the silicon substrate may be within the range of the orthogonal projection of the 43rd connection electrode 143 onto the silicon substrate. The fourth insulating layer within the 83rd via V83 is etched away, exposing the surface of the 43rd connection electrode 143. The 83rd via V83 is configured to allow the subsequently formed 62nd connection electrode to be connected to the 43rd connection electrode 143 through the via.

[0375] In an exemplary embodiment, the orthographic projection of the 84th via V84 onto the silicon substrate may be within the range of the orthographic projection of the 44th connection electrode 144 onto the silicon substrate. The fourth insulating layer within the 84th via V84 is etched away, exposing the surface of the 44th connection electrode 144. The 84th via V84 is configured to allow the subsequently formed 67th connection electrode to be connected to the 44th connection electrode 144 through the via.

[0376] In an exemplary embodiment, the orthographic projection of the 85th via V85 onto the silicon substrate may be within the range of the orthographic projection of the 45th connection electrode 145 onto the silicon substrate. The fourth insulating layer within the 85th via V85 is etched away, exposing the surface of the 45th connection electrode 145. The 85th via V85 is configured to allow the subsequently formed 62nd connection electrode to be connected to the 45th connection electrode 145 through the via.

[0377] In an exemplary embodiment, the orthographic projection of the 86th via V86 onto the silicon substrate may be within the range of the orthographic projection of the 46th connection electrode 146 onto the silicon substrate. The fourth insulating layer within the 86th via V86 is etched away, exposing the surface of the 46th connection electrode 146. The 86th via V86 is configured to allow the subsequently formed 69th connection electrode to be connected to the 46th connection electrode 146 through the via.

[0378] In an exemplary embodiment, the orthographic projection of the 87th via V87 onto the silicon substrate may be within the range of the orthographic projection of the 47th connection electrode 147 onto the silicon substrate. The fourth insulating layer within the 87th via V87 is etched away, exposing the surface of the 47th connection electrode 147. The 87th via V87 is configured to allow the subsequently formed 71st connection electrode to be connected to the 47th connection electrode 147 through the via.

[0379] In an exemplary embodiment, the orthographic projection of the 88th via V88 onto the silicon substrate may be within the range of the orthographic projection of the 48th connection electrode 148 onto the silicon substrate. The fourth insulating layer within the 88th via V88 is etched away, exposing the surface of the 48th connection electrode 148. The 88th via V88 is configured to allow the subsequently formed 69th connection electrode to be connected to the 48th connection electrode 148 through the via.

[0380] In an exemplary embodiment, the orthographic projection of the 89th via V89 onto the silicon substrate may be within the range of the orthographic projection of the 49th connection electrode 149 onto the silicon substrate. The fourth insulating layer within the 89th via V89 is etched away, exposing the surface of the 49th connection electrode 149. The 89th via V89 is configured to allow the subsequently formed 72nd connection electrode to be connected to the 49th connection electrode 149 through the via.

[0381] In an exemplary embodiment, the orthogonal projection of the 90th via V90 onto the silicon substrate may be within the range of the orthogonal projection of the 53rd connection electrode 153 onto the silicon substrate. The fourth insulating layer within the 90th via V90 is etched away, exposing the surface of the 53rd connection electrode 153. The 90th via V90 is configured to allow the subsequently formed 61st or 71st connection electrode to be connected to the 53rd connection electrode 153 through the via.

[0382] In an exemplary embodiment, the orthogonal projection of the ninety-first via V91 onto the silicon substrate may be within the range of the orthogonal projection of the fifty-first connecting electrode 151 onto the silicon substrate. The fourth insulating layer within the ninety-first via V91 is etched away, exposing the surface of the fifty-first connecting electrode 151. The ninety-first via V91 is configured to allow the subsequently formed seventy-second connecting electrode to be connected to the fifty-first connecting electrode 151 through the via.

[0383] In an exemplary embodiment, the orthogonal projection of the 92nd via V92 onto the silicon substrate may be within the range of the orthogonal projection of the 52nd connection electrode 152 onto the silicon substrate. The fourth insulating layer within the 92nd via V92 is etched away, exposing the surface of the 52nd connection electrode 152. The 92nd via V92 is configured to allow the subsequently formed 72nd connection electrode to be connected to the 52nd connection electrode 152 through the via.

[0384] In an exemplary embodiment, one or more of the seventy-first vias V71 to the ninety-second via V92 may be multiple to reduce contact resistance and increase connection reliability.

[0385] (10) Forming a third conductive layer pattern. In an exemplary embodiment, forming a third conductive layer pattern may include: depositing a third conductive film on a silicon substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process, and forming the third conductive layer pattern on a fourth insulating layer, as shown in Figures 16A and 16B, where Figure 16B is a schematic diagram of the third conductive layer in Figure 16A. In an exemplary embodiment, the third conductive layer may be referred to as a third metal (Metal3) layer.

[0386] In an exemplary embodiment, the third conductive layer pattern may include at least the sixty-first connecting electrode 161 to the sixty-ninth connecting electrode 169.

[0387] In an exemplary embodiment, the sixty-first connecting electrode 161 may be a strip shape extending along the second direction Y, and the sixty-first connecting electrode 161 may be connected to the thirty-first connecting electrode 131 through the seventy-first via V71.

[0388] In an exemplary embodiment, the shape of the sixty-second connecting electrode 162 can be a strip shape extending along the second direction Y. The sixty-second connecting electrode 162 can be connected to the thirty-second connecting electrode 132 through the seventy-second via V72, and to the thirty-fifth connecting electrode 135 through the seventy-fifth via V75. It can also be connected to the forty-third connecting electrode 143 through the eighty-third via V83, and to the forty-fifth connecting electrode 145 through the eighty-fifth via V85. Since the 32nd connecting electrode 132 is connected to the 2nd connecting electrode 102, the 2nd connecting electrode 102 can serve as the second electrode of the first P-type transistor. The 35th connecting electrode 135 is connected to the 6th connecting electrode 106, the 6th connecting electrode 106 can serve as the second electrode of the first N-type transistor. The 43rd connecting electrode 143 is connected to the 20th connecting electrode 120, the 20th connecting electrode 120 is connected to the gate electrode of the second P-type transistor through the second P-type gate connection line 34P. The 45th connecting electrode 145 is connected to the 22nd connecting electrode 122, the 22nd connecting electrode 122 is connected to the gate electrode of the second N-type transistor through the second N-type gate connection line 34N. Therefore, the 62nd connecting electrode 162 realizes the interconnection between the second electrode of the first P-type transistor PT1, the second electrode of the first N-type transistor NT1, the gate electrode of the second P-type transistor PT2, and the gate electrode of the second N-type transistor NT2, forming the second node N2 of the electrostatic discharge protection device.

[0389] In an exemplary embodiment, the sixty-third connecting electrode 163 can be a strip extending along the second direction Y. The sixty-third connecting electrode 163 can be connected to the thirty-third connecting electrode 133 via the seventy-third via V73, and also to the thirty-ninth connecting electrode 139 via the seventy-ninth via V79. Since the thirty-third connecting electrode 133 is connected to the fourth connecting electrode 104, which is connected to the P-type drain region of the second P-type active region 12P, and the thirty-ninth connecting electrode 139 is connected to the thirteenth connecting electrode 113, which is connected to the first end of the second resistor 40B, the sixty-third connecting electrode 163 achieves the interconnection between the second electrode of the second P-type transistor PT2 and the first end of the second resistor 40B. In an exemplary embodiment, the four sixty-third connecting electrodes 163 can be arranged sequentially along the first direction X.

[0390] In an exemplary embodiment, the sixty-fourth connecting electrode 164 may be a strip shape extending along the second direction Y, and the sixty-fourth connecting electrode 164 may be connected to the thirty-fourth connecting electrode 134 through the seventy-fourth via V74.

[0391] In an exemplary embodiment, the sixty-fifth connection electrode 165 can be a strip extending along the second direction Y. The sixty-fifth connection electrode 165 can be connected to the thirty-sixth connection electrode 136 via the seventy-sixth via V76, and to the fortieth connection electrode 140 via the eightieth via V80. Since the thirty-sixth connection electrode 136 is connected to the eighth connection electrode 108, and the eighth connection electrode 108 is connected to the N-type drain region of the second N-type active region 12N, and the fortieth connection electrode 140 is connected to the fifteenth connection electrode 115, and the fifteenth connection electrode 115 is connected to the first terminal of the third resistor 40C, the sixty-fifth connection electrode 165 achieves the interconnection between the second electrode of the second N-type transistor NT2 and the first terminal of the third resistor 40C. In an exemplary embodiment, the four sixty-fifth connection electrodes 165 can be arranged sequentially along the first direction X.

[0392] In an exemplary embodiment, the sixty-sixth connecting electrode 166 can be a strip extending along the second direction Y. The sixty-sixth connecting electrode 166 can be connected to the thirty-seventh connecting electrode 137 through the seventy-seventh through-hole V77. Since the thirty-seventh connecting electrode 137 is connected to the eleventh connecting electrode 111, and the eleventh connecting electrode 111 is connected to the first end of the first resistor 40A, the sixty-sixth connecting electrode 166 can serve as the input terminal of the electrostatic discharge protection device.

[0393] In an exemplary embodiment, the shape of the sixty-seventh connecting electrode 167 can be a strip shape extending along the second direction Y. The sixty-seventh connecting electrode 167 can be connected to the thirty-eighth connecting electrode 138 through the seventy-eighth via V78, to the forty-second connecting electrode 142 through the eighty-second via V82, and to the forty-fourth connecting electrode 144 through the eighty-fourth via V84. Since the thirty-eighth connecting electrode 138 is connected to the twelfth connecting electrode 112, and the twelfth connecting electrode 112 is connected to the second end of the first resistor 40A, the forty-second connecting electrode 142 is connected to the nineteenth connecting electrode 119, and the nineteenth connecting electrode 119 is connected to the first P-type gate electrode 31P through the first P-type gate connection line 33P, the forty-fourth connecting electrode 144 is connected to the twenty-first connecting electrode 121, and the twenty-first connecting electrode 121 is connected to the first N-type gate electrode 31N through the first N-type gate connection line 33N, the sixty-seventh connecting electrode 167 realizes the mutual connection between the second end of the first resistor 40A, the gate electrode of the first P-type transistor PT1, and the gate electrode of the first N-type transistor NT1, forming the first node N1 of the electrostatic discharge protection device.

[0394] In an exemplary embodiment, the sixty-eighth connecting electrode 168 can be a strip extending along the second direction Y, and can be disposed on one side of the sixty-sixth connecting electrode 166 in the second direction Y. The sixty-eighth connecting electrode 168 can be connected to the forty-first connecting electrode 141 through the eighty-first via V81. The sixty-eighth connecting electrode 168 is configured to be connected to a subsequently formed output terminal. Since the forty-first connecting electrode 141 is connected to the fourteenth connecting electrode 114 and the sixteenth connecting electrode 116, the fourteenth connecting electrode 114 is connected to the second end of the second resistor 40B, and the sixteenth connecting electrode 116 is connected to the second end of the third resistor 40C, the sixty-eighth connecting electrode 168 realizes the interconnection between the second end of the second resistor 40B and the second end of the third resistor 40C.

[0395] In an exemplary embodiment, the sixty-ninth connecting electrode 169 can be block-shaped (e.g., rectangular), and can be connected to the forty-first connecting electrode 141 via the eighty-first via V81. In another exemplary embodiment, the sixty-ninth connecting electrode 169 can serve as an auxiliary connecting electrode, improving etching uniformity. The four sixty-ninth connecting electrodes 169 can be arranged sequentially in the first direction X.

[0396] In an exemplary embodiment, the third conductive layer pattern may further include a power trace 61, a ground trace 62, an output trace 63, and an output connection line 64.

[0397] In an exemplary embodiment, the power trace 61 can be a strip shape extending along the second direction Y. Multiple power traces 61 can be connected to the forty-seventh connecting electrode 147 through the eighty-seventh via V87, and to the fifty-third connecting electrode 153 through the ninetieth via V90. One power trace 61 is also connected to the sixty-first connecting electrode 161. Since the sixty-first connecting electrode 161 is connected to the thirty-first connecting electrode 131, the thirty-first connecting electrode 131 realizes the connection between the first terminal of the first P-type transistor, the first terminal of the second P-type transistor, and the first conductive ring 51; the forty-seventh connecting electrode 147 is connected to the twenty-fifth connecting electrode 125, the twenty-fifth connecting electrode 125 is connected to the fourth P-type active region 14P; and the fifty-third connecting electrode 153 is connected to the seventh conductive ring 57, the seventh conductive ring 57 is connected to the fifth conductive ring 55 and the sixth conductive ring 56, thus realizing the connection between the first terminal of the first P-type transistor PT1, the first terminal of the second P-type transistor PT2, the second terminal of the P-type diode PD, the first conductive ring 51, the fifth conductive ring 55, the sixth conductive ring 56, and the seventh conductive ring 57.

[0398] In an exemplary embodiment, the grounding trace 62 can be a strip extending along the second direction Y. Multiple grounding traces 62 can be connected to the forty-ninth connecting electrode 149 via the eighty-ninth via V89, to the fifty-first connecting electrode 151 via the ninety-first via V91, and to the fifty-second connecting electrode 152 via the ninety-second via V92. Since the forty-ninth connecting electrode 149 is connected to the twenty-seventh connecting electrode 127, the twenty-seventh connecting electrode 127 is connected to the fourth N-type active region 14N, the fifty-first connecting electrode 151 is connected to the fourth conductive ring 54, and the fifty-second connecting electrode 152 achieves the connection between the third conductive ring 53 and the fourth conductive ring 54, the interconnection between the first electrode of the N-type diode ND, the third conductive ring 53, and the fourth conductive ring 54 is achieved.

[0399] In an exemplary embodiment, the output trace 63 can be a strip extending along the second direction Y. Multiple output traces 63 can be connected to the forty-sixth connecting electrode 146 via the eighty-sixth via V86, and to the forty-eighth connecting electrode 148 via the eighty-eighth via V88. One output trace 63 is also connected to the sixty-eighth connecting electrode 168. Since the forty-sixth connecting electrode 146 is connected to the twenty-fourth connecting electrode 124, the twenty-fourth connecting electrode 124 is connected to the third P-type active region 13P, the forty-eighth connecting electrode 148 is connected to the twenty-sixth connecting electrode 126, and the twenty-sixth connecting electrode 126 is connected to the third N-type active region 13N, the sixty-eighth connecting electrode 168 achieves the interconnection between the second terminal of the second resistor 40B and the second terminal of the third resistor 40C. This achieves the interconnection between the first terminal of the P-type diode PD, the second terminal of the N-type diode ND, the second terminal of the second resistor 40B, and the second terminal of the third resistor 40C, forming the third node N3 of the electrostatic discharge protection device.

[0400] In an exemplary embodiment, the output connection line 64 may be a strip shape extending along the first direction X, and the output connection line 64 may be connected to a plurality of output traces 63.

[0401] In an exemplary embodiment, the sixty-eighth connecting electrode 168, the output connecting line 64, and the multiple output traces 63 can be an integrated structure that is interconnected.

[0402] In an exemplary embodiment, multiple power traces 61 can be arranged sequentially in the first direction X, and the power traces 61 are configured to connect to a subsequently formed first power line. Multiple ground traces 62 can be arranged sequentially in the first direction X, and the ground traces 62 are configured to connect to a subsequently formed ground line. Multiple output traces 63 can be arranged sequentially in the first direction X, and the output traces 63 are configured to connect to a subsequently formed output terminal via a sixty-eighth connecting electrode 168. In the first direction X, the power traces 61 and ground traces 62 can be disposed between two adjacent output traces 63, and in the second direction Y, multiple ground traces 62 can be correspondingly disposed on one side of the multiple power traces 61 in the second direction Y. In this way, the output traces 63, power traces 61, and ground traces 62 form an interdigitated arrangement structure. This disclosure, by setting an interdigitated arrangement structure for output traces, power traces, and ground traces, can symmetrically arrange output traces, power traces, and ground traces while satisfying the connection relationship between P-type diodes and N-type diodes, thus ensuring the trace width of the electrostatic discharge protection device.

[0403] (11) Forming a fifth insulating layer pattern. In an exemplary embodiment, forming a fifth insulating layer pattern may include: depositing a fifth insulating film on a silicon substrate on which the aforementioned pattern is formed, and patterning the fifth insulating film by a patterning process to form a fifth insulating layer covering the pattern of the third conductive layer, wherein a plurality of vias are provided on the fifth insulating layer, as shown in FIG17.

[0404] In an exemplary embodiment, the plurality of vias may include vias V101 to V107.

[0405] In an exemplary embodiment, the orthographic projection of the first 101 via V101 onto the silicon substrate may be within the range of the orthographic projection of the sixty-first connection electrode 161 onto the silicon substrate. The fifth insulating layer within the first 101 via V101 is etched away, exposing the surface of the sixty-first connection electrode 161. The first 101 via V101 is configured to allow a subsequently formed first power line to be connected to the sixty-first connection electrode 161 through the via.

[0406] In an exemplary embodiment, the orthogonal projection of the first 102 via V102 onto the silicon substrate may be within the range of the orthogonal projection of the sixty-fourth connection electrode 164 onto the silicon substrate. The fifth insulating layer within the first 102 via V102 is etched away, exposing the surface of the sixty-fourth connection electrode 164. The first 102 via V102 is configured to allow a subsequently formed ground wire to be connected to the sixty-fourth connection electrode 164 through the via.

[0407] In an exemplary embodiment, the orthographic projection of the first 103 via V103 on the silicon substrate may be within the range of the orthographic projection of the sixty-eighth connecting electrode 168 on the silicon substrate. The fifth insulating layer within the first 103 via V103 is etched away, exposing the surface of the sixty-eighth connecting electrode 168. The first 103 via V103 is configured to allow subsequently formed output signal lines to be connected to the sixty-eighth connecting electrode 168 through the via.

[0408] In an exemplary embodiment, the orthographic projection of the first 104 via V104 on the silicon substrate may be within the range of the orthographic projection of the output connection line 64 on the silicon substrate. The fifth insulating layer within the first 104 via V104 is etched away, exposing the surface of the output connection line 64. The first 104 via V104 is configured to allow the subsequently formed output terminal to be connected to the output connection line 64 through the via.

[0409] In an exemplary embodiment, the orthographic projection of the first 105 via V105 on the silicon substrate may be within the range of the orthographic projection of the power trace 61 on the silicon substrate. The fifth insulating layer within the first 105 via V105 is etched away, exposing the surface of the power trace 61. The first 105 via V105 is configured to allow the subsequently formed first power line to be connected to the power trace 61 through the via.

[0410] In an exemplary embodiment, the orthographic projection of the first 106 via V106 on the silicon substrate may be within the range of the orthographic projection of the ground trace 62 on the silicon substrate. The fifth insulating layer within the first 106 via V106 is etched away, exposing the surface of the ground trace 62. The first 106 via V106 is configured to allow a subsequently formed ground trace to be connected to the ground trace 62 through the via.

[0411] In an exemplary embodiment, the orthographic projection of the first 107 via V107 onto the silicon substrate may be within the range of the orthographic projection of the sixty-ninth connection electrode 169 onto the silicon substrate. The fifth insulating layer within the first 107 via V107 is etched away, exposing the surface of the sixty-ninth connection electrode 169. The first 107 via V107 is configured to allow a subsequently formed output terminal to be connected to the sixty-ninth connection electrode 169 through the via.

[0412] In an exemplary embodiment, one or more of the 101st via V101 to the 107th via V107 can be multiple to reduce contact resistance and increase connection reliability.

[0413] (12) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming a fourth conductive layer pattern may include: depositing a fourth conductive thin film on a silicon substrate on which the aforementioned pattern is formed, patterning the fourth conductive thin film using a patterning process, and forming the fourth conductive layer pattern on a fifth insulating layer, as shown in Figures 18A and 18B, where Figure 18B is a schematic diagram of the fourth conductive layer in Figure 18A. In an exemplary embodiment, the fourth conductive layer may be referred to as a fourth metal layer (Metal4).

[0414] In an exemplary embodiment, the fourth conductive layer pattern may include at least: a first power line 71, a ground line 72, and an output terminal 73.

[0415] In an exemplary embodiment, the first power line 71 can be a strip extending along the first direction X. The first power line 71 can be connected to the sixty-first connecting electrode 161 through the first 101 via V101, and to the power trace 61 through the first 105 via V105. Since the sixty-first connecting electrode 161 connects the first terminal of the first P-type transistor PT1, the first terminal of the second P-type transistor PT2, the second terminal of the P-type diode PD, and the first conductive ring 51, and the power trace 61 connects the second terminal of the P-type diode PD, the fifth conductive ring 55, the sixth conductive ring 56, and the seventh conductive ring 57, the first terminal of the first P-type transistor PT1, the first terminal of the second P-type transistor PT2, the second terminal of the P-type diode PD, the first conductive ring 51, the fifth conductive ring 55, the sixth conductive ring 56, and the seventh conductive ring 57 have the potential of the first power line.

[0416] In an exemplary embodiment, a plurality of first openings K1 may be provided on the first power line 71.

[0417] In an exemplary embodiment, the grounding wire 72 can be a strip extending along the first direction X. The grounding wire 72 can be connected to the sixty-fourth connecting electrode 164 via the first 102 via V102, and to the grounding trace 62 via the first 106 via V106. Since the sixty-fourth connecting electrode 164 connects the first electrode of the first N-type transistor NT1, the first electrode of the second N-type transistor NT2, the first electrode of the grounding transistor GT, and the second conductive ring 52, and the grounding trace 62 connects the first electrode of the N-type diode ND, the third conductive ring 53, and the fourth conductive ring 54, the first electrode of the first N-type transistor NT1, the first electrode of the second N-type transistor NT2, the gate electrode and first electrode of the grounding transistor GT, the first electrode of the N-type diode ND, the second conductive ring 52, the third conductive ring 53, and the fourth conductive ring 54 all have the potential of a grounding wire.

[0418] In an exemplary embodiment, a plurality of second openings K2 may be provided on the grounding wire 72.

[0419] In an exemplary embodiment, the output terminal 73 can be a strip extending along the first direction X. The output terminal 73 can be connected to the sixty-eighth connecting electrode 168 via the first 103 via V103, to the output connecting line 64 via the first 104 via V104, and to the sixty-ninth connecting electrode 169 via the first 107 via V107. Since the sixty-eighth connecting electrode 168 is the third node N3 of the electrostatic discharge protection device, the connection between the output terminal 73 and the third node N3 is achieved.

[0420] In an exemplary embodiment, the first conductive ring 51 has the potential of the first power line, forming a protective structure for the first P-type transistor PT1 and the second P-type transistor PT2. The second conductive ring 52 has the potential of the ground line, forming a protective structure for the N-type transistor and the resistor. The third conductive ring 53 has the potential of the ground line, forming a protective structure for the P-type diode PD. The fourth conductive ring 54 has the potential of the ground line, forming a protective structure for the N-type diode ND. The fifth conductive ring 55, the sixth conductive ring 56, and the seventh conductive ring 57 have the potential of the first power line, which, on the one hand, isolates the transistors, P-type diodes, and N-type diodes, and on the other hand, isolates this electrostatic discharge protection device from other electrostatic discharge protection devices, effectively preventing latch-up effects caused by silicon substrate bias due to electrostatic discharge spike current.

[0421] In an exemplary embodiment, since the second conductive ring 52 has the potential of a ground wire, the second conductive sub-ring 52B in the second conductive ring 52 is connected to a plurality of seventeenth connecting electrodes 117 and a plurality of eighteenth connecting electrodes 118. The seventeenth connecting electrodes 117 are connected to the first ends of three fourth resistors 40D, and the eighteenth connecting electrodes 118 are connected to the second ends of the fourth resistors 40D. Therefore, the first and second ends of the fourth resistors 40D have the potential of a ground wire. This disclosure effectively ensures the resistance accuracy of the first resistor by setting fourth resistors on both sides of the first resistor in the first direction X. By setting the first and second ends of the fourth resistors to the ground wire, it effectively ensures that the fourth resistors have no electrical influence and will not affect the electrostatic protection device.

[0422] In an exemplary embodiment, the first power line 71 can be disposed on one side of the output terminal 73 in the second direction Y, and the grounding line 72 can be disposed on one side of the first power line 71 in the second direction Y, that is, the first power line 71 and the grounding line 72 of the output terminal 73 are arranged sequentially in the second direction Y.

[0423] This completes the fabrication of the electrostatic protection device of the exemplary embodiments of this disclosure.

[0424] In an exemplary embodiment, the first to fifth insulating layers can be silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON), etc., and can be a single-layer structure or a multi-layer composite structure. The first to fourth conductive layers can be made of metallic materials, such as silver (Ag), copper (Cu), aluminum (Al), or molybdenum (Mo), etc., or can be made of alloy materials composed of metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), etc. The alloy material can be a single-layer structure or a multi-layer composite structure, such as a composite structure composed of Mo, Cu, and Mo layers, etc. In an exemplary embodiment, the planar shape of the via can be rectangular, circular, or elliptical, etc., and the dimensions of multiple vias can be substantially the same or different; this disclosure does not limit this.

[0425] An exemplary embodiment of this disclosure provides an electrostatic discharge protection device that can be installed at the output port of a display driving circuit in a non-display area. This device can not only discharge electrostatic current generated inside and outside the integrated circuit IC, but also enhance the signal output by the integrated circuit IC.

[0426] This disclosure effectively reduces the mutual influence between the P-type and N-type gate electrodes by placing the resistor array between the P-type gate electrode group and the N-type gate electrode group, and the distance between the resistor array and the P-type gate electrode group is greater than the distance between the resistor array and the N-type gate electrode group. This improves the anti-interference capability, enhances the working reliability of the third circuit, and ensures the signal output quality of the third circuit.

[0427] This disclosure provides a fourth resistor on both sides of the first resistor in the first direction X, with the first and second ends of the fourth resistor connected to the grounding wire. This not only effectively ensures the resistance accuracy of the first resistor, but also effectively ensures that the fourth resistor has no electrical influence and will not affect the electrostatic protection device.

[0428] This disclosure effectively ensures impedance matching between the second and third resistors by setting the second and third resistors to be arranged alternately.

[0429] This disclosure, by setting a structure in which the first node electrode is surrounded by the output node electrode, can effectively reduce the interference of static electricity on the first node and improve the anti-interference capability.

[0430] This disclosure, by setting a wider conductive ring connection line between the P-type diode and the N-type diode, and having the conductive ring connection line have the potential of a ground wire, can not only effectively prevent crosstalk between the P-type diode and the N-type diode and improve the anti-interference capability, but also effectively increase the discharge current capability of the electrostatic protection device.

[0431] This disclosure, by setting an interdigitated arrangement structure for output traces, power traces, and ground traces, can symmetrically arrange output traces, power traces, and ground traces while satisfying the connection relationship between P-type diodes and N-type diodes. This not only ensures the trace width of the electrostatic discharge device but also ensures uniform discharge of metal, effectively improving heat dissipation and maximizing the discharge area while keeping the area of ​​the electrostatic discharge device as small as possible.

[0432] This disclosure, by setting multiple conductive rings, with the inner conductive rings isolating the P-type transistor, N-type transistor, P-type diode, N-type diode and multiple resistors respectively, and the outer conductive rings isolating this electrostatic discharge protection device from other electrostatic discharge protection devices, can effectively prevent latch-up effect caused by silicon substrate bias due to electrostatic discharge peak current, and avoid the failure of electrostatic discharge protection device.

[0433] This disclosure optimizes the layout of the electrostatic discharge (ESD) protection device through the above-described structural design, optimizes the layout space, reduces the area occupied by the ESD protection device, and improves circuit quality and signal quality. It can be applied to various pad types, functions, pitches, and quantities in silicon-based OLEDs.

[0434] The preparation process disclosed herein can be achieved using mature preparation equipment, requires minimal process modification, has high compatibility, is simple to implement, is easy to carry out, has high production efficiency, low production cost, and high yield.

[0435] The structure and fabrication process of the electrostatic protection device of the exemplary embodiments disclosed herein are merely illustrative examples. The corresponding structure and the patterning process may be modified or increased or decreased according to the actual situation. This disclosure does not limit the scope of the invention.

[0436] An exemplary embodiment of this disclosure also provides a display substrate, which may include a display area and a non-display area. The display area may include a plurality of sub-pixels, at least one sub-pixel including a pixel driving circuit and a light-emitting device connected to the pixel driving circuit, and the non-display area may include at least one of the aforementioned electrostatic discharge protection devices.

[0437] This exemplary embodiment also provides a display device including the aforementioned display substrate. The display device of this disclosure can be used in virtual reality (VR) devices, augmented reality (AR) devices, extended reality (XR) devices, mixed reality (MR) devices, sights, rangefinders, etc.

[0438] While the embodiments disclosed herein are as described above, it should be noted that these embodiments are merely exemplary and not restrictive. Therefore, this disclosure is not limited to the specific content shown and described herein. Various modifications, substitutions, or omissions can be made to the form and details of the embodiments without departing from the scope of this disclosure.

Claims

1. An electrostatic discharge (ESD) protection device, comprising a P-type transistor group, an N-type transistor group, and a resistor array, wherein the P-type transistor group includes a plurality of first P-type transistors and a plurality of second P-type transistors connected in parallel, the N-type transistor group includes a plurality of first N-type transistors and a plurality of second N-type transistors connected in parallel, and the resistor array includes a plurality of resistors, the plurality of resistors including at least a plurality of second resistors and a plurality of third resistors connected in parallel; the gate electrodes of the first P-type transistors and the gate electrodes of the first N-type transistors are connected, the first terminals of the first P-type transistors and the first terminals of the second P-type transistors are connected to a first power supply line, and the first terminals of the first N-type transistors and the first terminals of the second N-type transistors are connected to a first power supply line. The grounding wire is connected, and the second terminals of the first P-type transistor, the first N-type transistor, the gate electrode of the second P-type transistor, and the gate electrode of the second N-type transistor are connected. The second terminal of the second P-type transistor is connected to the output terminal through the second resistor, and the second terminal of the second N-type transistor is connected to the output terminal through the third resistor. The plurality of first P-type transistors and the plurality of second P-type transistors are arranged sequentially in a first direction, and the plurality of first N-type transistors and the plurality of second N-type transistors are arranged sequentially in a first direction. The P-type transistor group and the N-type transistor group are respectively disposed on both sides of the resistor array in a second direction, and the first direction and the second direction intersect.

2. The electrostatic discharge protection device of claim 1, wherein, At least one of the resistors has a first spacing with the gate electrode of at least one first P-type transistor or the gate electrode of at least one second P-type transistor, and at least one of the resistors has a second spacing with the gate electrode of at least one first N-type transistor or the gate electrode of at least one second N-type transistor, wherein the first spacing is greater than the second spacing, and the first spacing and the second spacing are dimensions in the second direction.

3. The electrostatic protection device according to claim 1, wherein, The plurality of second resistors are divided into m1 first subgroups, each first subgroup including m2 second resistors arranged sequentially along the first direction. The plurality of third resistors are divided into m1 second subgroups, each second subgroup including m2 third resistors arranged sequentially along the first direction. The first subgroups and the second subgroups are alternately arranged in the first direction, and m1 and m2 are positive integers greater than 1.

4. The electrostatic protection device according to claim 1, wherein, The N-type transistor group further includes a ground transistor, and the plurality of resistors further includes a first resistor. The first end of the first resistor is connected to the input terminal, and the second end of the first resistor is connected to the second electrode of the ground transistor, the gate electrode of the first P-type transistor, and the gate electrode of the first N-type transistor, respectively. The gate electrode of the ground transistor and the first electrode of the ground transistor are connected to the grounding wire. The plurality of first N-type transistors are disposed on one side of the ground transistor in the first direction, and the plurality of second N-type transistors are disposed on one side of the plurality of first N-type transistors in the first direction.

5. The electrostatic protection device according to claim 4, wherein, The plurality of resistors also includes a plurality of fourth resistors, the first end and the second end of the fourth resistors being connected to the grounding wire.

6. The electrostatic protection device according to claim 5, wherein, The plurality of fourth resistors are divided into a third subgroup and a fourth subgroup. The third subgroup includes n1 fourth resistors arranged sequentially along the first direction, and the second subgroup includes n2 fourth resistors arranged sequentially along the first direction, where n1 and n2 are positive integers greater than 1. The third subgroup is located on the side opposite to the first direction of the first resistor, and the fourth subgroup is located on the side of the first direction of the first resistor.

7. The electrostatic protection device according to claim 1, wherein, The first end of the second resistor is connected to the second electrode of the second P-type transistor, the first end of the third resistor is connected to the second electrode of the second N-type transistor, the second ends of the second resistor and the second ends of the third resistor are connected to each other through the output node electrode, the gate electrode of the first P-type transistor and the gate electrode of the first N-type transistor are connected to each other through the first node electrode, the output node electrode is provided with a shielding opening, and the first node electrode is disposed in the shielding opening.

8. The electrostatic protection device according to claim 7, wherein, The electrostatic discharge protection device includes multiple conductive layers, with the first node electrode and the output node electrode disposed in the same conductive layer.

9. The electrostatic discharge protection device according to any one of claims 1 to 8, wherein, The electrostatic discharge protection device further includes a first conductive ring and a second conductive ring. The second conductive ring is disposed on one side of the first conductive ring in the second direction. The first conductive ring and the second conductive ring are ring-shaped. The first conductive ring is connected to the first power line, and the second conductive ring is connected to the grounding wire. The P-type transistor group is disposed in the space surrounded by the first conductive ring, and the N-type transistor group and the resistor array are disposed in the space surrounded by the second conductive ring.

10. The electrostatic protection device according to claim 9, wherein, The second conductive ring includes a first conductive sub-ring and a second conductive sub-ring disposed on the side of the first conductive sub-ring close to the first conductive ring. The first conductive sub-ring and the second conductive sub-ring are in the shape of a ring. The N-type transistor group is disposed in the space surrounded by the first conductive sub-ring, and the resistor array is disposed in the space surrounded by the second conductive sub-ring.

11. The electrostatic protection device according to claim 10, wherein, The first conductive sub-ring and the second conductive sub-ring are connected to each other, and the conductive frame of the first conductive sub-ring near the second conductive sub-ring and the conductive frame of the second conductive sub-ring near the first conductive sub-ring are the same conductive frame.

12. The electrostatic protection device according to claim 10, wherein, The electrostatic protection device further includes a fifth conductive ring, which is ring-shaped and connected to the first power line. The first conductive ring and the second conductive ring are disposed within the space surrounded by the fifth conductive ring.

13. The electrostatic discharge protection device according to any one of claims 1 to 8, wherein, The electrostatic discharge protection device further includes a P-type diode group and an N-type diode group. The P-type diode group includes multiple P-type diodes connected in parallel, and the N-type diode group includes multiple N-type diodes connected in parallel. The first terminal of the N-type diode is connected to the grounding wire, and the second terminal of the P-type diode is connected to the first power supply line. The first terminals of the P-type diodes and the second terminals of the N-type diodes are connected to the output terminal. The P-type diode group is located on one side of the N-type transistor group in the second direction, and the N-type diode group is located on one side of the P-type diode group in the second direction.

14. The electrostatic discharge protection device according to claim 13, wherein, The output terminal is connected to the first terminal of the plurality of P-type diodes and the second terminal of the plurality of N-type diodes through multiple output traces. The first power line is connected to the second terminal of the plurality of P-type diodes through multiple power traces. The ground line is connected to the first terminal of the plurality of N-type diodes through multiple ground traces. The output traces, the power traces, and the ground traces are strip-shaped extending along the second direction. In the first direction, the power traces and the ground traces are arranged between two adjacent output traces. In the second direction, the ground trace is arranged on one side of the power trace in the second direction. The output traces, the power traces, and the ground traces form an interdigitated arrangement.

15. The electrostatic discharge protection device according to claim 14, wherein, The electrostatic discharge protection device further includes a third conductive ring and a fourth conductive ring. The fourth conductive ring is disposed on one side of the third conductive ring in the second direction. The third and fourth conductive rings are ring-shaped and are both connected to the grounding wire. The P-type diode group is disposed within the space surrounded by the third conductive ring, and the N-type diode group is disposed within the space surrounded by the fourth conductive ring.

16. The electrostatic discharge protection device according to claim 15, wherein, The electrostatic discharge protection device further includes a conductive ring connecting wire, which is disposed between the P-type diode group and the N-type diode group. The conductive ring connecting wire is connected to the conductive frame of the third conductive ring near the fourth conductive ring and the conductive frame of the fourth conductive ring near the third conductive ring, respectively.

17. The electrostatic discharge protection device according to claim 16, wherein, The conductive frame of the third or fourth conductive ring has a first width, the conductive ring connecting line has a second width, the ratio of the second width to the first width is greater than or equal to 3, and the first width and the second width are dimensions in the second direction.

18. The electrostatic protection device according to claim 16, wherein, The electrostatic discharge protection device further includes a sixth conductive ring and a seventh conductive ring; the sixth conductive ring and the seventh conductive ring are ring-shaped and are both connected to the first power line; the third conductive ring is disposed within the space surrounded by the sixth conductive ring, and the fourth conductive ring is disposed within the space surrounded by the seventh conductive ring.

19. The electrostatic discharge protection device according to claim 18, wherein, The sixth conductive ring and the seventh conductive ring are interconnected, and the conductive frame of the sixth conductive ring near the seventh conductive ring and the conductive frame of the seventh conductive ring near the sixth conductive ring are the same conductive frame.

20. A display substrate, comprising a display area and a non-display area; the display area comprising a plurality of sub-pixels, at least one sub-pixel comprising a pixel driving circuit and a light-emitting device connected to the pixel driving circuit, the non-display area comprising at least one electrostatic discharge protection device as described in any one of claims 1 to 19.

21. A display device comprising the display substrate as claimed in claim 20.

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