Display device and driving method therefor

Abstract

The present invention provides a display device and a driving method therefor. The display device comprises a display panel and a timing controller which are electrically connected. The timing controller is configured to increase a first refresh rate to a second refresh rate when the first refresh rate is less than a preset refresh rate, and is configured to acquire at least part of first picture information corresponding to the first refresh rate from a storage unit as repeated picture information, and is configured to drive, at the second refresh rate on the basis of the repeated picture information, the display panel to display pictures.

Description

Display device and its driving method

[0001] This application claims priority to Chinese patent application No. 202510088374.1, filed on January 20, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, and more specifically to display devices and their driving methods. Background Technology

[0003] When displaying a static image, the power consumption of the display device can generally be reduced by lowering the screen refresh rate. However, if the screen refresh rate is too low, flickering may occur. Invention Overview

[0004] The purpose of this invention is to provide a display device and its driving method to solve the problem of flickering caused by a low screen refresh rate.

[0005] In a first aspect, embodiments of the present invention provide a display device, comprising:

[0006] Display panel;

[0007] A timing controller, electrically connected to the display panel, is used to obtain the first refresh rate;

[0008] The source driver is electrically connected to the timing controller and the display panel;

[0009] The timing controller is configured to increase the first refresh rate to a second refresh rate when the first refresh rate is less than a preset refresh rate, and to obtain at least a portion of the first screen information corresponding to the first refresh rate from the storage unit as repeated screen information, and to drive the display panel to display the screen at the second refresh rate according to the repeated screen information.

[0010] The timing controller is used to control the source driver to generate a first data signal according to the first refresh rate, or to control the source driver to generate a second data signal according to the second refresh rate.

[0011] Wherein, the first data signal includes a first sub-data signal and a first sub-blank signal in each frame, the second data signal includes a second sub-data signal and a second sub-blank signal in each frame, and the total duration of the first sub-data signal and the first sub-blank signal is greater than the total duration of the second sub-data signal and the second sub-blank signal.

[0012] The multiple frames include a first type of frame corresponding to the first refresh rate and a second type of frame corresponding to the second refresh rate;

[0013] Among them, in the adjacent first type of frame and second type of frame, the first image information of the first type of frame and the second image information of the second type of frame both include the repeated image information.

[0014] Secondly, embodiments of the present invention provide a display device, including:

[0015] Display panel;

[0016] A timing controller, electrically connected to the display panel, is used to obtain the first refresh rate;

[0017] The timing controller is configured to increase the first refresh rate to a second refresh rate when the first refresh rate is less than a preset refresh rate, and to obtain at least a portion of the first screen information corresponding to the first refresh rate from the storage unit as repeated screen information, and to drive the display panel to display the screen at the second refresh rate according to the repeated screen information.

[0018] Thirdly, embodiments of the present invention also provide a driving method for a display device, including:

[0019] The timing controller acquires the first refresh rate;

[0020] When the first refresh rate is less than a preset refresh rate, the timing controller increases the first refresh rate to a second refresh rate.

[0021] The timing controller obtains at least a portion of the first screen information corresponding to the first refresh rate from the storage unit as repeated screen information;

[0022] The timing controller drives the display panel to display the image at the second refresh rate according to the repeated image information.

[0023] Beneficial Effects: This invention provides a display device and its driving method. The display device includes a display panel and a timing controller electrically connected to the display panel and used to obtain a first refresh rate. The timing controller improves flicker by increasing the first refresh rate to a second refresh rate when the first refresh rate is less than a preset refresh rate. It also improves flicker by obtaining at least a portion of the first screen information corresponding to the first refresh rate from a storage unit as repeated screen information and driving the display panel to display the screen at the second refresh rate according to the repeated screen information. This eliminates the need for the front end to send repeated screen information to the timing controller, and only sends other screen information (if any) in the second screen information besides the repeated screen information. Thus, this invention balances reducing the power consumption of the display device and reducing the risk of screen flicker. Attached Figure Description

[0024] Figure 1 is a structural diagram of the display device provided in an embodiment of the present invention.

[0025] Figures 2 and 3 are timing diagrams of some signals of the display device provided in the embodiments of the present invention.

[0026] Figure 4 is a simulation diagram of some of the signals in Figure 3.

[0027] Figures 5 and 6 are flowcharts of the driving method for the display device provided in the embodiments of the present invention. Embodiments of the present invention

[0028] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0029] In the description of this invention, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified; "electrical connection" indicates that the two are conductive, and is not limited to a direct or indirect connection.

[0030] In addition, it should be noted that the accompanying drawings only provide structures and steps that are closely related to the present invention, and omit some details that are not closely related to the invention. The purpose is to simplify the drawings and make the inventive points clear at a glance, rather than indicating that the actual device is exactly the same as the drawings, and not as a limitation on the actual device.

[0031] The present invention provides a display device, which may include, but is not limited to, the following embodiments and combinations thereof.

[0032] In some embodiments, as shown in FIG1, the display device 100 includes: a display panel 60; a timing controller 20 electrically connected to the display panel 60, configured to acquire a first refresh rate; wherein the timing controller 20 is configured to increase the first refresh rate to a second refresh rate when the first refresh rate is less than a preset refresh rate, to acquire at least a portion of the first screen information corresponding to the first refresh rate from the storage unit 201 as repeated screen information, and to drive the display panel 60 to display a screen at the second refresh rate according to the repeated screen information.

[0033] The display device 100 is, but is not limited to, an organic self-emissive display device, an inorganic self-emissive direct-view display device, or a liquid crystal display device. As shown in Figure 1, taking the arrangement of multiple sub-pixel P arrays in the display panel 60 as an example, the display device 100 may also include multiple gate lines 30, multiple pixel circuits 40 corresponding to the multiple sub-pixels P, a source driver 501 electrically connected to multiple data lines 10, and a gate driver 502 electrically connected to the multiple gate lines 30. The multiple gate lines 30, multiple data lines 10, multiple sub-pixels P, and multiple pixel circuits 40 may be located on a substrate (i.e., the display panel 60 included in the display device 100), and the gate driver 502 may be a gate driving circuit located on the substrate of the display device 100 or a chip independently of the substrate (Figure 1 only illustrates the former case).

[0034] Specifically, each sub-pixel P is electrically connected to the corresponding pixel circuit 40, and each gate line 30 is electrically connected to the multiple pixel circuits 40 corresponding to the multiple sub-pixels P in the corresponding row, and outputs the corresponding gate signal (gate or gate', including a first gate signal gateA or gateA' corresponding to the first refresh rate and a second gate signal gateB or gateB' corresponding to the second refresh rate). Under normal circumstances, in each frame, the gate signal includes a gate pulse p for controlling the opening of the corresponding multiple pixel circuits 40. The multiple row pixel circuits 40 are opened sequentially under the control of the multiple gate pulses p in the multiple gate signals gate. Each data line 10 is connected to the multiple pixel circuits 40 corresponding to the multiple sub-pixels P in the corresponding column to output the corresponding data signal (data or data', including a first data signal dataA or dataA' corresponding to the first refresh rate and a second data signal dataB or dataB' corresponding to the second refresh rate). The multiple data signals corresponding to the multiple columns of sub-pixels P are set to transmit the corresponding multiple valid data voltages to the multiple sub-pixels P in the corresponding row through the multiple data lines 10 when each row of sub-pixels P is turned on.

[0035] The timing controller 20 can obtain the current refresh rate of the display panel 60 as the first refresh rate, and the specific method of obtaining the first refresh rate is not limited. The display panel 60 displays the image at the first refresh rate based on the first frame information, that is, when the display panel 60 displays the image at the first refresh rate, at least one frame of the display image is generated based on the first frame information.

[0036] Specifically, in this embodiment, when the first refresh rate is less than the preset refresh rate, the timing controller 20 increases the first refresh rate to the second refresh rate, and obtains at least a portion of the first screen information corresponding to the first refresh rate from the storage unit 201 as repeated screen information, and drives the display panel 60 to display the screen at the second refresh rate according to the repeated screen information. That is, when the display panel 60 displays the screen at a larger second refresh rate, the second screen information and the first screen information on which at least one frame of the display screen is based both include repeated screen information.

[0037] The storage unit 201 may be included in the timing controller 20 or set independently of the timing controller 20. Figure 1 only illustrates the former.

[0038] Understandably, in this embodiment, the storage unit 201 stores the repeated screen information in the first screen information, and this repeated screen information is also used to constitute the second screen information. This eliminates the need for the front end to send repeated screen information to the timing controller 20, and only sends other screen information in the second screen information besides the repeated screen information (if any), thus reducing the power consumption of the display device 100. Simultaneously, when the first refresh rate is lower than the preset refresh rate, increasing the first refresh rate to the second refresh rate and displaying the screen according to the second screen information at a larger second refresh rate can improve the flickering phenomenon caused by the excessively low screen refresh rate. Therefore, this embodiment can simultaneously reduce the power consumption of the display device 100 and reduce the risk of screen flickering.

[0039] In some embodiments, as shown in FIG1 and FIG2, the multiple frames include a first type of frame corresponding to the first refresh rate and a second type of frame corresponding to the second refresh rate; wherein, in adjacent first type of frame and second type of frame, the first screen information of the first type of frame and the second screen information of the second type of frame both include the repeated screen information.

[0040] As discussed above, the display panel 60 displays the image at a first refresh rate in multiple first-type frames and at a second refresh rate in multiple second-type frames. In the two frames where the refresh rate switches (i.e., adjacent first-type frames and second-type frames), the corresponding two image informations both include repeated image information. By storing the repeated image information through the storage unit 201, in order to display the latter image in adjacent first-type frames and second-type frames, the timing controller 20 does not need to obtain the complete second image information from the front end, thereby reducing the power consumption of the display device 100.

[0041] Furthermore, in adjacent first-type frames and second-type frames, the first screen information of the first-type frame and the second screen information of the second-type frame are the same. That is, the two screen information corresponding to the two frames with refresh rate switching are the same. At this time, since the first screen information stored in the storage unit 201 is the same as the second screen information required for screen display in the second-type frame, in order to display the latter's screen, the timing controller 20 does not need to obtain the second screen information from the front end, but directly uses the first screen information stored in the storage unit 201 as the second screen information for screen display, thereby reducing the power consumption of the display device 100.

[0042] In some embodiments, as shown in Figures 1 and 2, the display device 100 further includes: the aforementioned source driver 501, electrically connected to the timing controller 20 and the display panel 60; wherein the timing controller 20 is configured to control the source driver 501 to generate the aforementioned first data signal dataA or dataA' according to the first refresh rate. Alternatively, it can be used to control the source driver 501 to generate the aforementioned second data signal dataB or dataB' according to the second refresh rate; wherein, the first data signal (taking dataA as an example here) includes a first sub-data signal data1A or data2A... and a first sub-blank signal Vblank1A or Vblank2A... in each frame, the second data signal (taking dataB as an example here) includes a second sub-data signal data1B or data2B... and a second sub-blank signal Vblank1B or Vblank2B... in each frame, and the total duration of the first sub-data signal (taking data1A as an example) and the first sub-blank signal Vblank1 (taking Vblank1A as an example) is greater than the total duration of the second sub-data signal (taking data1B as an example) and the second sub-blank signal (taking Vblank1B as an example).

[0043] It is important to note that the data signal transmitted by each data line 10 can include sequentially arranged sub-data signals and sub-blank signals in each frame. The sub-data signals can include multiple valid data voltages corresponding to multiple sub-pixels P in that column, arranged sequentially. The sub-blank signals can be used to separate the two sets of valid data voltages corresponding to the sub-pixels P in two adjacent frames. For example, if multiple sub-pixels P are arranged in n rows (n is a positive integer greater than 1), it can be assumed that the n gate pulses p of the n gate signals (gate1 or gate1', gate2 or gate2'...gaten or gaten') corresponding to the multiple sub-pixels P in that column are only within the time period of the sub-data signals. That is, no gate pulse p is set within the time period of the sub-blank signals. At this time, all sub-pixels P in all rows are turned off, and the sub-blank signals are not transmitted to the sub-pixels P.

[0044] As shown in Figure 2, this example illustrates the first two frames (F1, F2, F3, F4, and F5) with smaller first refresh rates, and the latter three frames with larger second refresh rates. Specifically, the total duration of the first sub-data signal and the first sub-blank signal (data1A and Vblank1A, data2A and Vblank2A, respectively) of the first data signal dataA in both the first frame F1 and the second frame F2 is equal. Similarly, the total duration of the second sub-data signal and the second sub-blank signal (data1B and Vblank1B, data2B and Vblank2B, data3B and Vblank3B, respectively) of the second data signal dataB in the third frame F3, the fourth frame F4, and the fifth frame F5 is equal, and the total duration of each of the first two is less than the total duration of each of the latter three.

[0045] That is, the total duration of each frame displayed at a smaller first refresh rate (the total duration of the corresponding first sub-data signal and the first sub-blank signal) is greater than the total duration of each frame displayed at a larger second refresh rate (the total duration of the corresponding second sub-data signal and the second sub-blank signal).

[0046] In some embodiments, as shown in FIG2, the ratio of the duration of the first sub-data signal (data1A or data2A) to the duration of the first sub-blank signal (Vblank1A or Vblank2A) in the data signal data is the same as the ratio of the duration of the second sub-data signal (data1B or data2B or data3B) to the duration of the second sub-blank signal (Vblank1B or Vblank2B or Vblank3B).

[0047] As discussed above, the duration of each frame (first frame F1 or second frame F2) corresponding to the first refresh rate is equal to the sum of the duration of the first sub-data signal and the duration of the first sub-blank signal. Similarly, the duration of each frame (third frame F3, fourth frame F4, or fifth frame F5) corresponding to the second refresh rate is equal to the sum of the duration of the second sub-data signal and the duration of the second blanking signal.

[0048] Specifically, in this embodiment, the duration percentage of the first sub-data signal (data1A or data2A) in the first data signal dataA corresponding to the first refresh rate within the corresponding frame (first frame F1 or second frame F2) is the same as the duration percentage of the second sub-data signal (data1B or data2B or data3B) in the second data signal dataB corresponding to the second refresh rate within the corresponding frame (third frame F3 or fourth frame F4 or fifth frame F5).

[0049] Understandably, when the first refresh rate is increased to the second refresh rate, the duration of each frame is reduced. Based on this, this embodiment does not change the ratio of the duration of the sub-data signal to the duration of the sub-blank signal, but reduces both proportionally, so that the duration ratio of the total duration of the effective data voltage in a frame corresponding to the first refresh rate and the duration ratio of the total duration of the effective data voltage in a frame corresponding to the second refresh rate are still the same. That is, the time ratio of the charging time of sub-pixel P in a frame has not changed, and correspondingly, the time ratio of the leakage time of sub-pixel P has not changed either.

[0050] Therefore, in this embodiment, regardless of the refresh rate, the ratio of charging time to leakage time of sub-pixel P in each frame is the same, which makes the brightness of sub-pixel P in each frame more consistent and further improves the phenomenon of screen flicker.

[0051] Furthermore, referring to Figures 1 and 2, the multiple frames include a first type of frame (first frame F1 or second frame F2) corresponding to the first refresh rate and a second type of frame (third frame F3 or fourth frame F4 or fifth frame F5) corresponding to the second refresh rate. The display panel 60 includes multiple pixel groups (i.e., multiple rows of sub-pixels P, here we take n as an example for both the number of rows and the number of groups). The display device 100 also includes the aforementioned gate driver 502, which is used to output multiple gate signals (gate1, gate2...gaten) corresponding to the multiple pixel groups. Each gate signal includes a first gate pulse p1 in each first type of frame and a second gate pulse p2 in each second type of frame; wherein the pulse width of the first gate pulse p1 is greater than the pulse width of the second gate pulse p2.

[0052] As discussed above, since the duration of the second sub-data signal (data1B, data2B, or data3B) in the second type of frame is equal to the duration of the first sub-data signal (data1A or data2A) in the first type of frame, the duration of the second sub-data signal is shorter than that of the first sub-data signal. In order to match the turn-on period of sub-pixel P with the period of the corresponding effective data voltage, the pulse width of the second gate pulse p2 can also be set smaller, so that each second gate pulse p2 in the second type of frame can overlap with the period of the corresponding effective data voltage, thereby achieving charging of the corresponding sub-pixel P.

[0053] Furthermore, as shown in Figures 1 and 2, the timing controller 20 is used to output a frame start signal STV to the gate driver 502. The frame start signal STV includes a first frame start pulse sp1 located in the first type of frame (first frame F1 or second frame F2) and a second frame start pulse sp2 located in the second type of frame (third frame F3 or fourth frame F4 or fifth frame F5). The pulse width of the first frame start pulse sp1 is greater than the pulse width of the second frame start pulse sp2.

[0054] Understandably, since the multiple gate pulses corresponding to multiple pixel groups in each frame are formed based on the frame start signal STV in that frame, it can be considered that the pulse widths of the two are positively correlated. Therefore, in order to form a second gate pulse p2 with a smaller pulse width, the pulse width of the second frame start pulse sp2 can also be set to be smaller.

[0055] As discussed above, as shown in Figures 2 and 3, the timing controller 20 outputs a frame start signal STV or STV' to the gate driver 502. The gate driver 502 generates multiple gate signals gate or gate' based on the frame start signal STV or STV', thereby controlling the sequential activation of multiple rows of sub-pixels P. The higher the refresh rate, the smaller the interval between the multiple gate pulses in the frame start signal STV or STV'. For example, if the interval between multiple first frame start pulses sp1 is relatively large, then the multiple gate signals gate or gate' generated by the gate driver 502 and the data signal data or data' generated by the source driver 501 under the control of the timing controller 20 drive the first frame F1 and the second frame F2 displayed by the display device 100, which are defined as first type frames. For another example, if the interval between multiple second frame start pulses sp2 is relatively small, then the multiple gate signals gate or gate' generated by the gate driver 502 and the data signal data or data' generated by the source driver 501 under the control of the timing controller 20 drive the third frame F3, the fourth frame F4, and the fifth frame F5 displayed by the display device 100, which are defined as second type frames.

[0056] In some embodiments, as shown in FIG2, in the data signal data', the ratio of the duration of the first sub-data signal (data1A' or data2A') to the duration of the first sub-blank signal (Vblank1A' or Vblank2A') is less than the ratio of the duration of the second sub-data signal (data1B' or data2B' or data3B') to the duration of the second sub-blank signal (Vblank1B' or Vblank2B' or Vblank3B'), and the duration of the first sub-data signal (data1A' or data2A') is equal to the duration of the second sub-data signal (data1B' or data2B' or data3B').

[0057] Understandably, when the first refresh rate is increased to the second refresh rate, the duration of each frame is reduced. Based on this, unlike the data signal data mentioned above, the duration of the sub-data signal data' in this embodiment is not changed. Instead, the duration of the first sub-data signal (data1A' or data2A') is set to be equal to the duration of the second sub-data signal (data1B' or data2B' or data3B'). Therefore, the latter has a larger proportion of duration in the corresponding frame. That is, by compressing the proportion of duration of the sub-blank signal in a frame, the duration of the sub-data signal can remain unchanged even if the refresh rate is increased.

[0058] Therefore, in this embodiment, regardless of the refresh rate, the charging time of sub-pixel P is the same in each frame, which allows sub-pixel P to be charged to a greater extent in each frame, thereby improving the overall brightness of the image.

[0059] Furthermore, based on the first type of frame (first frame F1 or second frame F2), the second type of frame (third frame F3 or fourth frame F4 or fifth frame F5) discussed above, the gate driver 502, the first gate pulse p1 and the second gate pulse p2; wherein, the pulse width of the first gate pulse p1 is equal to the pulse width of the second gate pulse p2.

[0060] As discussed above, since the duration of the second sub-data signal (data1B' or data2B' or data3B') in the second type of frame is equal to the duration of the first sub-data signal (data1A' or data2A') in the first type of frame, in order to match the on-time of sub-pixel P with the time period of the corresponding effective data voltage, the pulse width of the second gate pulse p2 can also be set to be equal to the pulse width of the first gate pulse p1. Even if the refresh rate increases, the width of the gate pulse p remains unchanged, and the original charging level is maintained.

[0061] Furthermore, referring to Figures 1 and 2, based on the frame start signal STV', the first frame start pulse sp1, and the second frame start pulse sp2 discussed above; wherein the pulse width of the first frame start pulse sp1 is equal to the pulse width of the second frame start pulse sp2.

[0062] Similarly, since the multiple gate pulses corresponding to multiple pixel groups in each frame are formed based on the frame start signal STV' in that frame, it can be considered that the pulse widths of the two are positively correlated. Therefore, in order to form the first gate pulse p1 and the second gate pulse p2 with the same pulse width, the pulse widths of the first frame start pulse sp1 and the second frame start pulse sp2 can also be set to be equal.

[0063] In some embodiments, as shown in FIG1 and FIG2, the timing controller 20 is used to obtain the first refresh rate according to the frame start signal STV or STV', wherein the frame start signal STV or STV' includes a frame start pulse (a first frame start pulse sp1 or a second frame start pulse sp2) in each frame.

[0064] As discussed above, since the frame start signal STV or STV' includes a frame start pulse in each frame, the first refresh rate can be calculated by counting the number of frame start pulses within a unit of time. The first refresh rate is positively correlated with the number of frame start pulses. For example, if the unit of time is 1 second, then the first refresh rate is "1 or the number of frame start pulses".

[0065] Based on the above embodiment, as shown in Figure 3, a first control signal Con1 can be set, and the potential of the first control signal Con1 can change when the refresh rate needs to be switched so that the timing controller 20 can recognize it, thereby changing the interval between two adjacent frame start pulses in the frame start signal STV or STV'. For example, at the end of the second frame F2 (i.e., the start time of the frame start pulse of the third frame F3), the potential of the first control signal Con1 changes, and the interval between two adjacent frame start pulses changes from the third frame F3 onwards (the specific change needs to be set in advance, that is, the second refresh rate needs to be determined in advance to determine the corresponding interval between two adjacent frame start pulses).

[0066] Based on the above discussion, the frame start pulse before the potential change of the first control signal Con1 can be called the first frame start pulse sp1, and the frame start pulse after the potential change of the first control signal Con1 can be called the second frame start pulse sp2.

[0067] Furthermore, as shown in Figure 3, a second control signal Con2 can be set, and the potential of the second control signal Con2 can also change when the refresh rate needs to be switched so that the timing controller 20 can recognize it, thereby changing the interval between two adjacent sub-data signals in the data signal data or data'. For example, at the end of the sub-data signal in the third frame F3, the potential of the second control signal Con2 changes, and the interval between two adjacent sub-data signals changes from the third frame F3 onwards (the specific change needs to be set in advance, that is, the second refresh rate needs to be determined in advance to determine the interval of the corresponding two adjacent frame start pulses).

[0068] Based on the above discussion, the sub-data signal before the potential jump of the second control signal Con2 can be called the first sub-data signal (data1A or data2A... or data1A' or data2A'...), and the sub-data signal after the potential jump of the second control signal Con2 can be called the second sub-data signal (data1B or data2B... or data1B' or data2B'...).

[0069] Figure 4 is a simulation diagram of some signals in Figure 3. The simulation diagram in Figure 4 can at least implement the embodiment corresponding to Figure 3, as described above. Referring to Figures 2 to 4, the first refresh rate and the second refresh rate mentioned above can be 20Hz and 40Hz respectively. That is, multiple first-type frames (first frame F1 or second frame F2) are displayed at 20Hz, and multiple second-type frames (third frame F3, fourth frame F4, or fifth frame F5) are displayed at 40Hz.

[0070] To better illustrate the above-described display device, embodiments of the present invention also provide a driving method for the display device, as shown in FIG5, which may include, but is not limited to, the following steps:

[0071] S1, the timing controller obtains the first refresh rate.

[0072] The timing controller 20 can obtain the current refresh rate of the display panel 60 as the first refresh rate. It can obtain the first refresh rate based on the frame start signal STV or STV'. For details, please refer to the relevant description above.

[0073] S2, when the timing controller increases the first refresh rate to the second refresh rate when the first refresh rate is less than the preset refresh rate.

[0074] The timing controller 20 can obtain the current refresh rate of the display panel 60 as the first refresh rate, and can achieve the second refresh rate by changing the interval between two adjacent frame start pulses in the frame start signal STV or STV'. For details, please refer to the relevant description above.

[0075] S3, the timing controller obtains at least a portion of the first screen information corresponding to the first refresh rate from the storage unit as repeated screen information.

[0076] The storage unit 201 stores the repeated screen information in the first screen information, and this repeated screen information is also used to constitute the second screen information. Therefore, the timing controller 20 does not need to obtain all the second screen information from the front end. The repeated screen information in the second screen information is directly obtained from the storage unit 201, which reduces the power consumption of the display device 100. For details, please refer to the relevant description above.

[0077] S4, the timing controller drives the display panel to display the image at the second refresh rate according to the repeated image information.

[0078] Specifically, the timing controller 20 displays the image based on the second screen information at a relatively high second refresh rate, which can improve the flickering phenomenon caused by an excessively low screen refresh rate. Please refer to the relevant description above for details.

[0079] Furthermore, as shown in Figure 6, the driving method for the display device can also be understood as including but not limited to the following steps:

[0080] S01, Start;

[0081] S02, the timing controller identifies the first refresh rate;

[0082] S03, determine whether the first refresh rate is less than the preset refresh rate;

[0083] If S03 is "Yes", then execute:

[0084] S04, by proportionally reducing the duration of the sub-data signal and the duration of the sub-blank signal in the data signal to increase the first refresh rate to the second refresh rate;

[0085] or,

[0086] S05, by reducing the duration of the sub-blank signal in the data signal to increase the first refresh rate to the second refresh rate;

[0087] If S03 is "No", then execute:

[0088] S06, maintain the duration of the sub-data signal and the duration of the sub-blank signal in the data signal to maintain the first refresh rate.

[0089] In step S04, the duration of the sub-data signal and the duration of the sub-blank signal in the data signal are reduced proportionally. This can be referred to in the above discussion about the data signal data. That is, the ratio of the duration of the first sub-data signal (data1A or data2A) to the duration of the first sub-blank signal (Vblank1A or Vblank2A) is the same as the ratio of the duration of the second sub-data signal (data1B or data2B or data3B) to the duration of the second sub-blank signal (Vblank1B or Vblank2B or Vblank3B).

[0090] In step S05, the duration of the sub-data signal and the duration of the sub-blank signal in the data signal are reduced proportionally. This can be referred to the discussion of the data signal data' above. That is, the ratio of the duration of the first sub-data signal (data1A' or data2A') to the duration of the first sub-blank signal (Vblank1A' or Vblank2A') is less than the ratio of the duration of the second sub-data signal (data1B' or data2B' or data3B') to the duration of the second sub-blank signal (Vblank1B' or Vblank2B' or Vblank3B'). The duration of the first sub-data signal (data1A' or data2A') is equal to the duration of the second sub-data signal (data1B' or data2B' or data3B').

[0091] In step S06, it is assumed that the current first refresh rate is large enough, so there is no need to adjust the duration of the sub-data signal and the duration of the sub-blank signal in the current data signal, and the current first refresh rate can be maintained directly.

[0092] It should be noted that the gate driver 502, source driver 501, timing controller 20, memory cell 201, pixel circuit 40, etc. mentioned in this application can actually be composed of at least one transistor device, and may also include at least one of capacitors and resistors, as well as wires electrically connected between different components. For specific configuration details, please refer to the above discussion.

[0093] The structure of the display device and its driving method provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display device, wherein, include: Display panel; A timing controller, electrically connected to the display panel, is used to obtain the first refresh rate; The source driver is electrically connected to the timing controller and the display panel; The timing controller is configured to increase the first refresh rate to a second refresh rate when the first refresh rate is less than a preset refresh rate, and to obtain at least a portion of the first screen information corresponding to the first refresh rate from the storage unit as repeated screen information, and to drive the display panel to display the screen at the second refresh rate according to the repeated screen information. The timing controller is used to control the source driver to generate a first data signal according to the first refresh rate, or to control the source driver to generate a second data signal according to the second refresh rate. Wherein, the first data signal includes a first sub-data signal and a first sub-blank signal in each frame, the second data signal includes a second sub-data signal and a second sub-blank signal in each frame, and the total duration of the first sub-data signal and the first sub-blank signal is greater than the total duration of the second sub-data signal and the second sub-blank signal. The multiple frames include a first type of frame corresponding to the first refresh rate and a second type of frame corresponding to the second refresh rate; Among them, in the adjacent first type of frame and second type of frame, the first image information of the first type of frame and the second image information of the second type of frame both include the repeated image information.

2. The display device as claimed in claim 1, wherein, The ratio of the duration of the first sub-data signal to the duration of the first sub-blanking signal is the same as the ratio of the duration of the second sub-data signal to the duration of the second sub-blanking signal.

3. The display device as claimed in claim 2, wherein, The display panel includes multiple pixel groups, and the display device further includes: A gate driver is configured to output a plurality of gate signals corresponding to a plurality of said pixel groups, each of said gate signals including a first gate pulse in each first type of frame and including a second gate pulse in each second type of frame; The pulse width of the first gate pulse is greater than the pulse width of the second gate pulse.

4. The display device as claimed in claim 3, wherein, The timing controller is used to output a frame start signal to the gate driver. The frame start signal includes a first frame start pulse located in the first type of frame and a second frame start pulse located in the second type of frame. The pulse width of the first frame start pulse is greater than the pulse width of the second frame start pulse.

5. The display device as claimed in claim 1, wherein, The ratio of the duration of the first sub-data signal to the duration of the first sub-blanking signal is less than the ratio of the duration of the second sub-data signal to the duration of the second sub-blanking signal, and the duration of the first sub-data signal is equal to the duration of the second sub-data signal.

6. The display device as claimed in claim 5, wherein, The display panel includes multiple pixel groups, and the display device further includes: A gate driver is configured to output a plurality of gate signals corresponding to a plurality of said pixel groups, each of said gate signals including a first gate pulse in each first type of frame and including a second gate pulse in each second type of frame; The pulse width of the first gate pulse is equal to the pulse width of the second gate pulse.

7. The display device as claimed in claim 6, wherein, The timing controller is used to output a frame start signal to the gate driver. The frame start signal includes a first frame start pulse located in the first type of frame and a second frame start pulse located in the second type of frame. Wherein, the pulse width of the first frame start pulse is equal to the pulse width of the second frame start pulse.

8. The display device as claimed in claim 1, wherein, In adjacent first-type frames and second-type frames, the first image information of the first-type frame and the second image information of the second-type frame are the same.

9. A display device, wherein, include: Display panel; A timing controller, electrically connected to the display panel, is used to obtain the first refresh rate; The timing controller is configured to increase the first refresh rate to a second refresh rate when the first refresh rate is less than a preset refresh rate, and to obtain at least a portion of the first screen information corresponding to the first refresh rate from the storage unit as repeated screen information, and to drive the display panel to display the screen at the second refresh rate according to the repeated screen information.

10. The display device as claimed in claim 9, wherein, Also includes: The source driver is electrically connected to the timing controller and the display panel; The timing controller is used to control the source driver to generate a first data signal according to the first refresh rate, or to control the source driver to generate a second data signal according to the second refresh rate. The first data signal includes a first sub-data signal and a first sub-blank signal in each frame, and the second data signal includes a second sub-data signal and a second sub-blank signal in each frame. The total duration of the first sub-data signal and the first sub-blank signal is greater than the total duration of the second sub-data signal and the second sub-blank signal.

11. The display device as claimed in claim 10, wherein, The ratio of the duration of the first sub-data signal to the duration of the first sub-blanking signal is the same as the ratio of the duration of the second sub-data signal to the duration of the second sub-blanking signal.

12. The display device as claimed in claim 11, wherein, The multiple frames include a first type of frame corresponding to the first refresh rate and a second type of frame corresponding to the second refresh rate. The display panel includes multiple pixel groups, and the display device further includes: A gate driver is configured to output a plurality of gate signals corresponding to a plurality of said pixel groups, each of said gate signals including a first gate pulse in each first type of frame and including a second gate pulse in each second type of frame; The pulse width of the first gate pulse is greater than the pulse width of the second gate pulse.

13. The display device as claimed in claim 12, wherein, The timing controller is used to output a frame start signal to the gate driver. The frame start signal includes a first frame start pulse located in the first type of frame and a second frame start pulse located in the second type of frame. The pulse width of the first frame start pulse is greater than the pulse width of the second frame start pulse.

14. The display device as claimed in claim 10, wherein, The ratio of the duration of the first sub-data signal to the duration of the first sub-blanking signal is less than the ratio of the duration of the second sub-data signal to the duration of the second sub-blanking signal, and the duration of the first sub-data signal is equal to the duration of the second sub-data signal.

15. The display device as claimed in claim 14, wherein, The multiple frames include a first type of frame corresponding to the first refresh rate and a second type of frame corresponding to the second refresh rate. The display panel includes multiple pixel groups, and the display device further includes: A gate driver is configured to output a plurality of gate signals corresponding to a plurality of said pixel groups, each of said gate signals including a first gate pulse in each first type of frame and including a second gate pulse in each second type of frame; The pulse width of the first gate pulse is equal to the pulse width of the second gate pulse.

16. The display device as claimed in claim 15, wherein, The timing controller is used to output a frame start signal to the gate driver. The frame start signal includes a first frame start pulse located in the first type of frame and a second frame start pulse located in the second type of frame. Wherein, the pulse width of the first frame start pulse is equal to the pulse width of the second frame start pulse.

17. The display device according to any one of claims 9 to 16, wherein, The multiple frames include a first type of frame corresponding to the first refresh rate and a second type of frame corresponding to the second refresh rate; Among them, in the adjacent first type of frame and second type of frame, the first image information of the first type of frame and the second image information of the second type of frame both include the repeated image information.

18. The display device as claimed in claim 17, wherein, In adjacent first-type frames and second-type frames, the first image information of the first-type frame and the second image information of the second-type frame are the same.

19. The display device according to any one of claims 9 to 16, wherein, The timing controller is used to obtain the first refresh rate based on the frame start signal, wherein the frame start signal includes a frame start pulse in each frame.

20. A driving method for a display device, wherein, include: The timing controller acquires the first refresh rate; When the first refresh rate is less than a preset refresh rate, the timing controller increases the first refresh rate to a second refresh rate. The timing controller obtains at least a portion of the first screen information corresponding to the first refresh rate from the storage unit as repeated screen information; The timing controller drives the display panel to display the image at the second refresh rate according to the repeated image information.

Images