Dynamic random access memory and manufacturing method therefor

Abstract

The present application relates to the technical field of memories, and discloses a dynamic random access memory and a manufacturing method therefor, used for implementing one-time formation of a multi-layer memory cell array, thereby improving the integration density of the dynamic random access memory while ensuring the electrical performance and stability of memory cells. The dynamic random access memory comprises a plurality of memory cells distributed in a three-dimensional array. Each memory cell comprises a first transistor and a second transistor; a second source region, a second channel region, and a second drain region are disposed in a first through hole along a first direction; a second gate is disposed in the first through hole; the second transistor comprises a first gate disposed in a first recess; one of a first source and a first drain that is not electrically connected to the first gate is disposed in a second through hole; and a first source region, a first channel region, and a first drain region are distributed in a second recess along a third direction. The manufacturing method for a dynamic random access memory is used for manufacturing the described dynamic random access memory.

Description

Dynamic random access memory and manufacturing method thereof

[0001] The present application claims priority to the Chinese patent application No. 202510072351.1, filed on January 16, 2025, and entitled "Dynamic random access memory and manufacturing method thereof", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of memory technology, and in particular to a dynamic random access memory and a manufacturing method thereof. BACKGROUND

[0003] In a computer system, memory is a key component for storing data and programs. Dynamic random access memory (DRAM) as an important type of memory plays a key role in modern computer architecture. Dynamic random access memory includes a 2T0C storage cell structure. One storage cell of such dynamic random access memory is composed of two transistors, one of which is responsible for gating, and the other is responsible for gating and storing charge.

[0004] In the prior art, the storage cells of dynamic random access memory are arrayed along the horizontal direction of the wafer, i.e., two-dimensional dynamic random access memory. However, the development of computer systems puts forward higher requirements for the density of dynamic random access memory, and the density of two-dimensional dynamic random access memory is limited by the process, which cannot meet the density requirements.

[0005] SUMMARY

[0006] The purpose of the present application is to provide a dynamic random access memory and a manufacturing method thereof, which can realize the formation of a multi-layer storage cell array at one time, and improve the integration density of dynamic random access memory under the premise of ensuring the electrical performance and stability of the storage cell.

[0007] To achieve the above objectives, in a first aspect, this application provides a dynamic random access memory (DRAM), comprising: a plurality of memory cells arranged in a three-dimensional array, and a dielectric structure for isolating the different memory cells. The plurality of memory cells arranged in a three-dimensional array include multiple memory layers spaced apart along a first direction, each memory layer including a plurality of memory groups spaced apart along a second direction, and each memory group including a plurality of memory cells spaced apart along a third direction. The first direction, the second direction, and the third direction are different from each other. Each memory cell includes a first transistor and a second transistor arranged along the third direction. The second transistor has a dual-gate structure. In the same memory cell, one of the first source and the first drain of the first transistor is electrically connected to the first gate of the second transistor. A first via and a second via are disposed within the dielectric structure spaced apart along the third direction. The second source region, the second channel region, and the second drain region of the second transistor are disposed within the first via along the first direction. The second gate of the second transistor is disposed within the first via, and the second channel region of the second transistor surrounds the outer periphery of the second gate. The dielectric structure has an inwardly recessed first notch corresponding to the second channel region of the second transistor, and the first gate of the second transistor is disposed within the first notch. One of the first source and the first drain, which is not electrically connected to the first gate, is disposed within a second via. The dielectric structure has an inwardly recessed second notch corresponding to the portion of the second via, and the second notch communicates with the first notch. The first source region, the first channel region, and the first drain region of the first transistor are distributed along a third direction within the second notch.

[0008] With the above technical solution, the dynamic random access memory (DRAM) provided in this application not only has multiple memory groups spaced apart along the second direction in the same layer, but also includes multiple memory layers spaced apart along the first direction, in which case the multiple memory cells are arranged in a three-dimensional array. Compared with a two-dimensional DRAM with only a single memory layer, each memory layer in this application can form a structure analogous to the two-dimensional DRAM of the prior art. Furthermore, the multiple memory layers stacked along the first direction in this application can multiply the storage density of the DRAM provided in this application, effectively solving the problem of low density in two-dimensional DRAMs. Furthermore, the first through hole is connected to the first recess, and the second through hole is connected to the second recess. Since the aforementioned structures of the first transistor and the aforementioned structures of the second transistor included in the memory cell are all disposed within the first through hole, the second through hole, the first recess, and the second recess, when manufacturing the dynamic random access memory provided in this application, a multi-layer memory cell array can be formed at one time by operating the first through hole and the second through hole. Under the premise of ensuring the electrical performance and stability of the memory cell, the integration density and storage density of the dynamic random access memory are greatly improved.

[0009] Furthermore, the first transistor acts as a write transistor, and the second transistor acts as a read transistor. Based on this, during the manufacturing of the dynamic random access memory (DRAM) provided in this application, process errors can lead to deviations in the structure and design of the memory cells, particularly the second transistor. This results in different threshold voltages for the second transistors in different memory cells, potentially causing data errors during data reading. Therefore, the second transistor has a dual-gate structure, allowing for the regulation and compensation of its threshold voltage through its second gate, thus preventing data reading errors and improving the accuracy of data storage in the DRAM provided in this application.

[0010] As one possible implementation, the first transistor has a dual-gate structure; the third gate and the fourth gate of the first transistor are respectively disposed on both sides of the first channel region along the third direction.

[0011] With the above technical solution, traditional transistors have only one gate to control the current in the channel region, while the first transistor provided in this application has two gates. The dual-gate transistor can have twice the gate control area with the same channel region area, effectively improving the gate's control capability over the channel region. This makes the gate's control of the charge carriers in the channel region more precise and flexible, allowing for more effective regulation of current conduction and cutoff, thereby improving the switching performance of the transistor provided in this application. It can effectively suppress short-channel effects and is conducive to further reducing the size of the transistor provided in this application, thus increasing the storage density of the dynamic random access memory provided in this application. For example, under low-voltage operation, the first transistor with the dual-gate structure can more precisely control the current, achieving faster switching transitions, which helps to reduce the power consumption of the dynamic random access memory provided in this application.

[0012] As one possible implementation, the gate structure of the first transistor is disposed in the second notch and located on at least one side of the first channel region along the first direction; the first source and the first drain that are not electrically connected to the first gate are isolated from the gate structure by the first gate dielectric layer included in the first transistor.

[0013] With the above technical solution, the one of the first source and the first drain that is not electrically connected to the first gate is in close contact with the gate structure, which helps to reduce the area occupied by the one of the first source and the first drain that is not electrically connected to the first gate, thereby helping to reduce the area occupied by the first transistor and enabling the formation of a multi-layer memory cell array in one go. Under the premise of ensuring the electrical performance and stability of the memory cell, the integration density of the dynamic random access memory is greatly improved.

[0014] In one possible implementation, the second transistor includes a second source and a second drain disposed within a third recess and a fourth recess, respectively. The third recess and the fourth recess are respectively disposed on opposite sides of the first gate along a first direction. The second source is electrically connected to a second source region; the second drain is electrically connected to a second drain region.

[0015] With the above technical solution, the third and fourth notches are formed on both sides of the first notch in the third direction and are connected to the first via. The second transistor has a vertical channel structure, which reduces the area occupied by the second source region, second channel region, and second drain region of the second transistor while ensuring the channel length of the second transistor, thereby reducing the area occupied by the second transistor and improving the storage density of the dynamic random access memory. Furthermore, the second source, second drain, and the first gate of the second transistor are vertically stacked in the first direction, reducing the area occupied by the second transistor and improving the storage density of the dynamic random access memory. At the same time, the vertical stacking of the second source region, second channel region, and second drain region within the first via allows the formation of the second source region, second channel region, and second drain region in the same second transistor, as well as the formation of the second source region, second channel region, and second drain region in different second transistors connected through the first via, to be achieved in a single deposition operation within the first via. This facilitates the formation of multi-layer memory cell arrays in one step, significantly improving the integration density of the dynamic random access memory while ensuring the electrical performance and stability of the memory cells.

[0016] As one possible implementation, the first transistor is an indium zinc oxide thin-film transistor, a tin-doped indium oxide thin-film transistor, an indium oxide thin-film transistor, a zinc oxide thin-film transistor, or a titanium oxide thin-film transistor.

[0017] With the above-described technical solution, the turn-off current of the aforementioned metal-oxide-slim thin-film transistors is low, resulting in low power consumption of the first transistor in the off-state, which helps to reduce the power consumption of the dynamic random access memory (DRAM) provided in this application. Furthermore, since the first transistor acts as a write transistor, the low turn-off current of these metal-oxide-slim thin-film transistors significantly slows down the discharge rate of the second transistor's gate capacitor through the channel of the first transistor, thereby significantly extending the hold time of the second transistor's gate capacitor. This, in turn, reduces the refresh frequency of the DRAM provided in this application, thereby reducing the power consumption of the DRAM provided in this application. The use of these metal-oxide-slim thin-film transistors as the first transistor results in a relatively high carrier mobility, leading to faster signal transmission and switching speeds, thus improving the operating efficiency and response speed of the DRAM provided in this application. Simultaneously, when manufacturing the DRAM provided in this application, these metal-oxide-slim thin-film transistors can be fabricated using a cryogenic process. Cryogenic processes reduce the need for expensive high-temperature equipment and complex process steps, thereby reducing costs. Furthermore, the channel regions of the above-mentioned metal oxide thin film transistors can be formed in parallel through processes such as deposition, which can form the first channel regions of multiple first transistors at one time. This is beneficial for forming the first transistors of multiple memory cells at the same time, and for realizing the formation of multi-layer memory cell arrays at one time. Under the premise of ensuring the electrical performance and stability of memory cells, the integration density of dynamic random access memory is greatly improved.

[0018] As one possible implementation, one of the first source and the first drain that is electrically connected to the first gate is integrally continuous with the first gate.

[0019] With the above-described solution, in manufacturing the dynamic random access memory (DRAM) provided in this application, the first source and the first drain, which are electrically connected to the first gate, can be formed in the same process step as the first gate. This reduces the number of process steps and facilitates the one-time formation of a multi-layer memory cell array. While ensuring the electrical performance and stability of the memory cells, this significantly improves the integration density of the DRAM. Furthermore, since the two structures are integrally continuous, no additional structure is needed to connect them, which helps reduce the area occupied by the memory cells, thereby increasing the density of the DRAM provided in this application.

[0020] Secondly, this application also provides a method for manufacturing a dynamic random access memory (DRAM). The method includes: forming a plurality of memory cells arranged in a three-dimensional array; and forming a dielectric structure for isolating different memory cells. The plurality of memory cells arranged in a three-dimensional array includes multiple memory layers spaced apart along a first direction. Each memory layer includes a plurality of memory groups spaced apart along a second direction, and each memory group includes a plurality of memory cells spaced apart along a third direction. The first direction, the second direction, and the third direction are different from each other. Each memory cell includes a first transistor and a second transistor arranged along the third direction. The second transistor has a dual-gate structure. In the same memory cell, one of the first source and the first drain of the first transistor is electrically connected to the first gate of the second transistor. A first via and a second via are spaced apart along the third direction within the dielectric structure. The second source region, the second channel region, and the second drain region of the second transistor are disposed within the first via along the first direction. The second gate of the second transistor is disposed within the first via, and the second channel region of the second transistor surrounds the outer periphery of the second gate. The dielectric structure has an inwardly recessed first notch corresponding to the second channel region of the second transistor, and the first gate of the second transistor is disposed within the first notch. One of the first source and the first drain, which is not electrically connected to the first gate, is disposed within a second via. The dielectric structure has an inwardly recessed second notch corresponding to the portion of the second via, and the second notch communicates with the first notch. The first source region, the first channel region, and the first drain region of the first transistor are distributed along a third direction within the second notch.

[0021] Compared with the prior art, the beneficial effects of the manufacturing method of dynamic random access memory provided in this application are the same as those of the dynamic random access memory provided in the first aspect, and will not be repeated here.

[0022] As one possible implementation, forming a plurality of memory cells arranged in a three-dimensional array and forming a dielectric structure for isolating different memory cells includes: forming a stacked structure, and a first dielectric filling portion and a second dielectric filling portion penetrating the stacked structure along a first direction; the stacked structure includes multiple stacked cells stacked along the first direction. Each stacked cell includes two first dielectric layers spaced apart along the first direction, and a stack layer located between the two first dielectric layers. The stack layer includes two metal layers spaced apart along the first direction, and a second dielectric layer located between the two metal layers. The materials of the first dielectric layers, the metal layers, and the second dielectric layers are different from each other. A third via and a fourth via are provided within the stacked structure, penetrating along the first direction and spaced apart. The first dielectric filling portion fills the third via, and the second dielectric filling portion fills the fourth via. Next, a plurality of first vias penetrating the stacked structure and spaced apart along the second direction are formed. Next, along a third direction, the edge portions of the two metal layers near the first vias are selectively etched to form a third notch and a fourth notch. Next, a dielectric isolation layer is formed within the third notch, the fourth notch, and the first vias. Next, a second source of the second transistor is formed in the third notch, and a second drain of the second transistor is formed in the fourth notch. Next, along the first direction, a second source region, a second channel region, and a second drain region of the second transistor are formed in the first via; the second source and the second source region are connected; the second drain and the second drain region are connected. Next, a second gate dielectric layer of the second transistor is formed in the first via. The second gate dielectric layer is formed on the second source region, the second channel region, and the second drain region. Next, a second gate of the second transistor is formed in the first via. Next, a plurality of second vias are formed, penetrating the stacked structure and spaced apart along the second direction. Next, the second dielectric layer is partially removed to form a first notch and a second notch, and the remaining metal layer forms the gate structure of the first transistor. Next, a first gate dielectric layer of the first transistor is formed in the second notch and the second via. Next, a first gate of the second transistor, and one of the first source and the first drain electrically connected to the first gate, are formed in the first notch. A first source region, a first channel region, and a first drain region of the first transistor are formed in the second notch. Next, one of the first source and the first drain that is not electrically connected to the first gate is formed in the second via.

[0023] With the above technical solution, the first through-hole is connected to the first recess, the first through-hole is connected to the third recess, the first through-hole is connected to the fourth recess, and the second through-hole is connected to the second recess. After forming the first and second through-holes, the above-mentioned structures of the first transistor and the second transistor are formed through the processing technology within the first and second through-holes, thereby realizing the simultaneous manufacturing of memory cells disposed in the same first through-hole. The stacked structure includes multiple first through-holes, which allows for the simultaneous processing of multiple memory cells disposed in multiple first through-holes. This enables the simultaneous manufacturing of all memory cells included in the dynamic random access memory, which is beneficial for realizing the one-time formation of multi-layer memory cell arrays. While ensuring the electrical performance and stability of the memory cells, the integration density of the dynamic random access memory is greatly improved.

[0024] As one possible implementation, forming a stacked structure and forming a first dielectric filling portion and a second dielectric filling portion through the stacked structure along a first direction includes: forming a stacked material layer. The stacked material layer includes multiple stacked units stacked along the first direction. Next, forming a third through-hole and a fourth through-hole through the stacked material layer. Along a second direction, the third through-hole is disposed between two adjacent first through-holes; along the second direction, the fourth through-hole is disposed between two adjacent second through-holes. Next, the third through-hole is filled with a first dielectric filling portion, and the fourth through-hole is filled with a second dielectric filling portion.

[0025] With the above technical solution, the third through-hole is spaced apart from the first through-hole, and the fourth through-hole is spaced apart from the second through-hole. The first dielectric filling portion filled in the third through-hole and the second dielectric filling portion filled in the fourth through-hole serve as isolation layers between adjacent memory cells along the second direction, which helps to prevent leakage current between adjacent memory cells along the second direction. Furthermore, in the step of partially removing the second dielectric layer, the two metal layers in the stacked cell are suspended, and the first and second dielectric filling portions can serve as supports, preventing the stacked structure from bending. This is beneficial for the structural regularity of the memory cells, thereby ensuring the normal operation and stable performance of the memory cells manufactured by the manufacturing method of the dynamic random access memory provided in this application, and thus improving the yield.

[0026] As one possible implementation, partial removal of the second dielectric layer further includes: removing a portion of the second dielectric layer located between the first via and the second via in a third direction, and adjacent to the second via, so that the remaining second dielectric layer forms a second dielectric portion. Along the second direction, the second dielectric portion electrically isolates the first source region, first channel region, first drain region, and first gate of two adjacent memory cells.

[0027] With the above technical solution, the second dielectric portion isolates the first source region, first channel region, first drain region, and first gate of two adjacent memory cells along the second direction, thereby isolating the data stored in the two adjacent memory cells. Furthermore, the second dielectric portion can also serve as a support, preventing bending of the stacked structure after the formation of the first and second notches, which is beneficial for the structural regularity of the memory cells. This ensures the normal operation and stable performance of the memory cells manufactured by the dynamic random access memory manufacturing method provided in this application, thereby improving yield. Attached Figure Description

[0028] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0029] Figure 1(a) is a front view of the structure of the dynamic random access memory provided in an embodiment of this application;

[0030] Figure 1(b) is a top view of the structure of the dynamic random access memory provided in the embodiment of this application;

[0031] Figure 2 is a flowchart of a method for manufacturing a dynamic random access memory provided in an embodiment of this application;

[0032] Figure 3(a) is a front view of a schematic diagram of a stacked structure provided in an embodiment of this application;

[0033] Figure 3(b) is a top view of a schematic diagram of a stacked structure provided in an embodiment of this application;

[0034] Figure 4 is a flowchart of the formation of the stacked structure in an embodiment of this application;

[0035] Figure 5 is a front view of a schematic diagram showing the formation of the third and fourth through holes provided in an embodiment of this application;

[0036] Figure 6(a) is a front view of a schematic diagram provided in an embodiment of this application, in which a first medium filling part is filled in a third through hole and a second medium filling part is filled in a fourth through hole;

[0037] Figure 6(b) is a top view of a schematic diagram provided in an embodiment of this application, in which a first medium filling part is filled in a third through hole and a second medium filling part is filled in a fourth through hole;

[0038] Figure 7(a) is a front view of a schematic diagram showing the formation of the first through hole, the third notch, and the fourth notch provided in an embodiment of this application;

[0039] Figure 7(b) is a top view of a schematic diagram showing the formation of the first through hole, the third notch, and the fourth notch provided in an embodiment of this application;

[0040] Figure 8(a) is a front view of a schematic diagram of the formation of a dielectric isolation layer provided in an embodiment of this application;

[0041] Figure 8(b) is a top view of a schematic diagram of the formation of a dielectric isolation layer provided in an embodiment of this application;

[0042] Figure 9(a) is a front view of a schematic diagram of forming a first source and a first drain provided in an embodiment of this application;

[0043] Figure 9(b) is a top view of a schematic diagram of forming a first source and a first drain provided in an embodiment of this application;

[0044] Figure 10(a) is a front view of a schematic diagram of the formation of a second source region, a second channel region, a second drain region, a second gate dielectric layer, and a second gate according to an embodiment of this application;

[0045] Figure 10(b) is a top view of a schematic diagram of the formation of a second source region, a second channel region, a second drain region, a second gate dielectric layer, and a second gate according to an embodiment of this application;

[0046] Figure 11(a) is a front view of a schematic diagram of forming a second through hole provided in an embodiment of this application;

[0047] Figure 11(b) is a top view of a schematic diagram of the formation of the second through hole provided in an embodiment of this application;

[0048] Figure 12(a) is a front view of a schematic diagram showing partial removal of the second dielectric layer provided in an embodiment of this application;

[0049] Figure 12(b) is a top view of a schematic diagram showing partial removal of the second dielectric layer provided in an embodiment of this application;

[0050] Figure 12(c) is a cross-sectional view of the partial removal of the second dielectric layer along the A-A' direction in Figure 12(a) provided in an embodiment of this application;

[0051] Figure 13(a) is a front view of a schematic diagram of forming a first gate dielectric layer provided in an embodiment of this application;

[0052] Figure 13(b) is a top view of a schematic diagram of the formation of the first gate dielectric layer provided in an embodiment of this application;

[0053] Figure 14(a) is a front view of a schematic diagram of forming a first source region, a first channel region, a first drain region, a first gate, and one of the first source and the first drain that is electrically connected to the first gate, provided in an embodiment of the present application.

[0054] Figure 14(b) is a top view of a schematic diagram of forming a first source region, a first channel region, a first drain region, a first gate, and one of the first source and the first drain that is electrically connected to the first gate, provided in an embodiment of the present application.

[0055] Figure 15(a) is a front view of a schematic diagram provided in an embodiment of the present application for forming one of the first source and the first drain that is not electrically connected to the first gate;

[0056] Figure 15(b) is a top view of a schematic diagram of a first source and a first drain that are not electrically connected to the first gate, provided in an embodiment of this application.

[0057] Reference numerals: 110-First dielectric portion, 111-First dielectric layer, 120-Second dielectric portion, 121-Second dielectric layer, 122-First notch, 123-Second notch, 130-First dielectric filling portion, 131-Third via, 140-Second dielectric filling portion, 141-Fourth via, 150-Third dielectric filling portion, 200-First transistor, 211-First source region, 212-First channel region, 213-First drain region, 220-Gate structure, 221-Third gate, 222-Fourth gate, 223-Metal layer, 231-First source, 232-First drain, 240-First gate dielectric layer, 250-Second via, 300-Second transistor, 311-Second source region, 312-Second channel region, 313-Second drain region, 321-First gate, 322- Second gate, 331-second source, 332-second drain, 333-third notch, 334-fourth notch, 341-dielectric isolation layer, 342-second gate dielectric layer, 340-first via, 400-memory cell. Detailed Implementation

[0058] To make the technical problems, technical solutions, and beneficial effects to be solved by the embodiments of this application clearer, the embodiments of this application will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the embodiments of this application and are not intended to limit the embodiments of this application.

[0059] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0060] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, "multiple" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0061] In the description of the embodiments of this application, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0062] In the description of the embodiments of this application, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this application according to the specific circumstances.

[0063] In computer systems, memory is a crucial component for storing data and programs. Dynamic Random Access Memory (DRAM), as an important type of memory, plays a key role in modern computer architecture. Common DRAM can include a 2T0C memory cell structure. In this type of DRAM, each memory cell consists of two transistors: one transistor is responsible for selection, and the other transistor is responsible for both selection and storing charge.

[0064] In existing technologies, the memory cells of dynamic random access memory (DRAM) are arrayed along the horizontal direction of the wafer, which is called two-dimensional DRAM. However, the development of computer systems has placed higher demands on the density of DRAM, and the density of two-dimensional DRAM is limited by the manufacturing process and cannot meet the density requirements.

[0065] To address the aforementioned problems, in a first aspect, embodiments of this application provide a dynamic random access memory (DRAM). Referring to Figures 1(a) and 1(b), the DRAM includes: a plurality of memory cells 400 arranged in a three-dimensional array, and a dielectric structure for isolating the different memory cells 400. The plurality of memory cells 400 arranged in a three-dimensional array includes multiple memory layers spaced apart along a first direction, each memory layer including a plurality of memory groups spaced apart along a second direction, and each memory group including a plurality of memory cells 400 spaced apart along a third direction. The first direction, the second direction, and the third direction are different from each other. Each memory cell 400 includes a first transistor 200 and a second transistor 300 arranged along the third direction. The second transistor 300 has a dual-gate structure. In the same memory cell 400, one of the first source 231 and the first drain 232 of the first transistor 200 is electrically connected to the first gate 321 of the second transistor 300. The dielectric structure is provided with a first via 340 and a second via 250 spaced apart along the third direction. The second transistor 300, including a second source region 311, a second channel region 312, and a second drain region 313, is disposed within the first via 340 along a first direction. The second gate 322 of the second transistor 300 is disposed within the first via 340, and the second channel region 312 surrounds the outer periphery of the second gate 322. A portion of the dielectric structure corresponding to the second channel region 312 of the second transistor 300 has an inwardly recessed first notch 122, and the first gate 321 of the second transistor 300 is disposed within the first notch 122. One of the first source 231 and the first drain 232, which is not electrically connected to the first gate 321, is disposed within the second via 250. A portion of the dielectric structure corresponding to the second via 250 has an inwardly recessed second notch 123, and the second notch 123 communicates with the first notch 122. The first transistor 200 includes a first source region 211, a first channel region 212, and a first drain region 213, which are distributed along a third direction within the second notch 123.

[0066] With reference to Figures 1(a) and 1(b) when the above technical solution is adopted, the dynamic random access memory (DRAM) provided in this embodiment not only has multiple memory groups spaced apart along the second direction in the same layer, but also includes multiple memory layers spaced apart along the first direction. In this case, the multiple memory cells 400 are arranged in a three-dimensional array. Compared with a two-dimensional DRAM with only a single memory layer, each memory layer in this embodiment can form a structure analogous to the two-dimensional DRAM of the prior art. The multiple memory layers stacked along the first direction in this embodiment can multiply the storage density of the DRAM provided in this embodiment, effectively solving the problem of low density in two-dimensional DRAM. Furthermore, the first through-hole 340 is connected to the first recess 122, and the second through-hole 250 is connected to the second recess 123. Since the aforementioned structures of the first transistor 200 and the aforementioned structures of the second transistor 300 included in the storage cell 400 are all disposed within the first through-hole 340, the second through-hole 250, the first recess 122, and the second recess 123, when manufacturing the dynamic random access memory provided in this application embodiment, a multi-layer storage cell array can be formed at one time by operating the first through-hole 340 and the second through-hole 250. Under the premise of ensuring the electrical performance and stability of the storage cell 400, the integration density and storage density of the dynamic random access memory are greatly improved.

[0067] Furthermore, the first transistor acts as a write transistor, and the second transistor acts as a read transistor. Based on this, during the manufacturing of the dynamic random access memory (DRAM) provided in this embodiment, process errors can lead to deviations in the structure and design of the memory cells, particularly the second transistor. This results in different threshold voltages for the second transistors in different memory cells, potentially causing data errors during data reading. Therefore, the second transistor has a dual-gate structure, allowing for the regulation and compensation of its threshold voltage through its second gate, thus preventing data errors and improving the accuracy of data storage in the DRAM provided in this embodiment.

[0068] In practical applications, this application does not specifically limit the specific arrangement direction or distribution of different storage units, as long as the different storage units are distributed in a three-dimensional array. As for the specific directions referred to by the first direction, the second direction, and the third direction, no specific limitation is made here, as long as any two of the above three directions are different.

[0069] For example, the first direction is the height direction of the dynamic random access memory provided in this application embodiment. Secondly, the second and third directions can be determined according to the distribution of different memory cells 400 in the same memory layer. For example, referring to Figures 1(a) and 1(b), when different memory cells 400 in the same memory layer are distributed in a rectangular array, the second and third directions can be the length and width directions of the rectangular array, respectively. As another example, when different memory cells 400 in the same memory layer are distributed in a parallelogram array, the second and third directions can be the directions of two adjacent sides of the parallelogram array, respectively. In another instance, for example, when different memory cells 400 in the same memory layer are distributed in a concentric circle array, the second and third directions can be the radial and circumferential directions of the concentric circle array, respectively. It is understood that when the distribution of memory cells in the same memory layer is different, the second and third directions can be changed according to their distribution.

[0070] The structure and materials of the first transistor will be further explained below.

[0071] Regarding the device type of the first transistor, this application embodiment does not specifically limit it, and it can be determined according to actual needs.

[0072] For example, the first transistor is an indium zinc oxide thin-film transistor, a tin-doped indium oxide thin-film transistor, an indium oxide thin-film transistor, a zinc oxide thin-film transistor, or a titanium oxide thin-film transistor.

[0073] With the above-described technical solution, the turn-off current of the aforementioned metal-oxide-slim thin-film transistors is low, resulting in low power consumption of the first transistor in the off-state, which is beneficial for reducing the power consumption of the dynamic random access memory (DRAM) provided in this embodiment. Furthermore, since the first transistor acts as a write transistor and the second transistor as a read transistor, the low turn-off current of the aforementioned metal-oxide-slim thin-film transistors significantly slows down the discharge speed of the second transistor's gate capacitor through the channel of the first transistor, thereby significantly extending the hold time of the second transistor's gate capacitor. This, in turn, reduces the refresh frequency of the DRAM provided in this embodiment, thereby reducing the power consumption of the DRAM provided in this embodiment. The use of the aforementioned metal-oxide-slim thin-film transistors as the first transistor results in a relatively high carrier mobility, leading to faster signal transmission and switching speeds, thus improving the operating efficiency and response speed of the DRAM provided in this embodiment. Simultaneously, when manufacturing the DRAM provided in this embodiment, the channel region of the aforementioned metal-oxide-slim thin-film transistors can be fabricated using a cryogenic process. Cryogenic processes reduce the need for expensive high-temperature equipment and complex process steps, thereby reducing costs. Furthermore, the channel regions of the aforementioned metal-oxide-slim thin-film transistors can be formed in parallel through processes such as deposition, allowing for the simultaneous formation of multiple first channel regions including the first transistors. This facilitates the simultaneous formation of first transistors within multiple memory cells, enabling the simultaneous formation of multi-layer memory cell arrays. While ensuring the electrical performance and stability of the memory cells, this significantly improves the integration density of the dynamic random access memory (DRAM). Moreover, in the DRAM provided in this embodiment, selecting the aforementioned types of transistors for the first transistors allows for a wider range of device types to be chosen, thereby meeting the memory cell's requirements for parameters such as switching speed, power consumption, conductivity type, and operating voltage.

[0074] It is understandable that when the device type of the first transistor is any of the above, the materials of the first source region, the first channel region, and the first drain region can also be determined. For example, when the first transistor is a tin-doped indium oxide thin-film transistor, the materials of the first source region, the first channel region, and the first drain region are all tin-doped indium oxide.

[0075] For example, referring to Figures 1(a) and 1(b), the first transistor 200 includes: a first source 231, a first drain 232, a gate structure 220, a first source region 211, a first channel region 212, a first drain region 213, and a first gate dielectric layer 240. The first source region 211, the first channel region 212, and the first drain region 213 are distributed within a second recess 123 along a third direction. The first drain 232 is electrically connected to the first drain region 213 and is also distributed within the second recess 123. The second recess 123 is recessed inward from the second via 250. The first source 231 is electrically connected to the first source region 211 and is disposed within the second via 250. In other words, the first source 231 is disposed at the top of the second recess 123, and along a third direction, the first source 231, the first source region 211, the first channel region 212, the first drain region 213, and the first drain 232 are distributed sequentially. The gate structure 220 is disposed within the second recess 123 and is located on at least one side of the first channel region 212 along the first direction. A first gate dielectric layer 240 is also disposed between the gate structure 220 and the first channel region 212 included in the first transistor 200. The one of the first source 231 and the first drain 232 that is not electrically connected to the first gate, namely the first source 231 in the figure, is isolated from the gate structure 220 by the first gate dielectric layer 240 included in the first transistor 200.

[0076] With the above technical solution, please refer to Figures 1(a) and 1(b). The one of the first source 231 and the first drain 232 that is not electrically connected to the first gate 321 is in close contact with the gate structure 220. This helps to reduce the area occupied by the one of the first source 231 and the first drain 232 that is not electrically connected to the first gate 321, thereby helping to reduce the area occupied by the first transistor 200. This also helps to realize the formation of a multi-layer memory cell array at one time, and significantly improves the integration density of the dynamic random access memory while ensuring the electrical performance and stability of the memory cells. Furthermore, the second notch 123 is connected to the second via 250, and the formation of the first source region 211, the first channel region 212 and the first drain region 213 in the same first transistor 200 can be achieved in a single deposition operation within the second via 250, as well as the formation of the first source region 211, the first channel region 212 and the first drain region 213 in different first transistors 200 connected through the first via. This is beneficial for achieving the formation of a multi-layer memory cell array in one step, and significantly improves the integration density of dynamic random access memory while ensuring the electrical performance and stability of the memory cells.

[0077] Regarding the gate structure 220, please refer to Figures 1(a) and 1(b). The gate structure 220 is disposed within the second recess 123 and located on at least one side of the first channel region 212 along the first direction. When manufacturing the gate structure 220 disposed within the second recess 123, multiple second vias can be operated on, thereby enabling the simultaneous manufacturing of all gate structures 220 included in the memory cells 400. This facilitates the simultaneous formation of a multi-layer memory cell array, significantly improving the integration density of the dynamic random access memory while ensuring the electrical performance and stability of the memory cells 400.

[0078] Regarding the specific structure of the gate structure of the first transistor, the embodiments of this application do not specifically limit it. It can be a single-gate structure, a double-gate structure, or other possible gate structures, which can be determined according to actual needs.

[0079] For example, the first transistor may be a single-gate structure. The gate structure of the first transistor is disposed on any side of the first channel region along a third direction.

[0080] For example, the first transistor may be a dual-gate structure. Referring to Figures 1(a) and 1(b), the third gate 221 and the fourth gate 222 of the first transistor 200 are respectively disposed on both sides of the first channel region 212 along the third direction.

[0081] With the above technical solution, traditional transistors have only one gate to control the current in the channel region, while the first transistor provided in this application embodiment has two gates. The dual-gate transistor can have twice the gate control area with the same channel region area, effectively improving the gate's control capability over the channel region. This makes the gate's control of the charge carriers in the channel region more precise and flexible, allowing for more effective regulation of current conduction and cutoff, thereby improving the switching performance of the transistor provided in this application embodiment. It can effectively suppress short-channel effects and is beneficial for further reducing the size of the transistor provided in this application embodiment, thus increasing the storage density of the dynamic random access memory provided in this application embodiment. For example, under low-voltage operation, the first transistor with the dual-gate structure can more precisely control the current, achieving faster switching transitions, which is beneficial for reducing the power consumption of the dynamic random access memory provided in this application embodiment.

[0082] It is understood that, in conjunction with the above description of the gate structure 220, referring to Figures 1(a) and 1(b), along the first direction, the third gate 221, the first channel region 212, and the fourth gate 222 are stacked sequentially and are all disposed within the second notch 123. The first gate dielectric layer 240 is disposed between the third gate 221 and the first channel region 212, and between the fourth gate 222 and the first channel region 212, respectively.

[0083] Regarding the material of the gate of the first transistor, this application embodiment does not specifically limit it. It can be tantalum, titanium, tantalum nitride, titanium nitride, atomic crystal tungsten selenide, atomic crystal molybdenum selenide, or other possible materials, which can be determined according to actual needs. In addition, when the first transistor is a dual-gate structure, the materials of the third gate and the fourth gate can be the same to facilitate the simultaneous formation of the third gate and the fourth gate; or, the materials of the third gate and the fourth gate can be different, which can be determined according to actual needs.

[0084] Regarding the first source 231 and the first drain 232 described above, as one possible implementation, please refer to Figures 1(a) and 1(b). The first source 231 and the first drain 232 that are electrically connected to the first gate 321 are integrally continuous with the first gate 321. The first source 231 and the first drain 232 that are not electrically connected to the first gate 321 are disposed within the second via 250.

[0085] When using the above-described scheme, during the manufacturing of the dynamic random access memory (DRAM) provided in this embodiment, one of the first source and the first drain that is electrically connected to the first gate can be formed in the same process step as the first gate. This facilitates the simultaneous formation of a multi-layer memory cell array, significantly improving the integration density of the DRAM while ensuring the electrical performance and stability of the memory cells. Furthermore, since the two structures are integrally continuous, no additional structure is needed to connect them, which helps reduce the area occupied by the memory cells, thereby increasing the density of the DRAM provided in this embodiment.

[0086] It should be noted that in Figures 1(a) and 1(b), the first drain 232 and the first gate 321 may be electrically connected. This is only an example. The positions of the first drain 232 and the first source 231 may be interchanged, and the positions of the first source region 211 and the first drain region 213 may also be interchanged. This application embodiment does not make specific limitations on this.

[0087] Regarding the materials of the first source and the first drain, this application embodiment does not specifically limit them. They can be copper, aluminum, chromium, silver, gold, or other possible materials, which can be determined according to actual needs. In addition, the materials of the first source and the first drain can be the same, so as to form the first source and the first drain simultaneously; or, the materials of the first source and the first drain can be different, which can be determined according to actual needs.

[0088] Regarding the first gate dielectric layer 240, in addition to the distribution described above, please refer to Figures 1(a) and 1(b), it extends to the first gate 321 and the first source 231 or the first drain 232 integrally continuous with the first gate 321; and covers the sidewall of the first notch 122, extends to the sidewall of the first via 340, so that the first gate dielectric layer 240 also serves as part of the gate dielectric layer between the first gate 321 and the second channel region 312; and covers the sidewall of the second via 250.

[0089] When using the above technical solution, please refer to Figures 1(a) and 1(b). When forming the first gate dielectric layer 240, after forming the first notch 122 and the second notch 123 connected to the first notch 122, the material of the first gate dielectric layer 240 can be directly deposited to simultaneously cover the first notch 122 and the second via 250 through processes such as deposition. This simultaneously forms the first gate dielectric layer 240 of the multiple first transistors 200 included in the dynamic random access memory. This is beneficial for forming a multi-layer memory cell array at one time, and significantly improves the integration density of the dynamic random access memory while ensuring the electrical performance and stability of the memory cells.

[0090] Regarding the material of the first gate dielectric layer, traditional materials such as silicon dioxide can be selected to reduce the difficulty of manufacturing the first gate dielectric layer. Alternatively, high dielectric constant materials such as hafnium oxide, aluminum oxide, zirconium oxide, and tantalum oxide can be selected to reduce the thickness of the first gate dielectric layer, thereby reducing the volume of the first transistor. This facilitates the formation of a multi-layer memory cell array in one step, significantly improving the integration density of the dynamic random access memory while ensuring the electrical performance and stability of the memory cells.

[0091] The structure and materials of the second transistor will be further explained below.

[0092] Referring to Figures 1(a) and 1(b), the second transistor 300, by way of example, includes: a second source region 311, a second channel region 312, a second drain region 313, a first gate 321, a second gate 322, a second source 331, a second drain 332, a dielectric isolation layer 341, and a second gate dielectric layer 342. The second source region 311, the second channel region 312, and the second drain region 313 are disposed within a first via 340 along a first direction. The second gate 322 is disposed within the first via 340, and the second channel region 312 surrounds the outer periphery of the second gate 322. A first recess 122 is provided inwardly on the portion of the dielectric structure corresponding to the second channel region 312, and the first gate 321 is disposed within the first recess 122. The second transistor 300 includes a second source 331 and a second drain 332 respectively disposed within a third recess 333 and a fourth recess 334; the third recess 333 and the fourth recess 334 are respectively disposed on both sides of the first gate 321 along a first direction; the second source 331 is electrically connected to the second source region 311; and the second drain 332 is electrically connected to the second drain region 313. The bottom of the third recess 333 and / or the fourth recess 334 contacts the gate structure 220, and a dielectric isolation layer 341 is also covered on the inner wall of the third recess 333 and the inner wall of the fourth recess 334. The dielectric isolation layer 341 electrically isolates the second source 331 and the second drain 332 from the gate structure 220, and the dielectric isolation layer 341 and the first gate dielectric layer 240 electrically isolate the second source 331 from the first gate 321 and the second drain 332 from the first gate 321. The dielectric isolation layer 341 also covers at least the portion where the first gate 321 contacts the first via 340, so that the dielectric isolation layer 341 and the first gate dielectric layer 240 together serve as the gate dielectric layer between the first gate 321 and the second channel region 312.

[0093] With the above technical solution, please refer to Figures 1(a) and 1(b). The third notch 333 and the fourth notch 334 are formed on both sides of the first notch 122 in the third direction and are connected to the first through hole 340. The second transistor 300 has a vertical channel structure, which reduces the area occupied by the second source region 311, the second channel region 312 and the second drain region 313 of the second transistor 300 while ensuring the channel length of the second transistor 300, thereby reducing the area occupied by the second transistor 300 and improving the storage density of the dynamic random access memory. Furthermore, the second source 331, the second drain 332 and the first gate 321 of the second transistor 300 are vertically stacked in the first direction, reducing the area occupied by the second transistor 300 and improving the storage density of the dynamic random access memory. Simultaneously, the second source region 311, the second channel region 312, and the second drain region 313 are vertically stacked within the first via 340. This allows for the formation of the second source region 311, the second channel region 312, and the second drain region 313 within the same second transistor 300, as well as the formation of the second source region 311, the second channel region 312, and the second drain region 313 in different second transistors 300 connected through the first via 340, all within a single deposition operation. Furthermore, the first gate dielectric layer 240 is separated from the second source 331 and the second drain 332 by only a dielectric isolation layer 341, preventing them from occupying additional area. This helps reduce the area occupied by the memory cell 400 and facilitates the one-time formation of a multi-layer memory cell array. While ensuring the electrical performance and stability of the memory cell 400, this significantly improves the integration density of the dynamic random access memory.

[0094] Regarding the first gate 321 included in the second transistor 300, please refer to Figures 1(a) and 1(b), which serves as a memory node (SN) included in the 2TOC memory cell 400. Furthermore, the first gate 321 is electrically connected to either the first source 231 or the first drain 232. Exemplarily, the first gate 321 is integrally continuous with the first source 231 or the first drain 232.

[0095] Regarding the material of the first gate, this application embodiment does not specifically limit it. It can be tantalum, titanium, tantalum nitride, titanium nitride, atomic crystal tungsten selenide, atomic crystal molybdenum selenide, or other possible materials, which can be determined according to actual needs.

[0096] Regarding the second source region 311, the second channel region 312, and the second drain region 313, please refer to Figures 1(a) and 1(b). They are disposed in the first via 340 along the first direction. In other words, they cover the inner wall of the first via 340 near the first gate 321, and make the second transistor 300 form a vertical channel.

[0097] Regarding the materials of the second source region, the second channel region, and the second leak region, this application embodiment does not impose specific limitations on them, and they can be determined according to actual needs.

[0098] For example, the materials of the second source region, the second channel region, and the second drain region can be indium zinc oxide, tin-doped indium oxide, indium oxide, zinc oxide, titanium oxide, or other possible materials.

[0099] When the above technical solution is adopted, the beneficial effects of using the above-mentioned materials in the second source region, the second channel region, and the second drain region can be referred to the relevant description of the device type of the first transistor, which will not be repeated here.

[0100] Regarding the second source and the second drain included in the second transistor, the embodiments of this application do not specifically limit their positions, as long as they can facilitate the parallel integration of dynamic random access memory.

[0101] Regarding the materials of the aforementioned dielectric isolation layer, traditional materials such as silicon dioxide can be selected to reduce the difficulty of manufacturing the dielectric isolation layer. Alternatively, materials with high dielectric constants such as hafnium oxide, alumina, zirconium oxide, and tantalum oxide can be selected to reduce the thickness of the dielectric isolation layer, thereby reducing the size of the second transistor and increasing the integration density.

[0102] Regarding the materials of the second source and the second drain, this application does not specifically limit them. They can be copper, aluminum, chromium, silver, gold, or other possible materials, which can be determined according to actual needs. In addition, the materials of the second source and the second drain can be the same to facilitate the simultaneous formation of the second source and the second drain; or, the materials of the second source and the second drain can be different, which can be determined according to actual needs.

[0103] Regarding the second gate included in the second transistor, please refer to Figures 1(a) and 1(b), which is disposed within the first via 340 and on the second channel region 312.

[0104] Regarding the material of the second gate, this application embodiment does not specifically limit it. It can be copper tantalum, titanium, tantalum nitride, titanium nitride, atomic crystal tungsten selenide, atomic crystal molybdenum selenide, or other possible materials, which can be determined according to actual needs.

[0105] In addition, referring to Figures 1(a) and 1(b), the second channel region 312 surrounds the outer periphery of the second gate 322, and a second gate dielectric layer 342 is also provided between the second gate 322 and the second channel region 312.

[0106] Regarding the material of the second gate dielectric layer, traditional materials such as silicon dioxide can be selected to reduce the difficulty of manufacturing the second gate dielectric layer. Alternatively, high dielectric constant materials such as hafnium oxide, aluminum oxide, zirconium oxide, and tantalum oxide can be selected to reduce the thickness of the second gate dielectric layer, thereby reducing the size of the second transistor and increasing the integration density.

[0107] In practical applications, the shapes of the first and second through holes are not specifically limited in this application embodiment. They can be cylindrical holes, prism holes, or other possible shapes. For example, both the first and second through holes are prism holes, and the adjacent sides of the cross-sections of the first and second through holes are parallel to the second and third directions, respectively.

[0108] Regarding the media structure used to isolate different storage cells, exemplarily, the media structure includes a first media section, a second media section, a first media filling section, a second media filling section, and a third media filling section.

[0109] Specifically, referring to Figures 1(a) and 1(b), along the first direction, the first medium portion 110 isolates two adjacent storage cells 400, and forms a first recess 122 by being recessed inward from the first through hole 340 and a second recess 123 by being recessed inward from the second through hole 250.

[0110] Please refer to Figures 1(a) and 1(b). Along the second direction, the second dielectric section 120 electrically isolates the first source region 211, the first channel region 212, the first drain region 213 and the first gate 321 of two adjacent memory cells 400.

[0111] When the above technical solution is adopted, the second dielectric portion isolates the first source region, first channel region, first drain region, and first gate of two adjacent memory cells along the second direction, thereby achieving isolation of the data stored in the two adjacent memory cells. Furthermore, the second dielectric portion can also serve as a support, preventing bending of the stacked structure after the formation of the first and second notches, which is beneficial for the structural regularity of the memory cells. This ensures the normal operation and stable performance of the memory cells manufactured by the dynamic random access memory manufacturing method provided in this application embodiment, thereby improving yield.

[0112] Regarding the material of the second dielectric portion, this application embodiment does not specifically limit it, and it can be determined according to actual needs. For example, the material of the second dielectric portion may include silicon oxide, silicon nitride, or polycrystalline silicon.

[0113] Referring to Figures 1(a) and 1(b), along the second direction, the first medium filling portion 130 isolates two adjacent first through holes 340, and the second medium filling portion 140 isolates two adjacent second through holes 250. The third medium filling portion is disposed within the first through holes 340 and the second through holes 250.

[0114] Regarding the materials of the first dielectric portion, the first dielectric filler portion, the second dielectric filler portion, and the third dielectric filler portion, this application embodiment does not specifically limit them, as long as they can meet the insulation and strength requirements. For example, silicon oxide or silicon nitride can be used. Furthermore, the materials of the first dielectric portion, the first dielectric filler portion, the second dielectric filler portion, and the third dielectric filler portion can be the same to make the interfaces between them regular and the contact interface strength higher; alternatively, the materials of the first dielectric portion, the first dielectric filler portion, the second dielectric filler portion, and the third dielectric filler portion can also be different to meet other design needs.

[0115] The distribution of storage units is further explained below.

[0116] Referring to the example above, and to Figures 1(a) and 1(b), the one of the first source 231 and the second drain 332 that is not electrically connected to the first gate 321 extends along a first direction, covering the sidewall of the first dielectric portion 110 located at the second via 250, and is connected to the one of the first source 231 and the second drain 332 of the first transistor 200 adjacent along the first direction that is not electrically connected to the first gate 321, forming a write bit line (WBL). The first gate dielectric layer 240 also extends along the write bit line. In addition, a gate structure 220 is also disposed on the first dielectric portion 110 and extends along a second direction, connecting to the gate structure 220 of the first transistor adjacent along the second direction to form a write word line (WWL). The second source 331 and the second drain 332 are also disposed on the first dielectric portion 110 and extend along the second direction, connecting with the second source 331 and the second drain 332 of the first transistor 200 adjacent along the first direction to form a first signal line and a second signal line, respectively. The first signal line serves as a read bit line (RBL), and the second signal line is grounded. Within the first via 340, the second gate 322 extends along the first direction and connects with the second gate 322 of the second transistor 300 adjacent along the first direction, serving as a read word line (RWL). The second source region 311, the second channel region 312, the second drain region 313, and the second gate dielectric layer 342 disposed between the second channel region 312 and the second gate 322 also extend along the first direction.

[0117] Please refer to Figures 1(a) and 1(b). In the second via 250, a plurality of first transistors 200 connected to the write bit line disposed in the second via 250 form a column of first transistors 200. In the same second via 250, at least two columns of first transistors 200 are disposed and electrically isolated by the third dielectric filling portion 150.

[0118] Please refer to Figures 1(a) and 1(b). In the first via 340, a plurality of second transistors 300 connected to the write bit line disposed in the first via 340 form a column of second transistors 300. At least two columns of second transistors 300 are disposed in the same first via 340 and are electrically isolated by the third dielectric filling portion 150.

[0119] Secondly, embodiments of this application also provide a method for manufacturing a dynamic random access memory (DRAM). Referring to Figures 1(a) and 1(b), the method for manufacturing the DRAM includes: forming a plurality of memory cells 400 arranged in a three-dimensional array; and forming a dielectric structure for isolating different memory cells 400; the plurality of memory cells 400 arranged in a three-dimensional array includes multiple memory layers spaced apart along a first direction, each memory layer including a plurality of memory groups spaced apart along a second direction, each memory group including a plurality of memory cells 400 spaced apart along a third direction; the first direction, the second direction, and the third direction are different from each other; each memory cell 400 includes a first transistor 200 and a second transistor 300 spaced apart along the third direction; the second transistor 300 has a dual-gate structure; in the same memory cell 400, one of the first source 231 or the first drain 232 of the first transistor 200 is electrically connected to the first gate 321 of the second transistor 300; the dielectric structure is provided with a first via 340 and a second via 250 spaced apart along the third direction; the second transistor 300 includes... The second source region 311, the second channel region 312, and the second drain region 313 are disposed within the first via 340 along a first direction; the second gate 322 of the second transistor 300 is disposed within the first via 340, and the second channel region 312 of the second transistor 300 surrounds the outer periphery of the second gate 322; the dielectric structure corresponding to the portion of the second channel region 312 of the second transistor 300 is provided with an inwardly recessed first notch 122, and the first gate 321 of the second transistor 300 is disposed within the first via 340. Within a recess 122, one of the first source 231 or the first drain 232 that is not electrically connected to the first gate 321 is disposed within a second via 250; the portion of the second via 250 corresponding to the dielectric structure of the first source 231 or the first drain 232 is provided with an inwardly recessed second recess 123, and the second recess 123 communicates with the first recess 122; the first source region 211, the first channel region 212 and the first drain region 213 of the first transistor 200 are distributed in the second recess 123 along a third direction.

[0120] Compared with the prior art, the beneficial effects of the method for manufacturing dynamic random access memory provided in this application embodiment are the same as those of the dynamic random access memory provided in the first aspect, and will not be repeated here.

[0121] The process of manufacturing dynamic random access memory (DRAM) will be described below with reference to the schematic diagrams and flowcharts of the operation shown in Figures 1(a) and 1(b), up to Figures 15(a) and 15(b). Exemplarily, the method for manufacturing the DRAM includes the following steps:

[0122] As shown in Figures 3(a) and 3(b), a stacked structure is formed, including a first dielectric filling portion 130 and a second dielectric filling portion 140 that penetrate the stacked structure along a first direction. The stacked structure includes multiple stacked units stacked along the first direction. Each stacked unit includes two first dielectric layers 111 spaced apart along the first direction and a stack between the two first dielectric layers 111. The stack includes two metal layers 223 spaced apart along the first direction and a second dielectric layer 121 between the two metal layers 223. The materials of the first dielectric layer 111, the metal layer 223, and the second dielectric layer 121 are different. The stacked structure has a third through-hole 131 and a fourth through-hole 141 penetrating along the first direction, which are spaced apart. The first dielectric filling portion 130 fills the third through-hole 131, and the second dielectric filling portion 140 fills the fourth through-hole 141.

[0123] As one possible implementation, referring to Figures 3(a) and 3(b), along the second direction, the first medium filling part 130 is disposed between two adjacent first through holes 340; along the second direction, the second medium filling part 140 is disposed between two adjacent second through holes 250.

[0124] Specifically, referring to Figures 1(a) and 1(b), the first dielectric layer 111 is used to form the first dielectric portion 110, isolating the memory cell 400 along the first direction. The stacked layer includes two metal layers 223 used to form the third gate 221 and the fourth gate 222 of the first transistor 200, and as a placeholder layer, used to form the third notch 333 and the fourth notch 334. The second dielectric layer 121 serves as a sacrificial layer and is subsequently partially removed, pre-positioning the first source region 211, the first channel region 212, the first drain region 213, the first gate 321, and the first source 231 and the first drain 232 integrally continuous with the first gate 321, in order to facilitate the subsequent formation of these five structures.

[0125] It should be noted that, with reference to Figures 1(a) and 1(b), along the first direction, the two outermost layers of the stacked structure are the first dielectric layers 111, and the thickness of the two outermost first dielectric layers 111 of the stacked structure can be greater than that of the first dielectric layer 111 located inside the stacked structure, so as to protect the stacked structure and other structures formed subsequently.

[0126] In one example, referring to Figures 4, 3(a) and 3(b), 5, 6(a) and 6(b), the formation of the stacked structure and the formation of the first dielectric filling portion 130 and the second dielectric filling portion 140 through the stacked structure along the first direction include the following steps:

[0127] Please refer to Figure 4. The stacked material layer is formed through processes such as epitaxy. The stacked material layer includes multiple stacked units stacked along a first direction.

[0128] Next, referring to Figures 5, 6(a), and 6(b), a third through-hole 131 and a fourth through-hole 141 are formed through the stacked material layer by processes such as dry etching; along the second direction, the third through-hole 131 is disposed between two adjacent first through-holes 340; along the second direction, the fourth through-hole 141 is disposed between two adjacent second through-holes 250.

[0129] With the above technical solution adopted, please refer to Figures 3(a) and 3(b). The first dielectric filling portion 130 and the second dielectric filling portion 140 serve as an isolation layer between adjacent memory cells 400 along the second direction, which helps to avoid leakage current between adjacent memory cells 400 along the second direction. Furthermore, in the subsequent step of partially removing the second dielectric layer 121, the two metal layers 223 in the stacked cell will be suspended. The first dielectric filling portion 130 and the second dielectric filling portion 140 can serve as supports to prevent bending of the stacked structure, which is beneficial to the structural regularity of the memory cell 400. This ensures the normal operation and stable performance of the memory cell 400 manufactured by the manufacturing method of the dynamic random access memory provided in this application embodiment, thereby improving the yield.

[0130] In another example, the method of forming a stacked structure and forming a first dielectric filling portion and a second dielectric filling portion through the stacked structure along the first direction can also be to first form a portion of the stacked material layer and form a third through hole and a fourth through hole, then form another portion of the stacked material layer and form a third through hole and a fourth through hole; repeat the above process to finally form a stacked structure.

[0131] Next, referring to Figures 6(a) and 6(b), a deposition process is used to fill the third through hole 131 with the first medium filling portion 130 and the fourth through hole 141 with the second medium filling portion 140.

[0132] Next, referring to Figures 7(a) and 7(b), a plurality of first vias 340 are formed through the stacked structure and spaced apart along the second direction using processes such as dry etching. Along the second direction, a first dielectric filling portion 130 is disposed between two adjacent first vias 340.

[0133] Next, referring to Figures 7(a) and 7(b), along the third direction, selectively etch the two metal layers 223 near the edge of the first via 340 by dry etching or other methods to form the third notch 333 and the fourth notch 334.

[0134] Next, referring to Figures 8(a) and 8(b), a dielectric isolation layer 341 is formed in the third recess 333, the fourth recess 334 and the first through hole 340 through processes such as deposition and selective etching such as dry etching.

[0135] Next, referring to Figures 9(a) and 9(b), the second source 331 of the second transistor 300 is formed in the third recess 333 by processes such as deposition and selective etching processes such as dry etching, and the second drain 332 of the second transistor 300 is formed in the fourth recess 334.

[0136] In the actual manufacturing process, referring to Figures 9(a) and 9(b), a first electrode layer can be formed within the first through-hole 340, the third recess 333, and the fourth recess 334. Then, the portion of the first electrode layer located within the first through-hole 340 is selectively etched to form the second source 331 and the second drain 332.

[0137] With the above technical solution, the second source and second drain of the dynamic random access memory (DRAM) including multiple memory cells manufactured by the manufacturing method provided in this application embodiment can be formed simultaneously at one time, which is beneficial to realize the one-time formation of a multi-layer memory cell array. Under the premise of ensuring the electrical performance and stability of the memory cells, the integration density of the DRAM is greatly improved.

[0138] Next, referring to Figures 10(a) and 10(b), the second transistor 300, including the second source region 311, the second channel region 312, and the second drain region 313, is formed in the first via 340 along the first direction using processes such as deposition and selective etching processes such as dry etching; the second source 331 and the second source region 311 are connected; the second drain 332 and the second drain region 313 are connected.

[0139] Next, referring to Figures 10(a) and 10(b), a second gate dielectric layer 342, including the second transistor 300, is formed within the first via 340 using processes such as deposition and selective etching such as dry etching. The second gate dielectric layer 342 is formed on the second source region 311, the second channel region 312, and the second drain region 313.

[0140] Next, referring to Figures 10(a) and 10(b), the second gate 322 of the second transistor 300 is formed in the first via 340 by processes such as deposition.

[0141] It is understood that, in order to ensure the regularity of other structures subsequently formed in the first through hole, or to achieve electrical isolation, the manufacturing method provided in this application embodiment further includes: selectively etching the structure formed in the first through hole after the structure is formed in the first through hole, so that the structure formed in the first through hole is separated in the third direction.

[0142] Next, referring to Figures 11(a) and 11(b), a plurality of second vias 250 are formed through the stacked structure and spaced apart along the second direction using processes such as dry etching. Along the second direction, a second dielectric filling portion 140 is disposed between two adjacent second vias 250.

[0143] Next, referring to Figures 12(a) and 12(b), the portion of the second dielectric layer 121 located between and adjacent to the first via 340 and the second via 250 in the third direction is removed by dry etching or wet etching, so that the remaining second dielectric layer 121 forms the second dielectric portion 120. Along the second direction, the second dielectric portion 120 electrically isolates the first source region 211, the first channel region 212, the first drain region 213, and the first gate 321 of two adjacent memory cells.

[0144] When the above technical solution is adopted, the second dielectric portion isolates the first source region, first channel region, first drain region, and first gate of two adjacent memory cells along the second direction, thereby achieving isolation of the data stored in the two adjacent memory cells. Furthermore, the second dielectric portion can also serve as a support, preventing bending of the stacked structure after the formation of the first and second notches, which is beneficial for the structural regularity of the memory cells. This ensures the normal operation and stable performance of the memory cells manufactured by the dynamic random access memory manufacturing method provided in this application embodiment, thereby improving yield.

[0145] Next, referring to Figures 13(a) and 13(b), the first gate dielectric layer 240 of the first transistor 200 is formed in the third notch 333 and the second via 250 by processes such as deposition.

[0146] Next, referring to Figures 14(a) and 14(b), the second transistor 200 is formed within the first notch 122 using processes such as deposition and selective etching such as dry etching, comprising the first gate 321, the first source 231, and the first drain 232, which are electrically connected to the first gate 321. The first source region 211, the first channel region 212, and the first drain region 213 of the first transistor 200 are formed within the second notch 123.

[0147] It is understood that, referring to Figures 14(a) and 14(b), in the above process steps, the first gate 321 and one of the first source 231 and the first drain 232 that are electrically connected to the first gate 321 are formed first, and then the first source region 211, the first channel region 212 and the first drain region 213 are formed.

[0148] In the actual manufacturing process, referring to Figures 14(a) and 14(b), a second electrode layer can be formed within the second via 250, the first recess 122, and the second recess 123 through processes such as deposition. Next, the portions of the second electrode layer located within the second via 250 and the second recess 123 are selectively etched to form the first gate 321, and one of the first source 231 and the first drain 232 that is electrically connected to the first gate 321.

[0149] With the above technical solution, the first gate of the multiple memory cells and one of the first source and first drain of the dynamic random access memory manufactured by the manufacturing method provided in this application can be formed at one time. This is beneficial to realize the one-time formation of a multi-layer memory cell array, and significantly improves the integration density of the dynamic random access memory while ensuring the electrical performance and stability of the memory cells.

[0150] Please refer to the relevant description in the first aspect. The first transistor is an indium zinc oxide thin film transistor, a tin-doped indium oxide thin film transistor, an indium oxide thin film transistor, a zinc oxide thin film transistor, or a titanium oxide thin film transistor. That is, the materials of the first source region, the first channel region, and the first drain region include: indium zinc oxide, tin-doped indium oxide, indium oxide, zinc oxide, or titanium oxide.

[0151] With the above technical solutions, the above metal oxide thin film transistors can be manufactured using a low-temperature process. The low-temperature process can reduce the need for expensive high-temperature equipment and complex process steps, thereby reducing costs. Furthermore, in the manufacturing method provided in this application embodiment, the first transistor is formed only after the second transistor is formed. The first transistor is manufactured using a low-temperature process, which can avoid damaging the structure of other dynamically random access memories formed earlier, which is beneficial to the integrity of the structure of other dynamically random access memories, thereby improving the yield of the dynamically random access memory.

[0152] Next, by means of deposition and selective etching processes such as dry etching, referring to Figures 15(a) and 15(b), one of the first source 231 and the first drain 232 that is not electrically connected to the first gate 321 is formed in the second via 250.

[0153] It should be noted that Figures 15(a) and 15(b) only show the case where the first source 231 is disposed in the second via 250. The positions of the first source 231 and the first drain 232 can be interchanged, and the embodiments of this application do not specifically limit them.

[0154] It is understood that, in order to ensure the regularity of other structures subsequently formed in the second via or to achieve electrical isolation, the manufacturing method provided in this application embodiment further includes: selectively etching the structure formed in the second via after the structure is formed in the second via, so that the structure formed in the second via is separated in the third direction.

[0155] Next, through processes such as deposition, please refer to Figures 1(a) and 1(b), a third medium filling portion 150 is formed in the second through hole 250.

[0156] For details regarding the materials, locations, and other beneficial effects of the various structures manufactured by the aforementioned method of manufacturing dynamic random access memory, please refer to the relevant description in the first aspect; these details will not be repeated here.

[0157] With the above technical solution adopted, please refer to Figures 14(a) and 14(b). The first through hole 340 is connected to the first recess 122, the first through hole 340 is connected to the third recess 333, the first through hole 340 is connected to the fourth recess 334, and the second through hole 250 is connected to the second recess 123. After forming the first through hole 340 and the second through hole 250, the above-mentioned structures of the first transistor 200 and the second transistor 300 are formed by the processing technology in the first through hole 340 and the second through hole 250. This realizes the simultaneous manufacturing of memory cells 400 disposed in the same first through hole 340. The stacked structure includes multiple first through holes 340, which allows multiple memory cells 400 disposed in multiple first through holes 340 to be processed simultaneously. This allows all memory cells 400 included in the dynamic random access memory to be manufactured simultaneously, which is beneficial to realize the one-time formation of multi-layer memory cell arrays. Under the premise of ensuring the electrical performance and stability of memory cells, the integration density of dynamic random access memory is greatly improved.

[0158] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0159] The embodiments of this application have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of this application. The scope of this application is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this application, and all such substitutions and modifications should fall within the scope of this application.

Claims

1. A dynamic random access memory, wherein, include: Multiple storage cells arranged in a three-dimensional array, and a medium structure for isolating the different storage cells; The plurality of storage cells arranged in a three-dimensional array include multiple storage layers spaced apart along a first direction, each storage layer including multiple storage groups spaced apart along a second direction, and each storage group including multiple storage cells spaced apart along a third direction; the first direction, the second direction, and the third direction are different from each other; Each of the memory cells includes a first transistor and a second transistor distributed along the third direction; the second transistor has a dual-gate structure; in the same memory cell, one of the first source and the first drain of the first transistor is electrically connected to the first gate of the second transistor. The dielectric structure is provided with a first via and a second via spaced apart along the third direction; the second source region, the second channel region and the second drain region of the second transistor are disposed in the first via along the first direction; the second gate of the second transistor is disposed in the first via, and the second channel region of the second transistor surrounds the outer periphery of the second gate; the dielectric structure is provided with an inwardly recessed first notch corresponding to the portion of the second channel region of the second transistor, and the first gate of the second transistor is disposed in the first notch; One of the first source and the first drain that is not electrically connected to the first gate is disposed in the second via; the portion of the dielectric structure corresponding to the second via is provided with an inwardly recessed second notch, and the second notch communicates with the first notch; the first source region, the first channel region and the first drain region of the first transistor are distributed in the second notch along the third direction.

2. The dynamic random access memory according to claim 1, wherein, The first transistor has a dual-gate structure; the third gate and the fourth gate of the first transistor are respectively disposed on both sides of the first channel region along the third direction.

3. The dynamic random access memory according to claim 1, wherein, The first transistor includes a gate structure disposed within the second notch and located on at least one side of the first channel region along the first direction; the first source and the first drain that are not electrically connected to the first gate are isolated from the gate structure through a first gate dielectric layer included in the first transistor.

4. The dynamic random access memory according to claim 1, wherein, The second transistor includes a second source and a second drain, which are respectively disposed in a third recess and a fourth recess; the third recess and the fourth recess are respectively disposed on both sides of the first gate along the first direction; the second source is electrically connected to the second source region; and the second drain is electrically connected to the second drain region.

5. The dynamic random access memory according to claim 1, wherein, The first transistor is an indium zinc oxide thin-film transistor, a tin-doped indium oxide thin-film transistor, an indium oxide thin-film transistor, a zinc oxide thin-film transistor, or a titanium oxide thin-film transistor.

6. The dynamic random access memory according to claim 1, wherein, The first source and the first drain that are electrically connected to the first gate are integrally continuous with the first gate.

7. A method for manufacturing a dynamic random access memory, wherein, include: Multiple storage cells are formed in a three-dimensional array, and a medium structure is formed to isolate the different storage cells. The plurality of storage cells arranged in a three-dimensional array include multiple storage layers spaced apart along a first direction, each storage layer including multiple storage groups spaced apart along a second direction, and each storage group including multiple storage cells spaced apart along a third direction; the first direction, the second direction, and the third direction are different from each other; Each of the memory cells includes a first transistor and a second transistor distributed along the third direction; the second transistor has a dual-gate structure; in the same memory cell, one of the first source or the first drain of the first transistor is electrically connected to the first gate of the second transistor. The dielectric structure is provided with a first via and a second via spaced apart along the third direction; the second source region, the second channel region and the second drain region of the second transistor are disposed in the first via along the first direction; the second gate of the second transistor is disposed in the first via, and the second channel region of the second transistor surrounds the outer periphery of the second gate; the dielectric structure is provided with an inwardly recessed first notch corresponding to the portion of the second channel region of the second transistor, and the first gate of the second transistor is disposed in the first notch; The first source or the first drain that is not electrically connected to the first gate is disposed in the second via; the portion of the dielectric structure corresponding to the first source or the first drain of the second via is provided with an inwardly recessed second notch, and the second notch communicates with the first notch; the first source region, the first channel region and the first drain region of the first transistor are distributed in the second notch along the third direction.

8. The method for manufacturing a dynamic random access memory according to claim 7, wherein, The formation of a plurality of said memory cells arranged in a three-dimensional array, and the formation of said media structure for isolating the different said memory cells, include: A stacked structure is formed, comprising a first dielectric filling portion and a second dielectric filling portion penetrating the stacked structure along a first direction; the stacked structure includes multiple stacked units stacked along the first direction; each stacked unit includes two first dielectric layers spaced apart along the first direction, and a stack between the two first dielectric layers; the stack includes two metal layers spaced apart along the first direction, and a second dielectric layer between the two metal layers; the materials of the first dielectric layer, the metal layer, and the second dielectric layer are different from each other; the stacked structure is provided with a third through hole and a fourth through hole penetrating along the first direction, the third through hole and the fourth through hole being spaced apart; the first dielectric filling portion fills the third through hole, and the second dielectric filling portion fills the fourth through hole; A plurality of first through holes are formed that penetrate the stacked structure and are spaced apart along the second direction; Along the third direction, selectively etch the two metal layers near the edge of the first through hole to form a third notch and a fourth notch; A dielectric isolation layer is formed in the third recess, the fourth recess, and the first through hole; The second source of the second transistor is formed in the third notch, and the second drain of the second transistor is formed in the fourth notch; Along the first direction, a second source region, a second channel region, and a second drain region of the second transistor are formed within the first via; the second source and the second source region are connected; the second drain and the second drain region are connected. A second gate dielectric layer comprising the second transistor is formed within the first via; the second gate dielectric layer is formed on the second source region, the second channel region, and the second drain region. The second gate of the second transistor is formed within the first through-hole; A plurality of second through holes are formed that penetrate the stacked structure and are spaced apart along the second direction; The second dielectric layer is partially removed to form the first notch and the second notch, and the remaining metal layer forms the gate structure included in the first transistor; A first gate dielectric layer comprising the first transistor is formed within the second notch and the second through hole; The first gate of the second transistor and one of the first source and first drain electrically connected to the first gate are formed in the first notch; and the first source region, the first channel region and the first drain region of the first transistor are formed in the second notch. One of the first source and the first drain that is not electrically connected to the first gate is formed in the second via.

9. The method for manufacturing a dynamic random access memory according to claim 8, wherein, The formation of the stacked structure, and the formation of a first dielectric filling portion and a second dielectric filling portion penetrating the stacked structure along the first direction, include: A stacked material layer is formed; the stacked material layer comprises multiple layers of the stacked units stacked along a first direction; A third through-hole and a fourth through-hole are formed through the stacked material layer; along the second direction, the third through-hole is disposed between two adjacent first through-holes; along the second direction, the fourth through-hole is disposed between two adjacent second through-holes; The first medium filling portion is filled into the third through hole, and the second medium filling portion is filled into the fourth through hole.

10. The method for manufacturing a dynamic random access memory according to claim 9, wherein, The partial removal of the second dielectric layer also includes: The portion of the second dielectric layer located between the first via and the second via and adjacent to the second via in the third direction is removed, so that the remaining second dielectric layer forms a second dielectric portion; along the second direction, the second dielectric portion electrically isolates the first source region, the first channel region, the first drain region and the first gate of two adjacent memory cells.

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