Synchronization and grid-connection method for grid-forming energy storage system

Abstract

The present invention relates to a synchronization and grid-connection method for a grid-forming energy storage system, comprising: collecting three-phase voltages at a line side and a load side of a grid-connected switch by means of an off-grid / grid-connected controller, calculating electrical angles of the three-phase voltages at the line side and the load side and a difference value of the electrical angles, and processing and adjusting the difference value to a stable value; using an intelligent real-time approximation algorithm to process the difference value of the electrical angles and then change same into an angular frequency adjustment value, and sending the angular frequency adjustment value to an optical fiber receiving port of a power conversion system by means of an optical fiber output port; the power conversion system sending the angular frequency adjustment value to virtual synchronous generator control, so as to adjust the output voltage frequency and phase of the power conversion system; and finally, when the phase angle difference value between the voltages of the line side and load side of the grid-connected switch is less than 2°, the off-grid / grid-connected controller sending a synchronization completion signal, and a superordinate computer turning on the grid-connected switch by means of control. The present invention can implement active convergence of a frequency difference within 1 s, active regulation of the output frequency and phase of an energy storage system, and rapid locking onto parameters of a main grid.

Description

A method for simultaneous grid connection of a grid-type energy storage system Technical Field

[0001] This invention belongs to the field of power grid operation and control technology, and in particular, it is a method for synchronous grid connection of a grid-type energy storage system. Background Technology

[0002] With the maturation of grid-connected energy storage converter technology, these converters can be used to establish off-grid isolated grids or provide support in parallel with the main grid. Furthermore, in the event of a grid failure, the grid-connected energy storage system can operate independently. When the grid recovers and needs to be reconnected, the system must synchronize with the main grid in terms of voltage, frequency, phase, and amplitude to ensure a smooth and reliable connection when grid connection conditions are met. Currently, the primary method for achieving synchronization is to passively wait for the phase difference between the energy storage-side grid and the main grid to reach a certain threshold before performing the closing operation within a specific synchronization window. This method is prone to inaccurate synchronization, small synchronization windows, and long synchronization waiting times. Summary of the Invention

[0003] The purpose of this invention is to overcome the shortcomings of existing technologies and propose a synchronous grid-connection method for grid-connected energy storage systems. This method can maintain stable grid operation, actively achieve frequency difference convergence within 1 second, actively adjust the output frequency and phase of the energy storage system, and quickly lock onto the parameters of the large power grid. It has a long synchronization window, allowing the grid-connection switch to be closed at any time, with very small current and voltage surges at the moment of closing.

[0004] The technical problem solved by this invention is achieved through the following technical solution:

[0005] A method for simultaneous grid connection of a grid-connected energy storage system includes the following steps:

[0006] Step 1: The off-grid controller collects the three-phase voltages at the upper and lower ports of the grid-connected switch, and calculates the electrical angle of the three-phase voltages at the upper and lower ports through the two phase-locked loops of the DSP.

[0007] Step 2: In the FPGA of the phase-locked loop controller, perform difference calculation on the electrical angle of the upper and lower voltages calculated by the phase-locked loop, and process and adjust the difference to a stable value.

[0008] Step 3: Using an intelligent real-time approximation algorithm, the electrical angle difference is processed and converted into an angular frequency adjustment value. When the off-grid controller receives the synchronization start command from the host computer, the angular frequency adjustment value is sent to the fiber optic receiving port of the energy storage converter through the fiber optic output port.

[0009] Step 4: The energy storage converter receives the angular frequency adjustment value through the fiber optic receiving port and sends it to the virtual synchronous machine control to adjust the output voltage frequency and phase of the energy storage converter.

[0010] Step 5: When the phase angle difference between the upper and lower voltages of the grid-connected switch is less than 2°, the grid-connected controller sends a synchronization completion signal, and the host computer closes the grid-connected switch by control.

[0011] Moreover, the specific implementation method of step 1 is as follows: the upper voltage electrical angle FIPU and the lower voltage electrical angle FIPD are input to the subtraction unit A1 and subtracted to obtain the electrical angle difference value. The electrical angle difference value and 16383 are input to the addition unit A2 to perform the addition operation of 16383 on the electrical angle difference value. The result of the addition unit A2 is input to the delay unit A3 to perform a delay of 25ns for one FPGA clock cycle. The electrical angle difference value and 0 are input to the addition unit A4 to perform the addition operation of 0 on the electrical angle difference value obtained by the subtraction unit A1 to maintain clock alignment. The result of the addition unit A4 is input to the delay unit A5 to perform a delay of 25ns for one FPGA clock cycle.

[0012] The upper voltage and electrical angle FIPU are input to an adder A6 with an enable function, and the upper voltage and electrical angle are added to 0. The result of adder A6 and 0 are input to an adder A7 with an enable function, and the result of adder A7 is added to 0. The result of adder A7 and K1 are input to a comparator A8, and the result of adder A7 is compared with K1. When the output of adder A7 is greater than K1, the output of A8 is 1. The result of adder A7 and K2 are input to a comparator A9, and the result of adder A7 is compared with K2. When the output of adder A7 is less than K2, the output of comparator A9 is 1. The results of comparators A8 and A9 are input to an AND logic unit A10, and the results of comparators A8 and A9 are ANDed. When the results of comparators A8 and A9 are both 1, the output of AND logic unit A10 is 1; otherwise, the output is 0.

[0013] The lower voltage electrical angle FIPD and 0 are input to adder A11 with enable function to add 0. The result of adder A11 and 0 are input to adder A12 with enable function to add 0. The result of adder A12 and K1 are input to comparator A13. The result of adder A12 and K1 are compared. If the output of adder A12 is greater than K1, the output of A13 is 1. Adder A11... The result of 2 and K2 are input to the comparator A13. The result of the adder A12 is compared with K2. When the output of the adder A12 is less than K2, the comparator A13 outputs 1. The results of the comparators A13 and A14 are input to the AND logic unit A15. The results of the comparators A13 and A14 are ANDed. When the results of the comparators A13 and A14 are both 1, the AND logic unit A15 outputs 1. Otherwise, the output is 0.

[0014] The results of AND logic operators A10 and A15 are input to RS flip-flop A16. When S=1, the output is 1; when R=1, the output is 0. In other states, the flip-flop maintains its current state. When the result of AND logic operator A15 is 1, RS flip-flop A16 outputs 1; when the result of AND logic operator A10 is 1, RS flip-flop A16 outputs 0.

[0015] The results of delay arithmetic units A3 and A5 and RS flip-flop A16 are input to selection switch A17. When the output of RS flip-flop A16 is 1, selection switch A17 selects the output result of delay arithmetic unit A5. When the output result of RS flip-flop A16 is 0, selection switch A17 selects the output result of delay arithmetic unit A3. The result of selection switch A17 and 16383 are input to AND operation A18, and the output result of selection switch A17 and 16383 are performed by bitwise AND calculation.

[0016] Furthermore, the specific implementation method of step 3 is as follows: the difference between FIPU and FIPD, UDF, after processing, is input to the subtraction operator A19 along with 100%. 100% is subtracted from the difference between FIPU and FIPD, UDF. The difference between FIPU and FIPD, UDF, is then input to the comparator A20 along with 50%. The value of UDF is compared with 50%. When UDF is greater than or equal to 50%, the comparator A20 outputs 1; otherwise, it outputs 0. The difference between FIPU and FIPD, UDF, the result of the subtraction operator A19, and the result of the comparator A20 are input to the selector A21. When the comparator A20 outputs 1, the selector A21 selects the result of the subtraction operator A19. When the comparator A20 outputs 0, it selects the UDF value for output. The result of the selector A21 and K3 are input to the multiplication operator A2. 2. The result of selector A21 is multiplied by K3 and output. The result of multiplier A22 and K4 are input to adder A23. The result of multiplier A22 is added to K4 and output. The result of adder A23, -K5, and K5 are input to limiter A24. The result of adder A23 is limited. When the result of adder A23 is greater than K5, limiter A24 outputs K5. When the result of adder A23 is less than -K5, limiter A24 outputs the value of -K5. When the result of adder A23 is between -K5 and K5, limiter A24 outputs the value of A23. The result of limiter A24 and 0 are input to selector switch A25. When EN=1, selector switch A25 outputs the result of limiter A24 to DK. When EN=0, selector switch A25 outputs the value of 0.

[0017] Furthermore, the specific implementation method of step 4 is as follows: the active power setpoint PR and the actual operating active power PE are input to the subtraction operator A26, the active power setpoint PR and the actual operating active power PE are subtracted to calculate the power difference, the result of the subtraction operator A26 and the multiplication operator A29 is input to the subtraction operator A27, the result of the subtraction operator A26 is subtracted from the result of the multiplication operator A29, the result of the subtraction operator A27 and J are input to the multiplication operator A28, the result of the subtraction operator A27 and J are multiplied, the addition operator A30 and D are input to the multiplication operator A29, the output result of the addition operator A30 is multiplied by D, the result of the multiplication operator A28 and the delay operator A31 is input to the addition operator A30, the result of the multiplication operator A30 and the output result of the delay operator A31 are added, and the result of the addition operator A30 is input to the delay operator A31. The result of adder A31 is delayed by one DSP operation cycle. The result of adder A30 and KA are input to adder A32, and the result of adder A30 is added to KA. The result of adder A32 and 100% are input to adder A33, and 100% is added to the result of adder A32. The result of adder A33 and 50 times TA are input to multiplier A34, and the result of adder A34 is multiplied by 50 times TA. The result of multiplier A34 and the result of bitwise AND operator A36 are input to adder A35, and the result of multiplier A34 and the result of bitwise AND operator A36 are added. The result of adder A35 and 16383 are input to bitwise AND operator A36, and the result of adder A35 and 16383 are ANDed bit by bit, limiting the electrical angle to 0 to 16383. The advantages and positive effects of this invention are:

[0018] This invention acquires the three-phase voltages at the upper and lower terminals of the grid-connected switch via an off-grid controller. The electrical angles of these voltages are calculated using two phase-locked loops (PLLs) in a DSP. Within the FPGA of the off-grid controller, the electrical angles calculated by the PLLs are calculated and adjusted to a stable value. An intelligent real-time approximation algorithm is used to convert the electrical angle difference into an angular frequency adjustment value. When the off-grid controller receives a synchronization start command from the host computer, it sends the angular frequency adjustment value to the fiber optic receiver port of the energy storage converter via the fiber optic output port. The energy storage converter receives the angular frequency adjustment value through the fiber optic receiver port and feeds it into the virtual synchronizing machine control, adjusting the output voltage frequency and phase of the energy storage converter. Finally, when the phase angle difference between the voltages at the upper and lower terminals of the grid-connected switch is less than 2°, the off-grid controller sends a synchronization completion signal, and the host computer closes the grid-connected switch. This invention can proactively achieve rapid frequency difference convergence within 1 second, actively adjust the output frequency and phase of the energy storage system, and quickly lock onto the mains grid parameters. It has a long synchronization window, and the grid-connected switch can be closed at any time, with very small current and voltage surges at the moment of closing. Attached Figure Description

[0019] Figure 1. Schematic diagram of a grid-type energy storage system;

[0020] Figure 2 is a flowchart of the rapid synchronous grid connection steps of the energy storage system of the present invention;

[0021] Figure 3 is a logic block diagram for processing the voltage angle difference between the upper and lower ports of the grid-connected switch according to the present invention.

[0022] Figure 4 is a schematic diagram of the calculation of electrical angle difference in this invention;

[0023] Figure 5 is a logic block diagram of the intelligent real-time approximation algorithm of the present invention;

[0024] Figure 6 is a logic block diagram of the grid-connected energy storage converter of the present invention for generating electrical angles. Detailed Implementation

[0025] The present invention will be further described in detail below with reference to the accompanying drawings.

[0026] Grid-based energy storage systems are a new type of intelligent and highly integrated power system capable of operating in both grid-connected and off-grid modes and switching freely. Figure 1 shows a schematic diagram of a grid-based energy storage system, which mainly consists of the following parts:

[0027] Power grid: refers to the national power grid, regional power grid, microgrid, or local power grid composed of diesel generators, etc.

[0028] Grid connection switch: The physical interface connecting the energy storage system and the power grid. The opening and closing operation of the grid connection switch realizes the electrical connection and isolation between the energy storage system and the power grid.

[0029] Grid-mounted energy storage converters (PCS): Grid-mounted energy storage converters are used to establish independent power grids or support grid operation. Operating multiple PCS units in parallel can increase system capacity and reliability.

[0030] Energy storage batteries: Energy storage batteries are used to store and release energy. Common types of batteries include lithium-ion batteries, lead-acid batteries, and sodium-sulfur batteries.

[0031] Load: Electrical equipment in the system that consumes the electrical energy provided by the system.

[0032] Host computer: Responsible for monitoring, scheduling and optimizing the operation of the entire energy storage system.

[0033] Off-grid / off-grid controller: The off-grid / off-grid controller is a key component for achieving smooth switching between on-grid and off-grid modes of energy storage systems. It is used to enable synchronous grid connection between the energy storage system and the power grid, as well as seamless switching between grid-connected and off-grid modes.

[0034] A method for simultaneous grid connection of a grid-connected energy storage system, as shown in Figure 2, includes the following steps:

[0035] Step 1: The off-grid controller collects the three-phase voltages at the upper and lower ports of the grid-connected switch, and calculates the electrical angle of the three-phase voltages at the upper and lower ports through the two phase-locked loops of the DSP.

[0036] After sampling and PLL operation in the DSP, the voltages at the upper and lower terminals of the grid-connected switch are sent to the FPGA of the off-grid controller for processing. The FPGA uses a 40MHz clock with a period of 25ns. Figure 3 shows the logic block diagram for processing the voltage angle difference between the upper and lower terminals of the grid-connected switch. FIPU represents the upper voltage angle, and FIPD represents the lower voltage angle. Both FIPU and FIPD have amplitudes from 0 to 16383 (in this digital system, 16383 is calibrated as 100%), and the period is a sawtooth wave of the grid cycle. TA is the DSP operation cycle, K1 is the threshold value for the maximum voltage angle, K2 corresponds to the threshold value for the minimum voltage angle, and UDF is the processed difference between FIPU and FIPD.

[0037] A1 is a subtraction unit that subtracts FIPU from FIPD to obtain the electrical angle difference. A2 is an addition unit that adds 16383 to the difference calculated by A1. A3 is a delay unit that delays the result of A2 by one FPGA clock cycle (25ns). A4 is an addition unit that adds 0 to the difference of A1 to maintain clock alignment with the result of A2. A5 is a delay unit that delays the result of A4 by one FPGA clock cycle (25ns). A6, A7, A11, and A12 are adders with enable functionality, performing an operation only when the enable signal EN=1 rises. A6 and A11 add 0 to the electrical angle of the upper and lower voltages to align the DSP operation clocks of FIPU and FIPD, ensuring simultaneous operation. A7 adds 0 to the result of A6, and A12 adds 0 to the result of A11 to delay the signals of FIPU and FIPD by one DSP operation cycle. A8, A9, A13, and A14 are comparison operators. A8 compares the result of A7 with K1; if A7's output is greater than K1, A8 outputs 1. A9 compares the result of A6 with K2; if A7's output is less than K2, A9 outputs 1. A13 compares the result of A12 with K1; if A12's output is greater than K1, A13 outputs 1. A14 compares the result of A6 with K2; if A7's output is less than K2, A9 outputs 1. A10 is an AND logic operator, performing a bitwise AND operation on the results of A8 and A9. If both A8 and A9 are 1, A10 outputs 1; otherwise, it outputs 0. A15 is also an AND logic operator, performing a bitwise AND operation on the outputs of A13 and A14. If both A13 and A14 are 1, A15 outputs 1; otherwise, it outputs 0. A16 is an RS flip-flop. When S=1, the output is 1; when R=1, the output is 0. In other states, the flip-flop maintains its current state. When the result of A15 is 1, the output of A16 is 1; when the result of A10 is 1, the output of A16 is 0. A17 is a selection switch. When the output of A16 is 1, A17 selects the output of A5; when the output of A16 is 0, A17 selects the output of A3. A18 performs a bitwise AND operation, calculating the bitwise AND of the output of A17 with 16383. This ensures that each bit is ANDed before outputting the result, limiting the result to the range of 0 to 16383.

[0038] Step 2: In the FPGA of the phase-locked loop controller, perform difference calculation on the electrical angle of the upper and lower voltages calculated by the phase-locked loop, and process and adjust the difference to a stable value.

[0039] As shown in Figure 4, assuming that the electrical angle of each power grid cycle is sampled and calculated 8 times, the actual number of samplings is related to the DSP operation cycle. FIPU corresponds to curve 1, FIPD to curve 2, the difference between FIPU and FIPD to curve 3, and the processed difference to curve 4. As can be seen from curve 3, the difference between FIPU and FIPD fluctuates between positive and negative values. This is mainly due to the abrupt change in value when the sawtooth wave changes from its maximum value to 0, requiring special handling. By determining the maximum and minimum values ​​of FIPU and FIPD, the location of the abrupt change is identified. When the difference becomes negative, 100% (i.e., 16383) is added to the difference, thus making the output difference at that location positive.

[0040] At time t1, the previous cycle value A12 of FIPD is greater than the maximum value threshold K1 and the current cycle value A11 is less than the minimum value threshold K2. At this time, the electrical angle of FIPD changes abruptly, and A13 and A14 output 1 at the same time. Then, the output of the arithmetic unit A15 is 1, and the corresponding RS flip-flop A16 outputs 1. A17 selects the output result of A5, which represents the difference between FIPU and FIPD, which is 2 / 8 at this time.

[0041] During the time intervals t1 to t2, RS flip-flop A16 maintains an output of 1, and A17 continuously outputs the result of A5, that is, it always maintains the value of 2 / 8.

[0042] At time t2, the FIPU's previous cycle value A8 is greater than the maximum value threshold K1, and its current cycle value A6 is less than the minimum value threshold K2. At this point, the FIPU's electrical angle changes abruptly, and A8 and A9 simultaneously output 1. Therefore, the AND operator A10 outputs 1, and the corresponding RS flip-flop A16 outputs 0. A17 selects the output result of A5, which represents adding 100% to the difference between FIPU and FIPD. Thus, the output result of selector A17 is: 100% + (-6 / 8) = 2 / 8.

[0043] During the time intervals t2 to t3, RS flip-flop A16 maintains an output of 0, while A17 continuously outputs the result of A3, i.e., it always maintains a value of 2 / 8.

[0044] After time t3, the next loop begins, and the same logic is followed each time. Ultimately, the difference between FIPU and FIPD can be guaranteed to remain at a stable value without any data mutations, thus providing reliable data for subsequent processing.

[0045] Step 3: Using an intelligent real-time approximation algorithm, the electrical angle difference is processed and converted into an angular frequency adjustment value. When the off-grid controller receives the synchronization start command from the host computer, it sends the angular frequency adjustment value to the fiber optic receiving port of the energy storage converter through the fiber optic output port.

[0046] As shown in Figure 5, K3 is the frequency difference adjustment rate, K4 is the frequency difference compensation value, K5 is the frequency difference limiting value, EN is the synchronization function enable signal, UDF is the difference between the processed FIPU and FIPD, and DK is the angular frequency adjustment value output to the energy storage converter. In the figure, A19 is a subtraction operator that subtracts 100% from the value of UDF; A20 is a comparator that compares the value of UDF with 50%; when UDF is greater than or equal to 50%, A20 outputs 1, otherwise it outputs 0; A21 is a selector; when A20 outputs 1, A21 selects the result of the operation of A19; when A20 outputs 0, it selects the value of UDF for output; A22 is a multiplication operator that multiplies the result of A21 with K3 and outputs the result; A23 is an addition operator that multiplies the result of A21 by K3 and outputs the result. The result of A22 is added to K4 and then output; A24 is a limiter that limits the output of A23. When the result of A23 is greater than K5, A24 outputs K5; when the result of A23 is less than -K5, A24 outputs the value of -K5; when the result of A23 is between -K5 and K5, A24 outputs the value of A23; A25 is a selection switch. When EN=1, A25 outputs the value of A24 and sends it to DK; when EN=0, A25 outputs the value of 0.

[0047] This function primarily uses the principle of real-time approximation. Based on the voltage and electrical angle difference between the upper and lower terminals of the grid-connected switch, it calculates the electrical angle adjustment value required for each adjustment by the energy storage system, considering factors such as adjustment direction judgment, adjustment speed, and adjustment amplitude limiting. The value of K3 affects the synchronization speed; a larger K3 value results in faster synchronization. By appropriately setting the value of k3, synchronization can be completed within 1 second. A19 to A21 are used to determine the direction of the energy storage system's electrical angle adjustment. When UDF is greater than or equal to 50%, it indicates a longer forward adjustment time compared to reverse adjustment, requiring reverse adjustment. This is achieved by subtracting 100% from UDF using the A19 subtractor, resulting in a negative output value. The adjustment direction is the energy storage system minus the corresponding adjustment value. When the UDF difference is less than 50%, it indicates a shorter forward adjustment time. No processing is performed on the UDF, resulting in a positive output value. The adjustment direction is the energy storage system plus the corresponding adjustment value. A22 is multiplied by K3 to control the adjustment speed each time; the smaller the value of K3, the slower the adjustment, and vice versa. A24 uses K5 to limit the amplitude to prevent excessive adjustment from causing drastic adjustments in the energy storage system and leading to system instability. A25 controls the enabling and disabling of this function. When EN=1, this function is enabled, and the energy storage system performs synchronous adjustment; when EN=0, this function is disabled, and the energy storage system does not respond to the adjustment.

[0048] Step 4: The energy storage converter receives the angular frequency adjustment value through the fiber optic receiving port and sends it to the virtual synchronous machine control to adjust the output voltage frequency and phase of the energy storage converter.

[0049] After receiving the phase angle adjustment value sent by the grid-connected controller via optical fiber, the grid-connected energy storage converter sends it as the angular frequency adjustment value to the virtual synchronous machine module to generate the electrical angle of the energy storage converter, thereby adjusting the output voltage frequency and phase angle of the energy storage converter. Figure 6 shows the logic block diagram of the energy storage converter generating the electrical angle, where P... R P is the given value for active power. E The actual operating active power is represented by J, the virtual synchronous machine inertia coefficient, D, the virtual synchronous machine damping coefficient, KA, the received angular frequency adjustment value, 50TA, and 50 times the DSP operation cycle. FIP_VSG represents the electrical angle output by the energy storage converter. A26 is a subtraction operator that subtracts PR and PE to calculate the power difference; A27 is a subtraction operator that subtracts the result of A26 from the result of A29; A28 is a multiplication operator that multiplies the result of A27 with J; A29 is a multiplication operator that multiplies the output result of A30 with D; A30 is an addition operator that adds the result of A28 to the output result of A31; A31 indicates that the result of A5 is delayed by one DSP operation cycle, which is the previous DSP operation cycle of A30. The data for the DSP cycle; A32 is an adder that adds the result of A30 to KA; A33 is an adder that adds 100% to the result of A32; A34 is a multiplier that multiplies the result of A33 by 50 times TA; A35 is an adder that adds the result of A34 to the result of A36; A36 is a bitwise AND operator that performs a bitwise AND operation on the result of A35 with 16383, limiting the electrical angle to 0 to 16383.

[0050] In Figure 6, A26 to A31 are the motion equations of the virtual synchronizer, mainly used for calculating the relationship between active power and frequency. The specific formulas are as follows:

[0051] In the formula, ω is the angular frequency of the output voltage, and Δω is the difference in angular frequency of the output voltage.

[0052] A26, A27, and A29 represent P R -P E -D·Δω, A28, A30 and A31 represent The output of A30 is Δω. A32 indicates that the received angular frequency adjustment value is added to the virtual synchronous machine to adjust the frequency of the grid-type energy storage converter. A33 indicates that the current real-time angular frequency is calculated by adding the voltage-rated angular frequency (per-unit corresponding to 100%, i.e., 50x2π corresponds to 100%) to the angular frequency difference. A34 to A36 indicate that the electrical angle required for the operation of the grid-type energy storage converter is calculated by integrating the angular frequency. Among them, A36 is used to return the electrical angle to zero by bitwise AND operation when the electrical angle is integrated to 16383. The final FIP_VSG is a sawtooth wave with an amplitude of 0 to 16383 and a period of the output voltage period.

[0053] Step 5: When the phase angle difference between the upper and lower voltages of the grid-connected switch is less than 2°, the grid-connected controller sends a synchronization completion signal, and the host computer closes the grid-connected switch by control.

[0054] The grid-connected converter utilizes the generated electrical angle to generate a three-phase AC voltage modulation signal through voltage and current loop calculations. This signal is then used by the IGBT module to generate a PWM waveform, which is finally output as a three-phase AC voltage after passing through an LCL filter. The phase angle and frequency of this voltage change with the electrical angle, and the corresponding electrical angle FIPD of the grid-connected switch's lower voltage will change accordingly. The difference between FIPU and FIPD in the grid-connected control is adjusted accordingly. When the voltage period corresponding to FIPD increases or decreases, the difference between FIPU and FIPD decreases, and the absolute value of DK calculated in Figure 5 decreases. After several cycles of this operation, when the absolute value of DK approaches 0, FIPU and FIPD become essentially identical. This ensures that the phase angle of the voltages at the upper and lower terminals of the grid-connected switch is less than 2°, meeting the grid connection conditions and achieving synchronous operation. When the frequency of the voltage at the upper terminal of the grid-connected switch fluctuates, the above adjustments can also be used to quickly track changes and achieve real-time tracking. When the phase angle of the voltage at the upper and lower ports of the grid-connected switch is always less than 2°, the grid-connected controller will send a synchronization completion signal to the host computer. Upon receiving this signal, the host computer can control the closing of the grid-connected switch.

[0055] It should be emphasized that the embodiments described in this invention are illustrative rather than limiting. Therefore, this invention includes, but is not limited to, the embodiments described in the specific implementation. Any other implementations derived by those skilled in the art based on the technical solutions of this invention are also within the scope of protection of this invention.

Claims

1. A method for simultaneous grid connection of a grid-type energy storage system, characterized in that: The method comprises the following steps: Step 1, the off-grid controller collects the three-phase voltage of the upper and lower ports of the grid-connected switch, and calculates the electrical angle of the three-phase voltage of the upper and lower ports through two phase-locked loops of the DSP respectively; Step 2, the FPGA in the off-grid controller carries out difference operation on the electrical angle of the upper and lower port voltage calculated by the phase-locked loop, and processes and adjusts the difference value to a stable value; Step 3, using an intelligent real-time approximation algorithm, the electrical angle difference is processed into an angular frequency adjustment value, and when the off-grid controller receives the synchronization start command from the upper computer, the angular frequency adjustment value is sent to the fiber receiving port of the energy storage converter through the fiber output port; Step 4, the energy storage converter receives the angular frequency adjustment value through the fiber receiving port and inputs it into the virtual synchronous machine control, and adjusts the frequency and phase of the output voltage of the energy storage converter; Step 5, when the phase angle difference of the upper and lower port voltage of the grid-connected switch is less than 2°, the off-grid controller sends a synchronization completion signal, and the upper computer controls the closing of the grid-connected switch. 2.The method of claim 1, wherein: The specific implementation method of step 1 is that the upper port voltage electrical angle FIPU and the lower port voltage electrical angle FIPD are input into a subtraction operator A1 to obtain an electrical angle difference, the electrical angle difference and 16383 are input into an addition operator A2 to perform an addition operation of 16383 on the electrical angle difference, the result of the addition operator A2 is input into a delay operator A3 to delay for one FPGA clock cycle of 25ns, and the electrical angle difference and 0 are input into an addition operator A4 to perform an addition operation of 0 on the electrical angle difference obtained by the subtraction operator A1, so as to keep the clock aligned, and the result of the addition operator A4 is input into a delay operator A5 to delay for one FPGA clock cycle of 25ns; The upper port voltage electrical angle FIPU and 0 are input into an addition operator A6 with an enable function to perform an addition operation of 0 on the upper port voltage electrical angle, the result of the addition operator A6 and 0 are input into an addition operator A7 with an enable function to perform an addition operation of 0 on the result of the addition operator A6, the result of the addition operator A7 and K1 are input into a comparison operator A8 to compare the result of the addition operator A7 with K1, when the output of the addition operator A7 is greater than K1, the output of A8 is 1, the result of the addition operator A7 and K2 are input into a comparison operator A9 to compare the result of the addition operator A7 with K2, when the output of the addition operator A7 is less than K2, the output of the comparison operator A9 is 1, and the results of the comparison operator A8 and the comparison operator A9 are input into an AND logic operator A10 to perform an AND operation on the results of the comparison operator A8 and the comparison operator A9, when the results of the comparison operator A8 and the comparison operator A9 are both 1, the output of the AND logic operator A10 is 1, and the output is 0 in other cases. The lower voltage electrical angle FIPD and 0 are input to the adder A11 with enable function, the lower voltage electrical angle is added by 0, the result of the adder A11 and 0 are input to the adder A12 with enable function, the result of the adder A11 is added by 0, the result of the adder A12 and K1 are input to the comparator A13, the result of the adder A12 and K1 are compared, when the result of the adder A12 is greater than K1, the A13 outputs 1, the result of the adder A12 and K2 are input to the comparator A13, the result of the adder A12 and K2 are compared, when the result of the adder A12 is less than K2, the comparator A13 outputs 1, the results of the comparator A13 and the comparator A14 are input to the AND logic operator A15, the results of the comparator A13 and the comparator A14 are ANDed, when the results of the comparator A13 and the comparator A14 are both 1, the AND logic operator A15 outputs 1, otherwise, the AND logic operator A15 outputs 0; The results of the AND logic operator A10 and the AND logic operator A15 are input to the RS flip-flop A16, when S=1, the output is 1, when R=1, the output is 0, in other states, the flip-flop keeps the current state, when the result of the AND logic operator A15 is 1, the RS flip-flop A16 outputs 1, when the result of the AND logic operator A10 is 1, the RS flip-flop A16 outputs 0; The results of the delay operator A3, the delay operator A5 and the RS flip-flop A16 are input to the selection switch A17, when the RS flip-flop A16 outputs 1, the selection switch A17 selects the output result of the delay operator A5, when the RS flip-flop A16 outputs 0, the selection switch A17 selects the output result of the delay operator A3; the result of the selection switch A17 and 16383 are input to the AND operator A18, the output result of the selection switch A17 and 16383 are ANDed. 3.The method of claim 1, wherein: The specific implementation method of step 3 is as follows: the difference UDF between the processed FIPU and FIPD is input into subtracter A19 with 100%, and the difference UDF between the processed FIPU and FIPD is subtracted by 100%; the difference UDF between the processed FIPU and FIPD is input into comparator A20 with 50%, and the value of UDF is compared with 50%; when UDF is greater than or equal to 50%, comparator A20 outputs 1, otherwise 0; the difference UDF between the processed FIPU and FIPD, the result of subtracter A19 and comparator A20 are input into selector A21; when the output of comparator A20 is 1, selector A21 selects the result of subtracter A19; when the output of comparator A20 is 0, the value of UDF is selected and output; the result of selector A21 and K3 are input into multiplier A22, and the result of selector A21 is multiplied by K3 and output; the result of multiplier A22 and K4 are input into adder A23, and the result of multiplier A22 is added by K4 and output; the result of adder A23, -K5 and K5 are input into limiter A24, and the output of adder A23 is limited; when the result of adder A23 is greater than K5, limiter A24 outputs K5; when the result of adder A23 is less than -K5, limiter A24 outputs -K5; when the result of adder A23 is between -K5 and K5, limiter A24 outputs the value of A23; the result of limiter A24 and 0 are input into selection switch A25; when EN=1, selection switch A25 outputs the result of limiter A24 to DK; when EN=0, the output of selection switch A25 is 0.

4. The method of claim 1, wherein the method further comprises: The specific implementation method of step 4 is: the active power given value PR and the actual running active power PE are input to the subtraction operator A26, the active power given value PR and the actual running active power PE are subtracted to calculate the power difference, the results of the subtraction operator A26 and the multiplication operator A29 are input to the subtraction operator A27, the results of the subtraction operator A26 and the multiplication operator A29 are subtracted, the results of the subtraction operator A27 and J are input to the multiplication operator A28, the results of the subtraction operator A27 and J are multiplied, the addition operator A30 and D are input to the multiplication operator A29, the output results of the addition operator A30 and D are multiplied, the results of the multiplication operator A28 and the delay operator A31 are input to the addition operator A30, the results of the multiplication operator A30 and the output results of the delay operator A31 are added, the results of the addition operator A30 are input to the delay operator A31, the results of the addition operator A31 are delayed for one DSP operation period, the results of the addition operator A30 and KA are input to the addition operator A32, the results of the addition operator A30 and KA are added; the results of the addition operator A32 and 100% are input to the addition operator A33, the results of the addition operator A32 are added by 100%, the results of the addition operator A33 and 50 times TA are input to the multiplication operator A34, the results of the addition operator A34 are multiplied by 50 times TA, the results of the multiplication operator A34 and the results of the bitwise AND operator A36 are input to the addition operator A35, the results of the multiplication operator A34 and the results of the bitwise AND operator A36 are added; the results of the addition operator A35 and 16383 are input to the bitwise AND operator A36, the results of the addition operator A35 and 16383 are ANDed according to each bit, and the electrical angle is limited to 0-16383.

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