Array substrate and display apparatus

Abstract

An array substrate and a display apparatus. The array substrate comprises a base substrate and a first transistor, wherein the first transistor is disposed on one side of the base substrate, and the first transistor comprises a first active layer. The first active layer comprises a first conductor portion, a first channel portion and a second conductor portion, which are connected in sequence, wherein the first channel portion comprises at least a part of at least one first crystal grain, and at least one of the first conductor portion and the second conductor portion comprises a grain boundary. The mobility of the first channel portion of the array substrate is relatively high, so that the first transistor has a relatively high mobility and lower power consumption, which meets the requirements of micro-LED display technology.

Description

Array substrate and display device

[0001] Cross-references

[0002] This disclosure claims priority to Chinese Patent Application No. 202510059802.8, filed on January 14, 2025, entitled "Array Substrate and Display Device", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and more specifically, to an array substrate and a display device. Background Technology

[0004] Low-temperature poly-silicon (LTPS) materials have a high mobility of 50 cm⁻¹ 2 / V·s~100cm 2 / V·s is beneficial for the miniaturization of thin film transistors (TFTs), thereby improving the resolution, aperture ratio, and clarity of display devices.

[0005] With the development of the display industry, Micro-LED (Micro-Light Emitting Diode) display technology, with its unique advantages and broad application prospects, is gradually becoming an important development direction in the field of display technology. However, Micro-LED display technology requires a larger driving current, posing challenges to thin-film transistors in terms of higher mobility and lower power consumption. Currently, thin-film transistors in array substrates are difficult to meet these requirements.

[0006] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0007] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide an array substrate and a display device.

[0008] According to one aspect of this disclosure, an array substrate is provided, comprising:

[0009] Substrate;

[0010] A first transistor is disposed on one side of the substrate. The first transistor includes a first active layer. The first active layer includes a first conductor portion, a first channel portion, and a second conductor portion connected in sequence. The first channel portion includes at least a portion of at least one first grain. At least one of the first conductor portion and the second conductor portion includes a grain boundary.

[0011] In one exemplary embodiment of this disclosure, the first conductor portion, the first channel portion, and the second conductor portion are sequentially connected along a first direction, wherein the first channel portion does not include a grain boundary extending along a second direction, and the second direction intersects the first direction.

[0012] In one exemplary embodiment of this disclosure, the first channel portion includes a channel grain boundary that extends along the first direction.

[0013] In one exemplary embodiment of this disclosure, the first conductor portion includes a grain boundary extending along the first direction, and the second conductor portion includes a grain boundary extending along the first direction; the length of the first channel portion in the second direction is greater than the distance between two adjacent channel grain boundaries in the second direction.

[0014] In one exemplary embodiment of this disclosure, the first conductor portion includes a grain boundary, and the second conductor portion includes a grain boundary.

[0015] In one exemplary embodiment of this disclosure, the grain boundary extends along the second direction, and the length of the first channel portion in the first direction is less than the distance between two adjacent grain boundaries in the first direction.

[0016] In one exemplary embodiment of this disclosure, the size of the first grain is greater than or equal to 1 micrometer and less than or equal to 10 micrometers, and / or the spacing between two adjacent and oppositely disposed grain boundaries is greater than or equal to 1 micrometer and less than or equal to 10 micrometers.

[0017] In one exemplary embodiment of this disclosure, the grain boundaries form a closed pattern, and the first channel portion is disposed within the closed pattern; the first conductor portion includes one grain boundary, or the first conductor portion includes at least two interconnected grain boundaries; the second conductor portion includes one grain boundary, or the second conductor portion includes at least two interconnected grain boundaries.

[0018] In one exemplary embodiment of this disclosure, the grain boundaries form a closed pattern; the second conductor portion is configured as an annular or arc-shaped portion, the first channel portion is configured as an annular or arc-shaped portion, the first channel portion surrounds the periphery of the first conductor portion, the second conductor portion surrounds the periphery of the first channel portion, and the edge line of the second conductor portion near the first channel portion is located within the closed pattern.

[0019] In one exemplary embodiment of this disclosure, the second conductor portion includes a grain boundary, and the first conductor portion includes a poorly crystallized portion.

[0020] In one exemplary embodiment of this disclosure, the array substrate further includes:

[0021] A crystallization guiding layer is disposed on the side of the first active layer close to the substrate, or on the side of the first active layer away from the substrate, wherein the orthographic projection of the crystallization guiding layer on the substrate does not overlap with the orthographic projection of the first channel portion on the substrate.

[0022] In one exemplary embodiment of this disclosure, the crystal guiding layer is configured as a dot, and the orthographic projection of the crystal guiding layer on the substrate overlaps with the orthographic projection of the first conductor portion on the substrate; or, the crystal guiding layer is provided with a plurality of hollow portions, and the orthographic projection of the crystal guiding layer on the substrate overlaps with the orthographic projection of the second conductor portion on the substrate.

[0023] In one exemplary embodiment of this disclosure, the array substrate further includes:

[0024] A first gate insulating layer is disposed on the side of the first active layer away from the substrate.

[0025] A first gate layer is disposed on the side of the first gate insulating layer opposite to the substrate. The first gate layer includes a first gate, and the orthographic projection of the first channel portion on the substrate is located within the orthographic projection of the first gate on the substrate.

[0026] The first interlayer dielectric layer is disposed on the side of the first gate layer away from the substrate.

[0027] A first connecting conductor layer is disposed on the side of the first interlayer dielectric layer away from the substrate. The first connecting conductor layer includes a first connecting portion and a second connecting portion, wherein the first connecting portion is connected to the first conductor portion and the second connecting portion is connected to the second conductor portion.

[0028] In one exemplary embodiment of this disclosure, the first connecting portion is configured with the same shape as the first conductor portion, and the orthographic projection of the first connecting portion on the substrate at least partially overlaps with the orthographic projection of the first conductor portion on the substrate; and / or, the second connecting portion is configured with a shape adapted to the second conductor portion, and the orthographic projection of the second connecting portion on the substrate at least partially overlaps with the orthographic projection of the second conductor portion on the substrate.

[0029] In an exemplary embodiment of this disclosure, the orthographic projection of the first connecting portion on the substrate overlaps with the orthographic projection of the grain boundary included in the first conductor portion on the substrate, and the orthographic projection of the second connecting portion on the substrate overlaps with the orthographic projection of the grain boundary included in the second conductor portion on the substrate.

[0030] In an exemplary embodiment of this disclosure, a first sub-via and a second sub-via are provided on the first gate insulating layer, and a third sub-via and a fourth sub-via are provided on the first interlayer dielectric layer. The third sub-via is connected to the first sub-via to form a first via, and the fourth sub-via is connected to the second sub-via to form a second via. The first connecting portion is connected to the first conductor portion through the first via, and the second connecting portion is connected to the second conductor portion through the second via.

[0031] In a first direction, the distance between the portion of the first connection located within the first via and the portion of the second connection located within the second via is less than the distance between two adjacent grain boundaries.

[0032] In one exemplary embodiment of this disclosure, the first connecting portion is connected to the grain boundary of the first conductor portion, or the first connecting portion is connected to a poorly crystallized portion of the first conductor portion;

[0033] And / or, the second connection portion is connected to the grain boundary of the second conductor portion.

[0034] In one exemplary embodiment of this disclosure, the first grain is configured as rectangular, regular hexagonal, or circular.

[0035] In one exemplary embodiment of this disclosure, the array substrate further includes:

[0036] A second transistor is disposed on one side of the substrate. The second transistor includes a second active layer. The second active layer includes a third conductor portion, a second channel portion, and a fourth conductor portion connected in sequence. The second channel portion includes a second grain. The size of the first grain is larger than the size of the second grain.

[0037] In one exemplary embodiment of this disclosure, the array substrate further includes:

[0038] The CMOS structure includes a first transistor and a second transistor, wherein the first transistor is a P-type transistor and the second transistor is an N-type transistor.

[0039] In an exemplary embodiment of this disclosure, the first gate insulating layer is disposed on the side of the first active layer and the second active layer away from the substrate, the first gate layer further includes a second gate, and the orthographic projection of the second channel portion on the substrate is located within the orthographic projection of the second gate on the substrate.

[0040] Alternatively, the first active layer is disposed on the side of the second active layer away from the substrate, and the orthographic projection of the second transistor on the substrate overlaps with the orthographic projection of the first transistor on the substrate.

[0041] Alternatively, the second active layer is disposed on the side of the first active layer away from the substrate, and the orthographic projection of the second transistor on the substrate overlaps with the orthographic projection of the first transistor on the substrate.

[0042] The first connecting conductor layer further includes a sixth connecting portion and a seventh connecting portion, wherein the sixth connecting portion is connected to the third conductor portion and the seventh connecting portion is connected to the fourth conductor portion.

[0043] In one exemplary embodiment of this disclosure, the first transistor includes two first gates disposed on opposite sides of the first channel portion along a third direction; and / or, the second transistor includes two second gates disposed on opposite sides of the second channel portion along a third direction; the third direction is perpendicular to the substrate.

[0044] In one exemplary embodiment of this disclosure, the first active layer and the second active layer are spaced apart, or the first active layer is connected to the second active layer.

[0045] In one exemplary embodiment of this disclosure, the array substrate further includes:

[0046] The third transistor is an oxide transistor, and its orthogonal projection on the substrate overlaps with the CMOS structure, or its orthogonal projection on the substrate does not overlap with the CMOS structure.

[0047] According to another aspect of this disclosure, a display device is provided, comprising: an array substrate as described in any one of the preceding claims.

[0048] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0049] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0050] Figure 1 is a schematic diagram of the structure of a first example embodiment of the array substrate disclosed herein.

[0051] Figure 2 is a schematic diagram of the structure of a second exemplary embodiment of the array substrate disclosed herein.

[0052] Figure 3 is a schematic diagram of the structure of a third exemplary embodiment of the array substrate disclosed herein.

[0053] Figure 4 is a schematic diagram of the structure of a fourth exemplary embodiment of the array substrate disclosed herein.

[0054] Figure 5 is a schematic diagram of the structure of the first example implementation of the active layer in Figure 2.

[0055] Figure 6 is a schematic diagram of the structure of the second example implementation of the active layer in Figure 2.

[0056] Figure 7 is a schematic diagram of the third example implementation of the active layer in Figure 2.

[0057] Figure 8 is a schematic diagram of the fourth example implementation of the active layer in Figure 2.

[0058] Figure 9 is a schematic diagram of the structure of the fifth exemplary embodiment of the active layer in the array substrate of this disclosure.

[0059] Figure 10 is a schematic diagram of the structure of the first example implementation of the active layer in Figures 3 and 4.

[0060] Figure 11 is a schematic diagram of the structure of the second example implementation of the active layer in Figures 3 and 4.

[0061] Figure 12 is a schematic diagram of the third example implementation of the active layer in Figures 3 and 4.

[0062] Figure 13 is a schematic diagram of the structure after an amorphous silicon film layer is formed on the buffer layer 2.

[0063] Figure 14 is a schematic diagram of the structure after the mask plate is set in Figure 13.

[0064] Figure 15 is a schematic diagram of the structure in Figure 13 where the amorphous silicon film is formed as an active material layer.

[0065] Figure 16 is a schematic diagram of the mask plate in Figure 14.

[0066] Figure 17 is a schematic diagram of the growth of the first grain in the amorphous silicon film layer 3a in Figure 14.

[0067] Figure 18 is a schematic diagram of another example embodiment of the crystallization guiding layer.

[0068] Figures 19-21 are schematic diagrams of the various steps in forming the array substrate in Figure 3.

[0069] Figures 22-25 are schematic diagrams of the various steps in forming the array substrate in Figure 4.

[0070] Figures 26 and 27 are schematic diagrams of the remaining steps in forming the array substrate in Figure 1.

[0071] Figures 28-30 are schematic diagrams of the various steps in forming the array substrate in Figure 31.

[0072] Figure 31 is a schematic diagram of the structure of a fifth exemplary embodiment of the array substrate of this disclosure.

[0073] Figure 32 is a schematic diagram of the structure of a sixth exemplary embodiment of the array substrate disclosed herein.

[0074] Figure 33 is a schematic diagram of the structure after forming the gate layer and the first connecting conductor layer based on Figure 10.

[0075] Figure 34 is a structural schematic diagram of a seventh exemplary embodiment of the array substrate disclosed herein.

[0076] Figure 35 is a schematic diagram of the circuit principle of CMOS structure as an inverter.

[0077] Figure 36 is a top view of the CMOS structure in the array substrate of this disclosure.

[0078] Figure 37 is a schematic diagram of the structure in which the first polysilicon layer and the second polysilicon layer are formed based on Figure 13.

[0079] Figure 38 is a cross-sectional view of Figure 37.

[0080] Figure 39 is a schematic diagram of the structure after patterning based on Figure 37.

[0081] Figure 40 is a cross-sectional view of Figure 39.

[0082] Figure 41 is a schematic diagram of the structure in which the first gate layer is formed based on Figure 39.

[0083] Figure 42 is a cross-sectional view of Figure 41.

[0084] Figure 43 is a schematic diagram of the structure in which the first interlayer dielectric layer is formed based on Figure 41.

[0085] Figure 44 is a cross-sectional view of Figure 43.

[0086] Figure 45 is a schematic diagram of the structure in which the first connecting conductor layer is formed based on Figure 41.

[0087] Figure 46 is a schematic diagram of the structure of the eighth exemplary embodiment of the array substrate of this disclosure.

[0088] Figure 47 is a structural schematic diagram of the ninth exemplary embodiment of the array substrate of this disclosure.

[0089] Figure 48 is a schematic diagram of the structure of the tenth exemplary embodiment of the array substrate of this disclosure.

[0090] Figure 49 is a schematic diagram comparing the transfer characteristic curves of different transistors.

[0091] Explanation of reference numerals in the attached figures: 1. Substrate; 2. Buffer layer; 3a. Amorphous silicon film; 3a1. Masked area; 3b. Active material layer; 3c. First polysilicon layer; 3d. Second polysilicon layer; 3. First active layer; 31. First conductor portion; 32. First channel portion; 321. Channel grain boundary; 33. Second conductor portion; 34. First grain; 35. Grain boundary; 36. Poor crystallization portion; 3e. Second active layer; 3e1. Third conductor portion; 3e2. Second channel portion; 3e21. Second grain; 3e3. Fourth conductor portion; 3f. Third active layer; 4. Crystallization guiding layer; 41. Clear cutout portion; 5. First gate insulating layer; 51. First sub-via; 52. Second sub-via; 53. Fifth sub-via; 54. Sixth sub-via; 5e. Second gate insulating layer; 5f. Third gate insulating layer; 6. First gate layer; 61. First gate; 62. Second gate; 6e. Second gate layer; 6f. Third gate layer; 6f1. Third gate; 7. First interlayer dielectric layer; 71. Third sub-via; 72. Fourth sub-via; 73. Seventh sub-via; 74. Eighth sub-via; 7a. First via; 7b. Second via; 7e. Second interlayer dielectric layer; 7f. Third interlayer dielectric layer; 8. First connecting conductor layer; 81. First connection portion; 82. Second connection portion; 83. Fifth connection portion; 84. Sixth connection portion; 85. Seventh connection portion; 86. Eighth connection portion; 87. Ninth connection portion; 9. Planarization layer; 10. First protective layer; 11. Second connecting conductor layer; 111. Third connection portion; 112. Fourth connection portion; 12. Second protective layer; 13. Photomask; 131. Light-shielding part; 132. Light-transmitting part; 14. Photoresist; T1. First transistor; T2. Second transistor; T3. Third transistor; X. First direction; Y. Second direction. Detailed Implementation

[0092] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0093] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0094] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0095] In this application, unless otherwise expressly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. "And / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Furthermore, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0096] Polycrystalline silicon, a silicon-based material, is composed of numerous tightly bonded silicon particles. In the semiconductor manufacturing industry, polycrystalline silicon is typically processed using LPCVD (Low Pressure Chemical Vapor Deposition), followed by an annealing process at temperatures exceeding 900 degrees Celsius, a method known as SPC (Solid Phase Crystallization). However, this manufacturing method is not suitable for flat panel displays because glass's temperature tolerance limit is only 650 degrees Celsius. Therefore, low-temperature polycrystalline silicon technology was specifically developed to meet the manufacturing requirements of flat panel displays.

[0097] This disclosure provides an array substrate, as shown in Figures 1-48. The array substrate may include a substrate 1 and a first transistor T1. The first transistor T1 is disposed on one side of the substrate 1. The first transistor T1 may include a first active layer 3. The first active layer 3 may include a first conductor portion 31, a first channel portion 32 and a second conductor portion 33 connected in sequence. The first channel portion 32 includes at least a portion of at least one first grain 34. At least one of the first conductor portion 31 and the second conductor portion 33 includes a grain boundary 35.

[0098] The array substrate disclosed herein, on the one hand, when the first transistor T1 is small, the first channel portion 32 may include a portion of a first die 34, or the first channel portion 32 may include the entire first die 34, so that the first channel portion 32 does not include grain boundaries 35, thereby resulting in a higher mobility of the first channel portion 32, and consequently a higher mobility and lower power consumption of the first transistor T1, meeting the requirements of Micro-LED display technology; when the first transistor T1 is large, the first channel portion 32 may also include a portion of two or more first dies 34, or the first channel portion 32 may include the entirety of two or more first dies 34, resulting in a smaller number of first dies 34 included in the first channel portion 32, which also results in a higher mobility of the first channel portion 32, and consequently a higher mobility and lower power consumption of the first transistor T1, meeting the requirements of Micro-LED display technology. On the other hand, the grain boundaries 35 do not affect the conductivity of the conductor portion; at least one of the first conductor portion 31 and the second conductor portion 33 includes grain boundaries 35, which does not affect the mobility and conductivity of the first transistor T1. On the other hand, the size of the first die 34 is limited. By effectively utilizing the limited size of the first die 34, the mobility of the first channel portion 32 can be guaranteed to be high under limited conditions, thereby ensuring that the mobility of the first transistor T1 is high and the power consumption is low, which meets the requirements of Micro-LED display technology.

[0099] In this exemplary embodiment, the material of the substrate 1 may include inorganic materials, such as glass, quartz, or metal. The material of the substrate 1 may also include organic materials, such as resins like polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate. The substrate 1 may be formed from multiple material layers; for example, the substrate 1 may include multiple substrate layers, and the substrate layers may be made of any of the materials described above. Of course, the substrate 1 may also be a single layer, and may be any of the materials described above.

[0100] Referring to Figures 1-4, a buffer layer 2 is disposed on one side of the substrate 1. The buffer layer 2 serves to block water vapor and impurity ions in the substrate 1 (especially organic materials) and to increase hydrogen ions for the subsequently formed first active layer 3. The buffer layer 2 can be a single-layer structure made of SiOx (silicon oxide); or it can be a double-layer structure, for example, the buffer layer 2 may include a first film layer and a second film layer. The first film layer is made of SiNx (silicon nitride), and its thickness is greater than or equal to 50 angstroms and less than or equal to 5000 angstroms. For example, the thickness of the first film layer can be 100 angstroms, 250 angstroms, 500 angstroms, 750 angstroms, 1000 angstroms, 1500 angstroms, 2000 angstroms, 2500 angstroms, 3000 angstroms, 3500 angstroms, 4000 angstroms, 4500 angstroms, etc. The material of the second film layer is SiOx (silicon oxide), and the thickness of the second film layer is greater than or equal to 800 angstroms and less than or equal to 10,000 angstroms. For example, the thickness of the second film layer can be 1,000 angstroms, 1,500 angstroms, 2,000 angstroms, 2,500 angstroms, 3,000 angstroms, 3,500 angstroms, 4,000 angstroms, 4,500 angstroms, 5,000 angstroms, 5,500 angstroms, 6,000 angstroms, 6,500 angstroms, 7,000 angstroms, 7,500 angstroms, 8,000 angstroms, 8,500 angstroms, 9,000 angstroms, 9,500 angstroms, etc.

[0101] Of course, in some other example embodiments of this disclosure, the thickness of the first film layer (SiNx) may also be greater than or equal to 100 angstroms and less than or equal to 1500 angstroms.

[0102] A first active layer 3 is provided on one side of the substrate 1. Specifically, the first active layer 3 is provided on the side of the buffer layer 2 away from the substrate 1. The first active layer 3 may include a first conductor portion 31, a first channel portion 32, and a second conductor portion 33 connected in sequence. The first channel portion 32 may include at least a portion of at least one first grain 34. For example, as shown in Figures 2-4, the first channel portion 32 may include a portion of a first grain 34, or the first channel portion 32 may include all of a first grain 34. As shown in Figure 1, the first channel portion 32 may also include portions of two or more first grains 34, or the first channel portion 32 may include all of two or more first grains 34. At least one of the first conductor portion 31 and the second conductor portion 33 includes a grain boundary 35. For example, both the first conductor portion 31 and the second conductor portion 33 may include a grain boundary 35; the first conductor portion 31 may include a grain boundary 35, but the second conductor portion 33 may not include a grain boundary 35; or the second conductor portion 33 may include a grain boundary 35, but the first conductor portion 31 may not include a grain boundary 35.

[0103] Grain boundary 35 is the cause of increased roughness in polycrystalline silicon materials. Grain boundary 35 has prominent protrusions, which can cause undulations and is the main defect for carrier trapping, making it the most important factor affecting mobility. Subgrain boundary 35 does not cause significant undulations and does not have a significant impact on mobility.

[0104] The mobility of the first transistor T1 depends on the mobility of the first channel portion 32. When the first transistor T1 is small, the first channel portion 32 may include a portion of a first die 34, or the first channel portion 32 may include the entire first die 34, so that the first channel portion 32 does not include the grain boundary 35, thereby making the mobility of the first channel portion 32 higher, and thus making the mobility of the first transistor T1 higher and the power consumption lower, meeting the requirements of Micro-LED display technology. When the first transistor T1 is large, the first channel portion 32 may also include a portion of two or more first dies 34, or the first channel portion 32 may also include the entire first dies 34, making the number of first dies 34 included in the first channel portion 32 less, which can also make the mobility of the first channel portion 32 higher, and thus making the mobility of the first transistor T1 higher and the power consumption lower, meeting the requirements of Micro-LED display technology.

[0105] Furthermore, since the grain boundary 35 has no effect on the conductivity of the conductor portion, the inclusion of the grain boundary 35 in at least one of the first conductor portion 31 and the second conductor portion 33 will not affect the mobility and conductivity of the first transistor T1.

[0106] Furthermore, given the limited size of the first die 34, by configuring the first active layer 3 as a first channel portion 32 including at least a portion of at least one of the first die 34, and at least one of the first conductor portion 31 and the second conductor portion 33 including a grain boundary 35, the limited size of the first die 34 can be effectively utilized to create a larger first channel portion 32. Under limited conditions, the mobility of the first channel portion 32 can be guaranteed to be high, thereby ensuring that the first transistor T1 has a high mobility and lower power consumption, meeting the requirements of Micro-LED display technology.

[0107] In some exemplary embodiments of this disclosure, referring to Figures 2-8, the first channel portion 32 may not include the grain boundary 35. For example, when the first transistor T1 is small, the first channel portion 32 may include a portion of a first grain 34, or the first channel portion 32 may include the entire first grain 34, so that the first channel portion 32 does not include the grain boundary 35, thereby making the mobility of the first channel portion 32 higher, and thus making the mobility of the first transistor T1 higher, meeting the requirements of Micro-LED display technology.

[0108] In some exemplary embodiments of this disclosure, referring to FIG2 and FIG5-9, the first conductor portion 31, the first channel portion 32 and the second conductor portion 33 are sequentially connected along the first direction X. The first channel portion 32 does not include the grain boundary 35 extending along the second direction Y. The second direction Y intersects the first direction X. For example, the second direction Y may be perpendicular to the first direction X.

[0109] When the first transistor T1 is turned on, the charge carriers migrate along the connection direction of the first conductor portion 31, the first channel portion 32, and the second conductor portion 33, that is, the charge carriers migrate along the first direction X. Therefore, the grain boundary 35 extending along the second direction Y is the main defect of charge carrier trapping and is the most important factor affecting the mobility. The first channel portion 32 does not include the grain boundary 35 extending along the second direction Y, thereby making the mobility of the first channel portion 32 higher, which in turn makes the mobility of the first transistor T1 higher, meeting the requirements of Micro-LED display technology.

[0110] Specifically, referring to FIG9, the first channel portion 32 may include a channel grain boundary 321, which extends along a first direction X. The first direction X is the connection direction of the first conductor portion 31, the first channel portion 32, and the second conductor portion 33. The channel grain boundary 321 extending along the first direction X has a small or even negligible effect on carrier trapping, and its influence on mobility is negligible or small. Therefore, even though the first channel portion 32 includes a channel grain boundary 321 extending along the first direction X, the mobility of the first channel portion 32 is high, which in turn makes the mobility of the first transistor T1 high, meeting the requirements of Micro-LED display technology.

[0111] It should be noted that the channel grain boundary 321 is also a grain boundary 35. It is called the channel grain boundary 321 in order to distinguish it from the grain boundary 35 in other regions and to avoid misunderstanding.

[0112] The first conductor portion 31 may include a grain boundary 35 extending along the first direction X. For example, the grain boundary 35 of the first conductor portion 31 may be a portion of the channel grain boundary 321 extending to the first conductor portion 31, that is, the grain boundary 35 of the first conductor portion 31 may be connected to the channel grain boundary 321. The second conductor portion 33 may include a grain boundary 35 extending along the first direction X. For example, the grain boundary 35 of the second conductor portion 33 may be a portion of the channel grain boundary 321 extending to the second conductor portion 33, that is, the grain boundary 35 of the second conductor portion 33 may be connected to the channel grain boundary 321.

[0113] The length of the first channel portion 32 in the second direction Y is greater than the distance between two adjacent channel grain boundaries 321 in the second direction Y, so that the first channel portion 32 may include two adjacent channel grain boundaries 321, thereby allowing the length of the first channel portion 32 in the second direction Y to be set to be longer, satisfying the aspect ratio requirement of the first channel portion 32.

[0114] In some example embodiments of this disclosure, the first conductor portion 31 may include a grain boundary 35, and the second conductor portion 33 may include a grain boundary 35.

[0115] Alternatively, as shown in FIG5, the grain boundary 35 may extend along the second direction Y, and the length of the first channel portion 32 in the first direction X may be less than the distance between two adjacent grain boundaries 35 in the first direction X, so that the first channel portion 32 does not include the grain boundary 35, thereby making the mobility of the first channel portion 32 higher, and thus making the mobility of the first transistor T1 higher, meeting the requirements of Micro-LED display technology.

[0116] In this example embodiment, the size of the first die 34 is at the micrometer level. Specifically, the size of the first die 34 is greater than or equal to 1 micrometer and less than or equal to 10 micrometers. For example, the size of the first die 34 can be 1.5 micrometers, 2 micrometers, 2.5 micrometers, 3 micrometers, 3.5 micrometers, 4 micrometers, 4.5 micrometers, 5 micrometers, 5.5 micrometers, 6 micrometers, 6.5 micrometers, 7 micrometers, 7.5 micrometers, 8 micrometers, 8.5 micrometers, 9 micrometers, 9.5 micrometers, etc. This results in a higher carrier mobility in the formed first transistor T1, reducing the power consumption of the array substrate and improving overall performance.

[0117] The spacing between two adjacent and oppositely arranged grain boundaries 35 is greater than or equal to 1 micrometer and less than or equal to 10 micrometers. For example, the spacing between two adjacent and oppositely arranged grain boundaries 35 can be 1.5 micrometers, 2 micrometers, 2.5 micrometers, 3 micrometers, 3.5 micrometers, 4 micrometers, 4.5 micrometers, 5 micrometers, 5.5 micrometers, 6 micrometers, 6.5 micrometers, 7 micrometers, 7.5 micrometers, 8 micrometers, 8.5 micrometers, 9 micrometers, 9.5 micrometers, etc.

[0118] The size of the first grain 34 is relatively large, and the spacing between the two adjacent and opposite grain boundaries 35 is relatively large. When the first transistor T1 is relatively large, as shown in FIG1, the number of the first grain 34 and the grain boundary 35 included in the first channel portion 32 can be reduced, thereby making the mobility of the first channel portion 32 higher, and thus making the mobility of the first transistor T1 higher, which meets the requirements of Micro-LED display technology.

[0119] Referring to FIG5, in some exemplary embodiments of this disclosure, the first active layer 3 may be rectangular, and the first conductor portion 31, the first channel portion 32, and the second conductor portion 33 may also all be rectangular. The first grain 34 is also configured to be approximately rectangular. The first channel portion 32 may be located between two adjacent grain boundaries 35, such that the first channel portion 32 does not include the grain boundary 35, while the first conductor portion 31 and the second conductor portion 33 both include the grain boundary 35.

[0120] Referring to FIG9, in some exemplary embodiments of this disclosure, the first active layer 3 may be rectangular, and the first conductor portion 31, the first channel portion 32, and the second conductor portion 33 may also all be rectangular. The first grains 34 are also configured to be approximately rectangular, and the plurality of first grains 34 are arranged along the second direction Y, that is, the grain boundaries 35 extend along the first direction X. The first channel portion 32 may include a portion of the three first grains 34, and the first channel portion 32 may include two grain boundaries 35 extending along the first direction X.

[0121] Referring to Figures 6-8, in some exemplary embodiments of this disclosure, the grain boundary 35 can form a closed pattern, that is, the grain boundary 35 can form a ring. For example, the grain boundary 35 can form a ring that is approximately hexagonal or circular. Correspondingly, the first grain 34 is configured to have a structure that is approximately hexagonal or circular, such that the size of the first grain 34 in the first direction X is substantially the same as the size in the second direction Y. Since the growth rate of the first grain 34 is not significantly different in each direction, this configuration is more conducive to the formation of the first grain 34 and can form a first grain 34 with excellent performance.

[0122] Of course, in some other exemplary embodiments of this disclosure, the grain boundary 35 may be formed in a ring shape that is generally elliptical, pentagonal, heptagonal and more deformed, and so on. Correspondingly, the first grain 34 is configured to have a structure that is generally elliptical, pentagonal, heptagonal and more deformed, etc., which will not be described in detail here.

[0123] In this case, the first channel portion 32 is enclosed within the grain boundary 35. The first channel portion 32 can be located inside the grain boundary 35 forming a closed pattern, that is, the first channel portion 32 can be located inside the hexagonal or circular first grain 34, so that the first channel portion 32 does not include the grain boundary 35. Both the first conductor portion 31 and the second conductor portion 33 include grain boundaries 35. When the grain boundaries 35 are arranged in a generally hexagonal shape, for example, as shown in FIG7, the first conductor portion 31 may include one grain boundary 35, and the second conductor portion 33 may also include one grain boundary 35; the first conductor portion 31 may include two interconnected grain boundaries 35, and the second conductor portion 33 may also include two interconnected grain boundaries 35; as shown in FIG6, the first conductor portion 31 may include three interconnected grain boundaries 35. Specifically, one end of the three grain boundaries 35 is connected together, and the included angle between any two adjacent grain boundaries 35 is substantially the same, approximately 120°; the second conductor portion 33 may also include three interconnected grain boundaries 35. Specifically, one end of the three grain boundaries 35 is connected together, and the included angle between any two adjacent grain boundaries 35 is substantially the same, approximately 120°.

[0124] In this case, the first active layer 3 can be set as a rectangle, and the first conductor portion 31, the first channel portion 32, and the second conductor portion 33 can also all be set as rectangles. Of course, the first conductor portion 31, the first channel portion 32, and the second conductor portion 33 can also be set as other shapes, which will not be described one by one here.

[0125] Referring to Figure 8, the first conductor portion 31 and the first channel portion 32 are connected in a rectangular shape, and a predetermined angle is provided between the second conductor portion 33 and the first channel portion 32. The first conductor portion 31 may include three interconnected grain boundaries 35. Specifically, one end of the three grain boundaries 35 is connected together, and the included angle between any two adjacent grain boundaries 35 is substantially the same, approximately 120°. The second conductor portion 33 may also include one grain boundary 35. Alternatively, the second conductor portion 33 and the first channel portion 32 may be connected in a rectangular shape, and a predetermined angle is provided between the first conductor portion 31 and the first channel portion 32. The first conductor portion 31 may include one grain boundary 35, and the second conductor portion 33 may also include three interconnected grain boundaries 35. Specifically, one end of the three grain boundaries 35 is connected together, and the included angle between any two adjacent grain boundaries 35 is substantially the same, approximately 120°.

[0126] Referring to Figures 3, 4, 10, and 11, when the grain boundary 35 can form a closed pattern, i.e., when the grain boundary 35 can form a ring, the first channel portion 32 can be configured as a ring, and the second conductor portion 33 can be configured as a ring. For example, the first channel portion 32 can be configured as a circular ring, and correspondingly, the second conductor portion 33 can also be configured as a circular ring, and the first conductor portion 31 can be configured as a circle; the first channel portion 32 can also be configured as a hexagonal ring, and correspondingly, the second conductor portion 33 can also be configured as a hexagonal ring, and the first conductor portion 31 can be configured as a hexagon.

[0127] The first channel portion 32 is disposed around the first conductor portion 31, and the second conductor portion 33 is disposed around the first channel portion 32. The edge of the second conductor portion 33 near the first channel portion 32 is located within the closed pattern. The edge of the second conductor portion 33 near the first channel portion 32 is also the edge of the first channel portion 32 near the second conductor portion 33. This makes the first channel portion 32 and the first conductor portion 31 located inside the closed pattern formed by the grain boundary 35. That is, the first channel portion 32 and the first conductor portion 31 can be located inside the hexagonal or circular first grain 34, so that the first channel portion 32 and the first conductor portion 31 do not include the grain boundary 35.

[0128] Of course, in some other exemplary embodiments of this disclosure, the first channel portion 32 can be configured as an elliptical ring or other various polygonal rings, and correspondingly, the second conductor portion 33 can also be configured as an elliptical ring or other various polygonal rings, and the first conductor portion 31 can be configured as an ellipse or other various polygons. These will not be described in detail here.

[0129] Referring to FIG12, when the grain boundary 35 can form a closed pattern, that is, when the grain boundary 35 can form a ring, the first channel portion 32 can be set as an arc and the second conductor portion 33 can be set as an arc. For example, the first channel portion 32 can be set as a circular arc, and correspondingly, the second conductor portion 33 can also be set as a circular arc, and the first conductor portion 31 can be set as a circle or a part of a circle; the first channel portion 32 can also be set as an elliptical arc, and correspondingly, the second conductor portion 33 can also be set as an elliptical arc, and the first conductor portion 31 can be set as an ellipse or a part of an ellipse.

[0130] The first channel portion 32 is disposed around the first conductor portion 31, and the second conductor portion 33 is disposed around the first channel portion 32. The edge of the second conductor portion 33 near the first channel portion 32 is located within the closed pattern. The edge of the second conductor portion 33 near the first channel portion 32 is also the edge of the first channel portion 32 near the second conductor portion 33. This makes the first channel portion 32 and the first conductor portion 31 located inside the closed pattern formed by the grain boundary 35. That is, the first channel portion 32 and the first conductor portion 31 can be located inside the hexagonal or circular first grain 34, so that the first channel portion 32 and the first conductor portion 31 do not include the grain boundary 35.

[0131] Of course, in some other exemplary embodiments of this disclosure, the first channel portion 32 may be configured as a parabolic arc, or other regular or irregular arcs. Correspondingly, the second conductor portion 33 may also be configured as a parabolic arc, or other regular or irregular arcs, and the first conductor portion 31 may also be configured accordingly. These will not be described in detail here.

[0132] Alternatively, referring to Figures 10-12, the second conductor portion 33 may include a grain boundary 35, and the first conductor portion 31 may include a crystallization defect portion 36. The first conductor portion 31 is located in the middle of the first grain 34, serving as the starting or ending growth region of the first grain 34, resulting in the presence of a crystallization defect portion 36 in the middle of the first grain 34. The crystallization defect portion 36 does not affect the conductivity of the first conductor portion 31, but it does affect the carrier mobility of the first channel portion 32. By placing the first conductor portion 31 in the middle of the first grain 34, the first conductor portion 31 may include the crystallization defect portion 36, while the first channel portion 32 does not. Even if the first conductor portion 31 includes the crystallization defect portion 36, its conductivity will not be affected, thus ensuring the electrical performance of the first transistor T1. Furthermore, the first channel portion 32 does not include the crystallization defect portion 36, resulting in a higher mobility for the first channel portion 32, which in turn leads to a higher mobility for the first transistor T1, meeting the requirements of Micro-LED display technology.

[0133] The aforementioned first active layer 3 can be formed by laser irradiation. Specifically, as shown in Figure 13, an amorphous silicon film 3a (a-Si) is deposited on the side of the buffer layer 2 facing away from the substrate 1, followed by a dehydrogenation process and an HF (hydrofluoric acid) cleaning process. The thickness of the amorphous silicon film 3a is greater than or equal to 100 angstroms and less than or equal to 100,000 angstroms. For example, the thickness of the amorphous silicon film 3a can be 500 angstroms, 1000 angstroms, 5000 angstroms, 10000 angstroms, 20000 angstroms, 50000 angstroms, 80000 angstroms, etc. The hydrogen content of the amorphous silicon film 3a is ≤1% to prevent hydrogen explosions during the crystallization process.

[0134] Of course, in some other example embodiments of this disclosure, the thickness of the amorphous silicon film 3a is greater than or equal to 50 angstroms and less than or equal to 1500 angstroms.

[0135] Referring to FIG14, a mask 13 is disposed on the side of the amorphous silicon film layer 3a facing away from the substrate 1. The mask 13 may include a light-shielding portion 131 and a light-transmitting portion 132. Referring to FIG16, multiple light-shielding portions 131 are arranged at intervals and are arranged in an array. A surface beam passes through the mask 13 to form a pattern on the mask 13, with a magnification ratio of 0.5-10, that is, the pattern magnification or reduction ratio ranges from 0.5-10. Due to the change in pattern magnification, the energy density changes synchronously. The light-shielding portion 131 is used to block the passage of the laser beam. The light-shielding portion 131 may be circular, and the diameter of the light-shielding portion 131 is greater than or equal to 0.5 micrometers and less than or equal to 5 micrometers. For example, the diameter of the light-shielding portion 131 may be 1 micrometer, 1.5 micrometers, 2 micrometers, 2.5 micrometers, 3 micrometers, 3.5 micrometers, 4 micrometers, 4.5 micrometers, etc. The arrangement period of the light-shielding part 131 is 1 micrometer to 25 micrometers. For example, the arrangement period of the light-shielding part 131 can be 3 micrometers, 5 micrometers, 8 micrometers, 10 micrometers, 12 micrometers, 15 micrometers, 17 micrometers, 20 micrometers, 23 micrometers, etc. When the laser beam irradiates the amorphous silicon film layer 3a to grow the first grain 34, the area blocked by the light-shielding part 131 is the blocked area 3a1. The energy density of the blocked area 3a1 is low, which forms a sharp contrast with the area opposite to the light-transmitting part 132. Referring to Figure 17, the arrow in the figure indicates the growth direction of the first grain 34. This difference in energy density will cause the first grain 34 to grow from the blocked area 3a1, that is, the blocked area 3a1 is the starting growth area, that is, the first grain 34 grows outward from the blocked area 3a1 blocked by the light-shielding part 131.

[0136] Referring to Figure 15, after the amorphous silicon film layer 3a is irradiated by a laser to grow the first grain 34, a low-temperature polycrystalline silicon including the first grain 34 and the grain boundary 35 is formed. Then, after patterning, an active material layer 3b is formed. The active material layer 3b is almost entirely semiconductor low-temperature polycrystalline silicon.

[0137] Of course, in some other exemplary embodiments of this disclosure, a light-transmitting hole may be provided on the mask plate 13. When the laser beam irradiates the amorphous silicon film layer 3a to grow the first grain 34, the area blocked by the light-shielding part 131 is the blocked area 3a1. The energy density of the blocked area 3a1 is low, which forms a sharp contrast with the area opposite to the light-transmitting part 132. This difference in energy density will cause the first grain 34 to grow from the blocked area 3a1, that is, the blocked area 3a1 is the starting growth area, that is, the first grain 34 grows from the blocked area 3a1 blocked by the light-shielding part 131 into the light-transmitting hole.

[0138] Optionally, referring to FIG3, the array substrate may further include a crystal guiding layer 4. The crystal guiding layer 4 may be disposed on the side of the first active layer 3 facing away from the substrate 1. The thickness of the crystal guiding layer 4 is greater than or equal to 50 angstroms and less than or equal to 5000 angstroms. For example, the thickness of the crystal guiding layer 4 may be 100 angstroms, 250 angstroms, 500 angstroms, 750 angstroms, 1000 angstroms, 1500 angstroms, 2000 angstroms, 2500 angstroms, 3000 angstroms, 3500 angstroms, 4000 angstroms, 4500 angstroms, etc. The crystal guiding layer 4 can be formed into a guiding pattern using a conventional exposure etching process. The crystal guiding layer 4 can guide the formation of the first grain 34. The material of the crystal guiding layer 4 may be a metal material such as Mo, Ti, or Ag.

[0139] Of course, in some other exemplary embodiments of this disclosure, as shown in FIG3 and FIG4, the crystal guiding layer 4 may be disposed on the side of the first active layer 3 near the substrate 1.

[0140] The orthographic projection of the crystal guiding layer 4 on the substrate 1 does not overlap with the orthographic projection of the first channel portion 32 on the substrate 1. Since the crystal guiding layer 4 is made of metal and the first channel portion 32 is a semiconductor, the crystal guiding layer 4 and the first channel portion 32 must not contact each other to ensure the semiconductor performance of the first channel portion 32. If the crystal guiding layer 4 contacts the first channel portion 32, it will affect the semiconductor performance of the first channel portion 32.

[0141] The crystallization guiding layer 4 can be set as dots, for example, it can be set as a circle, ellipse, rounded square, rounded rectangle, square, rectangle, rhombus and various regular or irregular polygons, etc.

[0142] It should be noted that "dot-shaped" refers to the ratio of the minimum size to the maximum size of the orthographic projection of the crystal guiding layer 4 on the substrate 1 being greater than or equal to 0.7 and less than or equal to 1. For example, if the crystal guiding layer 4 is set to an ellipse, the maximum size of the orthographic projection of the crystal guiding layer 4 on the substrate 1 is the major axis of the ellipse, and the minimum size of the orthographic projection of the crystal guiding layer 4 on the substrate 1 is the minor axis of the ellipse, that is, the length and width of the crystal guiding layer 4 are basically the same.

[0143] The orthographic projection of the crystal guiding layer 4 on the substrate 1 overlaps with the orthographic projection of the first conductor portion 31 on the substrate 1. For example, the edge line of the orthographic projection of the crystal guiding layer 4 on the substrate 1 may coincide with the edge line of the orthographic projection of the first conductor portion 31 on the substrate 1. Alternatively, the orthographic projection of the crystal guiding layer 4 on the substrate 1 may be located within the orthographic projection of the first conductor portion 31 on the substrate 1. Or, a portion of the orthographic projection of the crystal guiding layer 4 on the substrate 1 may overlap with a portion of the orthographic projection of the first conductor portion 31 on the substrate 1.

[0144] Of course, in some other exemplary embodiments of this disclosure, as shown in FIG18, a plurality of hollow portions 41 are provided on the crystal guiding layer 4. The plurality of hollow portions 41 can be arranged in an array. For example, the hollow portions 41 can be set as circles, ellipses, rounded squares, rounded rectangles, squares, rectangles, rhombuses and various regular or irregular polygons, etc.

[0145] The orthographic projection of the crystal guiding layer 4 on the substrate 1 overlaps with the orthographic projection of the second conductor portion 33 on the substrate 1. For example, the edge line of the orthographic projection of the crystal guiding layer 4 on the substrate 1 may coincide with the edge line of the orthographic projection of the second conductor portion 33 on the substrate 1. Alternatively, the orthographic projection of the crystal guiding layer 4 on the substrate 1 may be located within the orthographic projection of the second conductor portion 33 on the substrate 1. Or, a portion of the orthographic projection of the crystal guiding layer 4 on the substrate 1 may overlap with a portion of the orthographic projection of the second conductor portion 33 on the substrate 1.

[0146] Referring to FIG19, with the crystallization guiding layer 4 disposed on the side of the first active layer 3 facing away from the substrate 1, photoresist 14 is formed on the side of the amorphous silicon film layer 3a facing away from the substrate 1, and the photoresist 14 is patterned to form a hollow pattern, exposing a portion of the amorphous silicon film layer 3a. The exposed amorphous silicon film layer 3a is then heavily doped with boron (B) or phosphorus (P) to form a conductive first conductor portion 31. Referring to FIG20, the crystallization guiding layer 4 is then formed on the side of the first conductor portion 31 facing away from the substrate 1. Referring to FIG21, the amorphous silicon film layer 3a is then irradiated with a laser using the crystallization guiding layer 4 as an inducer to form a low-temperature polycrystalline silicon including first grains 34 and grain boundaries 35. After patterning, an active material layer 3b is formed, which is almost entirely semiconductor low-temperature polycrystalline silicon.

[0147] Referring to FIG22, with the crystallization guiding layer 4 disposed on the side of the first active layer 3 close to the substrate 1, the crystallization guiding layer 4 is formed on the side of the buffer layer 2 away from the substrate 1. Referring to FIG23, an amorphous silicon film layer 3a is formed on the side of the crystallization guiding layer 4 away from the substrate 1. Referring to FIG24, a photoresist 14 is formed on the side of the amorphous silicon film layer 3a away from the substrate 1, and the photoresist 14 is patterned to form a hollow pattern, exposing a portion of the amorphous silicon film layer 3a. The exposed amorphous silicon film layer 3a is then heavily doped with boron (B) or phosphorus (P) to form a conductive first conductor portion 31. Referring to FIG25, the amorphous silicon film layer 3a is then irradiated with a laser using the crystallization guiding layer 4 as an induction to form a low-temperature polycrystalline silicon including a first grain 34 and a grain boundary 35. After patterning, an active material layer 3b is formed, which is almost entirely semiconductor low-temperature polycrystalline silicon.

[0148] In some exemplary embodiments of this disclosure, referring to Figures 1-4, the array substrate may further include a first gate insulating layer 5, a first gate layer 6, a first interlayer dielectric layer 7, and a first interconnect conductor layer 8. Referring to Figure 26, the first gate insulating layer 5 is disposed on the side of the first active layer 3 facing away from the substrate 1. The first gate insulating layer 5 may be a single-layer structure; for example, the material of the first gate insulating layer 5 may be a single-layer structure of SiNx or SiOx. The first gate insulating layer 5 may be a double-layer or multi-layer stacked structure; for example, the first gate insulating layer 5 may be a double-layer stacked structure of SiNx and SiOx. The thickness of SiNx is approximately 400 angstroms, and the thickness of SiOx is approximately 800 angstroms.

[0149] Alternatively, the thickness of the first gate insulating layer 5 may be greater than or equal to 500 angstroms and less than or equal to 5000 angstroms. For example, the thickness of the first gate insulating layer 5 may also be 1000 angstroms, 1500 angstroms, 2000 angstroms, 2500 angstroms, 3000 angstroms, 3500 angstroms, 4000 angstroms, 4500 angstroms, etc.

[0150] A first gate layer 6 is disposed on the side of the first gate insulating layer 5 facing away from the substrate 1. The material of the first gate layer 6 may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first gate layer 6 may be a single-layer film structure or a multilayer film structure. The thickness of the first gate layer 6 is greater than or equal to 3100 angstroms and less than or equal to 3300 angstroms. For example, the thickness of the first gate layer 6 may be 3120 angstroms, 3150 angstroms, 3170 angstroms, 3200 angstroms, 3230 angstroms, 3250 angstroms, 3280 angstroms, etc.

[0151] Alternatively, the thickness of the first gate layer 6 may be greater than or equal to 500 angstroms and less than or equal to 5000 angstroms. For example, the thickness of the first gate layer 6 may also be 1000 angstroms, 1500 angstroms, 2000 angstroms, 2500 angstroms, 3000 angstroms, 3500 angstroms, 4000 angstroms, 4500 angstroms, etc.

[0152] The first gate layer 6 includes a first gate 61, which can be configured with the same shape as the first channel portion 32. For example, the first gate 61 can be rectangular, and the first channel portion 32 can also be rectangular; the first gate 61 can be annular, and the first channel portion 32 can also be annular; the first gate 61 can be arc-shaped, and the first channel portion 32 can also be arc-shaped. Since the active material layer 3b is doped to form the first active layer 3 using the first gate 61 as a shield, the active material layer 3b forms a first active layer 3 including a first conductor portion 31, a first channel portion 32, and a second conductor portion 33 connected in sequence. Therefore, the orthographic projection of the first channel portion 32 onto the substrate 1 lies within the orthographic projection of the first gate 61 onto the substrate 1. The doping material can be BF3 (boron trifluoride).

[0153] Referring to FIG27, a first interlayer dielectric layer 7 is disposed on the side of the first gate layer 6 facing away from the substrate 1. The first interlayer dielectric layer 7 can be a single-layer structure, for example, the material of the first interlayer dielectric layer 7 can be a single-layer structure of SiNx film or SiOx film. The first interlayer dielectric layer 7 can be a double-layer or multi-layer stacked structure, for example, the first interlayer dielectric layer 7 can be a double-layer stacked structure of SiNx film and SiOx film, the thickness of SiNx film is approximately 3000 angstroms, and the thickness of SiOx is approximately 2000 angstroms. After depositing the first interlayer dielectric layer 7, an activation process is performed, then an etching process is performed on the first interlayer dielectric layer 7 and the first gate insulating layer 5 to form vias, and finally a hydrogen replenishment process is performed.

[0154] Referring to Figures 1-4, a first connecting conductor layer 8 is provided on the side of the first interlayer dielectric layer 7 facing away from the substrate 1. The first connecting conductor layer 8 may include a first connecting portion 81 and a second connecting portion 82. The first connecting portion 81 is connected to the first conductor portion 31, and the second connecting portion 82 is connected to the second conductor portion 33. Specifically, the first connecting portion 81 is connected to the first conductor portion 31 through the first gate insulating layer 5 and the vias on the first interlayer dielectric layer 7, and the second connecting portion 82 is connected to the second conductor portion 33 through the first gate insulating layer 5 and the vias on the first interlayer dielectric layer 7.

[0155] The first connecting conductor layer 8 can be configured as a multilayer stacked structure. For example, the first connecting conductor layer 8 can be a three-layer stacked structure of titanium metal layer, aluminum metal layer and titanium metal layer, with the thickness of titanium metal layer being approximately 500 angstroms and the thickness of aluminum metal layer being approximately 6500 angstroms.

[0156] Alternatively, the first connecting portion 81 may be configured to have the same shape as the first conductor portion 31. For example, if the first conductor portion 31 is circular, the first connecting portion 81 may also be circular; if the first conductor portion 31 is elliptical, the first connecting portion 81 may also be elliptical; if the first conductor portion 31 is polygonal, the first connecting portion 81 may also be polygonal.

[0157] The orthographic projection of the first connecting portion 81 on the substrate 1 at least partially overlaps with the orthographic projection of the first conductor portion 31 on the substrate 1. For example, the edge line of the orthographic projection of the first connecting portion 81 on the substrate 1 may coincide with the edge line of the orthographic projection of the first conductor portion 31 on the substrate 1. Alternatively, the orthographic projection of the first connecting portion 81 on the substrate 1 may cover and be larger than the orthographic projection of the first conductor portion 31 on the substrate 1. Or, the orthographic projection of the first conductor portion 31 on the substrate 1 may cover and be larger than the orthographic projection of the first connecting portion 81 on the substrate 1. Or, a portion of the orthographic projection of the first connecting portion 81 on the substrate 1 may overlap with a portion of the orthographic projection of the first conductor portion 31 on the substrate 1.

[0158] The second connecting portion 82 can be configured to have the same shape as the second conductor portion 33. For example, if the second conductor portion 33 is rectangular, the second connecting portion 82 can also be rectangular; if the second conductor portion 33 is annular, the second connecting portion 82 can also be annular; if the second conductor portion 33 is arc-shaped, the second connecting portion 82 can also be arc-shaped.

[0159] The orthographic projection of the second connecting portion 82 on the substrate 1 and the orthographic projection of the second conductor portion 33 on the substrate 1 overlap at least partially. For example, the edge line of the orthographic projection of the second connecting portion 82 on the substrate 1 may coincide with the edge line of the orthographic projection of the second conductor portion 33 on the substrate 1. Alternatively, the orthographic projection of the second connecting portion 82 on the substrate 1 may cover and be larger than the orthographic projection of the second conductor portion 33 on the substrate 1. Or, the orthographic projection of the second conductor portion 33 on the substrate 1 may cover and be larger than the orthographic projection of the second connecting portion 82 on the substrate 1. Alternatively, a portion of the orthographic projection of the second connecting portion 82 on the substrate 1 may overlap with a portion of the orthographic projection of the second conductor portion 33 on the substrate 1.

[0160] Alternatively, referring to Figures 1-4 and 32, the orthographic projection of the first connecting portion 81 on the substrate 1 overlaps with the orthographic projection of the grain boundary 35 included in the first conductor portion 31 on the substrate 1. For example, the orthographic projection of the grain boundary 35 included in the first conductor portion 31 on the substrate 1 may be located within the orthographic projection of the first connecting portion 81 on the substrate 1, or a portion of the orthographic projection of the grain boundary 35 included in the first conductor portion 31 on the substrate 1 may overlap with a portion of the orthographic projection of the first connecting portion 81 on the substrate 1. The orthographic projection of the second connecting portion 82 on the substrate 1 overlaps with the orthographic projection of the grain boundary 35 included in the second conductor portion 33 on the substrate 1. For example, the orthographic projection of the grain boundary 35 included in the second conductor portion 33 on the substrate 1 may be located within the orthographic projection of the second connecting portion 82 on the substrate 1, or a portion of the orthographic projection of the grain boundary 35 included in the second conductor portion 33 on the substrate 1 may overlap with a portion of the orthographic projection of the second connecting portion 82 on the substrate 1.

[0161] For example, as shown in FIG32, a first sub-via 51 and a second sub-via 52 are provided on the first gate insulating layer 5. The first sub-via 51 is connected to the first conductor portion 31, and the second sub-via 52 is connected to the second conductor portion 33. A third sub-via 71 and a fourth sub-via 72 are provided on the first interlayer dielectric layer 7. The third sub-via 71 is connected to the first sub-via 51 to form a first via 7a, and the fourth sub-via 72 is connected to the second via 52 to form a second via 7b. The first connecting portion 81 is connected to the first conductor portion 31 through the first via 7a, and the second connecting portion 82 is connected to the second conductor portion 33 through the second via 7b.

[0162] In the first direction X, the distance between the portion of the first connecting portion 81 located within the first via 7a and the portion of the second connecting portion 82 located within the second via 7b is less than the distance between two adjacent grain boundaries 35. Specifically, the portion of the first connecting portion 81 located within the first via 7a is situated on the side of the grain boundary 35 closest to the first channel portion 32, and the portion of the second connecting portion 82 located within the second via 7b is also situated on the side of the grain boundary 35 closest to the first channel portion 32. This arrangement helps to reduce the size of the first transistor T1, thereby increasing the aperture ratio of the display device.

[0163] For example, the first connecting portion 81 can be connected to the grain boundary 35 of the first conductor portion 31, and the second connecting portion 82 can also be connected to the grain boundary 35 of the second conductor portion 33.

[0164] In some other exemplary embodiments of this disclosure, the first connecting portion 81 may be connected to the grain boundary 35 of the first conductor portion 31, while the second connecting portion 82 may not be connected to the grain boundary 35 of the second conductor portion 33. Alternatively, the second connecting portion 82 may be connected to the grain boundary 35 of the second conductor portion 33, while the first connecting portion 81 may not be connected to the grain boundary 35 of the first conductor portion 31.

[0165] Since the first die 34 is designed as a first channel portion 32 as much as possible, the area of ​​the first channel portion 32 is made as large as possible, thereby compressing the area of ​​the first conductor portion 31 and the second connection portion 82. Furthermore, the first conductor portion 31 and the second connection portion 82 include grain boundaries 35. If the connection between the first connection portion 81 and the first conductor portion 31 is misaligned with the grain boundary 35, and the connection between the second connection portion 82 and the second conductor portion 33 is also misaligned with the grain boundary 35, the volume of the first transistor T1 will increase, which is detrimental to the high aperture ratio design of the display device. The first connection portion 81 is connected to the grain boundary 35 of the first conductor portion 31, and the second connection portion 82 is connected to the grain boundary 35 of the second conductor portion 33. This not only ensures the connection and conductivity between them but also facilitates the high aperture ratio design of the display device.

[0166] The first connecting portion 81 is connected to the poorly formed portion 36 of the first conductor portion 31. Similarly, since the best portion of the first die 34 is preferably set as the first channel portion 32, the area of ​​the first channel portion 32 is made as large as possible, thereby compressing the area of ​​the first conductor portion 31 and the second connecting portion 82. Moreover, the first conductor portion 31 includes the poorly formed portion 36. If the connection between the first connecting portion 81 and the first conductor portion 31 is misaligned with the poorly formed portion 36, it will lead to an increase in the size of the first transistor T1, which is not conducive to the high aperture ratio design of the display device. The first connecting portion 81 is connected to the poorly formed portion 36 of the first conductor portion 31, which not only ensures the connection effect and conductivity between them, but also facilitates the high aperture ratio design of the display device.

[0167] In some exemplary embodiments of this disclosure, referring to Figures 3, 4, and 33, the first connection conductor layer 8 may include a fifth connection portion 83, which is connected to the first gate 61. Specifically, the fifth connection portion 83 is connected to the first gate 61 through vias on the first gate insulating layer 5 and the first interlayer dielectric layer 7.

[0168] In some exemplary embodiments of this disclosure, referring to Figures 28-31, a planarization layer 9 is provided on the side of the first interconnect conductor layer 8 facing away from the substrate 1. The planarization layer 9 is made of an organic material. The thickness of the planarization layer 9 is approximately 2 micrometers.

[0169] Referring to Figures 29-31, a first protective layer 10 is provided on the side of the planarization layer 9 facing away from the substrate 1. The material of the first protective layer 10 can be SiNx, and the thickness of the first protective layer 10 is greater than or equal to 1500 angstroms and less than or equal to 2000 angstroms. For example, the thickness of the first protective layer 10 can be 1550 angstroms, 1600 angstroms, 1650 angstroms, 1700 angstroms, 1750 angstroms, 1800 angstroms, 1850 angstroms, 1900 angstroms, 1950 angstroms, etc. A transition via and a venting via are provided on the first protective layer 10. The transition via connects to the first connection portion 81 and the second connection portion 82, and the venting via connects to the planarization layer 9. During subsequent fabrication, the planarization layer 9 may generate gas due to overheating or other reasons. The gas can be discharged through the venting via to prevent the first protective layer 10 from peeling off and to ensure the performance of the array substrate.

[0170] Referring to Figures 30-31, a second connecting conductor layer 11 is disposed on the side of the first protective layer 10 facing away from the substrate 1. The second connecting conductor layer 11 can be a single-layer structure or a multi-layer stacked structure. For example, the second connecting conductor layer 11 may include a first conductive layer and a second conductive layer. The material of the first conductive layer may be a molybdenum-nickel-titanium alloy (Mo-Ni-Ti alloy, MTD), and the thickness of the first conductive layer may be greater than or equal to 100 angstroms and less than or equal to 1000 angstroms. For example, the thickness of the first conductive layer may be 300 angstroms, 500 angstroms, 800 angstroms, etc. The material of the second conductive layer may be copper, and the thickness of the second conductive layer may be greater than or equal to 1 micrometer and less than or equal to 2 micrometers. For example, the thickness of the second conductive layer may be 1.2 micrometers, 1.5 micrometers, 1.7 micrometers, etc.

[0171] The second connecting conductor layer 11 may include a third connecting portion 111 and a fourth connecting portion 112. The third connecting portion 111 is connected to the first connecting portion 81 through vias on the planarization layer 9 and the first protective layer 10, and the fourth connecting portion 112 is connected to the second connecting portion 82 through vias on the planarization layer 9 and the first protective layer 10.

[0172] Referring to FIG31, a second protective layer 12 is provided on the side of the second interconnecting conductor layer 11 facing away from the substrate 1. The material of the second protective layer 12 can be SiNx, and the thickness of the second protective layer 12 is greater than or equal to 1500 angstroms and less than or equal to 2000 angstroms. For example, the thickness of the second protective layer 12 can be 1550 angstroms, 1600 angstroms, 1650 angstroms, 1700 angstroms, 1750 angstroms, 1800 angstroms, 1850 angstroms, 1900 angstroms, 1950 angstroms, etc. A connection via is provided on the second protective layer 12, which connects to the third connection portion 111 and the fourth connection portion 112. The MLED (Micro-Light Emitting Diode) chip can be connected to the third connection portion 111 and the fourth connection portion 112 through the connection via.

[0173] It should be noted that Figures 5-12 not only show the first active layer 3, but also the relationship between each part of the first active layer 3 and the first grain 34 and the grain boundary 35. Therefore, the area shown in the picture is relatively large. The parts other than the first conductor part 31, the first channel part 32 and the second conductor part 33 of the actual product will be removed.

[0174] A first conductor portion 31, a first channel portion 32, a second conductor portion 33, a first gate portion 251, a first connection portion 81, and a second connection portion 82 form a first transistor T1. The first conductor portion 31 can be the source, and the second conductor portion 33 can be the drain. This first transistor T1 can be used as a driving transistor, and of course, it can also be used as a switching transistor, etc.

[0175] It should be noted that the first transistor T1 described in this specification is a top-gate thin-film transistor. In other exemplary embodiments of this disclosure, the first transistor T1 may also be a bottom-gate or dual-gate thin-film transistor, and its specific structure will not be described in detail here. Moreover, in cases where thin-film transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" may be interchanged.

[0176] When the first transistor T1 is a dual-gate thin-film transistor, the first transistor T1 may include two first gates 61, which are disposed on opposite sides of the first channel portion 32 along a third direction, and an insulating layer is disposed between the two first gates 61 and the first channel portion 32. The third direction is perpendicular to the substrate 1.

[0177] In some exemplary embodiments of this disclosure, referring to FIG34, the array substrate may further include a second transistor T2, which is disposed on one side of the substrate 1. Specifically, the first transistor T1 and the second transistor T2 may be disposed on the same side of the substrate 1. The second transistor T2 may include a second active layer 3e, which may include a third conductor portion 3e1, a second channel portion 3e2, and a fourth conductor portion 3e3 connected in sequence. The second channel portion 3e2 may include a second die 3e21, and the size of the first die 34 is larger than the size of the second die 3e21. Specifically, the size of the second die 3e21 is greater than or equal to 0.2 micrometers and less than or equal to 0.4 micrometers. For example, the size of the second die 3e21 may be 0.23 micrometers, 0.25 micrometers, 0.28 micrometers, 0.3 micrometers, 0.32 micrometers, 0.35 micrometers, 0.37 micrometers, etc.

[0178] Referring to Figures 34-36, the array substrate may also include a CMOS (Complementary Metal-Oxide-Semiconductor) structure. The CMOS structure may include a first transistor T1 and a second transistor T2. The first transistor T1 is a P-type transistor, made of p-type semiconductor material, where holes become the primary charge carrier under the influence of the gate voltage. The second transistor T2 is an N-type transistor, made of n-type semiconductor material, where electrons are the primary charge carrier. By utilizing the complementary characteristics of N-type and P-type transistors, a large number of electronic components can be integrated, thereby realizing various complex electronic functions.

[0179] The switching characteristic is that the transistor's conduction and cutoff are controlled by controlling the gate voltage. For an N-type transistor, it conducts when the gate voltage is higher than the threshold voltage and cuts off when it is lower; conversely, for a P-type transistor, it conducts when the gate voltage is lower than the threshold voltage and cuts off when it is higher. In CMOS structures, this complementary switching characteristic is used to implement logic functions. Specific logic gate implementation: Referring to Figures 35 and 36, taking an inverter as an example, it consists of a P-type transistor (first transistor T1) and an N-type transistor (second transistor T2). The gates of the first transistor T1 and the second transistor T2 are connected to form the input terminal Vin. The drains of the first transistor T1 and the second transistor T2 are connected to form the output terminal Vout. The source of the first transistor T1 is connected to the power supply VDD (or a high potential), and the source of the second transistor T2 is connected to ground GND (or a low potential). When the input is high, the N-type transistor is on, the P-type transistor is off, and the output is low; when the input is low, the P-type transistor is on, the N-type transistor is off, and the output is high, thus achieving the logic inversion function. Other complex logic gates are also built on this principle, which will not be elaborated here.

[0180] In related technologies, both transistors in a CMOS structure can be MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). However, MOSFETs require silicon wafers as substrates, and current silicon wafer technology cannot achieve large substrate sizes, typically ≤12 inches, and is costly. In this disclosure, both the first transistor T1 and the second transistor T2 are thin-film transistors (TFTs). Thin-film transistors can use glass as substrates, enabling the creation of larger array substrates and thus larger display devices. This removes the size limitations of silicon-based substrates and effectively reduces costs.

[0181] However, due to the difference in mobility between N-type and P-type transistors—for example, the mobility of a P-type transistor, due to hole conduction, is only about 70.4, while that of an N-type transistor, due to electron conduction, can reach about 127.67—this difference limits the application of CMOS structures, affects circuit performance, and results in poor symmetry of the transfer characteristic curves of N-type and P-type transistors. Referring to Figure 49, the horizontal axis represents the gate voltage Vgate (in volts), with 0 in the middle, negative values ​​on the left, and positive values ​​on the right. The vertical axis represents the leakage current Id (in amperes). In the figure, L1 is the transfer characteristic curve of an N-type transistor, and L2 is the transfer characteristic curve of an existing P-type transistor. The poor symmetry between L1 and L2 makes its application in inverters more difficult.

[0182] In this disclosure, the size of the first die 34 is larger than the size of the second die 3e21, thereby increasing the carrier mobility of the first transistor T1, which is used as a P-type transistor, to a carrier mobility that is basically consistent with that of an N-type transistor. Matching the threshold voltage (Vth) of the first transistor T1 and the second transistor T2, the first transistor T1 and the second transistor T2 form a well-symmetrical transfer characteristic curve. Referring to FIG49, L3 is the transfer characteristic curve of the first transistor T1 in this disclosure. The good symmetry between L1 and L3 optimizes the inverter performance, thereby ensuring the performance of the CMOS structure and making the application of the CMOS structure more widespread.

[0183] It should be noted that Figure 49 shows the general direction of L1, L2 and L3 to indicate the symmetry between L1 and L2 and L3, but does not indicate the specific values ​​of each position of L1, L2 and L3.

[0184] The specific structure of the first transistor T1 has been described in detail above, and will not be repeated here. The positional relationship between the first transistor T1 and the second transistor T2 is explained below.

[0185] In some exemplary embodiments of this disclosure, referring to FIG34, the first active layer 3 and the second active layer 3e may be disposed on the same side of the buffer layer 2. A first gate insulating layer 5 is disposed on the side of the first active layer 3 and the second active layer 3e facing away from the substrate 1. A fifth sub-via 53 and a sixth sub-via 54 are also disposed on the first gate insulating layer 5. The fifth sub-via 53 is connected to the third conductor portion 3e1, and the sixth sub-via 54 is connected to the fourth conductor portion 3e3. A first gate layer 6 is disposed on the side of the first gate insulating layer 5 facing away from the substrate 1. The first gate layer 6 may include a first gate 61 and a second gate 62. The first gate 61 and the second gate 62 may be disposed at intervals, that is, a gap is provided between the first gate 61 and the second gate 62, and they are not connected.

[0186] Of course, in some other exemplary embodiments of this disclosure, such as when a CMOS structure is used as an inverter, the first gate 61 and the second gate 62 may also be connected as one unit.

[0187] A first interlayer dielectric layer 7 is provided on the side of the first gate layer 6 away from the substrate 1. A seventh sub-via 73 and an eighth sub-via 74 are provided on the first interlayer dielectric layer 7. The seventh sub-via 73 is connected to the fifth sub-via 53, and the eighth sub-via 74 is connected to the sixth sub-via 54.

[0188] In this case, the first connecting conductor layer 8 may further include a sixth connecting portion 84 and a seventh connecting portion 85. The sixth connecting portion 84 is connected to the third conductor portion 3e1. Specifically, the sixth connecting portion 84 is connected to the third conductor portion 3e1 through a fifth sub-via 53 and a seventh sub-via 73. The seventh connecting portion 85 is connected to the fourth conductor portion 3e3. Specifically, the seventh connecting portion 85 is connected to the fourth conductor portion 3e3 through a sixth sub-via 54 and an eighth sub-via 74.

[0189] The material and thickness of each film layer can be the same as those in the above example embodiments, so they will not be described again here.

[0190] Referring to Figures 37 and 38, the amorphous silicon film 3a is subjected to ELA (Excimer Laser Annealing) crystallization based on Figure 13. This crystallization is the first crystallization, transforming the amorphous silicon film 3a into a first polycrystalline silicon layer 3c (p-Si). The first polycrystalline silicon layer 3c includes multiple second grains 3e21, the size of which is greater than or equal to 200 nm and less than or equal to 400 nm. Then, the first polycrystalline silicon layer 3c is selectively crystallized a second time using the method of setting the mask 13 as shown in Figures 14 and 16 or setting the induced crystallization guiding layer 4 as shown in Figure 18 to form a second polycrystalline silicon layer 3d, which includes multiple first grains 34. Since the first polycrystalline silicon layer 3c or the induced crystallization guiding layer 4 can form an undercooled interface, the grains can grow rapidly, resulting in larger first grains 34. Since the second polysilicon layer 3d is selectively formed, the second polysilicon layer 3d can directly form the first active layer 3, that is, the range of the second polysilicon layer 3d is the range of the first active layer 3.

[0191] Referring to Figures 39 and 40, the first polysilicon layer 3c and the second polysilicon layer 3d formed above are patterned to form a first active layer 3 and a second active layer 3e. Referring to Figures 41 and 42, a gate insulating layer and a gate material layer are formed on the side of the first active layer 3 and the second active layer 3e facing away from the substrate 1, and the gate material layer is patterned to form a first gate 61 and a second gate 62. Referring to Figures 43 and 44, a first interlayer dielectric layer 7 is formed on the side of the first gate 61 and the second gate 62 facing away from the substrate 1, and the first interlayer dielectric layer 7 and the gate insulating layer are patterned to form vias. Referring to Figures 45 and 34, where Figure 34 is a cross-sectional schematic diagram of Figure 45, a first interconnecting conductor layer 8 is formed on the side of the first interlayer dielectric layer 7 facing away from the substrate 1.

[0192] In some exemplary embodiments of this disclosure, referring to FIG46, the first active layer 3 may be disposed on the side of the second active layer 3e facing away from the substrate 1. Specifically, the second active layer 3e may be disposed on the side of the buffer layer 2 facing away from the substrate 1, and the array substrate may further include a second gate insulating layer 5e, a second gate layer 6e, and a second interlayer dielectric layer 7e. The second gate insulating layer 5e is disposed on the side of the second active layer 3e facing away from the substrate 1, and a via is provided on the second gate insulating layer 5e to connect to the third conductor portion 3e1 and the fourth conductor portion 3e3. The second gate layer 6e is disposed on the side of the second gate insulating layer 5e facing away from the substrate 1, and the second gate layer 6e may include a second gate 62, the orthographic projection of the second channel portion 3e2 on the substrate 1 being located within the orthographic projection of the second gate 62 on the substrate 1. The second interlayer dielectric layer 7e is disposed on the side of the second gate layer 6e facing away from the substrate 1, and a via is provided on the second interlayer dielectric layer 7e to connect to the third conductor portion 3e1 and the fourth conductor portion 3e3. The first active layer 3 can be disposed on the side of the second interlayer dielectric layer 7e away from the substrate 1, and subsequent film layers are disposed sequentially, which will not be described in detail here. The first connecting conductor layer 8 is disposed on the side of the first interlayer dielectric layer 7 away from the substrate 1. The first connecting conductor layer 8 may also include a sixth connecting portion 84 and a seventh connecting portion 85. The sixth connecting portion 84 is connected to the third conductor portion 3e1. Specifically, the sixth connecting portion 84 can be connected to the third conductor portion 3e1 sequentially through vias on the first interlayer dielectric layer 7, the first gate insulating layer 5, the second interlayer dielectric layer 7e, and the second gate insulating layer 5e. The seventh connecting portion 85 is connected to the fourth conductor portion 3e3. Specifically, the seventh connecting portion 85 can be connected to the fourth conductor portion 3e3 sequentially through vias on the first interlayer dielectric layer 7, the first gate insulating layer 5, the second interlayer dielectric layer 7e, and the second gate insulating layer 5e.

[0193] In some exemplary embodiments of this disclosure, referring to FIG47, the second active layer 3e may be disposed on the side of the first active layer 3 facing away from the substrate 1. Specifically, the array substrate may further include a second gate insulating layer 5e, a second gate layer 6e, and a second interlayer dielectric layer 7e. The second active layer 3e may be disposed on the side of the first interlayer dielectric layer 7 facing away from the substrate 1, and the second gate insulating layer 5e is disposed on the side of the second active layer 3e facing away from the substrate 1. A via is provided on the second gate insulating layer 5e to connect to the third conductor portion 3e1 and the fourth conductor portion 3e3. The second gate layer 6e is disposed on the side of the second gate insulating layer 5e facing away from the substrate 1. The second gate layer 6e may include a second gate 62, and the orthographic projection of the second channel portion 3e2 on the substrate 1 is located within the orthographic projection of the second gate 62 on the substrate 1. The second interlayer dielectric layer 7e is disposed on the side of the second gate layer 6e facing away from the substrate 1. The second interlayer dielectric layer 7e has vias connecting to the third conductor portion 3e1 and the fourth conductor portion 3e3. The first connecting conductor layer 8 is disposed on the side of the second interlayer dielectric layer 7e facing away from the substrate 1. The first connecting conductor layer 8 may further include a sixth connecting portion 84 and a seventh connecting portion 85. The sixth connecting portion 84 is connected to the third conductor portion 3e1. Specifically, the sixth connecting portion 84 can be connected to the third conductor portion 3e1 sequentially through vias on the second interlayer dielectric layer 7e and the second gate insulating layer 5e. The seventh connecting portion 85 is connected to the fourth conductor portion 3e3. Specifically, the seventh connecting portion 85 can be connected to the fourth conductor portion 3e3 sequentially through vias on the second interlayer dielectric layer 7e and the second gate insulating layer 5e. In this case, the first connection portion 81 can be connected to the first conductor portion 31 in sequence through the second interlayer dielectric layer 7e, the second gate insulating layer 5e, the first interlayer dielectric layer 7, and the vias on the first gate insulating layer 5, and the second connection portion 82 can be connected to the second conductor portion 33 in sequence through the second interlayer dielectric layer 7e, the second gate insulating layer 5e, the first interlayer dielectric layer 7, and the vias on the first gate insulating layer 5.

[0194] In both of the above cases, the orthographic projection of the second transistor T2 on the substrate 1 can overlap with the orthographic projection of the first transistor T1 on the substrate 1. Moreover, when the second transistor T2 and the first transistor T1 need to be connected, as shown in FIG46, the second conductor portion 33 and the fourth conductor portion 3e3 can be directly connected through the second connecting portion 82; as shown in FIG47, the fourth conductor portion 3e3 and the second conductor portion 33 can be directly connected through the seventh connecting portion 85.

[0195] Of course, in some other exemplary embodiments of this disclosure, the orthographic projection of the second transistor T2 on the substrate 1 may not overlap with the orthographic projection of the first transistor T1 on the substrate 1.

[0196] The third conductor portion 3e1, the second channel portion 3e2, the fourth conductor portion 3e3, the second gate portion 62, the sixth connection portion 84, and the seventh connection portion 85 form the second transistor T2. The third conductor portion 3e1 can be the source, and the fourth conductor portion 3e3 can be the drain. This second transistor T2 can be used as a driving transistor, and of course, it can also be used as a switching transistor, etc.

[0197] It should be noted that the second transistor T2 described in this specification is a top-gate thin-film transistor. In other exemplary embodiments of this disclosure, the second transistor T2 can also be a bottom-gate or dual-gate thin-film transistor, and its specific structure will not be described in detail here. Moreover, in cases where thin-film transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged.

[0198] When the second transistor T2 is a dual-gate thin-film transistor, the second transistor T2 may include two second gates 62, which are disposed on opposite sides of the second channel portion 3e2 along the third direction, and an insulating layer is disposed between the two second gates 62 and the second channel portion 3e2.

[0199] Alternatively, as shown in Figures 34, 46 and 47, the first active layer 3 and the second active layer 3e are spaced apart, that is, there is a gap between the first active layer 3 and the second active layer 3e, and there is no connection between the first active layer 3 and the second active layer 3e.

[0200] Of course, in some other example embodiments of this disclosure, the first active layer 3 may be connected to the second active layer 3e; for example, when the first active layer 3 and the second active layer 3e are disposed on the same layer, the first active layer 3 may be directly connected to the second active layer 3e; when the first active layer 3 and the second active layer 3e are disposed on different layers, the first active layer 3 may be connected to the second active layer 3e through a via.

[0201] In some exemplary embodiments of this disclosure, referring to FIG48, the array substrate may further include a third transistor T3, which is an oxide transistor. The orthogonal projection of the third transistor T3 on the substrate 1 may overlap with the CMOS structure. For example, the orthogonal projection of the third transistor T3 on the substrate 1 may overlap with the first transistor T1, the orthogonal projection of the third transistor T3 on the substrate 1 may overlap with the second transistor T2, and the orthogonal projection of the third transistor T3 on the substrate 1 may overlap with both the first transistor T1 and the second transistor T2.

[0202] Of course, in some other example embodiments of this disclosure, the orthogonal projection of the third transistor T3 onto the substrate 1 may not overlap with the CMOS structure.

[0203] Specifically, referring to FIG48, the third transistor T3 may include a third active layer 3f, which may be disposed on the side of the first interlayer dielectric layer 7 facing away from the substrate 1. The array substrate may further include a third gate insulating layer 5f, a third gate layer 6f, and a third interlayer dielectric layer 7f. The third gate insulating layer 5f is disposed on the side of the third active layer 3f facing away from the substrate 1, and a via is provided on the third gate insulating layer 5f to connect to the third active layer 3f. The third gate layer 6f is disposed on the side of the third gate insulating layer 5f facing away from the substrate 1, and the third gate layer 6f may include a third gate 6f1. The orthogonal projection of the third channel portion on the substrate 1 may be located within the orthogonal projection of the third gate on the substrate 1. The third interlayer dielectric layer 7f is disposed on the side of the third gate layer 6f facing away from the substrate 1, and a via is provided on the third interlayer dielectric layer 7f to connect to the third active layer 3f. The first connecting conductor layer 8 is disposed on the side of the third interlayer dielectric layer 7f facing away from the substrate 1. The first connecting conductor layer 8 may also include an eighth connecting portion 86 and a ninth connecting portion 87. The eighth connecting portion 86 is connected to the third active layer 3f. Specifically, the eighth connecting portion 86 can be connected to the third active layer 3f through vias on the third interlayer dielectric layer 7f and the third gate insulating layer 5f in sequence. The ninth connecting portion 87 is connected to the third active layer 3f. Specifically, the ninth connecting portion 87 can be connected to the third active layer 3f through vias on the third interlayer dielectric layer 7f and the third gate insulating layer 5f in sequence. When the second transistor T2 and the third transistor T3 need to be connected, as shown in FIG48, the third active layer 3f and the fourth conductor portion 3e3 can be directly connected through the ninth connecting portion 87.

[0204] Based on the same inventive concept, this disclosure provides a display device that may include the array substrate described in any of the above-described embodiments. The specific structure of the array substrate has been described in detail above, and therefore will not be repeated here.

[0205] The display device can be a liquid crystal display panel, an OLED (Organic Light-Emitting Diode) display panel, a QLED (Quantum Dot Light Emitting Diodes) display panel, a micro-LED (micro-Light Emitting Diode) display panel, a mini-LED (mini-Light Emitting Diode) display panel, and so on.

[0206] Micro-LED display technology is a more advanced display technology. It achieves high-density integrated LED arrays by thinning, miniaturizing, and arraying the structure of LEDs (Light Emitting Diodes), resulting in LED sizes ranging from 1 to 10 μm. This technology boasts advantages such as self-illumination, high efficiency, low power consumption, high integration, high stability, and all-weather operation, and is considered one of the most promising next-generation display and light-emitting devices. The core of Micro-LED display technology lies in its high-pixel-density two-dimensional Micro-LED array and the ability of each pixel to be addressed, controlled, and independently driven to emit light. This technology is not only suitable for large display screens but can also be deployed in any display application, from the smallest to the largest size, and in many cases, it will offer more unique effects than liquid crystal displays and organic light-emitting diode displays.

[0207] The application of Micro LED display technology has gradually expanded to multiple fields. For example, the launch of the world's first true Micro LED 4K screen marks the entry of Micro LED products into a mature industrialization and mass production stage, and also unveils the prelude to the industrialization of Micro LED. In addition, the successful debugging and lighting of the first Micro LED silicon-based driver automotive pixel headlight chip, with more than 160,000 pixels, demonstrates the application potential of Micro LED in the automotive display field.

[0208] The advantages of Micro LED technology are not only reflected in its superior display performance, but also in its performance in color reproduction and high dynamic range lighting rendering. For example, color reproduction technology can reproduce the microscopic details of colors and present their true forms; contrast technology, through independent control of pixels, can showcase the microscopic expressiveness of different shades of the same color.

[0209] In summary, Micro LED display technology, with its unique advantages and broad application prospects, is gradually becoming an important development direction in the field of display technology. However, due to the need for larger driving current, Micro LED technology poses challenges to thin-film transistors (TFTs) in terms of higher mobility and smaller footprint. The thin-film transistors in the array substrate of this disclosure have advantages such as high mobility, low power consumption, small footprint (smaller channel size), and low heat generation, enabling the array substrate of this disclosure to meet the requirements of Micro LED display devices.

[0210] The specific type of display device is not particularly limited; any type of display device commonly used in the field is acceptable, such as mobile devices like mobile phones, wearable devices like watches, VR devices, etc. Those skilled in the art can make the appropriate selection based on the specific purpose of the display device, which will not be elaborated further here.

[0211] It should be noted that, in addition to the array substrate, the display device also includes other necessary components and parts. Taking the display as an example, these include, for instance, the casing, circuit board, power cord, etc. Those skilled in the art can supplement these components according to the specific usage requirements of the display device, and will not be elaborated here.

[0212] Compared with the prior art, the beneficial effects of the display device provided by the exemplary embodiments of the present invention are the same as the beneficial effects of the array substrate provided by the above exemplary embodiments, and will not be repeated here.

[0213] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. An array substrate, wherein, include: Substrate; A first transistor is disposed on one side of the substrate. The first transistor includes a first active layer. The first active layer includes a first conductor portion, a first channel portion, and a second conductor portion connected in sequence. The first channel portion includes at least a portion of at least one first grain. At least one of the first conductor portion and the second conductor portion includes a grain boundary.

2. The array substrate according to claim 1, wherein, The first conductor portion, the first channel portion, and the second conductor portion are connected sequentially along a first direction. The first channel portion does not include grain boundaries extending along a second direction, and the second direction intersects with the first direction.

3. The array substrate according to claim 2, wherein, The first channel portion includes a channel grain boundary, which extends along the first direction.

4. The array substrate according to claim 3, wherein, The first conductor portion includes a grain boundary extending along the first direction, and the second conductor portion includes a grain boundary extending along the first direction; the length of the first channel portion in the second direction is greater than the distance between two adjacent channel grain boundaries in the second direction.

5. The array substrate according to claim 2, wherein, The first conductor portion includes grain boundaries, and the second conductor portion includes grain boundaries.

6. The array substrate according to claim 5, wherein, The grain boundary extends along the second direction, and the length of the first channel portion in the first direction is less than the distance between two adjacent grain boundaries in the first direction.

7. The array substrate according to claim 1, wherein, The size of the first grain is greater than or equal to 1 micrometer and less than or equal to 10 micrometers, and / or the spacing between two adjacent and opposite grain boundaries is greater than or equal to 1 micrometer and less than or equal to 10 micrometers.

8. The array substrate according to claim 1, wherein, The grain boundaries form a closed pattern, and the first channel portion is enclosed within the closed pattern; the first conductor portion includes one grain boundary, or the first conductor portion includes at least two interconnected grain boundaries; the second conductor portion includes one grain boundary, or the second conductor portion includes at least two interconnected grain boundaries.

9. The array substrate according to claim 1, wherein, The grain boundaries form a closed pattern; the second conductor portion is configured as an annular or arc-shaped portion, the first channel portion is configured as an annular or arc-shaped portion, the first channel portion surrounds the outer periphery of the first conductor portion, the second conductor portion surrounds the outer periphery of the first channel portion, and the edge line of the second conductor portion near the first channel portion is located within the closed pattern.

10. The array substrate according to claim 9, wherein, The second conductor portion includes grain boundaries, and the first conductor portion includes poorly crystallized portions.

11. The array substrate according to claim 9, wherein, The array substrate further includes: A crystallization guiding layer is disposed on the side of the first active layer close to the substrate, or on the side of the first active layer away from the substrate, wherein the orthographic projection of the crystallization guiding layer on the substrate does not overlap with the orthographic projection of the first channel portion on the substrate.

12. The array substrate according to claim 11, wherein, The crystallization guiding layer is configured as a dot, and the orthographic projection of the crystallization guiding layer on the substrate overlaps with the orthographic projection of the first conductor portion on the substrate. Alternatively, the crystallization guiding layer may have multiple cutouts, and the orthographic projection of the crystallization guiding layer on the substrate may overlap with the orthographic projection of the second conductor portion on the substrate.

13. The array substrate according to any one of claims 1 to 12, wherein, The array substrate further includes: A first gate insulating layer is disposed on the side of the first active layer away from the substrate. A first gate layer is disposed on the side of the first gate insulating layer opposite to the substrate. The first gate layer includes a first gate, and the orthographic projection of the first channel portion on the substrate is located within the orthographic projection of the first gate on the substrate. The first interlayer dielectric layer is disposed on the side of the first gate layer away from the substrate. A first connecting conductor layer is disposed on the side of the first interlayer dielectric layer opposite to the substrate. The first connecting conductor layer includes a first connecting portion and a second connecting portion, wherein the first connecting portion is connected to the first conductor portion and the second connecting portion is connected to the second conductor portion.

14. The array substrate according to claim 13, wherein, The first connecting portion is configured to have the same shape as the first conductor portion, and the orthographic projection of the first connecting portion on the substrate at least partially overlaps with the orthographic projection of the first conductor portion on the substrate. And / or, the second connecting portion is configured to fit the shape of the second conductor portion, and the orthographic projection of the second connecting portion on the substrate at least partially overlaps with the orthographic projection of the second conductor portion on the substrate.

15. The array substrate according to claim 13, wherein, The orthographic projection of the first connecting portion on the substrate overlaps with the orthographic projection of the grain boundary included in the first conductor portion on the substrate, and the orthographic projection of the second connecting portion on the substrate overlaps with the orthographic projection of the grain boundary included in the second conductor portion on the substrate.

16. The array substrate according to claim 15, wherein, The first gate insulating layer is provided with a first sub-via and a second sub-via, and the first interlayer dielectric layer is provided with a third sub-via and a fourth sub-via. The third sub-via is connected to the first sub-via to form a first via, and the fourth sub-via is connected to the second sub-via to form a second via. The first connecting portion is connected to the first conductor portion through the first via, and the second connecting portion is connected to the second conductor portion through the second via. In a first direction, the distance between the portion of the first connection located within the first via and the portion of the second connection located within the second via is less than the distance between two adjacent grain boundaries.

17. The array substrate according to claim 15, wherein, The first connecting portion is connected to the grain boundary of the first conductor portion, or the first connecting portion is connected to the poorly crystallized portion of the first conductor portion; And / or, the second connection portion is connected to the grain boundary of the second conductor portion.

18. The array substrate according to claim 1, wherein, The first grain is configured as rectangular, regular hexagonal, or circular.

19. The array substrate according to claim 13, wherein, The array substrate further includes: A second transistor is disposed on one side of the substrate. The second transistor includes a second active layer. The second active layer includes a third conductor portion, a second channel portion, and a fourth conductor portion connected in sequence. The second channel portion includes a second grain. The size of the first grain is larger than the size of the second grain.

20. The array substrate according to claim 19, wherein, The array substrate further includes: The CMOS structure includes a first transistor and a second transistor, wherein the first transistor is a P-type transistor and the second transistor is an N-type transistor.

21. The array substrate according to claim 19, wherein, The first gate insulating layer is disposed on the side of the first active layer and the second active layer away from the substrate. The first gate layer also includes a second gate. The orthographic projection of the second channel portion on the substrate is located within the orthographic projection of the second gate on the substrate. Alternatively, the first active layer is disposed on the side of the second active layer away from the substrate, and the orthographic projection of the second transistor on the substrate overlaps with the orthographic projection of the first transistor on the substrate. Alternatively, the second active layer is disposed on the side of the first active layer away from the substrate, and the orthographic projection of the second transistor on the substrate overlaps with the orthographic projection of the first transistor on the substrate. The first connecting conductor layer further includes a sixth connecting portion and a seventh connecting portion, wherein the sixth connecting portion is connected to the third conductor portion and the seventh connecting portion is connected to the fourth conductor portion.

22. The array substrate according to claim 19, wherein, The first transistor includes two first gates, which are disposed on opposite sides of the first channel portion along a third direction; and / or, the second transistor includes two second gates, which are disposed on opposite sides of the second channel portion along a third direction; the third direction is perpendicular to the substrate.

23. The array substrate according to claim 19, wherein, The first active layer and the second active layer are spaced apart, or the first active layer is connected to the second active layer.

24. The array substrate according to claim 20, wherein, The array substrate further includes: The third transistor is an oxide transistor, and its orthogonal projection on the substrate overlaps with the CMOS structure, or its orthogonal projection on the substrate does not overlap with the CMOS structure.

25. A display device, wherein, include: The array substrate according to any one of claims 1 to 24.

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