Semiconductor device, manufacturing method, power module, power conversion circuit and vehicle
By designing semiconductor device structures in SiC devices and utilizing the bonding of the first and second wafers and deep region design, the problem of insufficient voltage resistance of SiC devices is solved, achieving high voltage resistance and low on-resistance, and simplifying the manufacturing process.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- YOFC ADVANCED SEMICONDUCTOR (WUHAN) CO LTD
- Filing Date
- 2025-07-25
- Publication Date
- 2026-07-23
AI Technical Summary
SiC devices have poor voltage withstand capability, and existing processes make it difficult to improve voltage withstand capability while reducing specific on-resistance.
The semiconductor device structure design includes bonding of a first wafer structure and a second wafer structure. By setting a gate in the first trench and setting a deeper second region in the second wafer structure, combined with the ion concentration difference between the epitaxial layer and the well region, a vertical conductive channel is formed, reducing the fabrication difficulty of deep trenches.
This improves the voltage resistance of SiC devices, reduces specific on-resistance, simplifies the manufacturing process, shortens the production cycle, and increases production efficiency.
Smart Images
Figure CN2025110638_23072026_PF_FP_ABST
Abstract
Description
Semiconductor devices, manufacturing methods, power modules, power conversion circuits, and vehicles
[0001] This application claims priority to Chinese Patent Application No. 202510073109.6, filed with the Chinese Patent Office on January 17, 2025, the entire contents of which are incorporated herein by reference. Technical Field
[0002] This application relates to the field of semiconductor device technology, such as semiconductor devices, manufacturing methods, power modules, power conversion circuits, and vehicles. Background Technology
[0003] Power devices can be silicon carbide (SiC) power devices. Compared with silicon (Si) materials, silicon carbide materials have unique performance advantages. They can have higher doping with thinner epitaxial thickness and have lower intrinsic carrier concentration. They also have excellent voltage withstand characteristics and thermal conductivity. Therefore, silicon carbide devices are more suitable for current and future power electronics applications than traditional silicon devices.
[0004] However, the manufacturing process of SiC devices is still immature, and their voltage withstand capability needs improvement. To achieve stronger voltage withstand capability, a trench-type device structure design is typically used. Trench-type devices usually employ ion implantation to form part of their structure, but the shallow implantation depth of ions in the device limits its voltage withstand capability. Increasing the number or depth of trenches leads to higher specific on-resistance and greater manufacturing difficulty. The problem of insufficient voltage withstand capability in SiC devices has become a pressing technical issue that needs to be addressed in the industry. Summary of the Invention
[0005] This application provides semiconductor devices, manufacturing methods, power modules, power conversion circuits, and vehicles to address the problem of poor voltage resistance in SiC devices.
[0006] This application provides a semiconductor device, comprising: a semiconductor body, the semiconductor body including a first wafer structure and a second wafer structure, the first wafer structure including a first surface and a second surface disposed opposite to each other, the second wafer structure including a third surface and a fourth surface disposed opposite to each other, the second surface and the third surface being bonded to each other; the first wafer structure further including a well region and a first region, the first region being disposed on the first surface, the well region being disposed on the side of the first region away from the first surface, the first surface also having a first trench, the first trench extending from the first surface into the first wafer structure; the first region having a first conductivity type, the well region having a second conductivity type; the second wafer structure further including a second region, the second region being disposed on the third surface, the second region having a second conductivity type, the orthographic projection of the second region on the fourth surface at least partially overlapping the orthographic projection of the first trench on the fourth surface; a gate, located within the first trench; a drain, located on the fourth surface; and a source, located on the first surface.
[0007] In one embodiment, the first wafer structure includes: a first epitaxial layer having the same conductivity type as the first region; and a first trench penetrating the first region, the well region, and a portion of the first epitaxial layer.
[0008] In one embodiment, the first wafer structure further includes a first insulating layer; the first insulating layer is disposed inside the first trench, and the gate is disposed on the side of the first insulating layer away from the inner wall of the first trench.
[0009] In one embodiment, the first wafer structure further includes: a third region disposed on the first surface, the third region penetrating the first region and a portion of the well region, the third region being of a second conductivity type; the ion concentration of the third region being greater than the ion concentration of the well region.
[0010] In one embodiment, the second wafer structure further includes: a substrate disposed on a fourth surface; a second epitaxial layer disposed on the side of the substrate away from the fourth surface, wherein the conductivity type of the second epitaxial layer is the same as that of the substrate, and the substrate is of a first conductivity type; a second region extending into the second epitaxial layer; and the ion concentration of the first epitaxial layer is greater than or equal to the ion concentration of the second epitaxial layer.
[0011] In one embodiment, the second wafer structure further includes: a second trench disposed on the third surface of the second wafer structure; the second trench penetrating a portion of the second epitaxial layer; the second region located on the sidewall and bottom of the second trench; and a planarization layer disposed within the second trench, wherein the side of the planarization layer away from the substrate is flush with the third surface.
[0012] This application also provides a method for fabricating a semiconductor device, comprising: providing a semiconductor body; the semiconductor body including a first wafer structure and a second wafer structure, the first wafer structure including a first surface and a second surface disposed opposite to each other, the second wafer structure including a third surface and a fourth surface disposed opposite to each other, the second surface and the third surface being bonded to each other; the first wafer structure further including a well region and a first region, the first region being disposed on the first surface, the well region being disposed on the side of the first region away from the first surface, the first surface also having a first trench, the first trench extending from the first surface into the first wafer structure; the first region having a first conductivity type, the well region having a second conductivity type; the second wafer structure further including a second region, the second region being disposed on the third surface, the second region having a second conductivity type, the orthographic projection of the second region on the fourth surface at least partially overlapping the orthographic projection of the first trench on the fourth surface; forming a gate on the first surface of the semiconductor body; the gate being located in the first trench and extending from the first surface into the semiconductor body; forming a drain on the fourth surface of the semiconductor body; and forming a source on the first surface of the semiconductor body.
[0013] In one embodiment, a semiconductor body is provided, comprising: providing a first wafer structure; providing a second wafer structure; bonding a second surface of the first wafer structure and a third surface of the second wafer structure; wherein the ion concentration in the second region is greater than the ion concentration in the well region.
[0014] In one embodiment, a first wafer structure is provided, comprising: forming a first epitaxial layer on one side of a substrate; the first epitaxial layer having the same conductivity type as a first region; forming a well region on the side of the first epitaxial layer away from the substrate; forming a first region on the side of the well region away from the substrate; the ion concentration of the first region being greater than the ion concentration of the first epitaxial layer; and removing the substrate.
[0015] In one embodiment, a first wafer structure is provided, further comprising: forming a third region on the first surface of the first wafer structure; the third region extending through the first region and a portion of the well region, the third region being of a second conductivity type, and the ion concentration of the third region being greater than the ion concentration of the well region.
[0016] In one embodiment, after forming the first epitaxial layer on one side of the substrate, the method further includes: forming a first trench on a first surface of the first wafer structure; the first trench extending from the first surface into the interior of the first wafer structure; the first trench penetrating a first region, a well region, and a portion of the first epitaxial layer; forming a first insulating layer inside the first trench; and forming a gate on a first surface of the semiconductor body, including: forming the gate on the side of the first insulating layer away from the inner wall of the first trench.
[0017] In one embodiment, a second wafer structure is provided, comprising: forming a second epitaxial layer on one side of a substrate; the second epitaxial layer having the same conductivity type as the substrate; the substrate having a first conductivity type; forming a second region extending from a surface of the second epitaxial layer away from the substrate into the second epitaxial layer; and the ion concentration of the first epitaxial layer being greater than or equal to the ion concentration of the second epitaxial layer.
[0018] In one embodiment, a second wafer structure is provided, comprising: forming a second epitaxial layer on one side of a substrate; forming a second trench on the side of the second epitaxial layer away from the substrate; the second trench penetrating a portion of the second epitaxial layer; forming a second region on the sidewalls and bottom of the second trench; forming a planarization layer within the second trench; and the side of the planarization layer away from the substrate being flush with a third surface.
[0019] This application also provides a power module, including a substrate and at least one of the above-described semiconductor devices, wherein the substrate is configured to support the semiconductor devices.
[0020] This application also provides a power conversion circuit, which is configured to perform one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one of the above-mentioned semiconductor devices, and the semiconductor device is electrically connected to the circuit board.
[0021] This application also provides a vehicle including a load and the aforementioned power conversion circuit, wherein the power conversion circuit is configured to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load. Attached Figure Description
[0022] Figure 1 is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application;
[0023] Figure 2 is a schematic diagram of another semiconductor device provided in an embodiment of this application;
[0024] Figure 3 is a schematic diagram of the structure of another semiconductor device provided in an embodiment of this application;
[0025] Figure 4 is a schematic diagram of the structure of another semiconductor device provided in an embodiment of this application;
[0026] Figure 5 is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application;
[0027] Figure 6 is a schematic diagram of the intermediate structure of the first wafer structure of a semiconductor device provided in an embodiment of this application;
[0028] Figure 7 is a schematic diagram of the intermediate structure of the first wafer structure of another semiconductor device provided in an embodiment of this application;
[0029] Figure 8 is a schematic diagram of the intermediate structure of the first wafer structure of another semiconductor device provided in the embodiments of this application;
[0030] Figure 9 is a schematic diagram of the intermediate structure of the first wafer structure of another semiconductor device provided in the embodiments of this application;
[0031] Figure 10 is a schematic diagram of the intermediate structure of the first wafer structure of another semiconductor device provided in the embodiments of this application;
[0032] Figure 11 is a schematic diagram of the intermediate structure of the first wafer structure of another semiconductor device provided in the embodiments of this application;
[0033] Figure 12 is a schematic diagram of the intermediate structure of the second wafer structure of a semiconductor device provided in an embodiment of this application;
[0034] Figure 13 is a schematic diagram of the intermediate structure of the second wafer structure of another semiconductor device provided in an embodiment of this application;
[0035] Figure 14 is a detailed flowchart of S110 in Figure 5;
[0036] Figure 15 is a detailed flowchart of S111 in Figure 14;
[0037] Figure 16 is a detailed flowchart of S111 in Figure 14;
[0038] Figure 17 is a detailed flowchart of S112 in Figure 14;
[0039] Figure 18 is a detailed flowchart of S112 in Figure 14;
[0040] Figure 19 is a schematic diagram of the intermediate structure of the second wafer structure of another semiconductor device provided in the embodiments of this application. Detailed Implementation
[0041] This application provides a semiconductor device. Figure 1 is a schematic diagram of the structure of a semiconductor device provided in this application. Referring to Figure 1, the semiconductor device provided in this application includes a semiconductor body 10, which includes a first wafer structure 20 and a second wafer structure 30. The first wafer structure 20 includes a first surface M1 and a second surface M2 disposed opposite to each other. The second wafer structure 30 includes a third surface M3 and a fourth surface M4 disposed opposite to each other. The second surface M2 and the third surface M3 are bonded to each other. The first wafer structure 20 also includes a well region 21 and a first region 22. The first region 22 is disposed on the first surface M1, and the well region 21 is disposed on the side of the first region 22 away from the first surface M1. The surface M1 is also provided with a first trench 23, which extends from the first surface M1 into the first wafer structure 20; the first region 22 is of a first conductivity type, and the well region 21 is of a second conductivity type; the second wafer structure 30 also includes a second region 31, which is disposed on the third surface M3 and is of a second conductivity type. The orthographic projection of the second region 31 on the fourth surface M4 at least partially overlaps with the orthographic projection of the first trench 23 on the fourth surface M4; the gate 40 is located in the first trench 23; the drain 50 is located on the fourth surface M4; and the source 60 is located on the first surface M1.
[0042] The semiconductor device provided in this embodiment can be a silicon carbide trench metal-oxide-semiconductor field-effect transistor (MOSFET). Referring to FIG1, the first wafer structure 20 may include a well region 21 and a first region 22. The first region 22 is of a first conductivity type, and the well region 21 is of a second conductivity type. The well region 21 and the first region 22 are configured to form a conductive channel for the semiconductor device. The well region 21 can be formed by epitaxial growth or by ion implantation. The first region 22 can be formed by ion implantation or epitaxial growth. By adjusting the dimensions of the well region 21 and the first region 22, the channel length can be controlled, the on-resistance of the device can be reduced, and the stability of the threshold voltage of the device can be improved.
[0043] A first trench 23 can be etched to form on the first surface M1 of the first wafer structure 20. The first trench 23 extends from the first surface M1 into the interior of the first wafer structure 20. A gate 40 is disposed within the first trench 23. The gate 40 extends from the first surface M1 into the semiconductor body 10. This configuration allows the semiconductor device to have a higher channel mobility. Setting the conductive channel as a vertical channel can eliminate the junction field-effect transistor (JFET) region, resulting in lower on-resistance of the semiconductor device. A higher density of vertical gates can reduce cell spacing and increase current density.
[0044] The source electrode 60 can be a metal conductive layer. For example, the metal conductive layer can be titanium (Ti), nickel (Ni), or silver (Ag), etc.
[0045] A second region 31 is disposed on the third surface M3 of the second wafer structure 30. The second region 31 is of a second conductivity type. After the second surface M2 of the first wafer structure 20 and the third surface M3 of the second wafer structure 30 are bonded together, the second region 31 disposed on the third surface M3 is located inside the semiconductor body 10, allowing the second region 31 to be located at a great depth within the semiconductor body 10. Due to the greater depth of the second region 31, the withstand voltage capability of the semiconductor body 10 is effectively improved. Since the second region 31 is located within the second wafer structure 30, the second region 31 does not require trenching, or does not require very deep trenching, thereby reducing the difficulty of fabricating deep trenches.
[0046] By placing the second region 31 within the second wafer structure 30, the orthographic projection of the second region 31 onto the fourth surface M4 at least partially overlaps with the orthographic projection of the first trench 23 onto the fourth surface M4. This arrangement avoids wasting the area of the second region 31 in the width direction of the semiconductor body 10, thereby effectively improving the specific on-resistance of the semiconductor device.
[0047] Furthermore, the first wafer structure 20 and the second wafer structure 30 can be fabricated simultaneously, which greatly shortens the production cycle of semiconductor devices.
[0048] A drain 50 is disposed on the fourth surface M4 of the second wafer structure 30. The drain 50 can be a metal conductive layer. For example, the metal conductive layer can be Ti, Ni, or Ag, etc. The drain 50 is located on the fourth surface M4 of the second wafer structure 30.
[0049] The semiconductor body 10 of the semiconductor device provided in this embodiment includes a first wafer structure 20 and a second wafer structure 30. A first surface M1 of the first wafer structure 20 is provided with a well region 21 and a first region 22, and a third surface M3 of the second wafer structure 30 is provided with a second region 31. The first region 22 and the well region 21 are configured to form a conductive channel. The second region 31 disposed on the third surface M3 of the second semiconductor can increase the depth and width of the depletion region, thereby improving the voltage resistance of the semiconductor device. Since the orthographic projection of the second region 31 onto the fourth surface M4 at least partially overlaps with the orthographic projection of the first trench 23 onto the fourth surface M4, the second region 31 is disposed along the thickness direction of the semiconductor device, reducing the size of the second region 31 occupying the width direction of the semiconductor device, thereby improving the specific on-resistance of the semiconductor device. This configuration facilitates the simultaneous fabrication of the first wafer structure 20 and the second wafer structure 30, greatly shortening the production cycle of the semiconductor device, improving production efficiency, and reducing the difficulty of the semiconductor device fabrication process.
[0050] Figure 2 is a schematic diagram of another semiconductor device provided in an embodiment of this application. Based on the above embodiment, referring to Figure 2, the first wafer structure 20 includes: a first epitaxial layer 24, the first epitaxial layer 24 having the same conductivity type as the first region 22; a first trench 23 penetrating the first region 22, the well region 21, and part of the first epitaxial layer 24; the ion concentration in the first region 22 is greater than the ion concentration in the first epitaxial layer 24; and the ion concentration in the second region 31 is greater than the ion concentration in the well region 21.
[0051] The first epitaxial layer 24 can be grown epitaxially. The material of the first epitaxial layer 24 can be silicon carbide. Referring to Figure 2, if the semiconductor device is an N-type device, the first epitaxial layer 24 can be an N-epitaxial layer, for example, an N-silicon carbide epitaxial layer. The first region 22 is an N+ type region, and the second region 31 is a P+ type region. If the semiconductor device is a P-type device, then the first epitaxial layer 24 is a P-epitaxial layer, for example, a P-silicon carbide epitaxial layer. The first region 22 is a P+ type region, and the second region 31 is an N+ type region.
[0052] The material of well region 21 can be silicon carbide. Silicon and carbon elements are provided during the growth of silicon carbide. Using silane and propane as reaction gas sources, and boron or aluminum as dopant elements, well region 21 is formed on the side of the first epitaxial layer 24 away from the second surface M2. If the semiconductor device is an N-type power device, well region 21 can be a P-type well region 21.
[0053] Based on the above embodiments, referring to FIG2, the first wafer structure 20 further includes a first insulating layer 41; the first insulating layer 41 is disposed inside the first trench 23, and the gate 40 is disposed on the side of the first insulating layer 41 away from the inner wall of the first trench 23.
[0054] The first insulating layer 41 can be a gate oxide layer. The gate oxide layer can be a high dielectric constant (K) material. The gate 40 can be a polysilicon layer. Referring again to Figure 2, a first trench 23 can be etched to form the first surface M1 of the first wafer structure 20. The first trench 23 extends from the first surface M1 into the interior of the first wafer structure 20. The extension of the gate 40 from the first surface M1 into the interior of the first wafer structure 20 allows the semiconductor device to have a higher channel mobility. The vertical conductive channel can eliminate the junction field-effect transistor region, resulting in a lower on-resistance of the semiconductor device. In addition, the high density of vertical gates 40 can reduce the cell spacing of the semiconductor device and increase the current density.
[0055] Figure 3 is a schematic diagram of another semiconductor device provided in an embodiment of this application. Based on the above embodiment, referring to Figure 3, the first wafer structure 20 further includes: a third region 25, which is disposed on the first surface M1, and penetrates the first region 22 and part of the well region 21. The third region 25 is of a second conductivity type; the ion concentration of the third region 25 is greater than the ion concentration of the well region 21.
[0056] A third region 25 is provided on the first surface M1 of the first wafer structure 20. For example, if the semiconductor device is an N-type power device, then the second region 31 is a P+ type region and the well region 21 is a P-well. If the semiconductor device is a P-type power device, then the second region 31 is an N+ type region and the well region 21 is an N-well.
[0057] Based on the above embodiments, referring to FIG3, the second wafer structure 30 may further include: a substrate 32 disposed on the fourth surface M4; a second epitaxial layer 33 disposed on the side of the substrate 32 away from the fourth surface M4, wherein the conductivity type of the second epitaxial layer 33 is the same as that of the substrate 32, and the substrate 32 is of the first conductivity type; a second region 31 extending into the second epitaxial layer 33; and the ion concentration of the first epitaxial layer 24 being greater than or equal to the ion concentration of the second epitaxial layer 33.
[0058] The second wafer structure 30 may include a substrate 32, a second epitaxial layer 33, and a second region 31. The substrate 32 may be a silicon substrate or a silicon carbide substrate. Referring to FIG3, if the semiconductor device is an N-type device, then the substrate 32 is an N+ substrate, for example, an N+ silicon carbide substrate. The second epitaxial layer 33 is an N- epitaxial layer, for example, an N- silicon carbide epitaxial layer. If the semiconductor device is a P-type device, then the substrate 32 is a P+ substrate, and the second epitaxial layer 33 is a P- epitaxial layer. The second epitaxial layer 33 is formed on one side of the substrate 32.
[0059] Figure 4 is a schematic diagram of another semiconductor device provided in an embodiment of this application. Based on the above embodiment, referring to Figure 4, the second wafer structure 30 may further include: a second trench 34 disposed on the third surface M3 of the second wafer structure 30; the second trench 34 penetrating a portion of the second epitaxial layer 33; the second region 31 located on the sidewall and bottom of the second trench 34; and a planarization layer 35 disposed in the second trench 34, the side of the planarization layer 35 away from the substrate 32 being flush with the third surface M3.
[0060] A second region 31 is formed on the sidewalls and bottom of the second trench 34. The second region 31 is of a second conductivity type. The second region 31 can be formed on the sidewalls and bottom of the second trench 34 using an ion implantation process. If the semiconductor device is an N-type power device, then the second region 31 is a P+ type region with a cavity pressure of 10. 3 ~10 7 The energy for P+ ion implantation is 10 keV to 800 keV, and the ion implantation dose is approximately 1 × 10⁻⁶ Pa. 14～30 .
[0061] A planarization layer 35 is formed inside the second trench 34. The planarization layer 35 can be formed using methods such as atomic layer deposition (ALD). The planarization layer 35 fills the second trench 34. The material of the planarization layer 35 can include non-conductive materials, and can include organic or inorganic materials. The planarization layer 35 is flush with the third surface M3, facilitating the bonding of the third surface M3 to the second surface M2 and improving the reliability of the semiconductor device.
[0062] Figure 5 is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application. Based on the above embodiments, and referring to Figures 1 and 5, the method for fabricating a semiconductor device provided in this embodiment includes:
[0063] S110, Provide a semiconductor body 10; the semiconductor body 10 includes a first wafer structure 20 and a second wafer structure 30, the first wafer structure 20 includes a first surface M1 and a second surface M2 disposed opposite to each other, the second wafer structure 30 includes a third surface M3 and a fourth surface M4 disposed opposite to each other, the second surface M2 and the third surface M3 are bonded to each other; the first wafer structure 20 also includes a well region 21 and a first region 22, the first region 22 is disposed on the first surface M1, the well region 21 is disposed on the side of the first region 22 away from the first surface M1, the first surface M1 is also provided with a first trench 23, the first trench 23 extends from the first surface M1 into the first wafer structure 20; the first region 22 is of a first conductivity type, the well region 21 is of a second conductivity type; the second wafer structure 30 also includes a second region 31, the second region 31 is disposed on the third surface M3, the second region 31 is of a second conductivity type, the orthographic projection of the second region 31 on the fourth surface M4 at least partially overlaps with the orthographic projection of the first trench 23 on the fourth surface M4.
[0064] Figure 6 is a schematic diagram of the intermediate structure of a first wafer structure of a semiconductor device according to an embodiment of the present invention. Figure 7 is a schematic diagram of the intermediate structure of a first wafer structure of another semiconductor device according to an embodiment of the present invention. Figure 8 is a schematic diagram of the intermediate structure of a first wafer structure of yet another semiconductor device according to an embodiment of the present invention. Figure 9 is a schematic diagram of the intermediate structure of a first wafer structure of yet another semiconductor device according to an embodiment of the present invention. Figure 10 is a schematic diagram of the intermediate structure of a first wafer structure of yet another semiconductor device according to an embodiment of the present invention. Figure 11 is a schematic diagram of the intermediate structure of a first wafer structure of yet another semiconductor device according to an embodiment of the present invention. Figure 12 is a schematic diagram of the intermediate structure of a second wafer structure of a semiconductor device according to an embodiment of the present invention. Figure 13 is a schematic diagram of the intermediate structure of a second wafer structure of another semiconductor device according to an embodiment of the present invention. Referring to Figures 1, 5, and 6 to 13, providing a semiconductor body 10 may include providing a first wafer structure 20 and providing a second wafer structure 30.
[0065] The first wafer structure 20 can be formed first, followed by the second wafer structure 30. Alternatively, the second wafer structure 30 can be formed first, followed by the first wafer structure 20. Or, the first wafer structure 20 and the second wafer structure 30 can be formed simultaneously. The second surface M2 of the first wafer structure 20 and the third surface M3 of the second wafer structure 30 are bonded together to form the semiconductor body 10.
[0066] By fabricating the first wafer structure 20 and the second wafer structure 30 simultaneously, the production cycle of semiconductor devices is greatly shortened.
[0067] S120, A gate 40 is formed on the first surface M1 of the semiconductor body 10; the gate 40 is located in the first trench 23 and extends from the first surface M1 into the semiconductor body 10.
[0068] The first insulating layer 41 can be a gate oxide layer. The gate oxide layer can be a high dielectric constant (K) material. The gate 40 can be a polysilicon layer. A first trench 23 can be etched to form the first surface M1 of the first wafer structure 20. The first trench 23 extends from the first surface M1 into the interior of the first wafer structure 20. The extension of the gate 40 from the first surface M1 into the interior of the first wafer structure 20 allows the semiconductor device to have a higher channel mobility. The conductive channel is a vertical channel, which can eliminate the junction field-effect transistor region and reduce the on-resistance of the semiconductor device. The high density of vertical gates 40 can reduce the cell spacing of the semiconductor device and increase the current density.
[0069] S130, a drain 50 is formed on the fourth surface M4 of the semiconductor body 10.
[0070] The drain 50 can be formed on the fourth surface M4 of the second wafer structure 30 by means of sputtering or other methods. The drain 50 is a metal conductive layer. For example, the metal conductive layer can be TiNi or Ag, etc. The fourth surface M4 of the second wafer structure 30 can be thinned first, and then the drain 50 can be formed by means of sputtering or other methods.
[0071] S140, a source electrode 60 is formed on the first surface M1 of the semiconductor body 10.
[0072] The source electrode 60 can be formed on the first surface M1 of the first wafer structure 20 by means of a sputter or similar method. The source electrode 60 is a metal conductive layer. For example, the metal conductive layer can be Ti, Ni, or Ag, etc. The source electrode 60 is located on the first surface M1.
[0073] Referring again to Figures 10 and 11, before the source 60 is formed on the first surface M1 of the semiconductor body 10, an interlayer insulating layer 61 may also be formed on the side of the gate 40 away from the second surface.
[0074] The semiconductor body 10 of the semiconductor device provided in this embodiment includes a first wafer structure 20 and a second wafer structure 30. A first surface M1 of the first wafer structure 20 is provided with a well region 21 and a first region 22, and a third surface M3 of the second wafer structure 30 is provided with a second region 31. The first region 22 and the well region 21 are configured to form a conductive channel. The second region 31 disposed on the third surface M3 of the second semiconductor can increase the depth and width of the depletion region, thereby improving the voltage resistance of the semiconductor device. Since the orthographic projection of the second region 31 onto the fourth surface M4 at least partially overlaps with the orthographic projection of the first trench 23 onto the fourth surface M4, the second region 31 is disposed along the thickness direction of the semiconductor device, reducing the size of the second region 31 occupying the width direction of the semiconductor device, thereby improving the specific on-resistance of the semiconductor device. This configuration facilitates the simultaneous fabrication of the first wafer structure 20 and the second wafer structure 30, greatly shortening the production cycle of the semiconductor device and reducing the difficulty of the semiconductor device fabrication process.
[0075] Figure 14 is a detailed flowchart of S110 in Figure 5. Based on the above embodiments, and referring to Figures 3 to 5 and Figure 14, S110, providing the semiconductor body 10, includes:
[0076] S111. A first wafer structure 20 is provided. The first wafer structure 20 includes a first surface M1 and a second surface M2 disposed opposite to each other. The first wafer structure 20 also includes a well region 21 and a first region 22. The first region 22 is disposed on the first surface M1, and the well region 21 is disposed on the side of the first region 22 away from the first surface M1. The first surface M1 is also provided with a first trench 23, which extends from the first surface M1 into the first wafer structure 20. The first region 22 is of a first conductivity type, and the well region 21 is of a second conductivity type.
[0077] A well region 21 and a first region 22 are formed on the first surface M1 of the first wafer structure 20. The well region 21 and the first region 22 can be formed by epitaxial growth or by ion implantation, without any limitation herein. A first trench 23 is formed on the first surface M1 of the first wafer structure 20. The first trench 23 extends from the first surface M1 into the first wafer structure 20.
[0078] S112. A second wafer structure 30 is provided; the second wafer structure 30 includes a third surface M3 and a fourth surface M4 disposed opposite to each other, and the second wafer structure 30 also includes a second region 31 disposed on the third surface M3, and the second region 31 is a second conductivity type.
[0079] A second region 31 is formed on the third surface M3 of the second wafer structure 30. The second region 31 can be formed by epitaxial growth or by ion implantation. The second region 31 is of a second conductivity type.
[0080] S113, the second surface M2 of the first wafer structure 20 and the third surface M3 of the second wafer structure 30 are bonded together; the orthographic projection of the second region 31 on the fourth surface M4 at least partially overlaps with the orthographic projection of the first trench 23 on the fourth surface M4; the ion concentration of the second region 31 is greater than the ion concentration of the well region 21.
[0081] Referring to Figures 1 and 14, the second surface M2 of the first wafer structure 20 and the third surface M3 of the second wafer structure 30 can be bonded together using bonding adhesive. After the second surface M2 of the first wafer structure 20 and the third surface M3 of the second wafer structure 30 are bonded together, the second region 31 disposed on the third surface M3 is located inside the semiconductor body 10, allowing the second region 31 to be located at a considerable depth within the semiconductor body 10. Due to the greater depth of the second region 31, the withstand voltage capability of the semiconductor body 10 is effectively improved, reducing the fabrication difficulty of deep trenches.
[0082] After the second surface M2 of the first wafer structure 20 and the third surface M3 of the second wafer structure 30 are bonded to each other, the orthographic projection of the second region 31 on the fourth surface M4 at least partially overlaps with the orthographic projection of the first trench 23 on the fourth surface M4, thus avoiding the second region 31 occupying the width dimension of the semiconductor body 10, thereby improving the specific on-resistance of the semiconductor device.
[0083] Figure 15 is a detailed flowchart of step S111 in Figure 14. Based on the above embodiments, and referring to Figures 3 to 5, Figure 14 and 15, step S111 provides a first wafer structure 20, including:
[0084] S1111, A first epitaxial layer 24 is formed on one side of the substrate 26; the first epitaxial layer 24 has the same conductivity type as the first region 22.
[0085] A substrate 26 is provided, on one side of which a first epitaxial layer 24 can be formed by epitaxial growth. The material of the first epitaxial layer 24 can be silicon carbide. The substrate 26 can be a silicon substrate or a silicon carbide substrate.
[0086] S1112, a well region 21 is formed on the side of the first epitaxial layer 24 away from the substrate 26.
[0087] A well region 21 can be formed on the side of the first epitaxial layer 24 away from the substrate 26. Forming the well region 21 by epitaxial growth can reduce damage caused by ion implantation, and can precisely control the film thickness and ion concentration of the well region 21, ensuring the stability of the ion concentration and facilitating the control of the channel length.
[0088] S1113, A first region 22 is formed on the side of the well region 21 away from the substrate 26; the ion concentration of the first region 22 is greater than the ion concentration of the first epitaxial layer 24.
[0089] A first region 22 can be formed on the side of the well region 21 away from the substrate 26. The first region 22 is located on the first surface M1 of the first wafer structure 20. Forming the first region 22 by epitaxial growth can reduce damage caused by ion implantation and precisely control the film thickness and ion concentration of the well region 21 and the first region 22, ensuring the stability of the ion concentration. It can also control the channel length, reduce the on-resistance of the semiconductor device, and improve the stability of the threshold voltage of the semiconductor device. The well region 21 and the first region 22 are configured to form a conductive channel.
[0090] S1114, Remove substrate 26.
[0091] Removing the substrate 26 allows the first epitaxial layer 24 to serve as the second surface M2 of the first wafer structure 20. This configuration facilitates bonding the surface of the first epitaxial layer 24 away from the first region 22 to the second wafer structure 30.
[0092] In another embodiment, this application provides a method for fabricating a semiconductor device based on the above embodiments. The fabrication method also includes processes S1111-S1114 and S111-S113, as well as the formation of a well region 21, a first region 22, and a second region 31.
[0093] The difference between the preparation method and the one described in the above embodiments is that:
[0094] Continuing with Figures 9 to 11, Figure 15, S111, providing the first wafer structure, also includes:
[0095] A third region 25 is formed on the first surface M1 of the first wafer structure 20; the third region 25 penetrates the first region 22 and part of the well region 21, the third region 25 is of the second conductivity type, and the ion concentration of the third region 25 is greater than the ion concentration of the well region 21.
[0096] A third region 25 can be formed on the first surface M1 of the first wafer structure 20 using an ion implantation process. For example, if the semiconductor device is an N-type power device, then the third region 25 is a P+ type region and the well region 21 is a P-well. If the semiconductor device is a P-type power device, then the third region 25 is an N+ type region and the well region 21 is an N-well.
[0097] Figure 16 is a detailed flowchart of step S111 in Figure 14. Based on the above embodiments, and referring to Figures 3 to 5, Figure 14, and Figure 16, step S111, providing the first wafer structure 20, may include:
[0098] S121, a first trench 23 is formed on the first surface M1 of the first wafer structure 20; the first trench 23 extends from the first surface M1 into the interior of the first wafer structure 20; the first trench 23 penetrates the first region 22, the well region 21 and part of the first epitaxial layer 24.
[0099] The first trench 23 is formed on the first surface M1 of the first wafer structure 20 by an etching process.
[0100] S122, A first insulating layer 41 is formed inside the first trench 23.
[0101] A first insulating layer 41 is deposited inside the first trench 23 using methods such as atomic layer deposition (ALD). The first insulating layer 41 inside the first trench 23 can be a gate oxide layer. The gate oxide layer can be a high-k material, which can improve the electron mobility at the gate 40 interface and reduce the on-resistance of the semiconductor device.
[0102] Based on the above embodiments, and continuing to refer to Figures 5 and 9, S120, forming a gate 40 on the first surface M1 of the semiconductor body 10 may include: forming the gate 40 on the side of the first insulating layer 41 away from the inner wall of the first trench 23.
[0103] The gate 40 is deposited by methods such as low-pressure chemical vapor deposition (LPCVD), and the material of the gate 40 can be polycrystalline silicon.
[0104] Figure 17 is a detailed flowchart of S112 in Figure 14. Based on the above embodiments, and referring to Figures 3 to 5, Figures 12 to 14, and Figure 17, S112 provides a second wafer structure 30, including:
[0105] S1121. A second epitaxial layer 33 is formed on one side of the substrate 32; the second epitaxial layer 33 has the same conductivity type as the substrate 32; the substrate 32 has the first conductivity type.
[0106] A substrate 32 is provided. The substrate 32 may be a silicon substrate 32 or a silicon carbide substrate 32. A second epitaxial layer 33 is formed on one side of the substrate 32. The material of the second epitaxial layer 33 may be silicon carbide.
[0107] S1122, Form a second region 31 extending from the surface of the second epitaxial layer 33 away from the substrate 32 into the second epitaxial layer 33; the second region 31 is of a second conductivity type; the ion concentration of the first epitaxial layer 24 is greater than or equal to the ion concentration of the second epitaxial layer 33.
[0108] A second region 31 is formed on the side of the second epitaxial layer 33 away from the substrate 32. For example, if the material of the second region 31 is silicon carbide, silicon and carbon elements are provided during the growth of the silicon carbide, and boron or aluminum elements are used as dopant elements to form the second region 31 on the side of the second epitaxial layer 33 away from the substrate 32, using silane and propane as reaction gas sources. If the semiconductor device is an N-type power device, the second region 31 can be a P+ type region.
[0109] The ion concentrations of the first epitaxial layer 24 and the second epitaxial layer 33 can be set differently as needed. For example, the ion concentration of the first epitaxial layer 24 can be set to be greater than or equal to the ion concentration of the second epitaxial layer 33. This setting facilitates the adjustment of the leakage current and on-resistance of the semiconductor device as needed.
[0110] Figure 18 is a detailed flowchart of step S112 in Figure 14. Figure 19 is a schematic diagram of an intermediate structure of a second wafer structure of a semiconductor device provided in an embodiment of this application. Based on the above embodiments, and referring to Figures 4, 18, and 19, the difference from the fabrication method of the above embodiments is that: S112, providing a second wafer structure, includes:
[0111] S11201, A second epitaxial layer 33 is formed on one side of the substrate 32; the second epitaxial layer 33 has the same conductivity type as the substrate 32; the substrate 32 has the first conductivity type.
[0112] S11202, a second trench 34 is formed on the side of the second epitaxial layer 33 away from the substrate 32; the first trench 23 penetrates a portion of the second epitaxial layer 33.
[0113] The second trench 34 can be formed by etching. The second trench 34 is formed by etching on the side of the second epitaxial layer 33 away from the substrate 32.
[0114] S11203, A second region 31 is formed on the sidewall and bottom of the second trench 34; the second region 31 is of a second conductivity type.
[0115] A second region 31 can be formed by ion implantation on the third surface M3 of the second epitaxial layer 33, the side surface and the bottom surface of the second trench 34. For example, if the semiconductor device is an N-type power device, then the second region 31 is a P+ type region and the well region 21 is a P-well. If the semiconductor device is a P-type power device, then the second region 31 is an N+ type region and the well region 21 is an N-well.
[0116] S11204, A planarization layer 35 is formed in the second trench 34; the side of the planarization layer 35 away from the substrate 32 is flush with the third surface M3.
[0117] A planarization layer 35 can be deposited inside the second trench 34 using methods such as atomic layer deposition (ALD). The planarization layer 35 inside the second trench 34 can be a non-conductive material layer, such as an oxide layer. The side of the planarization layer 35 away from the substrate 32 is flush with the third surface M3, so that the second epitaxial layer 33, the second region 31, and the planarization layer 35 together form the third surface M3 of the second wafer structure 30.
[0118] Based on the above embodiments, this application provides a power module including a substrate and at least one semiconductor device as described in any of the above embodiments, wherein the substrate is configured to support the semiconductor device. The power module provided by this application has the same beneficial effects as the semiconductor device described in any of the embodiments of this application, and will not be repeated here.
[0119] Based on the above embodiments, this application provides a power conversion circuit. The power conversion circuit is configured to perform one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and at least one semiconductor device as described in any of the above embodiments, with the semiconductor device electrically connected to the circuit board. The power conversion circuit provided by this application has the same beneficial effects as the semiconductor device described in any of the embodiments of this application, and will not be repeated here.
[0120] Based on the above embodiments, this application provides a vehicle including a load and the power conversion circuit proposed in any of the above embodiments. The power conversion circuit is configured to convert AC to DC, AC to AC, DC to DC, or DC to AC before inputting it to the load. The vehicle provided by this application includes the power conversion circuit proposed in any of the above embodiments, and has the same beneficial effects as the semiconductor device described in any of the embodiments of this application, which will not be repeated here.
Claims
1. A semiconductor device, comprising: The semiconductor body (10) includes a first wafer structure (20) and a second wafer structure (30). The first wafer structure (20) includes a first surface (M1) and a second surface (M2) disposed opposite to each other. The second wafer structure (30) includes a third surface (M3) and a fourth surface (M4) disposed opposite to each other. The second surface (M2) and the third surface (M3) are bonded to each other. The first wafer structure (20) further includes a well region (21) and a first region (22). The first region (22) is disposed on the first surface (M1), and the well region (21) is disposed on the side of the first region (22) away from the first surface (M1). The first surface (M1) is also provided with a first trench (23), which extends from the first surface (M1) into the first wafer structure (20). The first region (22) is of a first conductivity type, and the well region (21) is of a second conductivity type. The second wafer structure (30) further includes a second region (31), which is disposed on the third surface (M3). The second region (31) is of the second conductivity type. The orthographic projection of the second region (31) on the fourth surface (M4) at least partially overlaps with the orthographic projection of the first trench (23) on the fourth surface (M4). The gate (40) is located within the first trench (23); Drain (50) is located on the fourth surface (M4); The source electrode (60) is located on the first surface (M1).
2. The semiconductor device according to claim 1, wherein, The first wafer structure (20) includes: The first epitaxial layer (24) has the same conductivity type as the first region (22); The first trench (23) penetrates the first region (22), the well region (21) and part of the first epitaxial layer (24); the ion concentration of the first region (22) is greater than the ion concentration of the first epitaxial layer (24); the ion concentration of the second region (31) is greater than the ion concentration of the well region (21).
3. The semiconductor device according to claim 1, wherein, The first wafer structure (20) further includes a first insulating layer (41); The first insulating layer (41) is disposed inside the first trench (23), and the gate (40) is disposed on the side of the first insulating layer (41) away from the inner wall of the first trench (23).
4. The semiconductor device according to claim 1, wherein, The first wafer structure (20) further includes: A third region (25) is disposed on the first surface (M1), the third region (25) penetrates the first region (22) and part of the well region (21), the third region (25) is of the second conductivity type; the ion concentration of the third region (25) is greater than the ion concentration of the well region (21).
5. The semiconductor device according to claim 2, wherein, The second wafer structure (30) further includes: A substrate (32) is disposed on the fourth surface (M4); A second epitaxial layer (33) is disposed on the side of the substrate (32) away from the fourth surface (M4). The conductivity type of the second epitaxial layer (33) is the same as that of the substrate (32), which is of the first conductivity type. The second region (31) extends into the second epitaxial layer (33). The ion concentration of the first epitaxial layer (24) is greater than or equal to the ion concentration of the second epitaxial layer (33).
6. The semiconductor device according to claim 5, wherein, The second wafer structure (30) further includes: A second trench (34) is disposed on the third surface (M3) of the second wafer structure (30); The second trench (34) penetrates a portion of the second epitaxial layer (33); The second region (31) is located on the sidewall and bottom of the second trench (34); A planarization layer (35) is disposed in the second trench (34), and the side of the planarization layer (35) away from the substrate (32) is flush with the third surface (M3).
7. A method for fabricating a semiconductor device, comprising: A semiconductor body is provided; the semiconductor body includes a first wafer structure and a second wafer structure, the first wafer structure includes a first surface and a second surface disposed opposite to each other, the second wafer structure includes a third surface and a fourth surface disposed opposite to each other, the second surface and the third surface are bonded to each other; the first wafer structure further includes a well region and a first region, the first region is disposed on the first surface, the well region is disposed on the side of the first region away from the first surface, the first surface is further provided with a first trench, the first trench extends from the first surface into the first wafer structure; the first region is of a first conductivity type, the well region is of a second conductivity type; the second wafer structure further includes a second region, the second region is disposed on the third surface, the second region is of the second conductivity type, the orthographic projection of the second region on the fourth surface at least partially overlaps with the orthographic projection of the first trench on the fourth surface; A gate is formed on the first surface of the semiconductor body; the gate is located within the first trench and extends from the first surface into the semiconductor body; A drain electrode is formed on the fourth surface of the semiconductor body; A source electrode is formed on the first surface of the semiconductor body.
8. The method according to claim 7, wherein, The provision of the semiconductor body includes: Provide the first wafer structure; Provide the second wafer structure; The second surface of the first wafer structure and the third surface of the second wafer structure are bonded together; the ion concentration in the second region is greater than the ion concentration in the well region.
9. The method according to claim 8, wherein, Providing the first wafer structure includes: A first epitaxial layer is formed on one side of the substrate; the first epitaxial layer has the same conductivity type as the first region; The well region is formed on the side of the first epitaxial layer away from the substrate; The first region is formed on the side of the well region away from the substrate; the ion concentration of the first region is greater than the ion concentration of the first epitaxial layer; Remove the substrate.
10. The method according to claim 9, wherein, The provision of the first wafer structure further includes: A third region is formed on the first surface of the first wafer structure; the third region extends through the first region and part of the well region, the third region is of the second conductivity type, and the ion concentration of the third region is greater than the ion concentration of the well region.
11. The method of claim 9, further comprising, after forming the first epitaxial layer on one side of the substrate: The first trench is formed on the first surface of the first wafer structure; The first trench extends from the first surface into the interior of the first wafer structure; The first trench penetrates the first region, the well region, and a portion of the first epitaxial layer; A first insulating layer is formed inside the first trench; The formation of a gate on the first surface of the semiconductor body includes: The gate is formed on the side of the first insulating layer away from the inner wall of the first trench.
12. The method according to claim 9, wherein, The provision of the second wafer structure includes: A second epitaxial layer is formed on one side of the substrate; the second epitaxial layer has the same conductivity type as the substrate; the substrate has the first conductivity type. A second region is formed extending from the surface of the second epitaxial layer away from the substrate into the second epitaxial layer; the ion concentration of the first epitaxial layer is greater than or equal to the ion concentration of the second epitaxial layer.
13. The method according to claim 9, wherein, The provision of the second wafer structure includes: A second epitaxial layer is formed on one side of the substrate; A second trench is formed on the side of the second epitaxial layer away from the substrate; the second trench penetrates a portion of the second epitaxial layer; The second region is formed on the sidewalls and bottom of the second trench; A planarization layer is formed within the second trench; the side of the planarization layer away from the substrate is flush with the third surface.
14. A power module comprising a substrate and at least one semiconductor device according to any one of claims 1 to 6, the substrate being configured to support the semiconductor device.
15. A power conversion circuit, the power conversion circuit being configured to perform at least one of the following: current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device according to any one of claims 1 to 6, wherein the semiconductor device is electrically connected to the circuit board.
16. A vehicle comprising a load and the power conversion circuit of claim 15, the power conversion circuit being configured to convert alternating current to direct current, alternating current to alternating current, direct current to direct current, or direct current to alternating current before inputting it to the load.