Image sensor, image acquisition apparatus, and electronic device

Abstract

The present application relates to the technical field of image sensors, and discloses an image sensor, an image acquisition apparatus, and an electronic device. The image sensor comprises a first device layer, a first dielectric layer, a first signal line layer, a second dielectric layer, and a second device layer stacked in sequence; the first device layer comprises a semiconductor substrate, a plurality of photoelectric conversion elements, and a plurality of transfer transistors; the first signal line layer comprises a plurality of transfer control signal lines; and the second device layer comprises a pixel output circuit. The area occupied by the transfer transistors and the pixel output circuit is increased, and the first signal line layer is also further provided between the first device layer and the second device layer. Flexible routing of the first signal line layer is realized, and contact holes connecting the transfer transistors and the transfer control signal lines are also prevented from running through the second device layer. Thus, the area occupied by transistors in the pixel output circuit is increased, thereby achieving high FWC, wide dynamic range, and low-noise performance.

Description

An image sensor, an image acquisition device, and an electronic device.

[0001] Cross-reference of related applications

[0002] This application claims priority to Chinese Patent Application No. 202510076066.7, filed on January 15, 2025, entitled "An Image Sensor, Image Acquisition Device and Electronic Equipment", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of image sensor technology, and in particular to an image sensor, an image acquisition device, and an electronic device. Background Technology

[0004] Image sensors are widely used in digital cameras, mobile phones, and other electronic devices to capture digital images. Traditional image sensors consist of multiple pixels, each comprising a photoelectric conversion element and a pixel circuit. The photoelectric conversion element converts light signals into electrical signals, and the pixel circuit outputs a voltage related to the electrical signal to construct the image. As pixels gradually shrink, the full-well capacity (FWC) of traditional single-layer pixel structures gradually decreases, leading to a smaller dynamic range. To address this, existing technologies split the single-layer pixel structure into two device layers. The first device layer houses the photoelectric conversion element and some transistors in the pixel circuit, while the second device layer houses the remaining transistors in the pixel circuit.

[0005] One current process for forming the first and second device layers involves fabricating them separately on different silicon (Si) wafers to create two independent chips, which are then bonded together to form an image sensor. This results in a relatively thick image sensor, which contradicts the trend towards miniaturization, and also presents problems such as higher cost and larger parasitic capacitance.

[0006] Another process for forming the first and second device layers involves fabricating them sequentially on the same silicon wafer. Then, a back-end of line (BEOL) process is used to form an interconnect layer on the second device layer, and contact vias are used to connect the interconnect layer to the transistors in the first device layer. This inevitably means the contact vias must penetrate the second device layer. To avoid short circuits, additional space needs to be reserved in the second device layer for these contact vias, limiting the area of ​​the transistors in the second device layer. This is detrimental to achieving high field-wound capacity (FWC), high dynamic range, and low noise performance in image sensors. Summary of the Invention

[0007] This application provides an image sensor, an image acquisition device, and an electronic device to increase the occupied area of ​​transistors in the second device layer and achieve high FWC, high dynamic range, and low noise performance.

[0008] In a first aspect, this application provides an image sensor comprising: a first device layer, a first dielectric layer, a first signal line layer, a second dielectric layer, and a second device layer stacked together. The first device layer includes a semiconductor substrate, a plurality of photoelectric conversion elements, and a plurality of transmission transistors. The semiconductor substrate includes a pixel region, and the pixel region includes a plurality of sub-pixel regions. Each sub-pixel region is provided with a photoelectric conversion element and a transmission transistor, and the photoelectric conversion element and the first electrode of the transmission transistor are connected. Furthermore, the first signal line layer includes a plurality of transmission control signal lines. The gate of any transmission transistor is connected to a transmission control signal line through a first contact hole to transmit a control signal to the gate of the transmission transistor via the transmission control signal line, controlling the on / off state of the transmission transistor. The second device layer includes a pixel output circuit located in the pixel region. The pixel output circuit is connected to the second electrode of each transmission transistor in the pixel region through a second contact hole, thereby allowing the charge generated by the photoelectric conversion element to be input into the pixel output circuit when the transmission transistor is turned on. The first contact hole penetrates the first dielectric layer, and the second contact hole penetrates both the first and second dielectric layers. And, the first electrode of the transmission transistor is the source, and the second electrode of the transmission transistor is the drain, or the first electrode of the transmission transistor is the drain, and the second electrode of the transmission transistor is the source.

[0009] In this embodiment, an image sensor is formed by sequentially forming multiple film layers on a semiconductor substrate using a monolithic integration method. Compared to the prior art method of bonding two chips together, this reduces the thickness of the pixel array in the image sensor, thereby reducing the overall thickness of the image sensor, as well as lowering costs and parasitic capacitance. Furthermore, by separating the photoelectric conversion element, transmission transistor, and pixel output circuit into different film layers, not only can the area occupied by the photoelectric conversion element, transmission transistor, and pixel output circuit be increased, but a first signal line layer is also set between the first device layer and the second device layer. This not only allows for flexible wiring in the first signal line layer, but also eliminates the need for the contact holes used to connect the gate of the transmission transistor to the transmission control signal line to pass through the second device layer. This allows the space originally reserved for contact holes in the second device layer to be used for the transistors in the pixel output circuit, further increasing the area occupied by the transistors in the pixel output circuit, and thus achieving high FWC, high dynamic range, and low noise performance.

[0010] In some possible implementations, the image sensor further includes a transition conductive layer and a third dielectric layer, wherein the transition conductive layer is located between the first dielectric layer and the first device layer, and the third dielectric layer is located between the transition conductive layer and the first device layer. The transition conductive layer includes a gate transition portion located in each sub-pixel region, the gate transition portion connecting the gate of the transmission transistor to the transmission control signal line via a third contact hole and a first contact hole. Therefore, by electrically connecting the gate of the transmission transistor to the corresponding transmission control signal line via the gate transition portion, the transmission path between the corresponding transmission control signal line and the gate of the transmission transistor can be optimized, the wiring of the transmission control signal line can be optimized, and the parasitic capacitance between the transmission control signal lines can be reduced. Furthermore, the third contact hole penetrates the third dielectric layer.

[0011] In some possible implementations, the gate transition portion includes a main body and a protrusion connected to each other. The main body extends along a second direction, and the protrusion is located on one side of the main body in a first direction. Furthermore, the main body is connected to a transmission control signal line via a first contact hole, and the protrusion is connected to the gate of the transmission transistor via a third contact hole. This configuration not only allows for flexible design of the gate transition portion structure but also facilitates the placement of the first and third contact holes, which is beneficial for the layout of the transmission transistor's gate and the transmission control signal line.

[0012] In some possible implementations, the plurality of sub-pixel regions include a first sub-pixel region and a second sub-pixel region arranged along a first direction, with the gates and main bodies of the transmission transistors in the first and second sub-pixel regions respectively arranged along the first direction. Furthermore, the transmission control signal lines connecting the transmission transistors in the first and second sub-pixel regions are arranged adjacently and extend along the first direction. To prevent a short circuit between the gate transition portions in the first and second sub-pixel regions via the transmission control signal lines, the first contact holes in the first and second sub-pixel regions are staggered in the first direction, which can reduce the risk of a short circuit between the gate transition portions in the first and second sub-pixel regions via the transmission control signal lines.

[0013] In some possible implementations, in the same gate transition portion, the protrusion is located at one end of the main body portion in the second direction, which can make the shape of the gate transition portion approximately "L" shaped, which is simple in structure and convenient for layout.

[0014] In some possible implementations, the protrusions in the first sub-pixel region and the second sub-pixel region are arranged along the first direction, so that the protrusions are regularly set, optimizing the layout and reducing the difficulty of layout design.

[0015] In some possible implementations, the protrusions in the first sub-pixel region and the second sub-pixel region are located between the main body portions in the first sub-pixel region and the second sub-pixel region, further optimizing the layout and reducing the difficulty of layout design.

[0016] In some possible implementations, the gate transition portions in the first sub-pixel region and the second sub-pixel region are symmetrically arranged to further optimize the layout and reduce the difficulty of layout design.

[0017] In some possible implementations, the transmission control signal line connected to the transmission transistor in the first sub-pixel region is a first transmission control signal line, and the transmission control signal line connected to the transmission transistor in the second sub-pixel region is a second transmission control signal line. Furthermore, in the third direction, the first transmission control signal line overlaps with the main body and protrusion in the first sub-pixel region, and with the main body and protrusion in the second sub-pixel region, respectively; the second transmission control signal line overlaps with the main body in both the first and second sub-pixel regions, respectively. Therefore, the first and second transmission control signal lines can be tightly arranged while maintaining insulation between them. Furthermore, the third direction is perpendicular to both the second and first directions.

[0018] In some possible implementations, in a third-party direction, the first transmission control signal line overlaps with the first and third contact holes in the first sub-pixel region and the third contact hole in the second sub-pixel region, and the second transmission control signal line overlaps with the first contact hole in the second sub-pixel region. Therefore, while ensuring insulation between the first and second transmission control signal lines, they can be tightly coupled.

[0019] In some possible implementations, the multiple sub-pixel regions also include a third sub-pixel region to further improve resolution. Furthermore, the third sub-pixel region is arranged along a second direction with the first sub-pixel region, and the structures in the third and first sub-pixel regions are symmetrically arranged, which can optimize the layout and reduce the difficulty of layout design.

[0020] In some possible implementations, the transmission control signal line connected to the transmission transistor in the third sub-pixel region is a third transmission control signal line, which is symmetrically arranged with the first transmission control signal line.

[0021] In some possible implementations, the multiple sub-pixel regions also include a fourth sub-pixel region to further improve resolution. Furthermore, the fourth sub-pixel region and the second sub-pixel region are arranged along a second direction, and the structures in the fourth and second sub-pixel regions are symmetrically configured, which can optimize the layout and reduce the difficulty of layout design.

[0022] In some possible implementations, the transmission control signal line connected to the transmission transistor in the fourth sub-pixel region is the fourth transmission control signal line. The fourth transmission control signal line is symmetrically arranged with the second transmission control signal line, which further optimizes the layout and reduces the difficulty of layout design.

[0023] In some possible implementations, the fourth sub-pixel region and the third sub-pixel region are arranged along the first direction, and the fourth transmission control signal line and the second transmission control signal line are located between the first transmission control signal line and the third transmission control signal line, further optimizing the layout and reducing the difficulty of layout design.

[0024] In some possible implementations, the first signal line layer further includes a floating diffusion adapter line located in the pixel region. The second contact hole includes a first sub-contact hole and a second sub-contact hole. The floating diffusion adapter line is connected to the pixel output circuit through the second sub-contact hole, and the floating diffusion adapter line is connected to the second electrode of each transmission transistor in the pixel region through the first sub-contact hole. Therefore, by setting the floating diffusion adapter line, the transmission path between the pixel output circuit and the second electrode of the transmission transistor can be optimized, further optimizing the layout of the pixel output circuit.

[0025] In some possible implementations, the image sensor further includes a transition conductive layer and a third dielectric layer. The transition conductive layer is located between the first dielectric layer and the first device layer, and the third dielectric layer is located between the transition conductive layer and the first device layer. Furthermore, the transition conductive layer includes a floating diffusion transition portion located in the pixel region. The floating diffusion transition portion is connected to a floating diffusion transition line through a first sub-contact hole, and the floating diffusion transition portion is connected to the second electrode of each transmission transistor in the pixel region through a fourth contact hole. Thus, by providing the floating diffusion transition portion, the transmission path between the floating diffusion transition line and the second electrode of the transmission transistor can be optimized, further optimizing the layout. Moreover, the fourth contact hole penetrates the third dielectric layer.

[0026] In some possible implementations, the multiple sub-pixel regions include a sub-pixel region group, which includes a first sub-pixel region, a second sub-pixel region, a third sub-pixel region, and a fourth sub-pixel region. This allows the first, second, third, and fourth sub-pixel regions within the sub-pixel region group to be arranged in a 2×2 array, further optimizing the layout. Furthermore, the floating diffusion adapter is connected to the second electrode of each transmission transistor in the sub-pixel region group via a fourth contact hole, which can further optimize the layout of the sub-pixel regions.

[0027] In some possible implementations, the multiple sub-pixel regions include at least two sub-pixel region groups, and the at least two sub-pixel region groups include a first sub-pixel region group and a second sub-pixel region group arranged along a second direction. This allows for further optimization of the sub-pixel region layout while further improving resolution. Furthermore, the first end of the floating diffusion adapter is connected to the second electrode of each transmission transistor in the first sub-pixel region group through a fourth contact hole, and the second end of the floating diffusion adapter is connected to the second electrode of each transmission transistor in the second sub-pixel region group through another fourth contact hole. This allows a single pixel output circuit to connect to multiple transmission transistors arranged in a 2×4 array of sub-pixel regions, reducing the complexity of the layout.

[0028] In some possible implementations, the floating diffusion adapter extends along a second direction, and the floating diffusion adapter line extends along a first direction. Furthermore, within the same pixel area, the floating diffusion adapter line and the floating diffusion adapter have an overlapping area in a third direction, and the first sub-contact hole is located in the overlapping area, which can further regularize the wiring direction and optimize the layout.

[0029] In some possible implementations, the floating diffusion adapter line is located between the transmission control signal lines connected to the first sub-pixel group and the transmission control signal lines connected to the second sub-pixel group, which can further make the wiring direction regular and optimize the layout.

[0030] In some possible implementations, the symmetrical arrangement of structures in the first and second sub-pixel groups can further make the wiring direction regular and optimize the layout.

[0031] In some possible implementations, the transmission control signal lines connected to the first sub-pixel group and the transmission control signal lines connected to the second sub-pixel group are symmetrically arranged, which can further make the wiring direction regular and optimize the layout.

[0032] In some possible implementations, the negative terminal of the photoelectric conversion element is connected to the first terminal of the transmission transistor. The first signal line layer also includes a first power line that surrounds the pixel area and is connected to the positive terminal of each photoelectric conversion element in the pixel area. Thus, a ground voltage can be transmitted to the positive terminal of the photoelectric conversion element through the first power line. For example, the first power line is mesh-like, which can reduce the voltage drop on the first power line.

[0033] In some possible implementations, the pixel output circuit includes a reset transistor, a source follower transistor, a gating transistor, and a switching gain transistor, with the second terminal of each transmission transistor connected to the gate of the source follower transistor. This makes the pixel output circuit relatively simple to implement, thereby reducing design complexity and production costs.

[0034] For example, at least one of the reset transistor, source follower transistor, gating transistor, and switching gain transistor is an oxide thin-film transistor, which has a low process thermal budget and a large channel material bandgap, enabling short-channel devices and withstanding gate and source-drain voltages greater than 3V. Compared with Si transistors, it can further reduce the area, or design more complex circuits within the same area, or increase the area of ​​at least one of the reset transistor, source follower transistor, gating transistor, and switching gain transistor.

[0035] For example, at least one of the reset transistor, source follower transistor, gating transistor, and switching gain transistor is a low-temperature polycrystalline silicon thin-film transistor, which can achieve high electron mobility and better switching speed, and faster response.

[0036] In some possible implementations, the plurality of subpixel regions include at least two subpixel region groups, each subpixel region group including a first subpixel region, a second subpixel region, a third subpixel region and a fourth subpixel region, and the at least two subpixel region groups include a first subpixel region group and a second subpixel region group arranged along a second direction.

[0037] For example, in the third direction, the source follower transistor has overlapping areas with the fourth sub-pixel region in the first sub-pixel region group, and the second and fourth sub-pixel regions in the second sub-pixel region group, respectively. Due to this configuration, the occupied area of ​​the source follower transistor can be set as large as possible based on the overall area of ​​the miniaturized pixel region, thereby reducing noise.

[0038] For example, in the third direction, the gating transistors overlap with the second sub-pixel regions in the first sub-pixel region group. Due to this configuration, the area occupied by the gating transistors can be minimized while maintaining the overall area of ​​the minimized pixel region, thus saving area and allowing the source follower transistor to occupy a larger area, further reducing noise.

[0039] For example, in the third direction, the conversion gain transistor has overlapping areas with the first and third sub-pixel areas in the first sub-pixel group, respectively. Due to this configuration, the occupied area of ​​the conversion gain transistor can be set as large as possible based on the overall area of ​​the miniaturized pixel area, thereby increasing the dynamic range.

[0040] For example, in the third direction, the reset transistor has overlapping areas with the first and third sub-pixel areas in the second sub-pixel group, respectively. Due to this configuration, the area occupied by the reset transistor can be minimized based on the overall area of ​​the miniaturized pixel area to save area, while the area occupied by the conversion gain transistor can be set as large as possible to further increase the dynamic range.

[0041] In some possible implementations, the image sensor further includes a second signal line layer and a fourth dielectric layer, the fourth dielectric layer being located between the second signal line layer and the second device layer. The second signal line layer includes a reset control signal line, a gating control signal line, a conversion gain signal line, a second power supply line, and an output signal line. The reset control signal line is connected to the gate of a reset transistor via a fifth contact hole; the gating control signal line is connected to the gate of a gating transistor via a sixth contact hole; the output signal line is connected to the second terminal of the gating transistor via a seventh contact hole; the conversion gain signal line is connected to the gate of the conversion gain transistor via an eighth contact hole; and the second power supply line is connected to the first terminal of both the source follower transistor and the reset transistor via a ninth contact hole. Furthermore, the fifth, sixth, seventh, eighth, and ninth contact holes each penetrate the fourth dielectric layer.

[0042] In some possible implementations, the second signal line layer includes a first sub-signal line layer and a second sub-signal line layer, with a fifth dielectric layer disposed between the first and second sub-signal line layers. The reset control signal line, gating control signal line, and conversion gain signal line are located on the first sub-signal line layer and extend along a first direction, which can make the routing direction regular and optimize the layout. Furthermore, the output signal line is located on the second sub-signal line layer and extends along a second direction, which can reduce the interference of the reset control signal line, gating control signal line, and conversion gain signal line on the output signal line, further reducing noise.

[0043] In some possible implementations, the first sub-signal line layer is located between the fifth and fourth dielectric layers, and the second sub-signal line layer is located on the side of the fifth dielectric layer facing away from the second device layer. The output signal line is connected to the second terminal of the select transistor through the seventh and tenth contact holes, which can reduce the difficulty of fabrication and facilitate layout. Furthermore, the tenth contact hole penetrates through the fifth dielectric layer.

[0044] Secondly, this application provides an image acquisition device, which includes a processor and an image sensor, wherein the processor is electrically connected to the image sensor. The image sensor is the same as that in the first aspect or the embodiments thereof. Furthermore, the technical effects of the corresponding solutions in the second aspect can be referred to the technical effects obtainable by the corresponding solutions in the first aspect or the embodiments thereof, and repeated details are not described in detail.

[0045] Thirdly, this application provides an electronic device comprising: an image acquisition device as described in the second aspect or in the embodiments of the second aspect. Furthermore, the technical effects of the corresponding solutions in the third aspect can be referenced to the technical effects obtainable by the corresponding solutions in the second aspect or in the embodiments of the second aspect; repeated details will not be elaborated upon. Attached Figure Description

[0046] Figure 1 is a schematic diagram of the structure of the electronic device provided in an embodiment of this application;

[0047] Figure 2 is a structural block diagram of the image sensor provided in an embodiment of this application;

[0048] Figure 3A is a schematic diagram of an image sensor provided in an embodiment of this application;

[0049] Figure 3B is a schematic diagram of another structure of the image sensor provided in the embodiment of this application;

[0050] Figure 4A is a top view of the image sensor provided in an embodiment of this application;

[0051] Figure 4B is a top view of the structure from the first device layer to the transition conductive layer in the image sensor provided in the embodiment of this application;

[0052] Figure 4C is a top view of the first device layer in the image sensor provided in an embodiment of this application.

[0053] Figure 5A is a schematic cross-sectional view of the structure along the AA' direction in Figure 4A;

[0054] Figure 5B is a schematic cross-sectional view of the structure along the BB' direction in Figure 4A;

[0055] Figure 5C is a schematic cross-sectional view of the structure along the CC' direction in Figure 4A;

[0056] Figure 5D is a schematic cross-sectional view of the structure along the DD' direction in Figure 4A;

[0057] Figure 6 is an equivalent circuit diagram of a transistor and photoelectric conversion element in a pixel provided in an embodiment of this application;

[0058] Figure 7A is a top view of a structure from the first device layer to the second sub-signal line layer in an image sensor provided in an embodiment of this application.

[0059] Figure 7B is a top view of a structure from the second device layer to the second sub-signal line layer in an image sensor provided in an embodiment of this application.

[0060] Figure 7C is a top view of a structure from the second device layer to the first sub-signal line layer in an image sensor provided in an embodiment of this application.

[0061] Figure 7D is a top view of a second device layer in an image sensor provided in an embodiment of this application.

[0062] Figure 8A is a schematic cross-sectional view of the structure along the AA' direction in Figure 7A;

[0063] Figure 8B is a schematic cross-sectional view of the structure along the BB' direction in Figure 7A;

[0064] Figure 8C is a schematic cross-sectional view of the structure along the CC' direction in Figure 7A;

[0065] Figure 9A is a top view schematic diagram of the first device layer to the second sub-signal line layer in the image sensor provided in the embodiment of this application;

[0066] Figure 9B is a top view schematic diagram of another structure from the second device layer to the second sub-signal line layer in the image sensor provided in the embodiment of this application;

[0067] Figure 9C is a top view schematic diagram of another structure from the second device layer to the first sub-signal line layer in the image sensor provided in the embodiment of this application;

[0068] Figure 9D is a top view schematic diagram of another second device layer in the image sensor provided in the embodiment of this application;

[0069] Figure 10A is a schematic cross-sectional view of the structure along the AA' direction in Figure 9A;

[0070] Figure 10B is a schematic cross-sectional view of the structure along the BB' direction in Figure 9A;

[0071] Figure 11 is a top view schematic diagram of another image sensor structure from the first device layer to the second sub-signal line layer provided in the embodiment of this application;

[0072] Figure 12 is another equivalent circuit diagram of the transistor and photoelectric conversion element in a pixel provided in an embodiment of this application;

[0073] Figure 13 is a top view schematic diagram of the first device layer to the second sub-signal line layer in the image sensor provided in the embodiment of this application;

[0074] Figure 14 is another equivalent circuit diagram of the transistor and photoelectric conversion element in a pixel provided in an embodiment of this application.

[0075] Reference numerals: 1-Electronic device; 10-Image acquisition device; 11-Image sensor; 12-Processor; 13-Display device; 20-Pixel area; 20-Sub-pixel area; 21-First sub-pixel area; 22-Second sub-pixel area; 23-Third sub-pixel area; 24-Fourth sub-pixel area; 100-First device layer; 101-Semiconductor substrate; 110-Photoelectric conversion element; 111-Photoelectric conversion unit; 122-Floating diffusion electrode; 130-First gate dielectric layer; 140-Gate sidewall; 200-First dielectric layer; 300- First signal line layer; 301-Transmission control signal line; 310-First transmission control signal line; 320-Second transmission control signal line; 330-Third transmission control signal line; 340-Fourth transmission control signal line; 400-Second dielectric layer; 500-Second device layer; 531 / 532 / 533 / 534 / 535-Channel; 121 / 501 / 502 / 503 / 504 / 505-Gate; 600-Transition conductive layer; 610-Gate transition portion; 611-Main body portion; 612-Protrusion portion; 620 - Floating diffusion transition section; 630-First power line; 700-Third dielectric layer; 800-Fourth dielectric layer; 900-Second signal line layer; 910-First sub-signal line layer; 911-Reset control signal line; 912-Gating control signal line; 913-Conversion gain signal line; 914-Second power line; 915-Floating diffusion signal line; 916-Output transition signal line; 920-Second sub-signal line layer; 921-Output signal line; 930-Fifth dielectric layer; S1-First surface; S2-Second surface; CK1 - First contact hole; CK2 - Second contact hole; CK2a - First sub-contact hole; CK2b - Second sub-contact hole; CK3 - Third contact hole; CK4 - Fourth contact hole; CK5 - Fifth contact hole; CK6 - Sixth contact hole; CK7 - Seventh contact hole; CK8 - Eighth contact hole; CK9 - Ninth contact hole; CK10 - Tenth contact hole; CK11 - Eleventh contact hole; CK12 - Twelfth contact hole; CK13 - Thirteenth contact hole; CK14 - Fourteenth contact hole; CK15 - Fifteenth contact hole; M TG1_1 ~M TG4_2 -Transmission transistor; M RS - Reset transistor; M SF -Source follower transistor; M SE -Gating transistor; M DCG -Conversion gain transistor; M GS - Global exposure transistor; RST - Reset control signal; VDD - Power supply voltage; SEL - Gating control signal; DCG - Conversion gain signal; F1 - First direction; F2 - Second direction; F3 - Third direction. Detailed Implementation

[0076] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The specific operational methods in the method embodiments can also be applied to the device embodiments or system embodiments. It should be noted that in the description of this application, "multiple" can be understood as "at least two". Furthermore, it should be understood that in the description of this application, terms such as "first" and "second" are used only for distinguishing purposes and should not be construed as indicating or implying relative importance, nor as indicating or implying order.

[0077] It should be noted that the same reference numerals in the accompanying drawings of this application denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Terms expressing position and direction described in this application are illustrative based on the accompanying drawings, but may be modified as needed, and all modifications are included within the scope of protection of this application. The accompanying drawings of this application are for illustrating relative positional relationships only and do not represent actual scale.

[0078] To facilitate understanding of the technical solutions provided in the embodiments of this application, their specific application scenarios are first described below. The image sensor provided in the embodiments of this application can be applied to an image acquisition device with image acquisition capabilities. This image acquisition device can be applied to electronic devices in fields such as security, photography and videography, automotive electronics, or industrial machine vision. For example, the image acquisition device includes, but is not limited to, cameras, Internet Protocol cameras (IPCs), digital cameras, digital camcorders, vehicle-mounted cameras, or industrial cameras. The electronic devices include, but are not limited to, mobile phones with front and / or rear cameras, tablets with front and / or rear cameras, and vehicle-mounted products.

[0079] Figure 1 is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Referring to Figure 1, the electronic device 1 may include an image acquisition device 10, which includes an image sensor 11 and a processor 12. The processor 12 is electrically connected to the image sensor 11. The image sensor 11 can operate according to control commands received from the processor 12, and can convert light signals reflected or emitted from an object (i.e., the target to be photographed) into electrical signals and output electrical signals to the processor 12. The processor 12 is used to receive the electrical signals output by the image sensor 11 and process the electrical signals. Exemplarily, the processor 12 includes, but is not limited to, an image processor, a central processing unit, etc.

[0080] For example, the electronic device 1 further includes a display device 13, which is electrically connected to the processor 12. Under the control of the processor 12, the display device 13 can display a corresponding image based on a digital image signal. In other embodiments of this application, the electronic device 1 may not include a display device 13.

[0081] Figure 2 is a structural block diagram of an image sensor provided in an embodiment of this application. Referring to Figure 2, the image sensor 11 may include a pixel array, a row driving circuit, a column driving circuit, and a readout circuit, etc. Exemplarily, the pixel array includes a photoelectric conversion element and a pixel circuit. The photoelectric conversion element is used to receive light and generate charge, and the pixel circuit is used to output an electrical signal based on the charge generated by the photoelectric conversion element. Exemplarily, the pixel circuit includes a transistor connected to the negative terminal of the photoelectric conversion element, and is used to output an electrical signal based on the charge generated by the photoelectric conversion element.

[0082] Row driving circuits can drive pixel circuits in a pixel array on a row-by-row basis. For example, a row driving circuit can output control signals to control the on / off state of transistors in a pixel circuit.

[0083] Column driver circuits may include correlated double sampling (CDS), analog-to-digital converters (ADCs), etc. The CDS is connected to the pixel circuit via column lines. When the row driver circuit selects a pixel circuit, the CDS acquires the electrical signal output by the pixel circuit through the column lines. The ADC converts the electrical signal output by the CDS into a digital signal and transmits the digital signal to the readout circuit.

[0084] The readout circuit may include latch circuits or buffer circuits, amplifier circuits, etc., capable of temporarily storing digital signals. Furthermore, the readout circuit can process the digital signals received from the column drive circuit and generate image data Dout. The image data Dout is input to processor 12, which can perform signal processing on the image data output from the readout circuit and can output the processed image data to a device such as a display device 13, or store the processed image data in a storage device such as a memory.

[0085] Figure 3A is a schematic diagram of an image sensor structure provided in an embodiment of this application. Referring to Figure 3A, in some embodiments of this application, the pixel array in the image sensor may include: a first device layer 100, a first dielectric layer 200, a first signal line layer 300, a second dielectric layer 400, and a second device layer 500 stacked together to form the pixel array in the image sensor through monolithic integration. Here, forming the pixel array through monolithic integration can refer to: sequentially forming multiple film layers on a semiconductor substrate to form the pixel array.

[0086] In existing technologies, bonding two chips together typically involves deep through-silicon vias (TSVs), which can easily lead to large parasitic capacitances, and the bonding and deep TSV processes are costly. Therefore, this embodiment of the application forms the pixel array using a monolithic integration method. Compared to the existing method of bonding two chips together, this reduces the thickness of the pixel array in the image sensor, thereby reducing the overall thickness of the image sensor, as well as lowering costs and parasitic capacitance. Furthermore, the monolithic integration method in this embodiment allows for flexible wiring in the intermediate layers.

[0087] For example, referring to FIG3A, the first device layer 100 may include a semiconductor substrate 101, a plurality of photoelectric conversion elements 110, and a plurality of transmission transistors. The semiconductor substrate 101 includes one or more pixel regions 20. When the semiconductor substrate 101 includes a plurality of pixel regions 20, the plurality of pixel regions 20 may be arranged in an array or in other ways. Furthermore, the pixel region 20 may include a plurality of sub-pixel regions 020. Each sub-pixel region 020 is provided with a photoelectric conversion element 110 and a transmission transistor. The first electrode of the photoelectric conversion element 110 and the transmission transistor in the same sub-pixel region 020 are connected. For example, the negative electrode of the photoelectric conversion element 110 is connected to the first electrode of the transmission transistor, and the positive electrode of the photoelectric conversion element 110 is grounded. For example, the photoelectric conversion element 110 includes a photodiode (PD), the positive electrode of the PD serves as the positive electrode of the photoelectric conversion element 110, and the negative electrode of the PD serves as the negative electrode of the photoelectric conversion element 110.

[0088] For example, referring to FIG3A, the semiconductor substrate 101 may include a first surface S1 and a second surface S2 opposite to each other on the third direction F3. The gates 121 of a plurality of transmission transistors may be disposed on the first surface S1 of the semiconductor substrate 101 to maximize the area occupied by the transmission transistors, optimize the structure of the transmission transistors, and improve FWC.

[0089] Semiconductor substrate 101 includes, but is not limited to, silicon substrate, germanium substrate, silicon-germanium substrate, or silicon-on-insulator (SOI) substrate. Photoelectric conversion element 110 is disposed on semiconductor substrate 101. Exemplarily, photoelectric conversion element 110 includes a first photoelectric conversion portion 111 and a second photoelectric conversion portion 112. The second photoelectric conversion portion 112 may include a first conductivity type impurity. For example, the first conductivity type impurity may include p-type impurities, such as aluminum (Al), boron (B), indium (In), and / or gallium (Ga). The first photoelectric conversion portion 111 can receive light incident on the second surface S2 to achieve photoelectric conversion. The first photoelectric conversion portion 111 may be doped with a second conductivity type impurity, the conductivity type of which is opposite to that of the first conductivity type impurity. For example, the second conductivity type impurity may allow the region where it is disposed to accumulate negative charges, while the first conductivity type impurity may allow the region where it is disposed to accumulate positive charges in the form of "holes" (e.g., no electrons). The second conductivity type impurity may include n-type impurities, such as one or more of phosphorus, arsenic, bismuth, and antimony.

[0090] For example, the second photoelectric conversion section 112 is multiplexed as the first electrode of the transmission transistor. Furthermore, a first gate dielectric layer 130 is disposed between the gate 121 of the transmission transistor and the semiconductor substrate 101. The area covered by the gate 121 on the first surface S1 of the semiconductor substrate 101 can serve as the channel of the transmission transistor. The area on the first surface S1 of the semiconductor substrate 101 located on the other side of the gate 121 can form a floating diffusion (FD) region, and the FD region serves as the second electrode 124 of the transmission transistor. For example, at least some of the transmission transistors in the same pixel region 20 can share the same second electrode 124, that is, at least some of the transmission transistors share a single FD region.

[0091] It is understood that Figure 3A provides some structural schematics of the gate 121, the FD region, and the first photoelectric conversion portion 111. These schematics are intended to clearly illustrate the structures of the semiconductor substrate 101, the plurality of photoelectric conversion elements 110, and the plurality of transmission transistors in the embodiments of this application, and do not constitute a limitation on the first device layer 100 in the embodiments of this application. For example, the structures of the semiconductor substrate 101, the plurality of photoelectric conversion elements, and the plurality of transmission transistors can be formed using structures in the prior art.

[0092] It is understood that FIG3A does not show the structure disposed on the second surface S2 of the semiconductor substrate 101, which may be the same as the structure in the prior art. For example, a light receiving portion may be disposed on the second surface S2 of the semiconductor substrate 101. The light receiving portion is used to focus and filter incident light. For example, the light receiving portion may include a first back dielectric layer, an anti-reflection layer, a color filter, a second back dielectric layer, a microlens, and a lens coating disposed sequentially on the second surface S2 of the semiconductor substrate 101.

[0093] Referring to Figure 3A, the second device layer 500 includes a pixel output circuit located in the pixel region 20. The pixel output circuit is connected to the second electrode 124 of each transmission transistor in the pixel region 20 through the second contact hole CK2. Thus, when the transmission transistor is turned on, the charge generated by the photoelectric conversion element 110 can be output to the pixel output circuit through the transmission crystal, thereby outputting a corresponding electrical signal through the pixel output circuit.

[0094] Referring to Figure 3A, the first signal line layer 300 includes multiple transmission control signal lines 301. The gate 121 of any transmission transistor is connected to a transmission control signal line 301 through a first contact hole CK1. That is, in the same pixel area 20, the gates 121 of different transmission transistors are respectively connected to different transmission control signal lines 301 through the first contact hole CK1. Thus, corresponding control signals can be input to the gates 121 of the transmission transistors through the transmission control signal lines 301 to control the switching on and off of the transmission transistors. For example, the multiple transmission control signal lines 301 can extend along a first direction F1 and be arranged along a second direction F2, which not only makes the wiring direction regular and the layout simple, but also reduces mutual interference between signals and improves the stability of signal transmission.

[0095] In this embodiment, by separating the photoelectric conversion element 110, the transmission transistor, and the pixel output circuit into different film layers, not only can more photoelectric conversion elements 110 be set, improving resolution, but the area occupied by the transmission transistor and the pixel output circuit is also increased. The transistors in the pixel output circuit can be made larger and more flexible, optimizing the layout of the pixel output circuit, and even enabling more complex pixel output circuits. Furthermore, by placing the first signal line layer 300 between the first device layer 100 and the second device layer 500, not only can the first signal line layer 300 be flexibly wired, but the contact hole used to connect the gate 121 of the transmission transistor and the transmission control signal line 301 no longer passes through the second device layer 500. This allows the space originally reserved for the contact hole in the second device layer 500 to be used to set the transistors in the pixel output circuit, further increasing the area occupied by the transistors in the pixel output circuit, thereby achieving high FWC, high dynamic range, and low noise performance.

[0096] For example, the first contact hole CK1 penetrates the first dielectric layer 200. For instance, during fabrication, a conductive material (e.g., a metallic material) can be filled into the first contact hole CK1 to form a conductive portion, thereby electrically connecting the corresponding transmission control signal line and the gate 121 of the transmission transistor. For example, the conductive portion can be a multilayer conductive film structure; for example, the conductive portion comprises a combination structure of metal nitride and metal, such as TiN / Cu, TaN / Cu, etc.

[0097] For example, the second contact hole CK2 penetrates the first dielectric layer 200 and the second dielectric layer 400. For instance, during fabrication, conductive material can be filled into the second contact hole CK2 to form a conductive portion, thereby electrically connecting the pixel output circuit to the second electrode of the transmission transistor. For example, this conductive portion can be a multilayer conductive film structure, for example, the conductive portion includes a combination structure of metal nitride and metal, such as TiN / Cu, TaN / Cu, etc.

[0098] In addition, the design can be flexibly adapted to the actual application scenario: the first electrode of the transmission transistor is the source, and the second electrode of the transmission transistor is the drain, or the first electrode of the transmission transistor is the drain and the second electrode of the transmission transistor is the source, so as to improve the design flexibility of the transmission transistor. This application does not limit this.

[0099] It is understood that, in order to clearly illustrate the structure in the embodiments of this application, Figure 3A uses the structure of the first signal line layer 300 to the first device layer 100 as an example, and does not show the specific structure of the second device layer 500.

[0100] For example, referring to FIG3B, which is a schematic diagram of another structure of an image sensor provided in an embodiment of the present application, the first device layer 100 further includes a floating diffusion electrode 122. The floating diffusion electrode 122 is disposed on the FD region and is connected between the FD region and the pixel output circuit to improve conductivity. For example, one floating diffusion electrode 122 is disposed on each FD region.

[0101] In some embodiments of this application, to optimize the transmission path between the pixel output circuit and the second electrode of the transmission transistor, referring to FIG3B, the first signal line layer 300 further includes a floating diffusion adapter 350 located in the pixel region 20. The second contact hole CK2 includes a first sub-contact hole CK2a and a second sub-contact hole CK2b. The floating diffusion adapter 350 is connected to the pixel output circuit through the second sub-contact hole CK2b, and the floating diffusion adapter 350 is connected to the second electrode 124 (e.g., floating diffusion electrode 122) of each transmission transistor in the pixel region 20 through the first sub-contact hole CK2a. Thus, by setting the floating diffusion adapter 350, the transmission path between the pixel output circuit and the second electrode of the transmission transistor can be optimized, further optimizing the layout of the pixel output circuit.

[0102] For example, the first sub-contact hole CK2a penetrates the first dielectric layer 200, and the second sub-contact hole CK2b penetrates the second dielectric layer 400. For instance, during fabrication, conductive material can be filled into the first sub-contact hole CK2a and the second sub-contact hole CK2b to form conductive portions, thereby electrically connecting the floating diffusion adapter line 350, the second electrode 124 of the transmission transistor, and the pixel output circuit. For example, the conductive portion can be a multilayer conductive film structure, such as a combination structure of metal nitride and metal, such as TiN / Cu, TaN / Cu, etc.

[0103] As an example, the same process is used to fill material in the first contact hole CK1 and the first sub-contact hole CK2a, so that the conductive parts in the first contact hole CK1 and the first sub-contact hole CK2a are made of the same material, which reduces process complexity and cost.

[0104] Because there are a large number of transmission transistors in the pixel area, in order to optimize the transmission path between the transmission control signal line and the gate 121 of the transmission transistor, and to optimize the wiring of the transmission control signal line, in some embodiments of this application, referring to FIG3B, the image sensor further includes a transition conductive layer 600 and a third dielectric layer 700. The transition conductive layer 600 is located between the first dielectric layer 200 and the first device layer 100, and the third dielectric layer 700 is located between the transition conductive layer 600 and the first device layer 100. Furthermore, the transition conductive layer 600 includes a gate transition portion 610 located in each sub-pixel area 020. In the same sub-pixel area 020, the gate transition portion 610 connects the gate 121 of the transmission transistor to the corresponding transmission control signal line 301 through the third contact hole CK3 and the first contact hole CK1. That is, the gate transition portion 610 is connected to the gate 121 of the transmission transistor through the third contact hole CK3, and the gate transition portion 610 is connected to the corresponding transmission control signal line 301 through the first contact hole CK1. Therefore, by electrically connecting the gate 121 of the transmission transistor to the corresponding transmission control signal line 301 through the gate transition section 610, the transmission path between the corresponding transmission control signal line 301 and the gate 121 of the transmission transistor can be optimized, the wiring of the transmission control signal line 301 can be optimized, and the parasitic capacitance between the transmission control signal lines 301 can be reduced.

[0105] For example, the third contact hole CK3 penetrates the third dielectric layer 700. For instance, during fabrication, conductive material can be filled into the third contact hole CK3 to form a conductive portion, thereby electrically connecting the gate transition portion 610 and the gate 121 of the transmission transistor. For example, this conductive portion can be a multilayer conductive film structure, for example, the conductive portion comprising a combination structure of metal nitride and metal, such as TiN / Cu, TaN / Cu, etc.

[0106] In some embodiments of this application, to optimize the transmission path between the floating diffusion adapter 350 and the second electrode of the transmission transistor, referring to FIG3B, the adapter conductive layer 600 further includes a floating diffusion adapter portion 620 located in the pixel region 20. The floating diffusion adapter portion 620 is connected to the floating diffusion adapter 350 through a first sub-contact hole CK2a, and the floating diffusion adapter portion 620 is connected to the second electrode 124 (e.g., floating diffusion electrode 122) of each transmission transistor in the pixel region 20 through a fourth contact hole CK4. Therefore, by providing the floating diffusion adapter portion 620, the transmission path between the floating diffusion adapter 350 and the second electrode 124 of the transmission transistor can be optimized, further optimizing the layout. Exemplarily, the floating diffusion adapter portion 620 is connected to the floating diffusion electrode 122 in the pixel region 20 through the fourth contact hole CK4.

[0107] For example, the fourth contact hole CK4 penetrates the third dielectric layer 700. For instance, during fabrication, a conductive material can be filled into the fourth contact hole CK4 to form a conductive portion, electrically connecting the floating diffusion adapter 620 and the second electrode (e.g., the floating diffusion electrode 122) of the transmission transistor. For example, the conductive portion can be a multilayer conductive film structure, for example, the conductive portion comprising a combination structure of metal nitride and metal, such as TiN / Cu, TaN / Cu, etc.

[0108] As an example, the same process is used to fill the material in the third contact hole CK3 and the fourth contact hole CK4, so that the material in the third contact hole CK3 and the fourth contact hole CK4 is the same, which reduces the complexity of the process and reduces the cost.

[0109] It is understood that, in order to clearly illustrate the structure in the embodiments of this application, Figure 3B uses the structure of the first signal line layer 300 to the first device layer 100 as an example, and does not show the specific structure of the second device layer 500.

[0110] To further optimize the layout, referring to Figures 4A to 4C and Figures 5A to 5D, Figure 4A is a top view of the pixel array in the image sensor provided in an embodiment of this application; Figure 4B is a top view of the first device layer to the transition conductive layer in the image sensor provided in an embodiment of this application; Figure 4C is a top view of the first device layer in the image sensor provided in an embodiment of this application; Figure 5A is a cross-sectional view along the AA' direction in Figure 4A; Figure 5B is a cross-sectional view along the BB' direction in Figure 4A; Figure 5C is a cross-sectional view along the CC' direction in Figure 4A; and Figure 5D is a cross-sectional view along the DD' direction in Figure 4A. Exemplarily, the gate transition portion 610 may include a main body portion 611 and a protrusion 612 connected to each other. The main body portion 611 extends along the second direction F2, and the protrusion 612 is located on one side of the main body portion 611 in the first direction F1. Furthermore, the main body 611 is connected to the transmission control signal line 301 through the first contact hole CK1, and the protrusion 612 is connected to the gate 121 of the transmission transistor through the third contact hole CK3. This configuration not only allows for flexible design of the gate transition portion 610 but also facilitates the placement of the first contact hole CK1 and the third contact hole CK3, which is beneficial for the layout of the gate 121 of the transmission transistor and the transmission control signal line 301. In other embodiments of this application, the gate transition portion 610 may also include only the main body 611, which is not limited here.

[0111] It is understood that, in order to clearly illustrate the structure of the first signal line layer 300 to the first device layer 100 in the embodiments of this application, Figures 4A to 4C and 5A to 5D illustrate the structure of the first signal line layer 300 to the first device layer 100 as an example, and do not show the specific structure of the second device layer 500. Furthermore, the second device layer 500 shown in Figures 5A to 5C only indicates its position on the third direction F3, and does not show the specific structure of the second device layer 500. In addition, in other embodiments of this application, the transition conductive layer 600 and the third dielectric layer 700 may be omitted, and the gate 121 of the transmission transistor may be directly connected to the corresponding transmission control signal line 301 through the first contact hole CK1. Furthermore, the gate 121 in any sub-pixel region 020 also has gate sidewalls 140 on both sides to define the gate region of the transmission transistor, reducing leakage current and reliability issues. In addition, in order to isolate the photoelectric conversion elements 110 in different sub-pixels 020, an isolation structure 150 is also provided in the semiconductor substrate 101. The isolation structure 150 extends from the first surface S1 into the semiconductor substrate 101 to isolate the photoelectric conversion elements 110 in different sub-pixels.

[0112] In some embodiments of this application, in the same gate transition portion 610, the protrusion 612 can be located at one end of the main body portion 611 in the second direction F2, so that the shape of the gate transition portion 610 is approximately "L"-shaped, which is simple in structure and convenient for layout. In other embodiments of this application, the protrusion 612 can also be located at other positions of the main body portion 611 to realize other shapes of gate transition portion 610 structures, which are not limited here.

[0113] In some embodiments of this application, referring to Figures 4A to 4C and Figure 5A, the plurality of sub-pixel regions 020 may include a first sub-pixel region 21 and a second sub-pixel region 22, which are arranged along a first direction F1. Exemplarily, the first photoelectric conversion portion 111 in the first sub-pixel region 21 and the second sub-pixel region 22 is arranged along the first direction F1, which is beneficial for optimizing the layout. For example, the first photoelectric conversion portion 111 in the first sub-pixel region 21 and the second sub-pixel region 22 has an overlapping area in its orthographic projection onto a first reference plane. This first reference plane is perpendicular to the first direction F1.

[0114] Furthermore, the gates 121 of the transmission transistors in the first sub-pixel region 21 and the second sub-pixel region 22 are also arranged along the first direction F1, and the main body portions 611 in the first sub-pixel region 21 and the second sub-pixel region 22 are also arranged along the first direction F1, which is beneficial for optimizing the layout. For example, the main body portions 611 in the first sub-pixel region 21 and the second sub-pixel region 22 have overlapping regions in their orthographic projections onto the first reference plane.

[0115] The transmission control signal lines 301 connecting the transmission transistors in the first sub-pixel region 21 and the second sub-pixel region 22 are arranged adjacently and extend along the first direction F1. Since the gate transition portions 610 in the first sub-pixel region 21 and the second sub-pixel region 22 are respectively connected to the corresponding transmission control signal lines 301 through the first contact holes CK1, and these transmission control signal lines 301 extend along the first direction F1, in order to avoid short-circuiting the gate transition portions 610 in the first sub-pixel region 21 and the gate transition portions 610 in the second sub-pixel region 22 through the transmission control signal lines 301, the first contact holes CK1 in the first sub-pixel region 21 and the first contact holes CK1 in the second sub-pixel region 22 can be staggered in the first direction F1. For example, the staggered arrangement of the first contact holes CK1 in the first sub-pixel region 21 and the first contact holes CK1 in the second sub-pixel region 22 in the first direction F1 can mean that the orthographic projections of the first contact holes CK1 in the first sub-pixel region 21 and the first contact holes CK1 in the second sub-pixel region 22 are spaced apart from each other on the first reference plane.

[0116] In some embodiments of this application, referring to Figures 4A and 4B, the protrusions 612 in the first sub-pixel region 21 and the protrusions 612 in the second sub-pixel region 22 are arranged along the first direction F1, making the protrusions 612 regularly arranged, optimizing the layout, and reducing the difficulty of layout design. For example, the protrusions 612 in the first sub-pixel region 21 and the second sub-pixel region 22 have overlapping areas in their orthographic projections onto the first reference plane. In other embodiments of this application, the protrusions 612 in the first sub-pixel region 21 and the second sub-pixel region 22 can also be staggered in the first direction F1. For example, the protrusions 612 in the first sub-pixel region 21 and the second sub-pixel region 22 are spaced apart from each other in their orthographic projections onto the first reference plane.

[0117] In some embodiments of this application, referring to Figures 4A and 4B, the protrusion 612 in the first sub-pixel region 21 and the protrusion 612 in the second sub-pixel region 22 are located between the main body 611 in the first sub-pixel region 21 and the main body 611 in the second sub-pixel region 22, further optimizing the layout and reducing the difficulty of layout design.

[0118] In some embodiments of this application, referring to Figures 4A and 4B, the gate transition portions 610 in the first sub-pixel region 21 and the second sub-pixel region 22 are symmetrically arranged. This simplifies the structural design of the gate transition portions 610 in the first sub-pixel region 21 and the second sub-pixel region 22, reduces the complexity of the manufacturing process, lowers the difficulty of mask design, and reduces costs. For example, the gate transition portions 610 in the first sub-pixel region 21 and the second sub-pixel region 22 can be symmetrically arranged about a first axis of symmetry, which extends along a second direction F2.

[0119] In some embodiments of this application, referring to Figures 4A to 4C, the gates in the first sub-pixel region 21 and the second sub-pixel region 22 are symmetrically arranged, which can simplify the structural design of the gates in the first sub-pixel region 21 and the second sub-pixel region 22, reduce the complexity of the manufacturing process, reduce the difficulty of mask design, and reduce costs. Exemplarily, the gates in the first sub-pixel region 21 and the second sub-pixel region 22 can be symmetrically arranged about a first axis of symmetry.

[0120] In some embodiments of this application, referring to Figures 4A and 4B, and Figures 5A to 5C, the transmission control signal line 301 connected to the transmission transistor in the first sub-pixel region 21 is a first transmission control signal line 310, and the transmission control signal line 301 connected to the transmission transistor in the second sub-pixel region 22 is a second transmission control signal line 320. Furthermore, in the third direction F3, the first transmission control signal line 310 overlaps with the main body portion 611 and the protrusion portion 612 in the first sub-pixel region 21, and with the main body portion 611 and the protrusion portion 612 in the second sub-pixel region 22, respectively. The second transmission control signal line 320 also overlaps with the main body portion 611 in the first sub-pixel region 21 and with the main body portion 611 in the second sub-pixel region 22, respectively. This allows for a close arrangement while ensuring insulation between the first transmission control signal line 310 and the second transmission control signal line 320. The third direction F3 is perpendicular to both the second direction F2 and the first direction F1. This is an example. The first transmission control signal line 310 and the second transmission control signal line 320 are arranged adjacent to each other, further making the first transmission control signal line 310 and the second transmission control signal line 320 closely arranged.

[0121] In some embodiments of this application, when there are multiple pixel areas, the transmission transistors in the first sub-pixel areas 21 of the multiple pixel areas 20 arranged along the first direction F1 are connected to the same first transmission control signal line 310, and the transmission transistors in the first sub-pixel areas 21 of the multiple pixel areas 20 arranged along the second direction F2 are connected to different first transmission control signal lines 310.

[0122] In some embodiments of this application, when there are multiple pixel areas, the transmission transistors in the second sub-pixel areas 22 of the multiple pixel areas 20 arranged along the first direction F1 are connected to the same second transmission control signal line 320, and the transmission transistors in the second sub-pixel areas 22 of the multiple pixel areas 20 arranged along the second direction F2 are connected to different second transmission control signal lines 320.

[0123] In some embodiments of this application, referring to Figures 4A and 4B, and Figures 5A to 5C, on the third direction F3, the first transmission control signal line 310 overlaps with the first contact hole CK1 and the third contact hole CK3 in the first sub-pixel area 21, and the third contact hole CK3 in the second sub-pixel area 22. The second transmission control signal line 320 overlaps with the first contact hole CK1 in the second sub-pixel area 22. Furthermore, the first transmission control signal line 310 and the second transmission control signal line 320 can be tightly arranged while satisfying insulation.

[0124] In some embodiments of this application, referring to Figures 4A to 4C and Figure 5B, the plurality of sub-pixel regions 020 may further include a third sub-pixel region 23 to further improve resolution. The third sub-pixel region 23 and the first sub-pixel region 21 are arranged along the second direction F2. For example, the third sub-pixel region 23 and the first photoelectric conversion portion 111 in the first sub-pixel region 21 are arranged along the second direction F2. That is, the third sub-pixel region 23 and the first photoelectric conversion portion 111 in the first sub-pixel region 21 have an overlapping area in their orthogonal projections onto the second reference plane, which is beneficial for optimizing the layout. The second reference plane is perpendicular to the second direction F2.

[0125] For example, the structures in the third sub-pixel region 23 and the first sub-pixel region 21 are symmetrically arranged. Specifically, the structures in the third sub-pixel region 23 and the first sub-pixel region 21 are symmetrically arranged about a second axis of symmetry, which extends along a first direction F1. For example, the first photoelectric conversion portion 111 in the third sub-pixel region 23 and the first sub-pixel region 21 are symmetrically arranged about the second axis of symmetry; the gate 121 of the transmission transistor in the third sub-pixel region 23 and the first sub-pixel region 21 are symmetrically arranged about the second axis of symmetry; and the gate transition portion 610 in the third sub-pixel region 23 and the first sub-pixel region 21 are symmetrically arranged about the second axis of symmetry. This simplifies the structural design of the third sub-pixel region 23, reduces the complexity of the manufacturing process, lowers the difficulty of mask design, and reduces costs.

[0126] For example, the gates 121 of the transmission transistors in the third sub-pixel region 23 and the first sub-pixel region 21 are arranged along the second direction F2; the main body portion 611 in the third sub-pixel region 23 and the main body portion 611 in the first sub-pixel region 21 are arranged along the second direction F2; the protrusion 612 in the third sub-pixel region 23 and the protrusion 612 in the first sub-pixel region 21 are arranged along the second direction F2; the first contact hole CK1 in the third sub-pixel region 23 and the first contact hole CK1 in the first sub-pixel region 21 are arranged along one direction; and the third contact hole CK3 in the third sub-pixel region 23 and the third contact hole CK3 in the first sub-pixel region 21 are arranged along the first direction F1. This reduces the complexity of the manufacturing process, lowers the difficulty of mask design, and reduces costs. In other embodiments of this application, the arrangement of the third contact hole CK3 in the third sub-pixel region 23 and the third contact hole CK3 in the first sub-pixel region 21 can also be flexibly designed into other arrangements according to the actual application scenario, and is not limited here.

[0127] In some embodiments of this application, referring to Figures 4A to 4C and Figure 5B, the transmission control signal line 301 connected to the transmission transistor in the third sub-pixel region 23 is a third transmission control signal line 330. The third transmission control signal line 330 is symmetrically arranged with the first transmission control signal line 310, for example, the third transmission control signal line 330 and the first transmission control signal line 310 are symmetrically arranged about a second axis of symmetry. This simplifies the structural design of the third transmission control signal line 330 and the first transmission control signal line 310, reduces the complexity of the manufacturing process, lowers the difficulty of mask design, and reduces costs.

[0128] In some embodiments of this application, when there are multiple pixel areas, the transmission transistors in the third sub-pixel areas 23 of the multiple pixel areas 20 arranged along the first direction F1 are connected to the same third transmission control signal line 330, and the transmission transistors in the third sub-pixel areas 23 of the multiple pixel areas 20 arranged along the second direction F2 are connected to different third transmission control signal lines 330.

[0129] In some embodiments of this application, referring to Figures 4A to 4C and 5C, the plurality of sub-pixel regions 020 further includes a fourth sub-pixel region 24, which further improves the resolution. The fourth sub-pixel region 24 and the second sub-pixel region 22 are arranged along a second direction F2. For example, the first photoelectric conversion portion 111 in the fourth sub-pixel region 24 and the second sub-pixel region 22 are arranged along the second direction F2. That is, the first photoelectric conversion portion 111 in the fourth sub-pixel region 24 and the second sub-pixel region 22 have an overlapping area in their orthogonal projections onto the second reference plane, which is beneficial for optimizing the layout.

[0130] For example, the structures in the fourth sub-pixel region 24 and the second sub-pixel region 22 are symmetrically arranged, for instance, the structures in the fourth sub-pixel region 24 and the second sub-pixel region 22 are symmetrically arranged about a second axis of symmetry. For example, the first photoelectric conversion portion 111 in the fourth sub-pixel region 24 and the second sub-pixel region 22 are symmetrically arranged about the second axis of symmetry, the gate 121 of the transmission transistor in the fourth sub-pixel region 24 and the second sub-pixel region 22 are symmetrically arranged about the second axis of symmetry, and the gate transition portion 610 in the fourth sub-pixel region 24 and the second sub-pixel region 22 are symmetrically arranged about the second axis of symmetry. This simplifies the structural design of the fourth sub-pixel region 24, reduces the complexity of the manufacturing process, lowers the difficulty of mask design, and reduces costs.

[0131] For example, the gates 121 of the transmission transistors in the fourth sub-pixel region 24 and the second sub-pixel region 22 are arranged along the second direction F2; the main body portion 611 in the fourth sub-pixel region 24 and the main body portion 611 in the second sub-pixel region 22 are arranged along the second direction F2; the protrusion 612 in the fourth sub-pixel region 24 and the protrusion 612 in the second sub-pixel region 22 are arranged along the second direction F2; the first contact hole CK1 in the fourth sub-pixel region 24 and the first contact hole CK1 in the second sub-pixel region 22 are arranged along the second direction F2; and the third contact hole CK3 in the fourth sub-pixel region 24 and the third contact hole CK3 in the second sub-pixel region 22 are arranged along the second direction F2. This reduces the complexity of the manufacturing process, lowers the difficulty of mask design, and reduces costs.

[0132] In some embodiments of this application, referring to Figures 4A to 4C and 5C, the transmission control signal line 301 connected to the transmission transistor in the fourth sub-pixel region 24 is a fourth transmission control signal line 340. The fourth transmission control signal line 340 and the second transmission control signal line 320 are symmetrically arranged, for example, the fourth transmission control signal line 340 and the second transmission control signal line 320 are symmetrically arranged about a second axis of symmetry. This simplifies the structural design of the fourth transmission control signal line 340 and the second transmission control signal line 320, reduces the complexity of the manufacturing process, lowers the difficulty of mask design, and reduces costs.

[0133] In some embodiments of this application, when there are multiple pixel areas, the transmission transistors in the fourth sub-pixel areas 24 of the multiple pixel areas arranged along the first direction F1 are connected to the same fourth transmission control signal line 340, and the transmission transistors in the fourth sub-pixel areas 24 of the multiple pixel areas arranged along the second direction F2 are connected to different fourth transmission control signal lines 340.

[0134] In some embodiments of this application, referring to Figures 4A to 4C, the fourth sub-pixel region 24 and the third sub-pixel region 23 are arranged along a first direction F1. For example, the first photoelectric conversion portions 111 in the fourth sub-pixel region 24 and the third sub-pixel region 23 are arranged along the first direction F1, that is, the first photoelectric conversion portions 111 in the fourth sub-pixel region 24 and the third sub-pixel region 23 have overlapping areas in their orthogonal projections onto the first reference plane, which is beneficial for optimizing the layout. Thus, the first sub-pixel region 21, the second sub-pixel region 22, the third sub-pixel region 23, and the fourth sub-pixel region 24 can be arranged in a 2×2 array, which can optimize the layout of the sub-pixel regions. Exemplarily, the second electrodes of the transmission transistors in the first sub-pixel region 21, the second sub-pixel region 22, the third sub-pixel region 23, and the fourth sub-pixel region 24, arranged in a 2×2 array, share a single floating diffusion electrode 122.

[0135] Because the structures in the third sub-pixel region 23 and the first sub-pixel region 21 are symmetrically arranged, the structures in the fourth sub-pixel region 24 and the second sub-pixel region 22 are symmetrically arranged, and the structures in the first sub-pixel region 21 and the third sub-pixel region 23 are symmetrically arranged, the structures in the fourth sub-pixel region 24 and the third sub-pixel region 23 can also be symmetrically arranged about the first axis of symmetry. For example, the first photoelectric conversion portion 111 in the fourth sub-pixel region 24 and the third sub-pixel region 23 are symmetrically arranged about the first axis of symmetry, the gate 121 of the transmission transistor in the fourth sub-pixel region 24 and the third sub-pixel region 23 are symmetrically arranged about the first axis of symmetry, and the gate transition portion 610 in the fourth sub-pixel region 24 and the third sub-pixel region 23 are symmetrically arranged about the first axis of symmetry. This further simplifies the structural design of the first sub-pixel region 21 to the fourth sub-pixel region 24, reduces the complexity of the manufacturing process, lowers the difficulty of mask design, and reduces costs.

[0136] For example, the first contact hole CK1 in the fourth sub-pixel region 24 and the first contact hole CK1 in the third sub-pixel region 23 are offset in the first direction F1, and the third contact hole CK3 in the fourth sub-pixel region 24 and the first contact hole CK1, as well as the third contact hole CK3 in the third sub-pixel region 23, are arranged along the first direction F1. This reduces the complexity of the manufacturing process, lowers the difficulty of mask design, and reduces costs.

[0137] In some embodiments of this application, referring to Figures 4A, 5B and 5C, the fourth transmission control signal line 340 and the second transmission control signal line 320 are located between the first transmission control signal line 310 and the third transmission control signal line 330, thus optimizing the layout of the first transmission control signal line 310 to the fourth transmission control signal line 340.

[0138] In some embodiments of this application, referring to Figures 4A to 4C, the plurality of sub-pixel regions 020 may include sub-pixel region groups (e.g., PZ1, PZ2), each sub-pixel region group (e.g., PZ1, PZ2) including a first sub-pixel region 21, a second sub-pixel region 22, a third sub-pixel region 23, and a fourth sub-pixel region 24. The first sub-pixel region 21, the second sub-pixel region 22, the third sub-pixel region 23, and the fourth sub-pixel region 24 within the same sub-pixel region group (e.g., PZ1, PZ2) are arranged in a 2×2 array. Furthermore, the floating diffusion adapter 620 is connected to the second electrode of each transmission transistor in the sub-pixel region group through a fourth contact hole CK4.

[0139] In some embodiments of this application, referring to Figures 4A to 4C, the plurality of sub-pixel regions 020 may include at least two sub-pixel region groups (e.g., PZ1, PZ2). The at least two sub-pixel region groups may include a first sub-pixel region group PZ1 and a second sub-pixel region group PZ2 arranged along the second direction F2. That is, the first sub-pixel region group PZ1 includes a first sub-pixel region 21, a second sub-pixel region 22, a third sub-pixel region 23 and a fourth sub-pixel region 24, and the second sub-pixel region group PZ2 also includes a first sub-pixel region 21, a second sub-pixel region 22, a third sub-pixel region 23 and a fourth sub-pixel region 24. For example, the first sub-pixel region 21, the second sub-pixel region 22, the third sub-pixel region 23, and the fourth sub-pixel region 24 in the first sub-pixel region group PZ1 can be arranged in a 2×2 array, and the first sub-pixel region 21, the second sub-pixel region 22, the third sub-pixel region 23, and the fourth sub-pixel region 24 in the second sub-pixel region group PZ2 can also be arranged in a 2×2 array, so that the first sub-pixel region 21, the second sub-pixel region 22, the third sub-pixel region 23, and the fourth sub-pixel region 24 in the first sub-pixel region group PZ1 and the second sub-pixel region group PZ2 can be arranged in a 2×4 array, further optimizing the layout of the sub-pixel regions.

[0140] It is understood that, in order to clearly illustrate the structure of a pixel region in the embodiments of this application, Figures 4A to 4C illustrate a pixel region having two sub-pixel groups as an example. In other embodiments of this application, a pixel region may also include one sub-pixel group, or three, four, or more sub-pixel groups arranged along the second direction F2, all of which are implemented based on the structure of the sub-pixel groups in the embodiments of this application. Furthermore, any adjacent sub-pixel groups in the second direction F2 satisfy the structural relationship between the first sub-pixel group PZ1 and the second sub-pixel group PZ2 described above, which will not be elaborated here.

[0141] In some embodiments of this application, referring to Figures 4A to 4C, the structures in the first sub-pixel group PZ1 and the second sub-pixel group PZ2 are symmetrically arranged. Exemplarily, the structures in the first sub-pixel group PZ1 and the second sub-pixel group PZ2 are symmetrically arranged about a third axis of symmetry, which extends along a first direction F1. For example, the structures of the first sub-pixel region 21 in the first sub-pixel group PZ1 and the first sub-pixel region 21 in the second sub-pixel group PZ2 are symmetrically arranged about the third axis of symmetry; the structures of the second sub-pixel region 22 in the first sub-pixel group PZ1 and the second sub-pixel region 22 in the second sub-pixel group PZ2 are symmetrically arranged about the third axis of symmetry; the structures of the third sub-pixel region 23 in the first sub-pixel group PZ1 and the third sub-pixel region 23 in the second sub-pixel group PZ2 are symmetrically arranged about the third axis of symmetry; and the structures of the fourth sub-pixel region 24 in the first sub-pixel group PZ1 and the fourth sub-pixel region 24 in the second sub-pixel group PZ2 are symmetrically arranged about the third axis of symmetry. Furthermore, the way in which each transmission transistor in the second sub-pixel group PZ2 is connected to the corresponding transmission control signal line 301 can be referred to the way in which each transmission transistor in the first sub-pixel group PZ1 is connected to the corresponding transmission control signal line 301, which will not be elaborated here.

[0142] In some embodiments of this application, referring to FIG4A, the transmission control signal line 301 connected to the first sub-pixel group PZ1 and the transmission control signal line 301 connected to the second sub-pixel group PZ2 are symmetrically arranged. For example, the transmission control signal line 301 connected to the first sub-pixel group PZ1 and the transmission control signal line 301 connected to the second sub-pixel group PZ2 are symmetrically arranged about a third axis of symmetry. For instance, the first transmission control signal line 310 connected to the first sub-pixel group PZ1 and the first transmission control signal line 310 connected to the second sub-pixel group PZ2 are symmetrically arranged about a third axis of symmetry; the second transmission control signal line 320 connected to the first sub-pixel group PZ1 and the second transmission control signal line 320 connected to the second sub-pixel group PZ2 are symmetrically arranged about a third axis of symmetry; the third transmission control signal line 330 connected to the first sub-pixel group PZ1 and the third transmission control signal line 330 connected to the second sub-pixel group PZ2 are symmetrically arranged about a third axis of symmetry; and the fourth transmission control signal line 340 connected to the first sub-pixel group PZ1 and the fourth transmission control signal line 340 connected to the second sub-pixel group PZ2 are symmetrically arranged about a third axis of symmetry.

[0143] For example, referring to Figures 4A, 4B, and 5D, the first end of the floating diffusion adapter 620 is connected to the second electrode of each transmission transistor in the first sub-pixel group PZ1 through a fourth contact hole CK4, and the second end of the floating diffusion adapter 620 is connected to the second electrode of each transmission transistor in the second sub-pixel group PZ2 through another fourth contact hole CK4. This allows a single pixel output circuit to connect multiple transmission transistors arranged in a 2×4 array in the sub-pixel groups, reducing the complexity of the layout. For example, the pixel output circuit can sequentially output electrical signals based on the charge generated by the photoelectric conversion elements, or it can output electrical signals based on the charge generated by multiple photoelectric conversion elements. Based on this, the photoelectric conversion elements in multiple sub-pixels can generate signals together, which is suitable for scenarios such as low-light environments, ensuring the signal-to-noise ratio of the electrical signal.

[0144] For example, referring to Figures 4A, 4B, and 5D, the floating diffusion adapter 620 can extend along the second direction F2. For instance, the floating diffusion adapter 620 extends along the second direction F2 from the region where the first sub-pixel group PZ1 is located to the region where the second sub-pixel group PZ2 is located. Furthermore, the floating diffusion adapter line 350 extends along the first direction F1, such that the extension direction of the floating diffusion adapter line 350 is the same as that of the transmission control signal line 301, further making the wiring direction regular and optimizing the layout.

[0145] For example, referring to Figures 4A, 4B and 5D, in the same pixel area, the floating diffusion adapter 350 and the floating diffusion adapter 620 have an overlapping area on the third direction F3, and the first sub-contact hole CK2a is located in the overlapping area to improve the electrical connection performance between the floating diffusion adapter 350 and the floating diffusion adapter 620.

[0146] For example, referring to Figures 4A and 5D, the floating diffusion adapter line 350 is located between the transmission control signal line 301 connected to the first sub-pixel group PZ1 and the transmission control signal line 301 connected to the second sub-pixel group PZ2. Alternatively, the floating diffusion adapter line 350 is located between the third transmission control signal line 330 connected to the first sub-pixel group PZ1 and the third transmission control signal line 330 connected to the second sub-pixel group PZ2.

[0147] In some embodiments of this application, referring to Figures 4A, 4B, and 5B to 5D, the first signal line layer 300 further includes a first power line 630. The first power line 630 is disposed around the pixel area and is connected to the positive terminal of each photoelectric conversion element in the pixel area to ground the positive terminal of the photoelectric conversion element through the first power line 630, i.e., a ground voltage is transmitted on the first power line 630. Exemplarily, when the semiconductor substrate 101 has multiple pixel areas, the first power line 630 can be disposed around each pixel area. Exemplarily, the first power line is mesh-shaped, which can reduce the voltage drop on the first power line.

[0148] The pixel output circuit in this application embodiment can have various forms. For example, referring to Figure 6, which is an equivalent circuit diagram of a transistor and photoelectric conversion element in a pixel provided in this application embodiment, the pixel output circuit may include a reset transistor M. RS Source follower (SF) transistor M SF , Gating transistor M SE and conversion gain transistor M DCG Therefore, the pixel output circuit can use a reset transistor M. RS Source follower transistor M SF , Gating transistor M SE and conversion gain transistor M DCG The architecture is relatively mature, making the implementation of the pixel output circuit relatively simple, thereby reducing design difficulty and production costs.

[0149] Reset transistor M RS The gate of the reset transistor M is used to receive the reset control signal RST. RS The first terminal is used to receive the power supply voltage VDD, and the reset transistor M RS The second electrode is connected to the source follower transistor M. SF The gate of the transistor. Therefore, the reset control signal RST can control the reset transistor M. RS The on / off state of the reset transistor M RS When turned on, the power supply voltage VDD can be input to the source follower transistor M. SF The gate of the source follower transistor M SF The gate of the source follower transistor M is reset. Since the gate of the source follower transistor MSF is connected to the FD region, the source follower transistor M... SF Resetting the gate is equivalent to resetting the FD region.

[0150] Source follower transistor M SF The gate of the transistor is connected to the second terminal of each transmission transistor, and the source follows the transistor M. SFThe first terminal is used to receive the power supply voltage VDD, and the source follows the transistor M. SF The second electrode and the gate transistor M SE The first electrode is connected. Therefore, when the transmission transistor is turned on, the charge generated by the photoelectric conversion element can be input to the source follower transistor M. SF The gate and source follower transistor M SF The corresponding electrical signal is generated and output to the selection transistor M. SE .

[0151] Gating transistor M SE The gate is used to receive the gating control signal SEL, which selects the transistor M. SE The first and source follower transistors M SF The second terminal connection selects transistor M. SE The second terminal is used to output the electrical signal Vout. Therefore, the gating control signal SEL can control the gating transistor M. SE The on / off state of the selector transistor M SE When turned on, the source follower transistor M... SF It generates a corresponding electrical signal output.

[0152] Conversion gain transistor M DCG The gate of the transistor is used to receive the conversion gain signal DCG, and the conversion gain transistor M... DCG The first and source follower transistors M SF Gate and reset transistor M RS The second terminal is connected. Therefore, the gain switching transistor M can be used... DCG Adjusting source follower transistor M SF The equivalent capacitance of the gate. Among them, the conversion gain transistor M... DCG As an optional structure, in some embodiments, the conversion gain transistor M may or may not be included. DCG It can be flexibly designed according to actual application scenarios, and no limitations are imposed here. Furthermore, the conversion gain transistor M... DCG Based on the switching gain signal DCG being turned on, the switching gain transistor M DCG The gate and channel of the transistor are equivalent to a metal oxide semiconductor (MOS) capacitor structure. Based on this, the switching gain transistor M... DCG The second electrode can be in a floating state, i.e., the switching gain transistor M. DCG The second electrode is not electrically connected to other structures or films. Alternatively, the switching gain transistor M... DCG The second terminal can also be directly connected to its first terminal, or, no conversion gain transistor M can be provided. DCG The second electrode. Or, the switching gain transistor M.DCG It can also be used with reset transistor M RS Series connection.

[0153] For example, taking the first sub-pixel group PZ1 and the second sub-pixel group PZ2 as examples, referring to Figure 6, 110 represents a photoelectric conversion element, M TG1_1 M represents the transmission transistor in the first sub-pixel region 21 of the first sub-pixel region group PZ1. TG2_1 M represents the transmission transistor in the second sub-pixel region 22 within the first sub-pixel region group PZ1. TG3_1 M represents the transmission transistor in the third sub-pixel region 23 within the first sub-pixel region group PZ1. TG4_1 M represents the transmission transistor in the fourth sub-pixel region 24 within the first sub-pixel region group PZ1. TG1_2 M represents the transmission transistor in the first sub-pixel region 21 of the second sub-pixel region group PZ2. TG2_2 M represents the transmission transistor in the second sub-pixel region 22 of the second sub-pixel region group PZ2. TG3_2 M represents the transmission transistor in the third sub-pixel region 23 within the second sub-pixel region group PZ2. TG4_2 The transmission transistor M represents the transmission transistor in the fourth sub-pixel region 24 within the second sub-pixel region group PZ2. TG1_1 ~M TG4_2 The second electrode is connected to the source follower transistor M. SF The gate.

[0154] Furthermore, the transmission transistor M TG1_1 The gate is used to receive the transmission control signal TG1_1, which can be transmitted via the transmission transistor M. TG1_1 The gate is connected to the first transmission control signal line 310 for input, to control the transmission transistor M. TG1_1 The on / off state of the transmission transistor M. TG2_1 The gate is used to receive the transmission control signal TG2_1, which can be transmitted via the transmission transistor M. TG2_1 The gate is connected to the second transmission control signal line 320 for input, to control the transmission transistor M. TG2_1 The on / off state of the transmission transistor M. TG3_1 The gate is used to receive the transmission control signal TG3_1, which can be transmitted via the transmission transistor M. TG3_1 The gate is connected to the third transmission control signal line 330 for input, to control the transmission transistor M. TG3_1 The on / off state of the transmission transistor M. TG4_1 The gate is used to receive the transmission control signal TG4_1, which can be transmitted via the transmission transistor M. TG4_1The gate is connected to the fourth transmission control signal line 340 for input, to control the transmission transistor M. TG4_1 The on / off state of the transmission transistor M. TG1_2 The gate is used to receive the transmission control signal TG1_2, which can be transmitted via the transmission transistor M. TG1_2 The gate is connected to the first transmission control signal line 310 for input, to control the transmission transistor M. TG1_2 The on / off state of the transmission transistor M. TG2_2 The gate is used to receive the transmission control signal TG2_2, which can be transmitted via the transmission transistor M. TG2_2 The gate is connected to the second transmission control signal line 320 for input, to control the transmission transistor M. TG2_2 The on / off state of the transmission transistor M. TG3_2 The gate is used to receive the transmission control signal TG3_2, which can be transmitted via the transmission transistor M. TG3_2 The gate is connected to the third transmission control signal line 330 for input, to control the transmission transistor M. TG3_2 The on / off state of the transmission transistor M. TG4_2 The gate is used to receive the transmission control signal TG4_2, which can be transmitted via the transmission transistor M. TG4_2 The gate is connected to the fourth transmission control signal line 340 for input, to control the transmission transistor M. TG4_2 The on / off state.

[0155] And, transmission transistor M TG1_1 ~M TG4_2 The first electrode is connected to the negative electrode of the photoelectric conversion element 110 (e.g., the negative electrode of the PD), and the negative electrode of each photoelectric conversion element 110 (e.g., the negative electrode of the PD) is connected to the first power line 630 to achieve grounding. With this configuration, the transmission transistor M... TG1_1 ~M TG4_2 When the photoelectric conversion elements 110 are turned on sequentially, the charge generated by each element is transferred to the FD region, causing the source follower transistor M to turn on. SF Gate discharge. In other embodiments of this application, the transfer transistor M... TG1_1 ~M TG4_2 Some or all of them can be turned on simultaneously, thereby transferring the charge generated by multiple photoelectric conversion elements 110 to the source follower transistor M at the same time. SF The gate.

[0156] In some embodiments of this application, the reset transistor M RS Source follower transistor M SF , Gating transistor M SE and conversion gain transistor M DCGIt can be configured as a thin-film transistor (TFT), thus allowing the reset transistor M to be formed using existing TFT-forming processes. RS Source follower transistor M SF , Gating transistor M SE and conversion gain transistor M DCG This reduces the difficulty of fabrication. For example, the gate of the TFT can be the gate of the aforementioned transistor, and the source of the TFT is the first terminal of the aforementioned transistor, and the drain of the TFT is the second terminal of the aforementioned transistor, or the source of the TFT is the second terminal of the aforementioned transistor, and the drain of the TFT is the first terminal of the aforementioned transistor, without limitation.

[0157] LTPS TFTs, fabricated using low-temperature poly-silicon (LTPS) semiconductor material as the channel material, exhibit high electron mobility, better switching speed, and fast response. In some embodiments of this application, the reset transistor M... RS Source follower transistor M SF , Gating transistor M SE and conversion gain transistor M DCG At least one transistor in the configuration is configured as an LTPS TFT. For example, the reset transistor M can be configured as an LTPS TFT. RS Source follower transistor M SF , Gating transistor M SE and conversion gain transistor M DCG Some transistors in the circuit are configured as LTPS TFTs. Alternatively, the reset transistor M can be used. RS Source follower transistor M SF , Gating transistor M SE and conversion gain transistor M DCG All are set to LTPS TFT.

[0158] Oxide TFTs, fabricated using metal-oxide-semiconductor materials (such as indium gallium zinc oxide (IGZO)) as the channel material, offer advantages such as low thermal budget, large channel bandgap, enabling short-channel devices and withstanding gate and source-drain voltages greater than 3V. Compared to Si transistors, they allow for further area reduction, or the design of more complex circuits within the same area, or the enlargement of the source follower transistor M. SF , conversion gain transistor M DCG The area. In other embodiments of this application, the reset transistor M... RS Source follower transistor M SF , Gating transistor M SE and conversion gain transistor M DCGAt least one transistor in the configuration is configured as an Oxide TFT. For example, the reset transistor M can be configured as an Oxide TFT. RS Source follower transistor M SF , Gating transistor M SE and conversion gain transistor M DCG Some transistors in the circuit are configured as Oxide TFTs. Alternatively, the reset transistor M can be used. RS Source follower transistor M SF , Gating transistor M SE and conversion gain transistor M DCG All are configured as Oxide TFTs. Based on this, using metal-oxide-semiconductor materials as the channel materials for transistors in the pixel circuit allows for the realization of short-channel transistors, further reducing the pixel area.

[0159] In some embodiments of this application, the reset transistor M RS Source follower transistor M SF , Gating transistor M SE and conversion gain transistor M DCG At least one transistor in the configuration can be configured as a top-gate transistor, wherein the gate layer of the top-gate transistor is located on the side of the channel layer opposite to the first device layer 100. This achieves the advantages of simple fabrication and strong compatibility. Furthermore, the gate of the top-gate transistor can isolate the channel from other film layer processes at the top, thus protecting the channel. For example, the reset transistor M... RS Source follower transistor M SF , Gating transistor M SE and conversion gain transistor M DCG Some or all of the transistors in the configuration are set as top-gate transistors.

[0160] For example, FIG7A is a top view of an image sensor from the first device layer to the second sub-signal line layer provided in an embodiment of this application; FIG7B is a top view of an image sensor from the second device layer to the second sub-signal line layer provided in an embodiment of this application; FIG7C is a top view of an image sensor from the second device layer to the first sub-signal line layer provided in an embodiment of this application; FIG7D is a top view of an image sensor from the second device layer provided in an embodiment of this application. FIG8A is a cross-sectional view along the AA' direction in FIG7A; FIG8B is a cross-sectional view along the BB' direction in FIG7A; FIG8C is a cross-sectional view along the CC' direction in FIG7A. Referring to FIG7A to FIG7D and FIG8A to FIG8C, the source follower transistor M SF The gate 501 is located on the side of its channel 533 facing away from the first device layer 100, and the reset transistor M RSThe gate 502 is located on the side of its channel 531 facing away from the first device layer 100, and the selection transistor M SE The gate 503 is located on the side of its channel 534 facing away from the first device layer 100, and the switching gain transistor M DCG The gate 504 is located on the side of its channel 532 facing away from the first device layer 100. Furthermore, the source follower transistor M... SF Between the gate 501 and its channel 533, and the reset transistor M RS Between the gate 502 and its channel 531, the select transistor M SE The gate 503 and its channel 534, and the switching gain transistor M DCG The gate 504 and its channel 532 each have a gate dielectric layer 521.

[0161] It is understood that Figure 7A shows the floating diffusion adapter 350 and the first power line 630 in the first signal line layer 300, but does not show the other structures in the first signal line layer 300 and the structure in the transition conductive layer 600. For the other structures in the first signal line layer 300 and the structure in the transition conductive layer 600, please refer to the above description, which will not be repeated here.

[0162] For example, the source follower transistor M SF With gating transistor M SE Arranged along the second direction F2, with source follower transistor M. SF The channel 533 and the gate transistor M SE The channels 534 and 534 are connected, allowing the two channels to communicate, thus enabling the source follower transistor M to... SF The channel 533 and the gate transistor M SE The 534 channel does not require additional etching to form an isolation structure, which reduces the difficulty of fabrication. Source follower transistor M... SF The first electrode 511 is located opposite to the gate 501 of the gate transistor M. SE On the gate 503 side, the source follower transistor M SF The second electrode 515 is located between its gate 501 and the gate transistor M. SE Between the gate 503 and the source follower transistor M SF The second electrode 515 and the gate transistor M SE The first electrode is shared, and the gate transistor M is selected. SE The second electrode 514 is located away from the source follower transistor M at its gate 503. SF The gate 501 side facilitates layout.

[0163] For example, the reset transistor M RS and conversion gain transistor M DCGArranged along the second direction F2, and the reset transistor M RS The channel 531 and the conversion gain transistor M DCG The 532 channels are shared, reducing fabrication difficulty and facilitating layout. Furthermore, the reset transistor M... RS The second electrode 513 can be located at its gate 502 and the switching gain transistor M DCG Between the gates 504, the reset transistor M RS The first electrode 512 is located behind the gate 502 of the switching gain transistor M. DCG On the gate 504 side. Additionally, the reset transistor M... RS The second electrode 513 can be reused as a switching gain transistor M. DCG The first pole reduces the difficulty of process preparation and facilitates layout.

[0164] For example, on the third-party F3, the source follower transistor M SF These regions overlap with the fourth sub-pixel region 24 in the first sub-pixel region group PZ1, and the second sub-pixel region 22 and the fourth sub-pixel region 24 in the second sub-pixel region group PZ2, respectively. Due to this configuration, the source follower transistor M can be maximized while minimizing the overall area of ​​the pixel region. SF The footprint should be set larger to reduce noise.

[0165] For example, on the third-party F3, the gating transistor M is used. SE Each of these overlaps with the second sub-pixel region 22 in the first sub-pixel region group PZ1. Due to this design, the selection transistor M can be minimized while maintaining the overall area of ​​the miniaturized pixel region. SE To minimize the area occupied by the source follower transistor M, in order to save space and maximize the area occupied by the source follower transistor M. SF The footprint should be set larger to further reduce noise.

[0166] For example, on the third-party F3, the switching gain transistor M DCG The first sub-pixel region 21 and the third sub-pixel region 23 in the first sub-pixel region group PZ1 have overlapping areas, respectively. Due to this configuration, the conversion gain transistor M can be maximized while minimizing the overall area of ​​the pixel region. DCG Set the occupied area to be larger to increase the dynamic range.

[0167] For example, on the third-party F3, the reset transistor M RS It overlaps with the first sub-pixel region 21 and the third sub-pixel region 23 in the second sub-pixel region group PZ2, respectively. Due to this design, the reset transistor M can be minimized while maintaining the overall area of ​​the miniaturized pixel region. RSTo minimize the area occupied by the M switching gain transistor, in order to save space and maximize the area occupied by the M switching gain transistor. DCG The area occupied is set to be larger to further increase the dynamic range.

[0168] For example, referring to Figures 7A to 7D and Figures 8A to 8C, the pixel array in the image sensor further includes a second signal line layer 900 and a fourth dielectric layer 800, with the fourth dielectric layer 800 located between the second signal line layer 900 and the second device layer 500. Furthermore, the second signal line layer 900 includes a reset control signal line 911, a gating control signal line 912, a conversion gain signal line 913, a second power supply line 914, and an output signal line 921. The reset control signal line 911 is connected to the reset transistor M through a fifth contact hole CK5. RS The gate 502 is connected, and the selection control signal line 912 is connected to the selection transistor M through the sixth contact hole CK6. SE The gate 503 is connected, and the output signal line 921 is connected to the select transistor M through the seventh contact hole CK7. SE The second terminal 514 is connected, and the conversion gain signal line 913 is connected to the conversion gain transistor M through the eighth contact hole CK8. DCG The gate 504 is connected, and the second power line 914 is connected to the source follower transistor M through the ninth contact hole CK9_2. SF The first terminal 511 is connected, and the second power line 914 is also connected to the reset transistor M through the ninth contact hole CK9_1. RS The first pole 512 connection.

[0169] For example, the fifth contact hole CK5, the sixth contact hole CK6, the seventh contact hole CK7, the eighth contact hole CK8, and the ninth contact holes CK9_1 and CK9_2 respectively penetrate the fourth dielectric layer 800. For example, during the fabrication process, conductive material can be filled into the fifth contact hole CK5 to the ninth contact hole CK9_1 and CK9_2 to form conductive portions, so as to electrically connect the corresponding signal lines and the corresponding transistors. For example, the conductive portion can be a multilayer conductive film structure, for example, the conductive portion includes a combination structure of metal nitride and metal, such as TiN / Cu, TaN / Cu, etc.

[0170] For example, when there are multiple pixel regions 20, the reset transistor M in the multiple pixel regions 20 arranged along the first direction F1 RS The reset transistors M of multiple pixel regions 20 connected to the same reset control signal line 911 and arranged along the second direction F2 RS Connect different reset control signal lines 911.

[0171] For example, when there are multiple pixel regions 20, the gating transistors M in the multiple pixel regions 20 arranged along the first direction F1 SEThe gating transistors M of multiple pixel regions 20 connected to the same gating control signal line 912 and arranged along the second direction F2 SE Connect different strobe control signal lines 912.

[0172] For example, when there are multiple pixel regions 20, the conversion gain transistors M in the multiple pixel regions 20 arranged along the first direction F1 DCG The conversion gain transistors M of multiple pixel regions 20 connected to the same conversion gain control signal line and arranged along the second direction F2 DCG Connect different conversion gain control signal lines.

[0173] In some embodiments of this application, referring to Figures 7A to 7C and 8A to 8C, the second signal line layer 900 includes a first sub-signal line layer 910 and a second sub-signal line layer 920, with a fifth dielectric layer 930 disposed between the first sub-signal line layer 910 and the second sub-signal line layer 920. The reset control signal line 911, the gating control signal line 912, and the conversion gain signal line 913 are located in the first sub-signal line layer 910 and extend along a first direction F1, which makes the wiring direction regular and optimizes the layout. Furthermore, the output signal line 921 is located in the second sub-signal line layer 920 and extends along a second direction F2. Therefore, by placing the output signal line 921 and the reset control signal line 911, the gating control signal line 912, and the conversion gain signal line 913 in different layers, the interference of the reset control signal line 911, the gating control signal line 912, and the conversion gain signal line 913 on the output signal line 921 can be reduced, further reducing noise. In other embodiments of this application, the reset control signal line 911, the gating control signal line 912, the conversion gain signal line 913, and the output signal line 921 may all be disposed in the same second signal line layer 900, that is, the reset control signal line 911, the gating control signal line 912, the conversion gain signal line 913, and the output signal line 921 may be formed using the same film layer.

[0174] For example, referring to Figures 7A to 7C and 8A to 8C, the first sub-signal line layer 910 is located between the fifth dielectric layer 930 and the fourth dielectric layer 800, and the second sub-signal line layer 920 is located on the side of the fifth dielectric layer 930 facing away from the second device layer 500. Furthermore, referring to Figures 7A, 7B, and 8C, the output signal line 921 connects to the selection transistor M through the seventh contact hole CK7 and the tenth contact hole CK10. SE The second terminal 514 is connected to enable the output signal line 921 to connect with the gating transistor M. SE The interconnection of the second electrodes of the transistor enables the selection transistor M to... SE When turned on, the source follower transistor M SF The generated electrical signal can be output to the column drive circuit through the output signal line 921.

[0175] For example, the tenth contact hole CK10 penetrates the fifth dielectric layer 930. For instance, during fabrication, a conductive material (e.g., a metallic material) can be filled into the tenth contact hole CK10 to form a conductive portion, thereby connecting the output signal line 921 and the selection transistor M. SE The second electrode is electrically connected. For example, metallic materials include, but are not limited to, Cu, Mo, Ru, etc.

[0176] For example, referring to Figures 7A, 7B, and 8C, the first sub-signal line layer 910 further includes an output transition signal line 916 located in the pixel region 20. The output transition signal line 916 is connected to the selection transistor M through the seventh contact hole CK7. SE The second terminal 514 is connected, and the output signal line 921 is connected to the output adapter signal line 916 through the tenth contact hole CK10, thereby enabling the selection transistor M. SE The second pole 514 is connected to the output signal line 921 through the output adapter signal line 916, which reduces the difficulty of process fabrication and facilitates layout.

[0177] In some embodiments of this application, when there are multiple pixel areas 20, the output transition signal lines 916 in the multiple pixel areas 20 arranged along the second direction F2 are connected to the same output signal line 921, and the output transition signal lines 916 in the multiple pixel areas 20 arranged along the first direction F1 are connected to different output signal lines 921.

[0178] For example, referring to Figures 7A to 7C and Figure 8A, the first sub-signal line layer 910 further includes a floating diffusion signal line 915 located in the pixel region 20. In the same pixel region 20, the floating diffusion signal line 915 can be connected to the floating diffusion adapter line 350 through the second sub-contact hole CK2b, so that the second pole of each transmission transistor in the same pixel region 20 can be connected to the source follower transistor M in sequence through the floating diffusion adapter 620, the floating diffusion adapter line 350 and the floating diffusion signal line 915. SF The gate 501. At this time, the second sub-contact hole CK2b can also penetrate the fourth dielectric layer 800. Furthermore, the floating diffusion signal line 915 also connects to the source follower transistor M through the eleventh contact hole CK11. SF The gate 501 is connected, and the floating diffused signal line 915 is also connected to the reset transistor M through the twelfth contact hole CK12. RS The second electrode 513 is connected, thereby making the source follower transistor M SF Gate and reset transistor M RS The second electrode and the conversion gain transistor M DCGThe first poles are interconnected, reducing the difficulty of fabrication and facilitating layout. For example, the floating diffusion signal line 915 extends along the first direction F1, and in the third direction F3, the floating diffusion signal line 915 and the floating diffusion adapter line 350 have an overlapping area, which is beneficial for miniaturizing the pixel area.

[0179] In some embodiments of this application, the structures in two adjacent pixel regions 20 along the second direction F2 are symmetrically arranged, and the pixel output circuits in two adjacent pixel regions 20 along the second direction F2 can be symmetrically arranged to further optimize the layout.

[0180] Figure 9A is a top view of another possible structure from the first device layer to the second sub-signal line layer in the image sensor provided in this embodiment; Figure 9B is a top view of another possible structure from the second device layer to the second sub-signal line layer in the image sensor provided in this embodiment; Figure 9C is a top view of another possible structure from the second device layer to the first sub-signal line layer in the image sensor provided in this embodiment; Figure 9D is a top view of another possible structure from the second device layer 500 in the image sensor provided in this embodiment. Figure 10A is a cross-sectional view along the AA' direction in Figure 9A; Figure 10B is a cross-sectional view along the BB' direction in Figure 9A. Referring to Figures 9A to 9D, 10A, and 10B, this embodiment modifies the implementation methods described in the above embodiments. The similarities are not repeated here. The differences are: in some other embodiments of this application, the reset transistor M... RS Source follower transistor M SF , Gating transistor M SE and conversion gain transistor M DCG At least one transistor in the transistor can be configured as a bottom-gate transistor, wherein the gate layer of the bottom-gate transistor is located on the side of the channel layer facing the first device layer 100. Exemplarily, the reset transistor M... RS Source follower transistor M SF , Gating transistor M SE and conversion gain transistor M DCG Some or all of the transistors in the transistor are configured as bottom-gate transistors. For example, the source follower transistor M... SF The gate 501 is located on the side of its channel 533 facing the first device layer 100, and the reset transistor M RS The gate 502 is located on the side of its channel 531 facing the first device layer 100, and the selection transistor M SE The gate 503 is located on the side of its channel 534 facing the first device layer 100, and the switching gain transistor M DCG The gate 504 is located on the side of its channel 532 facing the first device layer 100.

[0181] It is understood that Figure 9A shows the floating diffusion adapter 350 and the first power line 630 in the first signal line layer 300, but does not show the other structures in the first signal line layer 300 and the structure in the transition conductive layer 600. For the other structures in the first signal line layer 300 and the structure in the transition conductive layer 600, please refer to the above description, which will not be repeated here.

[0182] For example, due to the source follower transistor M SF Since it is a bottom-gate transistor, the floating diffusion signal line 915 is not required in this application. Referring to Figures 9A to 9D and Figure 10B, the source follower transistor M... SF The gate is directly connected to the floating diffusion adapter 350 through the second sub-contact hole CK2b_1. The second sub-contact hole CK2b_1 penetrates the second dielectric layer 400.

[0183] For example, referring to Figures 9A to 9D and Figure 10A, the reset transistor M RS The second electrode 513 can also be connected to the floating diffusion adapter 350 through the second sub-contact hole CK2b_2, and the reset transistor M RS The second electrode 513 is multiplexed as a switching gain transistor M DCG The first electrode, thereby enabling the reset transistor M RS The second electrode, the conversion gain transistor M DCG The first electrode can be connected to the source follower transistor M via a floating diffusion adapter 350. SF The gate is electrically connected, further optimizing the layout. The second sub-contact CK2b_2 penetrates the second dielectric layer 400 and the gate dielectric layer 521.

[0184] For example, referring to Figures 9A to 9D and Figure 10B, the selection control signal line 912 is connected to the selection transistor M through the sixth contact hole CK6. SE The gate 503 is connected, and the sixth contact hole CK6 penetrates the fourth dielectric layer 800 and the gate dielectric layer 521. Furthermore, the conversion gain signal line 913 connects to the conversion gain transistor M through the eighth contact hole CK8. DCG The gate 504 is connected, and the eighth contact hole CK8 penetrates the fourth dielectric layer 800 and the gate dielectric layer 521. Additionally, the reset control signal line 911 connects to the reset transistor M through the fifth contact hole CK5. RS The gate 502 is connected, and the fifth contact hole CK5 penetrates the fourth dielectric layer 800 and the gate dielectric layer 521.

[0185] Figure 11 is a top view of another possible structure from the first device layer to the second sub-signal line layer in an image sensor provided in an embodiment of this application. Figure 12 is a schematic diagram of another possible equivalent circuit of the transistor and photoelectric conversion element in a pixel provided in an embodiment of this application. Referring to Figures 11 and 12, this embodiment modifies the implementation methods in the above embodiments. The similarities are not repeated here. The differences are: in some embodiments of this application, the pixel output circuit further includes a global shutter (GS) transistor M. GS Global exposure transistor M GS The gate is used to receive the global exposure signal GS, and the global exposure transistor M is controlled by the global exposure signal GS. GS On / off state, global exposure transistor M GS Set in the source follower transistor M SF Between the gate 501 and the second electrode of each transmission transistor, in the globally exposed transistor M GS When the transmission transistor is turned on, the charge generated by the photoelectric conversion element can be stored in the source follower transistor M. SF The gate of the photoelectric conversion element. In existing technologies, this is achieved by additionally fabricating a metal-insulator-metal (MIM) capacitor structure or directly bonding a dynamic random access memory (DRAM) die to store the charge generated by the photoelectric conversion element in the MIM capacitor structure or DRAM die. However, the MIM capacitor structure or DRAM die is complex and costly. In this embodiment, a globally exposed transistor M is used... GS This allows the charge generated by the photoelectric conversion element to be stored in the source follower transistor M. SF This improves the gate effect, reduces the difficulty of process fabrication, and facilitates layout.

[0186] Furthermore, the reset transistor M RS The second electrode 513 and the conversion gain transistor M DCG The first electrode is also exposed through global exposure of transistor M. GS With source follower transistor M SF The gate 501 is connected, and the transistor M is exposed globally. GS When turned on, the reset transistor M can also be activated. RS The second electrode and the conversion gain transistor M DCG The first electrode is respectively connected to the source follower transistor M SF The gate is connected, which enables the effects of reset and gain adjustment.

[0187] For example, the globally exposed transistor M GSIt can be set to an Oxide TFT, which can reduce the source follower transistor M. SF The voltage at the gate leaks into the first device layer 100. It is worth noting that the transfer transistor is a Si transistor. Compared to Si transistors, Oxide TFTs have much lower leakage current. In this embodiment, a global exposure transistor M, configured as an Oxide TFT, is added. GS This can further reduce leakage current and further improve the accuracy of image sensors.

[0188] For example, the globally exposed transistor M GS It can be a top-gate transistor or a bottom-gate transistor. The following example uses a globally exposed transistor M. GS The following example illustrates a top-gate transistor. For instance, referring to Figure 11, the transistor M is globally exposed. GS The gate 505 is located on the side of its channel 535 facing away from the first device layer 100, and the globally exposed transistor M GS The gate 505 is located between its first electrode 516 and its second electrode 517. Furthermore, the globally exposed transistor M... GS Located in reset transistor M RS and source follower transistor M SF between.

[0189] In order to expose the global exposure transistor M GS With source follower transistor M SF In terms of connection, the first sub-signal line layer 910 also includes a global transition signal line 917, which connects to the global exposure transistor M through the fourteenth contact hole CK14. GS The second terminal 517 is connected, and the global adapter signal line 917 is also connected to the source follower transistor M through the fifteenth contact hole CK15. SF The gate 501 is connected, thereby enabling the global exposure transistor M GS The second electrode 517 and the source follower transistor M SF The gates 501 are interconnected. For example, the global transition signal line 917 can extend along the first direction F1 to optimize the layout.

[0190] In order to expose the global exposure transistor M GS With reset transistor M RS , conversion gain transistor M DCG In connection with each transmission transistor, exemplarily, referring to FIG11, the floating diffusion signal line 915 is also connected to the global exposure transistor M through the thirteenth contact hole CK13. GS The first electrode 516 is connected, thereby enabling the global exposure transistor M. GS The first electrode 516 and the reset transistor M RS The second electrode 513, the conversion gain transistor MDCG The first electrode and the second electrode of each transmission transistor are interconnected.

[0191] It is understood that Figure 11 shows the floating diffusion adapter 350 and the first power line 630 in the first signal line layer 300, but does not show the other structures in the first signal line layer 300 and the structure in the transition conductive layer 600. For the other structures in the first signal line layer 300 and the structure in the transition conductive layer 600, please refer to the above description, which will not be repeated here.

[0192] Figure 13 is a top view schematic diagram of another image sensor structure from the first device layer to the second sub-signal line layer provided in the embodiment of this application. Figure 14 is a schematic diagram of another equivalent circuit of the transistor and photoelectric conversion element in a pixel provided in the embodiment of this application. Referring to Figures 13 and 14, this embodiment modifies the implementation method in the above embodiments. The similarities are not repeated here. The difference is that the pixel area includes a pixel area group, that is, the pixel area includes a first sub-pixel area 21, a second sub-pixel area 22, a third sub-pixel area 23, and a fourth sub-pixel area 24 arranged in a 2×2 array. With this configuration, the layout of the pixel output circuit can be realized simply by reducing the size of the above pixel output circuit.

[0193] It is understood that Figure 13 illustrates the floating diffusion adapter line 350 and the first power line 630 in the first signal line layer 300, but does not illustrate the remaining structures in the first signal line layer 300 and the structures in the transition conductive layer 600. The remaining structures in the first signal line layer 300 and the structures in the transition conductive layer 600 can be referred to the foregoing description, and will not be repeated here. Furthermore, the remaining structures in this embodiment can be referred to the above description, and will not be repeated here.

[0194] The above description is only a specific implementation of this application, but the protection scope of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the protection scope of this application.

Claims

1. An image sensor, characterized in that, include: A first device layer, a first dielectric layer, a first signal line layer, a second dielectric layer, and a second device layer are stacked together. The first device layer includes a semiconductor substrate, a plurality of photoelectric conversion elements and a plurality of transmission transistors. The semiconductor substrate includes a pixel region, the pixel region includes a plurality of sub-pixel regions, and each sub-pixel region is provided with a photoelectric conversion element and a transmission transistor, and the first pole of the photoelectric conversion element and the transmission transistor are connected. The first signal line layer includes multiple transmission control signal lines, and the gate of any of the transmission transistors is connected to one of the transmission control signal lines through a first contact hole; The second device layer includes a pixel output circuit located in the pixel region, the pixel output circuit being connected to the second terminal of each of the transmission transistors in the pixel region through a second contact hole; Wherein, the first terminal of the transmission transistor is the source, and the second terminal of the transmission transistor is the drain, or the first terminal of the transmission transistor is the drain, and the second terminal of the transmission transistor is the source; The first contact hole penetrates the first dielectric layer, and the second contact hole penetrates both the first dielectric layer and the second dielectric layer.

2. The image sensor according to claim 1, characterized in that, The image sensor further includes: a transition conductive layer and a third dielectric layer, wherein the transition conductive layer is located between the first dielectric layer and the first device layer, and the third dielectric layer is located between the transition conductive layer and the first device layer; The transition conductive layer includes a gate transition portion located in each of the sub-pixel regions. The gate transition portion connects the gate of the transmission transistor to the transmission control signal line through a third contact hole and a first contact hole. The third contact hole penetrates the third dielectric layer.

3. The image sensor according to claim 2, characterized in that, The gate transition portion includes a main body portion and a protrusion portion connected to each other, the main body portion extending along a second direction, and the protrusion portion located on one side of the main body portion in a first direction; The main body is connected to the transmission control signal line through the first contact hole, and the protrusion is connected to the gate of the transmission transistor through the third contact hole.

4. The image sensor according to claim 3, characterized in that, The plurality of sub-pixel regions include a first sub-pixel region and a second sub-pixel region arranged along the first direction, wherein the gate and the main body portion of the transmission transistor in the first sub-pixel region and the second sub-pixel region are respectively arranged along the first direction; The transmission control signal lines connected to the transmission transistors in the first sub-pixel region and the second sub-pixel region are arranged adjacently and extend along the first direction, and the first contact holes in the first sub-pixel region and the first contact holes in the second sub-pixel region are staggered in the first direction.

5. The image sensor according to claim 4, characterized in that, In the same gate transition portion, the protrusion is located at one end of the main body portion in the second direction; or, The protrusions in the first sub-pixel region and the second sub-pixel region are arranged along the first direction; or... The protrusions in the first sub-pixel region and the second sub-pixel region are located between the main body portions in the first sub-pixel region and the second sub-pixel region.

6. The image sensor according to claim 5, characterized in that, The gate transition portions in the first sub-pixel region and the second sub-pixel region are symmetrically arranged.

7. The image sensor according to any one of claims 4-6, characterized in that, The transmission control signal line connected to the transmission transistor in the first sub-pixel region is a first transmission control signal line, and the transmission control signal line connected to the transmission transistor in the second sub-pixel region is a second transmission control signal line. In the third direction, the first transmission control signal line has overlapping areas with the main body and protrusion in the first sub-pixel region and the main body and protrusion in the second sub-pixel region, respectively. The second transmission control signal line has overlapping areas with the main body in the first sub-pixel region and the main body in the second sub-pixel region, respectively. The third direction is perpendicular to the second direction and the first direction, respectively.

8. The image sensor according to claim 7, characterized in that, In the third direction, the first transmission control signal line has an overlapping area with the first contact hole and the third contact hole in the first sub-pixel area, and the third contact hole in the second sub-pixel area, and the second transmission control signal line has an overlapping area with the first contact hole in the second sub-pixel area.

9. The image sensor according to any one of claims 4-8, characterized in that, The plurality of sub-pixel regions also includes a third sub-pixel region, which is arranged along the second direction with the first sub-pixel region, and the structure in the third sub-pixel region is symmetrically arranged with that in the first sub-pixel region.

10. The image sensor according to claim 9, characterized in that, The transmission control signal line connected to the transmission transistor in the third sub-pixel region is the third transmission control signal line, which is symmetrically arranged with the first transmission control signal line.

11. The image sensor according to claim 9 or 10, characterized in that, The plurality of sub-pixel regions also includes a fourth sub-pixel region, which is arranged along the second direction with the second sub-pixel region, and the structures in the fourth sub-pixel region and the second sub-pixel region are symmetrically arranged.

12. The image sensor according to claim 11, characterized in that, The transmission control signal line connected to the transmission transistor in the fourth sub-pixel region is a fourth transmission control signal line, and the fourth transmission control signal line is symmetrically arranged with the second transmission control signal line; or... The fourth sub-pixel region and the third sub-pixel region are arranged along the first direction, and the fourth transmission control signal line and the second transmission control signal line are located between the first transmission control signal line and the third transmission control signal line.

13. The image sensor according to any one of claims 1-12, characterized in that, The first signal line layer further includes a floating diffusion adapter line located in the pixel area. The second contact hole includes a first sub-contact hole and a second sub-contact hole. The floating diffusion adapter line is connected to the pixel output circuit through the second sub-contact hole. The floating diffusion adapter line is connected to the second pole of each of the transmission transistors in the pixel area through the first sub-contact hole. The first sub-contact hole penetrates the first dielectric layer, and the second sub-contact hole penetrates the second dielectric layer.

14. The image sensor according to claim 13, characterized in that, The image sensor further includes a transition conductive layer and a third dielectric layer, wherein the transition conductive layer is located between the first dielectric layer and the first device layer, and the third dielectric layer is located between the transition conductive layer and the first device layer; The transition conductive layer further includes a floating diffusion transition portion located in the pixel area. The floating diffusion transition portion is connected to the floating diffusion transition line through the first sub-contact hole. The floating diffusion transition portion is connected to the second electrode of each of the transmission transistors in the pixel area through the fourth contact hole. The fourth contact hole penetrates the third dielectric layer.

15. The image sensor according to claim 14, characterized in that, The plurality of sub-pixel regions include a sub-pixel region group, and the sub-pixel region group includes a first sub-pixel region, a second sub-pixel region, a third sub-pixel region, and a fourth sub-pixel region; The floating diffusion adapter is connected to the second electrode of each of the transmission transistors in the sub-pixel group through the fourth contact hole.

16. The image sensor according to claim 15, characterized in that, The plurality of sub-pixel regions include at least two sub-pixel region groups, and the at least two sub-pixel region groups include a first sub-pixel region group and a second sub-pixel region group arranged along the second direction; The first end of the floating diffusion adapter is connected to the second electrode of each transmission transistor in the first sub-pixel group through one of the fourth contact holes, and the second end of the floating diffusion adapter is connected to the second electrode of each transmission transistor in the second sub-pixel group through another of the fourth contact holes.

17. The image sensor according to claim 16, characterized in that, The floating diffusion adapter extends along the second direction, and the floating diffusion adapter line extends along the first direction; The floating diffusion adapter cable and the floating diffusion adapter part have an overlapping area in the third direction, and the first sub-contact hole is located in the overlapping area.

18. The image sensor according to claim 17, characterized in that, The floating diffusion adapter line is located between the transmission control signal line connected to the first sub-pixel group and the transmission control signal line connected to the second sub-pixel group; or... The structures in the first sub-pixel group and the second sub-pixel group are symmetrically arranged; or... The transmission control signal lines connected to the first sub-pixel group and the transmission control signal lines connected to the second sub-pixel group are symmetrically arranged.

19. The image sensor according to any one of claims 1-18, characterized in that, The negative terminal of the photoelectric conversion element is connected to the first terminal of the transmission transistor. The first signal line layer also includes a first power line, which is arranged around the pixel area and is connected to the positive terminal of each photoelectric conversion element in the pixel area.

20. The image sensor according to any one of claims 1-19, characterized in that, The pixel output circuit includes a reset transistor, a source follower transistor, a gating transistor, and a conversion gain transistor, with the second terminal of each of the transmission transistors connected to the gate of the source follower transistor. At least one of the reset transistor, the source follower transistor, the gating transistor, and the conversion gain transistor is an oxide thin-film transistor or a low-temperature polycrystalline silicon thin-film transistor.

21. The image sensor according to claim 20, characterized in that, The plurality of sub-pixel regions include at least two sub-pixel region groups, each sub-pixel region group including a first sub-pixel region, a second sub-pixel region, a third sub-pixel region and a fourth sub-pixel region, and the at least two sub-pixel region groups include a first sub-pixel region group and a second sub-pixel region group arranged along the second direction; In a third direction, the source follower transistor has overlapping regions with the fourth sub-pixel region in the first sub-pixel region group, the second sub-pixel region in the second sub-pixel region group, and the fourth sub-pixel region; or... In a third direction, the reset transistor has overlapping areas with the first sub-pixel region and the third sub-pixel region in the second sub-pixel region group; or... In a third direction, the gating transistors overlap with the second sub-pixel regions in the first sub-pixel region group; or... In the third direction, the conversion gain transistor has overlapping regions with the first sub-pixel region and the third sub-pixel region in the first sub-pixel region group, respectively.

22. The image sensor according to claim 20 or 21, characterized in that, The image sensor further includes a second signal line layer and a fourth dielectric layer, wherein the fourth dielectric layer is located between the second signal line layer and the second device layer; The second signal line layer includes a reset control signal line, a gating control signal line, a conversion gain signal line, a second power supply line, and an output signal line. The reset control signal line is connected to the gate of the reset transistor through a fifth contact hole. The gating control signal line is connected to the gate of the gating transistor through a sixth contact hole. The output signal line is connected to the second terminal of the gating transistor through a seventh contact hole. The conversion gain signal line is connected to the gate of the conversion gain transistor through an eighth contact hole. The second power supply line is connected to the first terminal of the source follower transistor and the first terminal of the reset transistor through a ninth contact hole. The fifth, sixth, seventh, eighth, and ninth contact holes respectively penetrate the fourth dielectric layer.

23. The image sensor according to claim 22, characterized in that, The second signal line layer includes a first sub-signal line layer and a second sub-signal line layer, and a fifth dielectric layer is disposed between the first sub-signal line layer and the second sub-signal line layer; The reset control signal line, the gating control signal line, and the conversion gain signal line are located in the first sub-signal line layer and extend along the first direction; The output signal line is located in the second sub-signal line layer and extends along the second direction.

24. The image sensor according to claim 23, characterized in that, The first sub-signal line layer is located between the fifth dielectric layer and the fourth dielectric layer, and the second sub-signal line layer is located on the side of the fifth dielectric layer facing away from the second device layer. The output signal line is connected to the second terminal of the gate transistor through the seventh contact hole and the tenth contact hole, and the tenth contact hole penetrates the fifth dielectric layer.

25. An image acquisition device, characterized in that, include: The processor and the image sensor as described in any one of claims 1-24, wherein the processor is electrically connected to the image sensor.

26. An electronic device, characterized in that, include: The image acquisition device as described in claim 25.

Images