Tunable laser chip having high saturated power and narrow linewidth, and manufacturing method therefor

Abstract

The present application relates to a tunable laser chip having high saturated power and a narrow linewidth, and a manufacturing method therefor. The tunable laser chip having the high saturated power and the narrow linewidth comprises a chip substrate 1, and a first SOA 2, a first reflector 3, an active region 4, and a second reflector 5 that are sequentially arranged on the chip substrate 1 from front to back in a light exit direction; the total optical thickness of a first quantum well region 202 of the first SOA 2 is smaller than the total optical thickness of a second quantum well region 402 of the active region 4, and / or the number of quantum wells of the first quantum well region 202 of the first SOA 2 is smaller than the number of quantum wells of the second quantum well region 402 of the active region 4. In the present application, the tunable laser chip can obtain higher saturated output optical power and a narrower linewidth.

Description

A high-saturation-power, narrow-linewidth tunable laser chip and its fabrication method

[0001] Cross-reference of related applications

[0002] This application claims priority to the following patent application:

[0003] (1) A Chinese patent application filed on January 14, 2025, with application number 202510054017.3 and titled “A tunable laser chip with high saturation power and narrow linewidth and its manufacturing method”. Technical Field

[0004] This application relates to the field of semiconductor technology, and in particular to a high-saturation-power, narrow-linewidth tunable laser chip and its fabrication method. Background Technology

[0005] With the rapid development of the internet, the demand for network bandwidth is increasing. Monolithic integrated chips with comprehensive functions, powerful performance, and low power consumption are gaining increasing attention. For example, monolithic integrated tunable lasers are highly valued as core chips for future 5G networks and intelligent optical networks. As the transmission rate of coherent transmission networks increases, the system's requirements for laser linewidth are also increasing. Currently, typical coherent transmission systems require tunable laser chips with a linewidth below 300kHz. Generally, standalone tunable laser chips suffer from uneven power output and low optical power. To address this issue, the existing solution is to directly integrate a semiconductor optical amplifier (SOA) with the same active region structure as the tunable laser chip's gain region in the chip's output direction.

[0006] However, because the active region of the tunable laser chip uses the same quantum well structure design as that of the semiconductor optical amplifier, it is difficult to optimize the characteristics of the two quantum wells separately. Specifically, in the design of narrow-linewidth quantum well laser chips, it is usually considered to use more quantum wells, reduce the carrier filling density in each quantum well, increase the differential gain of the material, reduce the linewidth enhancement factor of the material, and reduce the linewidth of the emitted light signal of the laser. However, in the optical amplifier part, it is usually considered to increase the overall saturated output optical power of the chip. Under this requirement, it is usually necessary to reduce the number of quantum wells of the chip, reduce the mode field confinement factor of the active region, suppress the gain saturation effect, and increase the saturated output optical power of the final optical chip. Therefore, the design requirements of the two quantum wells are not the same, and it is difficult to obtain a high-performance tunable laser chip with narrow linewidth and high saturated output optical power by using a design with a unified quantum well active region.

[0007] Therefore, how to overcome the shortcomings of the existing technology and how to solve the above-mentioned technical problems is a difficult problem that urgently needs to be solved in this technical field.

[0008] Application content

[0009] To address the aforementioned technical problems or needs: in monolithically integrated SOA tunable laser chips, the design of a unified quantum well active region makes it difficult to simultaneously achieve narrow linewidth spectral performance and high saturation output power. This application provides a high-saturation-power, narrow-linewidth tunable laser chip and its fabrication method, whereby the total optical thickness of the first quantum well region of the first SOA is less than the total optical thickness of the second quantum well region of the active region, or the number of quantum wells in the first quantum well region of the first SOA is less than the number of quantum wells in the second quantum well region of the active region, thereby achieving a lower optical field confinement factor for the first SOA compared to the active region. Through this design, the optical field confinement factor at the first SOA is lower, making it easier to obtain higher saturation output power; the optical field confinement factor at the active region is higher, making it easier to obtain a lower linewidth enhancement factor, providing superior linewidth performance. This enables the tunable laser chip to achieve higher saturation output power and lower linewidth.

[0010] This application is implemented as follows:

[0011] In a first aspect, this application provides a high-saturation-power, narrow-linewidth tunable laser chip, comprising a chip substrate 1 and a first SOA2, a first reflector 3, an active region 4, and a second reflector 5 arranged sequentially from front to back on the chip substrate 1, starting from the light emission direction; wherein the total optical thickness of the first quantum well region 202 of the first SOA2 is less than the total optical thickness of the second quantum well region 402 of the active region 4, and / or the number of quantum wells in the first quantum well region 202 of the first SOA2 is less than the number of quantum wells in the second quantum well region 402 of the active region 4.

[0012] In some embodiments, the first quantum well region 202 includes a first lower waveguide layer 2021, a quantum well composed of several alternately stacked first quantum well thin layers 2022 and first quantum well barrier thin layers 2023, and a first upper waveguide layer 2024, arranged sequentially from bottom to top; the second quantum well region 402 includes a second lower waveguide layer 4021, a quantum well composed of several alternately stacked second quantum well thin layers 4022 and second quantum well barrier thin layers 4023, and a second upper waveguide layer 4024, arranged sequentially from bottom to top.

[0013] In some embodiments, the first quantum well region 202 includes 1 to 5 pairs of quantum wells, and the second quantum well region 402 includes 6 to 20 pairs of quantum wells.

[0014] In some embodiments, the chip substrate 1 includes a first InP buffer layer 101 and an InP spacer layer 103 arranged sequentially from bottom to top; the first SOA2 includes a second InP buffer layer 201, a first quantum well region 202 and a third upper waveguide layer 203 arranged sequentially from bottom to top starting from the chip substrate 1; the first reflector 3 includes a third InP buffer layer 301, a first optical waveguide region 302 and a fourth upper waveguide layer 303 arranged sequentially from bottom to top starting from the chip substrate 1; the active region 4 includes a fourth InP buffer layer 401, a second quantum well region 402 and a fifth upper waveguide layer 403 arranged sequentially from bottom to top starting from the chip substrate 1; and the second reflector 5 includes a fifth InP buffer layer 501, a second optical waveguide region 502 and a sixth upper waveguide layer 503 arranged sequentially from bottom to top starting from the chip substrate 1.

[0015] In some embodiments, the chip substrate 1 further includes a sparse waveguide layer 102, which is disposed between the first InP buffer layer 101 and the InP spacer layer 103.

[0016] In some embodiments, a phase waveguide region 6 is further provided on the chip substrate 1, the phase waveguide region 6 being disposed between the active region 4 and the second reflector 5.

[0017] In some embodiments, the phase waveguide region 6 includes, from bottom to top, a sixth InP buffer layer 601, a third optical waveguide region 602, and a seventh upper waveguide layer 603, arranged sequentially from bottom to top, starting from the chip substrate 1.

[0018] In some embodiments, a second SOA7 is further disposed on the chip substrate 1, the second SOA7 being disposed between the first SOA2 and the first reflector 3.

[0019] In some embodiments, the second SOA7 includes, starting from the chip substrate 1, a seventh InP buffer layer 701, a third quantum well region 702, and an eighth upper waveguide layer 703 arranged sequentially from bottom to top; the third quantum well region 702 includes, from bottom to top, a third lower waveguide layer 7021, a quantum well composed of several alternately stacked third quantum well thin layers 7022 and third quantum well barrier thin layers 7023 forming a quantum well, and a ninth upper waveguide layer 7024; the number of quantum wells in the third quantum well region 702 is greater than the number of quantum wells in the first quantum well region 202.

[0020] Secondly, this application provides a method for fabricating a high-saturation-power, narrow-linewidth tunable laser chip, applicable to the high-saturation-power, narrow-linewidth tunable laser chip described in the first aspect. The method includes: fabricating a first SOA2, a first reflector 3, an active region 4, and a second reflector 5 sequentially from front to back on a chip substrate 1, starting from the light emission direction; wherein the total optical thickness of the first quantum well region 202 of the fabricated first SOA2 is less than the total optical thickness of the second quantum well region 402 of the fabricated active region 4, and / or the number of quantum wells in the first quantum well region 202 of the fabricated first SOA2 is less than the number of quantum wells in the second quantum well region 402 of the fabricated active region 4.

[0021] Compared with existing technologies, the beneficial effects of this application are as follows: It provides a tunable laser chip with high saturation power and narrow linewidth, and a method for fabricating the same. This method makes the total optical thickness of the first quantum well region of the first SOA smaller than the total optical thickness of the second quantum well region of the active region, or makes the number of quantum wells in the first quantum well region of the first SOA smaller than the number of quantum wells in the second quantum well region of the active region, thereby achieving a lower optical field confinement factor for the first SOA than for the active region. Through this design, the optical field confinement factor at the first SOA is lower, making it easier to obtain higher saturated output optical power. The optical field confinement factor at the active region is higher, making it easier to obtain a lower linewidth enhancement factor, providing superior linewidth performance. This enables the tunable laser chip to achieve higher saturated output optical power and lower linewidth. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 is a cross-sectional schematic diagram of a high-saturation-power, narrow-linewidth tunable laser chip provided in an embodiment of this application;

[0024] Figure 2 is a cross-sectional schematic diagram of the first type of chip substrate provided in the embodiment of this application;

[0025] Figure 3 is a cross-sectional schematic diagram of the second type of chip substrate provided in the embodiment of this application;

[0026] Figure 4 is a schematic diagram of the layer arrangement of the first SOA provided in the embodiment of this application;

[0027] Figure 5 is a schematic diagram of the arrangement of each layer of the first reflector provided in the embodiment of this application;

[0028] Figure 6 is a schematic diagram of the arrangement of each layer of the active region provided in the embodiment of this application;

[0029] Figure 7 is a schematic diagram of the layer arrangement of the second reflector provided in the embodiment of this application;

[0030] Figure 8 is a schematic diagram of the arrangement of each layer of the phase waveguide region provided in the embodiment of this application;

[0031] Figure 9 is a schematic diagram of the layer arrangement of the second SOA provided in the embodiment of this application;

[0032] Figure 10 is a schematic diagram of a first example provided in the embodiments of this application;

[0033] Figure 11 is a schematic diagram of a second example provided in the embodiments of this application;

[0034] Figure 12 is a schematic diagram of a third example provided in the embodiments of this application;

[0035] Figure 13 is a schematic diagram of a fourth example provided in the embodiments of this application;

[0036] Figure 14 is a schematic diagram of the fifth example provided in the embodiments of this application. Detailed Implementation

[0037] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as openly inclusive, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples; that is, although they may be incorporated into embodiments or examples using the above terms for reasons such as order and position, it does not limit them to be incorporated in combination by a single embodiment or example.

[0038] In the description of this application, the terms "inner", "outer", "longitudinal", "lateral", "upper", "lower", "left", "right", "top", "bottom", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and do not require this application to be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0039] The present application will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present application, but do not limit the present application in any way. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present application. These all fall within the protection scope of the present application.

[0040] It should be noted that, unless otherwise defined, the various features in the embodiments of this application can be combined with each other, all of which are within the protection scope of this application. Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. The terminology and location descriptions used in this specification are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0041] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0042] Example 1

[0043] Referring to Figure 1, Embodiment 1 of this application provides a high-saturation-power, narrow-linewidth tunable laser chip, including a chip substrate 1 and a first SOA2, a first reflector 3, an active region 4, and a second reflector 5 arranged sequentially from front to back on the chip substrate 1, starting from the light emission direction. The total optical thickness of the first quantum well region 202 of the first SOA2 is less than the total optical thickness of the second quantum well region 402 of the active region 4, and / or the number of quantum wells in the first quantum well region 202 of the first SOA2 is less than the number of quantum wells in the second quantum well region 402 of the active region 4, so as to achieve a lower optical field confinement factor in the first quantum well region than in the second quantum well region 402. The total optical thickness of the quantum well region refers to the sum of the products of the physical thickness of each layer and the refractive index of each layer. Through the above configuration, the optical field confinement factor at the first SOA2 is lower, making it easier to obtain higher saturated output optical power; the optical field confinement factor at the active region 4 is higher, making it easier to obtain a lower linewidth enhancement factor, providing better linewidth performance.

[0044] Referring to Figure 2, in some embodiments, the chip substrate 1 includes a first InP buffer layer 101 and an InP spacer layer 103 disposed sequentially from bottom to top. The chip substrate 1 can serve as a common substrate for all other components, and all other components can be arranged on the chip substrate 1.

[0045] Referring to Figure 3, in some embodiments, the chip substrate 1 further includes a sparse waveguide layer 102, which is disposed between the first InP buffer layer 101 and the InP spacer layer 103. By further configuring the sparse waveguide layer 102, the difference between the optical field confinement factor at the first SOA2 and the active region 4 can be further increased. The mode field at the first SOA2 can more easily extend into the sparse waveguide layer 102, further reducing the optical field confinement factor; however, the mode field at the active region 4 is difficult to extend into the sparse waveguide layer 102, and the optical field confinement factor is essentially not reduced.

[0046] Referring to Figure 4, in some embodiments, the first SOA2 includes, from bottom to top, a second InP buffer layer 201, a first quantum well region 202, and a third upper waveguide layer 203, arranged sequentially from bottom to top, starting from the chip substrate 1. The first quantum well region 202 includes, from bottom to top, a first lower waveguide layer 2021 with a lower refractive index, a quantum well composed of several alternately stacked first quantum well thin layers 2022 and first quantum well barrier thin layers 2023, and a first upper waveguide layer 2024 with a lower refractive index. The first lower waveguide layer 2021 and the first upper waveguide layer 2024 can be composed of thin layers of a single component or multiple thin layers of multiple components.

[0047] Referring to Figure 5, in some embodiments, the first reflector 3 can be a waveguide reflector or a sampling grating waveguide reflector, etc.; the first reflector 3 includes, from bottom to top, a third InP buffer layer 301, a first optical waveguide region 302, and a fourth upper waveguide layer 303, arranged sequentially from bottom to top, starting from the chip substrate 1. The material of the first optical waveguide region 302 includes InGaAsP, and the composition of the InGaAsP material is an alloy material with a fluorescence wavelength of 1.35 micrometers and a strain matching that of InP.

[0048] Referring to Figure 6, in some embodiments, the active region 4, starting from the chip substrate 1, includes a fourth InP buffer layer 401, a second quantum well region 402, and a fifth upper waveguide layer 403 arranged sequentially from bottom to top. The second quantum well region 402 includes a second lower waveguide layer 4021 with a lower refractive index, a quantum well composed of several alternately stacked second quantum well thin layers 4022 and second quantum well barrier thin layers 4023, and a second upper waveguide layer 4024 with a lower refractive index, arranged sequentially from bottom to top. The second lower waveguide layer 4021 and the second upper waveguide layer 4024 can be composed of thin layers of a single component or multiple thin layers of multiple components.

[0049] In some embodiments, the first quantum well region 202 typically includes 1 to 5 pairs of quantum wells, and the second quantum well region 402 typically includes 6 to 20 pairs of quantum wells. This is to ensure that the number of quantum wells in the first quantum well region 202 of the first SOA2 is less than the number of quantum wells in the second quantum well region 402 of the active region 4. The number of quantum wells in Figures 4 and 6 are merely examples and are not intended to be limiting.

[0050] Referring to Figure 7, in some embodiments, the second reflector 5 can be a waveguide reflector or a sampling grating waveguide reflector, etc.; the second reflector 5 includes, from bottom to top, a fifth InP buffer layer 501, a second optical waveguide region 502, and a sixth upper waveguide layer 503, arranged sequentially from bottom to top, starting from the chip substrate 1. The material of the second optical waveguide region 502 includes InGaAsP, and the composition of the InGaAsP material is an alloy material with a fluorescence wavelength of 1.35 micrometers and a strain matching that of InP.

[0051] Referring to Figure 8, in some embodiments, a phase waveguide region 6 is further included on the chip substrate 1, the phase waveguide region 6 being disposed between the active region 4 and the second reflector 5. The phase waveguide region 6, starting from the chip substrate 1, includes a sixth InP buffer layer 601, a third optical waveguide region 602, and a seventh upper waveguide layer 603, arranged sequentially from bottom to top. The third optical waveguide region 602 is made of InGaAsP, the InGaAsP material having a fluorescence wavelength of 1.35 micrometers and a strain matching that of InP.

[0052] Referring to Figure 9, in some embodiments, a second SOA7 is further included on the chip substrate 1, disposed between the first SOA2 and the first reflector 3. The second SOA7, starting from the chip substrate 1, includes a seventh InP buffer layer 701, a third quantum well region 702, and an eighth upper waveguide layer 703 arranged sequentially from bottom to top. The third quantum well region 702 includes a third lower waveguide layer 7021, a quantum well composed of several alternately stacked third quantum well thin layers 7022 and third quantum well barrier thin layers 7023, and a ninth upper waveguide layer 7024 arranged sequentially from bottom to top. The number of quantum wells in the third quantum well region 702 is greater than the number of quantum wells in the first quantum well region 202.

[0053] This application provides a method for fabricating a high-saturation-power, narrow-linewidth tunable laser chip, applicable to the aforementioned high-saturation-power, narrow-linewidth tunable laser chip. The method includes: fabricating a first quantum well region 202, a first reflector 3, an active region 4, and a second reflector 5 sequentially from front to back on a chip substrate 1, starting from the light emission direction; wherein the total optical thickness of the first quantum well region 202 of the fabricated first SOA2 is less than the total optical thickness of the second quantum well region 402 of the fabricated active region 4, and / or, the number of quantum wells in the first quantum well region 202 of the fabricated first SOA2 is less than the number of quantum wells in the second quantum well region 402 of the fabricated active region 4. The specific structural design of each component is not detailed here.

[0054] In summary, this application provides a high-saturation-power, narrow-linewidth tunable laser chip and its fabrication method. The total optical thickness of the first quantum well region of the first SOA is less than the total optical thickness of the second quantum well region of the active region, or the number of quantum wells in the first quantum well region of the first SOA is less than the number of quantum wells in the second quantum well region of the active region. This achieves a lower optical field confinement factor for the first SOA compared to the active region. Through this design, the optical field confinement factor at the first SOA is lower, making it easier to obtain higher saturated output optical power. The optical field confinement factor at the active region is higher, making it easier to obtain a lower linewidth enhancement factor, providing superior linewidth performance. This enables the tunable laser chip to achieve higher saturated output optical power and lower linewidth.

[0055] Example 2

[0056] Referring to Figure 10, based on the solution provided in Embodiment 1, the first example is as follows:

[0057] On the same chip substrate 1, the chip contains five optical elements, starting from the light emission direction: a first SOA2, a first reflector 3, an active region 4, a phase waveguide region 6, and a second reflector 5, arranged sequentially from front to back in the light emission direction. A first InP buffer layer 101 and an InP spacer layer 103 are sequentially grown on the chip substrate 1. The structures of the first SOA2, first reflector 3, active region 4, phase waveguide region 6, and second reflector 5 are the same as in Embodiment 1 and will not be described again here.

[0058] It should be noted that, in this embodiment, the first quantum well region 202 comprises a quantum well consisting of three alternating layers of first quantum well thin layers 2022 and four alternating layers of first quantum well barrier thin layers 2023; the first quantum well thin layers 2022 have a fluorescence wavelength of 1.58 μm and are subjected to 1% compressive strain with InP; the first quantum well barrier thin layers 2023 have a fluorescence wavelength of 1.25 μm and are subjected to strain matching with InP. The second quantum well region 402 comprises a quantum well consisting of ten alternating layers of second quantum well thin layers 4022 and eleven alternating layers of second quantum well barrier thin layers 4023; the second quantum well thin layers 4022 have a fluorescence wavelength of 1.58 μm and are subjected to 1% compressive strain with InP; the second quantum well barrier thin layers 4023 have a fluorescence wavelength of 1.25 μm and are subjected to strain matching with InP.

[0059] In this embodiment, the first lower waveguide layer 2021, the first upper waveguide layer 2024, the second lower waveguide layer 4021, and the second upper waveguide layer 4024 all have the same InGaAsP material composition and the same thickness, specifically: an alloy material with a fluorescence wavelength of 1.2 micrometers, strain matching InP, and a thickness of 0.1 micrometers.

[0060] Based on the above settings, because the first SOA2 has fewer quantum wells and a lower optical field confinement factor, it has a very high saturated output optical power. The active region 4 has more quantum wells and a higher optical field confinement factor, approximately ten times that of the first SOA2. Under the same current, the carrier density within the quantum wells is about 1 / 10 that of the first SOA2, resulting in higher differential gain, a lower linewidth enhancement factor, and a narrower laser linewidth.

[0061] Example 3

[0062] Referring to Figure 11, based on the solution provided in Embodiment 1, a second example is as follows:

[0063] On the same chip substrate 1, the chip contains five optical elements, starting from the light emission direction: a first SOA2, a first reflector 3, an active region 4, a phase waveguide region 6, and a second reflector 5, arranged sequentially from front to back in the light emission direction. A first InP buffer layer 101 and an InP spacer layer 103 are sequentially grown on the chip substrate 1. The structures of the first SOA2, first reflector 3, active region 4, phase waveguide region 6, and second reflector 5 are the same as in Embodiment 1 and will not be described again here.

[0064] Unlike Example 2, in this example, the first quantum well region 202 comprises a quantum well consisting of 10 alternating layers of first quantum well thin layers 2022 and 11 alternating layers of first quantum well barrier thin layers 2023. The first quantum well thin layers 2022 have a fluorescence wavelength of 1.58 μm and are subjected to 1% compressive strain with InP. The first quantum well barrier thin layers 2023 have a fluorescence wavelength of 1.25 μm and are subjected to strain matching with InP. The second quantum well region 402 comprises a quantum well consisting of 10 alternating layers of second quantum well thin layers 4022 and 11 alternating layers of second quantum well barrier thin layers 4023. The second quantum well thin layers 4022 have a fluorescence wavelength of 1.58 μm and are subjected to 1% compressive strain with InP. The second quantum well barrier thin layers 4023 have a fluorescence wavelength of 1.25 μm and are subjected to strain matching with InP.

[0065] In this embodiment, the first lower waveguide layer 2021, the first upper waveguide layer 2024, the second lower waveguide layer 4021, and the second upper waveguide layer 4024 all have the same InGaAsP material composition, specifically: an alloy material with a fluorescence wavelength of 1.2 micrometers and strain matching InP; however, the material thicknesses are different, wherein the thickness of the first lower waveguide layer 2021 and the first upper waveguide layer 2024 is 0.05 micrometers; and the thickness of the second lower waveguide layer 4021 and the second upper waveguide layer 4024 is 0.1 micrometers.

[0066] Based on the above configuration, the number and structure of quantum wells in the first SOA2 are the same as those in the active region 4. However, because the first lower waveguide layer 2021 and the first upper waveguide layer 2024 of the first SOA2 are thinner, the waveguide's confinement effect on the optical field is weaker, resulting in a lower optical field confinement factor compared to the active region 4. Under the same mode gain, the active region 4 has a lower current, a higher differential gain, a lower linewidth enhancement factor, and a narrower laser linewidth. In contrast, in the first SOA2, under the same mode gain, the mode field confinement factor is lower, it is less affected by saturation gain, and the saturation optical power is greater.

[0067] Example 4

[0068] Referring to Figure 12, based on the solution provided in Embodiment 1, a third example is as follows:

[0069] On the same chip substrate 1, the chip contains five optical elements, starting from the light emission direction: a first SOA2, a first reflector 3, an active region 4, a phase waveguide region 6, and a second reflector 5, arranged sequentially from front to back in the light emission direction. A first InP buffer layer 101 and an InP spacer layer 103 are sequentially grown on the chip substrate 1. The structures of the first SOA2, first reflector 3, active region 4, phase waveguide region 6, and second reflector 5 are the same as in Embodiment 1 and will not be described again here.

[0070] It should be noted that, in this embodiment, the first quantum well region 202 comprises a quantum well consisting of three alternating layers of first quantum well thin layers 2022 and four alternating layers of first quantum well barrier thin layers 2023; the first quantum well thin layers 2022 have a fluorescence wavelength of 1.58 μm and are subjected to 1% compressive strain with InP; the first quantum well barrier thin layers 2023 have a fluorescence wavelength of 1.25 μm and are subjected to strain matching with InP. The second quantum well region 402 comprises a quantum well consisting of ten alternating layers of second quantum well thin layers 4022 and eleven alternating layers of second quantum well barrier thin layers 4023; the second quantum well thin layers 4022 have a fluorescence wavelength of 1.58 μm and are subjected to 1% compressive strain with InP; the second quantum well barrier thin layers 4023 have a fluorescence wavelength of 1.25 μm and are subjected to strain matching with InP.

[0071] In this embodiment, the first lower waveguide layer 2021, the first upper waveguide layer 2024, the second lower waveguide layer 4021, and the second upper waveguide layer 4024 all have the same InGaAsP material composition, specifically: an alloy material with a fluorescence wavelength of 1.2 micrometers and strain matching InP; however, the material thicknesses are different, wherein the thickness of the first lower waveguide layer 2021 and the first upper waveguide layer 2024 is 0.05 micrometers; and the thickness of the second lower waveguide layer 4021 and the second upper waveguide layer 4024 is 0.1 micrometers.

[0072] Based on the above configuration, because the first SOA2 has fewer quantum wells and a thinner waveguide layer, its optical field confinement factor is lower, resulting in a very high saturated output optical power. The active region 4 has more quantum wells and a thicker waveguide layer, resulting in a higher optical field confinement factor, approximately ten times that of the first SOA2. Under the same current, the carrier density within the quantum wells is about 1 / 10 to 1 / 20 that of the first SOA2, leading to higher differential gain, a lower linewidth enhancement factor, and a narrower laser linewidth.

[0073] Example 5

[0074] Referring to Figure 13, based on the solution provided in Embodiment 1, the fourth example is as follows:

[0075] On the same chip substrate 1, the chip contains five optical elements, starting from the light-emitting direction: a first SOA2, a first reflector 3, an active region 4, a phase waveguide region 6, and a second reflector 5, arranged sequentially from front to back in the light-emitting direction. A first InP buffer layer 101, a sparse waveguide layer 102, and an InP spacer layer 103 are sequentially grown on the chip substrate 1. The structures of the first SOA2, first reflector 3, active region 4, phase waveguide region 6, and second reflector 5 are the same as in Embodiment 1 and will not be described again here.

[0076] It should be noted that, in this embodiment, the first quantum well region 202 comprises a quantum well consisting of three alternating layers of first quantum well thin layers 2022 and four alternating layers of first quantum well barrier thin layers 2023; the first quantum well thin layers 2022 have a fluorescence wavelength of 1.58 μm and are subjected to 1% compressive strain with InP; the first quantum well barrier thin layers 2023 have a fluorescence wavelength of 1.25 μm and are subjected to strain matching with InP. The second quantum well region 402 comprises a quantum well consisting of ten alternating layers of second quantum well thin layers 4022 and eleven alternating layers of second quantum well barrier thin layers 4023; the second quantum well thin layers 4022 have a fluorescence wavelength of 1.58 μm and are subjected to 1% compressive strain with InP; the second quantum well barrier thin layers 4023 have a fluorescence wavelength of 1.25 μm and are subjected to strain matching with InP.

[0077] In this embodiment, the first lower waveguide layer 2021, the first upper waveguide layer 2024, the second lower waveguide layer 4021, and the second upper waveguide layer 4024 all have the same InGaAsP material composition, specifically: an alloy material with a fluorescence wavelength of 1.2 micrometers and strain matching InP; however, the material thicknesses are different, wherein the thickness of the first lower waveguide layer 2021 and the first upper waveguide layer 2024 is 0.05 micrometers; and the thickness of the second lower waveguide layer 4021 and the second upper waveguide layer 4024 is 0.1 micrometers.

[0078] Based on the above configuration, because the first SOA2 has fewer quantum wells and a thinner waveguide layer, its optical field confinement factor is lower. Furthermore, the presence of a sparse waveguide layer 102 on the substrate exerts a downward pull on the optical field, further reducing the optical field confinement factor. Therefore, the first SOA2 exhibits very high saturated output optical power. The active region 4 has more quantum wells and a thicker waveguide layer, resulting in a higher optical field confinement factor. The effect of the sparse waveguide layer is less significant, and most of the mode field remains within the quantum well region. Its optical field confinement factor is approximately tens of times that of the first SOA2. Under the same current, the carrier density within the quantum well is about 1 / 20 to 1 / 30 that of the first SOA2, resulting in higher differential gain, a lower linewidth enhancement factor, and a narrower laser linewidth.

[0079] Example 6

[0080] Referring to Figure 14, based on the solution provided in Embodiment 1, the fifth example is as follows:

[0081] On the same chip substrate 1, the chip contains six optical elements, starting from the light emission direction: a first SOA2, a second SOA7, a first reflector 3, an active region 4, a phase waveguide region 6, and a second reflector 5, arranged sequentially from front to back. For the first SOA2, the optical signal is amplified by the second SOA7, enters from the right side of the first SOA2, and exits from the left side. A first InP buffer layer 101, a sparse waveguide layer 102, and an InP spacer layer 103 are sequentially grown on the chip substrate 1. The structures of the first SOA2, second SOA7, first reflector 3, active region 4, phase waveguide region 6, and second reflector 5 are the same as in Embodiment 1 and will not be described again here.

[0082] It should be noted that, in this embodiment, the first quantum well region 202 comprises a quantum well consisting of three alternating layers of first quantum well thin layers 2022 and four alternating layers of first quantum well barrier thin layers 2023; the first quantum well thin layers 2022 have a fluorescence wavelength of 1.58 μm and are subjected to 1% compressive strain with InP; the first quantum well barrier thin layers 2023 have a fluorescence wavelength of 1.25 μm and are subjected to strain matching with InP. The second quantum well region 402 comprises a quantum well consisting of ten alternating layers of second quantum well thin layers 4022 and eleven alternating layers of second quantum well barrier thin layers 4023; the second quantum well thin layers 4022 have a fluorescence wavelength of 1.58 μm and are subjected to 1% compressive strain with InP; the second quantum well barrier thin layers 4023 have a fluorescence wavelength of 1.25 μm and are subjected to strain matching with InP. The third quantum well region 702 comprises a quantum well consisting of 10 alternating layers of third quantum well thin layers 7022 and 11 layers of third quantum well barrier thin layers 7023; the third quantum well thin layer 7022 is a thin layer with a fluorescence wavelength of 1.58 micrometers and a compressive strain of 1% with InP; the third quantum well barrier thin layer 7023 is a thin layer with a fluorescence wavelength of 1.25 micrometers and a strain-matched thin layer with InP.

[0083] In this embodiment, the first lower waveguide layer 2021, the first upper waveguide layer 2024, the second lower waveguide layer 4021, the second upper waveguide layer 4024, the third lower waveguide layer 7021, and the ninth upper waveguide layer 7024 all have the same InGaAsP material composition, specifically: an alloy material with a fluorescence wavelength of 1.2 micrometers and strain matching InP; however, the material thicknesses are different, wherein the thickness of the first lower waveguide layer 2021 and the first upper waveguide layer 2024 is 0.05 micrometers; and the thickness of the second lower waveguide layer 4021, the second upper waveguide layer 4024, the third lower waveguide layer 7021, and the ninth upper waveguide layer 7024 is 0.1 micrometers.

[0084] Based on the above configuration, because the first SOA2 has fewer quantum wells and a thinner waveguide layer, its optical field confinement factor is lower. Furthermore, the presence of a sparse waveguide layer 102 on the substrate exerts a downward pull on the optical field, further reducing the optical field confinement factor. Therefore, the first SOA2 exhibits very high saturated output optical power. The active region 4 has more quantum wells and a thicker waveguide layer, resulting in a higher optical field confinement factor. The effect of the sparse waveguide layer is less significant, and most of the mode field remains within the quantum well region. Its optical field confinement factor is approximately tens of times that of the first SOA2. Under the same current, the carrier density within the quantum well is about 1 / 20 to 1 / 30 that of the first SOA2, resulting in higher differential gain, a lower linewidth enhancement factor, and a narrower laser linewidth.

[0085] Furthermore, the purpose of placing the second SOA7 between the first SOA2 and the first reflector 3 is to improve the efficiency of optical signal amplification. Because the second SOA7 has a higher mode field confinement factor, it amplifies the optical signal more efficiently, allowing it to be amplified to its saturated output power with a lower current. The optical signal then enters the first SOA2. Although the first SOA2 has a lower amplification efficiency, its lower mode field confinement factor allows it to continue amplifying the optical signal, continuously increasing the output optical power and improving the utilization efficiency of the total injected current.

[0086] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of this application as described above. For the sake of brevity, they are not provided in detail; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A tunable laser chip with high saturation power and narrow linewidth, characterized in that, The device includes a chip substrate (1) and a first SOA (2), a first reflector (3), an active region (4), and a second reflector (5) arranged sequentially from front to back on the chip substrate (1) starting from the light emission direction; wherein the total optical thickness of the first quantum well region (202) of the first SOA (2) is less than the total optical thickness of the second quantum well region (402) of the active region (4), and / or the number of quantum wells in the first quantum well region (202) of the first SOA (2) is less than the number of quantum wells in the second quantum well region (402) of the active region (4).

2. The high-saturation-power, narrow-linewidth tunable laser chip according to claim 1, characterized in that, The first quantum well region (202) includes a first lower waveguide layer (2021) arranged from bottom to top, a quantum well composed of several alternately stacked first quantum well thin layers (2022) and first quantum well barrier thin layers (2023), and a first upper waveguide layer (2024); the second quantum well region (402) includes a second lower waveguide layer (4021) arranged from bottom to top, a quantum well composed of several alternately stacked second quantum well thin layers (4022) and second quantum well barrier thin layers (4023), and a second upper waveguide layer (4024).

3. The high-saturation-power, narrow-linewidth tunable laser chip according to claim 2, characterized in that, The first quantum well region (202) includes 1 to 5 pairs of quantum wells, and the second quantum well region (402) includes 6 to 20 pairs of quantum wells.

4. The high-saturation-power, narrow-linewidth tunable laser chip according to claim 1, characterized in that, The chip substrate (1) includes a first InP buffer layer (101) and an InP spacer layer (103) arranged sequentially from bottom to top; the first SOA (2) includes a second InP buffer layer (201), a first quantum well region (202) and a third upper waveguide layer (203) arranged sequentially from bottom to top starting from the chip substrate (1); the first reflector (3) includes a third InP buffer layer (301), a first optical waveguide region (302) and a fourth upper waveguide layer (303) arranged sequentially from bottom to top starting from the chip substrate (1); the active region (4) includes a fourth InP buffer layer (401), a second quantum well region (402) and a fifth upper waveguide layer (403) arranged sequentially from bottom to top starting from the chip substrate (1); the second reflector (5) includes a fifth InP buffer layer (501), a second optical waveguide region (502) and a sixth upper waveguide layer (503) arranged sequentially from bottom to top starting from the chip substrate (1).

5. The high-saturation-power, narrow-linewidth tunable laser chip according to claim 4, characterized in that, The chip substrate (1) further includes a sparse waveguide layer (102), which is disposed between the first InP buffer layer (101) and the InP spacer layer (103).

6. The high-saturation-power, narrow-linewidth tunable laser chip according to claim 1, characterized in that, It also includes a phase waveguide region (6) disposed on the chip substrate (1), the phase waveguide region (6) being disposed between the active region (4) and the second reflector (5).

7. The high-saturation-power, narrow-linewidth tunable laser chip according to claim 6, characterized in that, The phase waveguide region (6) includes, from bottom to top, a sixth InP buffer layer (601), a third optical waveguide region (602), and a seventh upper waveguide layer (603), arranged sequentially from bottom to top, starting from the chip substrate (1).

8. The high-saturation-power, narrow-linewidth tunable laser chip according to claim 1, characterized in that, It also includes a second SOA (7) disposed on the chip substrate (1), the second SOA (7) being disposed between the first SOA (2) and the first reflector (3).

9. The high-saturation-power, narrow-linewidth tunable laser chip according to claim 8, characterized in that, The second SOA (7) includes, from bottom to top, a seventh InP buffer layer (701), a third quantum well region (702), and an eighth upper waveguide layer (703); the third quantum well region (702) includes, from bottom to top, a third lower waveguide layer (7021), a quantum well composed of several alternately stacked third quantum well thin layers (7022) and third quantum well barrier thin layers (7023), and a ninth upper waveguide layer (7024); the number of quantum wells in the third quantum well region (702) is greater than the number of quantum wells in the first quantum well region (202).

10. The high-saturation-power, narrow-linewidth tunable laser chip according to claim 1, characterized in that, The first reflector (3) is a waveguide reflector or a sampling grating waveguide reflector.

11. The high-saturation-power, narrow-linewidth tunable laser chip according to claim 1, characterized in that, The second reflector (5) is a waveguide reflector or a sampling grating waveguide reflector.

12. The high-saturation-power, narrow-linewidth tunable laser chip according to claim 1, characterized in that, The total optical thickness of a quantum well region is the sum of the products of the physical thickness of each layer and the refractive index of each layer.

13. A method for fabricating a high-saturation-power, narrow-linewidth tunable laser chip, applicable to the high-saturation-power, narrow-linewidth tunable laser chip as described in any one of claims 1-12, characterized in that, include: On a chip substrate (1), a first SOA (2), a first reflector (3), an active region (4), and a second reflector (5) are fabricated sequentially from front to back, starting from the light-emitting direction; wherein the total optical thickness of the first quantum well region (202) of the fabricated first SOA (2) is less than the total optical thickness of the second quantum well region (402) of the fabricated active region (4), and / or the number of quantum wells in the first quantum well region (202) of the fabricated first SOA (2) is less than the number of quantum wells in the second quantum well region (402) of the fabricated active region (4).

Images