Semiconductor chip and manufacturing method therefor

Abstract

A semiconductor chip and a manufacturing method. The semiconductor chip comprises a chip substrate (1) and an electro-absorption modulator EAM (2) arranged on the chip substrate (1); the EAM (2) comprises a first substrate (201), a support column (202), a first active region (203), and a first upper waveguide region (204) which are sequentially arranged from bottom to top; the width of the support column (202) and the width of the first upper waveguide region (204) are both less than the width of the first active region (203). By reducing the area of a reverse PN junction, the degradation of the electrical performance and the optical performance of the semiconductor chip caused by sidewalls can be effectively suppressed, the bandwidth of the chip is increased, dark current and defects at an interface are reduced, and light output loss of the chip is reduced, thereby improving the light output power of the chip.

Description

A semiconductor chip and its fabrication method

[0001] Cross-reference of related applications

[0002] This application claims priority to the following patent application:

[0003] (1) A Chinese patent application filed with the Chinese Patent Office on January 14, 2025, with application number 202510052779.X and title "Semiconductor chip and method of manufacturing thereof". Technical Field

[0004] This application relates to the field of semiconductor technology, and in particular to a semiconductor chip and a method for manufacturing the same. Background Technology

[0005] With the rapid development of the Internet, the demand for network bandwidth is increasing, and the requirements for chip modulation rates are also rising. In traditional low-speed Passive Optical Networks (PONs), Distributed Feedback Laser (DFB) chips are generally used as the light source. However, as the modulation rate increases, DFB lasers are affected by chirp, significantly reducing the transmission distance. Therefore, in high-speed PON networks and data centers, External Modulated Laser (EML) chips, which separate the light source and modulation, have become the main light source chips. In this type of laser, the DFB laser is used only as a light source, with a fixed current bias to provide constant optical power; then, the intensity of the light is modulated by an integrated Electro Absorption Modulator (EAM). An EAM is a reverse device that operates using the quantum Stark effect or the FK effect. When different reverse voltages are applied to the electroabsorption modulator, the position of its absorption peak changes with the voltage, and the absorptivity of the laser emitted by the DFB laser also changes accordingly. Therefore, the intensity of the emitted light from the DFB laser can be modulated. The modulation rate is generally mainly controlled by the device capacitance, with the junction capacitance of the reverse PN junction accounting for a large proportion of the total capacitance.

[0006] The capacitance of a reverse PN junction can be effectively reduced by increasing its junction thickness and decreasing its area. One traditional method for reducing the area of ​​a reverse PN junction is through deep etching of the ridge waveguide. In this method, the width of the reverse PN junction is limited by the etched interfaces on both sides. Simultaneously, both optical and electric fields act on the junction, significantly reducing its area and improving electric field utilization efficiency. However, because this method exposes active regions such as the quantum well of the PN junction through etching, numerous dangling bonds are generated on this rough interface, leading to higher recombination defects and dark current. Furthermore, this rough interface enhances light scattering from the sidewalls, degrading the waveguide's loss characteristics and reducing the chip's output power.

[0007] Therefore, how to overcome the shortcomings of the existing technology and how to solve the above-mentioned technical problems is a difficult problem that urgently needs to be solved in this technical field.

[0008] Application content

[0009] To address the aforementioned technical problems or needs—namely, how to improve chip modulation bandwidth, reduce interface dark current and defects, reduce chip output loss, and increase chip output power while effectively reducing the junction area of ​​the reverse PN junction in the electro-absorption modulator (EAM)—this application provides a semiconductor chip and its fabrication method. The method ensures that the width of the support pillars and upper waveguide region in the EAM is smaller than the width of the active region. This limits the junction area width of the reverse PN junction in the active region to the upper waveguide region and support pillars, preventing it from widening. Simultaneously, because the width of the active region is much larger than the width of the reverse PN junction limited by the upper waveguide region and support pillars, exposed sidewall interface dangling bonds and defects in the active region are difficult to effectively enter the reverse PN junction, significantly reducing dark current. Furthermore, the transverse optical field of the waveguide is limited by the upper waveguide region and support pillars, and the mode edge is far from the sidewalls. Therefore, interface roughness has little impact on optical field transmission, reducing waveguide transmission loss. This scheme can effectively suppress the degradation of electrical and optical performance by the sidewalls while reducing the area of ​​the reverse PN junction, thereby increasing the chip's bandwidth, reducing interface dark current and defects, reducing chip light emission loss, and increasing chip light emission power.

[0010] This application is implemented as follows:

[0011] In a first aspect, this application provides a semiconductor chip, including a chip substrate 1 and an electroabsorption modulator (EAM) 2 disposed on the chip substrate 1; the electroabsorption modulator (EAM) 2 includes a first substrate 201, a support pillar 202, a first active region 203 and a first upper waveguide region 204 disposed sequentially from bottom to top; the width of the support pillar 202 and the width of the first upper waveguide region 204 are both smaller than the width of the first active region 203.

[0012] In some embodiments, the width of the support post 202 is smaller than the width of the first upper waveguide region 204.

[0013] In some embodiments, the width of the support post 202 is between 1-3 μm, the width of the first upper waveguide region 204 is between 1.2-3.5 μm, and the width of the first active region 203 is between 4-10 μm.

[0014] In some embodiments, the first substrate 201 includes an InP buffer layer 2011 and an InGaAsP etch-resistant layer 2012 disposed sequentially from bottom to top.

[0015] In some embodiments, the support column 202 includes an InP lower support column layer 2021, a sacrificial layer 2022, and an InP upper support column layer 2023 arranged sequentially from bottom to top, wherein the material of the sacrificial layer 2022 includes InGaAsP.

[0016] In some embodiments, the first active region 203 includes a first lower confinement layer 2031, a first quantum well region 2032, and a first upper confinement layer 2033 arranged sequentially from bottom to top; wherein the material of the first lower confinement layer 2031 includes InGaAsP, the first quantum well region 2032 includes a quantum well region formed by alternating layers of InGaAsP barrier material and InGaAsP well material, and the material of the first upper confinement layer 2033 includes InGaAsP.

[0017] In some embodiments, the first active region 203 is an unintentionally doped region, the first substrate 201 and the support pillar 202 are N-type doped regions, and the first upper waveguide region 204 is a P-type doped region.

[0018] In some embodiments, a semiconductor laser DFB 3 disposed on the chip substrate 1 is also included. The electroabsorption modulator EAM 2 and the semiconductor laser DFB 3 are arranged sequentially from front to back starting from the light emission direction. The semiconductor laser DFB 3 includes a second substrate 301, a second active region 302 and a second upper waveguide region 303 disposed sequentially from bottom to top.

[0019] In some embodiments, the second active region 302 includes a second lower confinement layer 3031, a second quantum well region 3032, and a second upper confinement layer 3033 arranged sequentially from bottom to top; wherein the material of the second lower confinement layer 3031 includes InGaAsP, the second quantum well region 3032 includes a quantum well region formed by alternating layers of InGaAsP barrier material and InGaAsP well material, and the material of the second upper confinement layer 3033 includes InGaAsP.

[0020] In some embodiments, the second active region 302 is an unintentionally doped region, the second substrate 301 is an N-type doped region, and the second upper waveguide region 303 is a P-type doped region.

[0021] In some embodiments, the chip substrate 1 includes a first InP layer 101, a first InGaAsP layer 102, a second InP layer 103, a second InGaAsP layer 104, and a third InP layer 105, which are disposed sequentially from bottom to top.

[0022] Secondly, this application provides a method for manufacturing a semiconductor chip, applied to the semiconductor chip described in the first aspect, the method comprising:

[0023] Holes are formed on both sides of the first upper waveguide region 204 using photolithography and etching methods to form a first etched hole 205 and a second etched hole 206. The first etched hole 205 and the second etched hole 206 penetrate the third InP layer 105 and remain on the second InGaAsP layer 104. The distance between the first etched hole 205 and the second etched hole 206 is W2, so that the width of the first active region 203 is W2 and the width of the first upper waveguide region 204 is W3, where W2 is greater than W3.

[0024] The chip surface is masked with photoresist, and a first etching hole 2051 is photolithographically formed in the first etching hole 205, and a second etching hole 2061 is photolithographically formed in the second etching hole 206.

[0025] The second InGaAsP layer 104 is laterally etched using a first selective etchant to form a sacrificial layer 2022 with a width of W1; wherein the first selective etchant is only corrosive to InGaAsP.

[0026] The third InP layer 105 and the second InP layer 103 are etched using a second selective etchant to form an upper InP support pillar layer 2023 and a lower InP support pillar layer 2021 with a width of W1. The upper InP support pillar layer 2023, the sacrificial layer 2022, and the lower InP support pillar layer 2021 are combined to form a support pillar 202 with a width of W1, where W2 is greater than W1. The second selective etchant is only corrosive to InP.

[0027] Compared with existing technologies, the beneficial effects of this application are as follows: It provides a semiconductor chip and its fabrication method, in which the width of the support pillars and upper waveguide region in the electro-absorption modulator (EAM) is smaller than the width of the active region. This limits the junction area width of the active region's reverse PN junction to the upper waveguide region and support pillars, preventing it from widening. Simultaneously, because the width of the active region is much larger than the width of the reverse PN junction limited by the upper waveguide region and support pillars, exposed sidewall interface dangling bonds and defects in the active region are difficult to effectively enter the reverse PN junction, significantly reducing dark current. Furthermore, the transverse optical field of the waveguide is limited by the upper waveguide region and support pillars, and the mode edge is far from the sidewalls. Therefore, interface roughness has little impact on optical field transmission, reducing waveguide transmission loss. Through this scheme, while reducing the reverse PN junction area, it is possible to effectively suppress the degradation of electrical and optical performance by the sidewalls, improve chip bandwidth, reduce interface dark current and defects, reduce chip output loss, and increase chip output power. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 is a cross-sectional schematic diagram of a semiconductor chip provided in an embodiment of this application;

[0030] Figure 2 is a cross-sectional schematic diagram of the electroabsorption modulator EAM provided in an embodiment of this application;

[0031] Figure 3 is a schematic cross-sectional view of the first active region provided in an embodiment of this application;

[0032] Figure 4 is a cross-sectional schematic diagram of the semiconductor laser DFB provided in the embodiment of this application;

[0033] Figure 5 is a schematic cross-sectional view of the second active region provided in an embodiment of this application;

[0034] Figure 6 is a flowchart of a semiconductor chip fabrication method provided in an embodiment of this application;

[0035] Figure 7 is a cross-sectional schematic diagram of the electroabsorption modulator (EAM) provided in the embodiment of this application before fabrication;

[0036] Figure 8 is a cross-sectional schematic diagram of the first upper waveguide region after opening holes on both sides according to an embodiment of this application;

[0037] Figure 9 is a schematic cross-sectional view of the photoresist masking provided in the embodiment of this application;

[0038] Figure 10 is a cross-sectional schematic diagram of the first selective etchant after corrosion according to an embodiment of this application;

[0039] Figure 11 is a cross-sectional schematic diagram of the second selective etchant after corrosion according to an embodiment of this application;

[0040] Figure 12 is a cross-sectional schematic diagram of the photoresist after removal provided in an embodiment of this application. Detailed Implementation

[0041] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as openly inclusive, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples; that is, although they may be incorporated into embodiments or examples using the above terms for reasons such as order and position, it does not limit them to be incorporated in combination by a single embodiment or example.

[0042] In the description of this application, the terms "inner", "outer", "longitudinal", "lateral", "upper", "lower", "left", "right", "top", "bottom", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and do not require this application to be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0043] The present application will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present application, but do not limit the present application in any way. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present application. These all fall within the protection scope of the present application.

[0044] It should be noted that, unless otherwise defined, the various features in the embodiments of this application can be combined with each other, all of which are within the protection scope of this application. Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. The terminology and location descriptions used in this specification are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0045] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0046] Example 1

[0047] Referring to Figures 1 and 2, Embodiment 1 of this application provides a semiconductor chip, including a chip substrate 1 and an electroabsorption modulator (EAM) 2 disposed on the chip substrate 1; the electroabsorption modulator (EAM) 2 includes a first substrate 201, a support pillar 202, a first active region 203 and a first upper waveguide region 204 disposed sequentially from bottom to top; the width of the support pillar 202 and the width of the first upper waveguide region 204 are both smaller than the width of the first active region 203.

[0048] Through the above scheme, the junction area width of the reverse PN junction in the first active region 203 of the electro-absorption modulator EAM 2 is limited by its first upper waveguide region 204 and support pillar 202, and cannot be widened. Simultaneously, since the width of the first active region 203 is much larger than the width of the reverse PN junction limited by the first upper waveguide region 204 and support pillar 202, dangling bonds and defects exposed on the sidewall interface of the first active region 203 are difficult to effectively enter the reverse PN junction, greatly reducing dark current. At the same time, the transverse optical field of the waveguide is limited by the first upper waveguide region 204 and support pillar 202, and the mode edge is far from the sidewall; therefore, interface roughness has little impact on optical field transmission, reducing waveguide transmission loss. This scheme can effectively suppress the degradation of electrical and optical performance by the sidewalls while reducing the reverse PN junction area, improve chip bandwidth, reduce interface dark current and defects, reduce chip output loss, and increase chip output power.

[0049] Furthermore, in some embodiments, the width of the support post 202 is smaller than the width of the first upper waveguide region 204. For example, the width of the support post 202 is between 1-3 μm, the width of the first upper waveguide region 204 is between 1.2-3.5 μm, and the width of the first active region 203 is between 4-10 μm. Specifically, the entire EAM injection region satisfies the condition that the width of the support post 202 and the width of the first upper waveguide region 204 are both smaller than the width of the first active region 203, and the width of the support post 202 is smaller than the width of the first upper waveguide region 204. The primary purpose of setting the width W1 of the support post 202 to be smaller than the width W3 of the first upper waveguide region 204 is to reduce capacitance and improve bandwidth. Conventional deep ridges have a width W1 of the support post 202 greater than or equal to the width W3 of the first upper waveguide region 204, which achieves limited bandwidth and suffers from interface dark current effects and reliability risks. This embodiment makes W1 smaller than W3 to solve this problem. Furthermore, after extensive experimentation, to achieve the best possible results, this embodiment also defined certain design ranges for each width. Specifically, the width W3 of the first upper waveguide region 204 is between 1.2 and 3.5 μm, and the corresponding width W1 of the support column 202 is between 1.0 and 3.0 μm. The purpose of this width range is twofold: to reduce capacitance and to provide sufficient support. Further, the width W2 of the first active region 203 is between 4.0 and 10.0 μm, aiming to eliminate sidewall dark current and optimize the electric field distribution without affecting beam transmission. The above parameter ranges represent the most reasonable ranges obtained after extensive experimentation, achieving the best balance between providing sufficient support, reducing capacitance, eliminating sidewall dark current, not affecting beam transmission, and optimizing the electric field distribution.

[0050] Referring to Figure 1, in some embodiments, a semiconductor laser DFB 3 disposed on the chip substrate 1 is also included, and the electroabsorption modulator EAM 2 and the semiconductor laser DFB 3 are arranged sequentially from front to back, starting from the light emission direction.

[0051] In some embodiments, the chip substrate 1 includes a first InP layer 101, a first InGaAsP layer 102, a second InP layer 103, a second InGaAsP layer 104, and a third InP layer 105, disposed sequentially from bottom to top. This chip substrate 1 can simultaneously serve as the substrate for both the electroabsorption modulator EAM 2 and the semiconductor laser DFB 3. In this embodiment, the electroabsorption modulator EAM 2 can be fabricated on this chip substrate 1; the specific fabrication method is described in Embodiment 2, and will not be repeated here.

[0052] Referring to Figure 2, in some embodiments, the electroabsorption modulator EAM 2 includes a first substrate 201, a support pillar 202, a first active region 203, and a first upper waveguide region 204 arranged sequentially from bottom to top; wherein, the first substrate 201 includes an InP buffer layer 2011 and an InGaAsP etch-resistant layer 2012 arranged sequentially from bottom to top; wherein, the InP buffer layer 2011 corresponds to the first InP layer 101, and the InGaAsP etch-resistant layer 2012 corresponds to the first InGaAsP layer 102. The support column 202 includes an InP lower support column layer 2021, a sacrificial layer 2022, and an InP upper support column layer 2023 arranged sequentially from bottom to top. The material of the sacrificial layer 2022 includes InGaAsP. The InP lower support column layer 2021 corresponds to the second InP layer 103 and is formed on the basis of the second InP layer 103. The sacrificial layer 2022 corresponds to the second InGaAsP layer 104 and is formed on the basis of the second InGaAsP layer 104. The InP upper support column layer 2023 corresponds to the third InP layer 105 and is formed on the basis of the third InP layer 105.

[0053] In some embodiments, the first active region 203 is an unintentionally doped region, the first substrate 201 and the support pillar 202 are N-type doped regions, and the first upper waveguide region 204 is a P-type doped region. Therefore, the support pillar 202, the first active region 203, and the first upper waveguide region 204 together constitute a PN junction region with a thickness approximately equal to the thickness of the first active region 203, as shown by the ellipse in Figure 2. The width of the first active region 203 is W2, the width of the support pillar 202 is W1, and the width of the first upper waveguide region 204 is W3. Both W1 and W3 are much smaller than W2, thereby effectively suppressing the degradation of electrical and optical performance by the sidewalls, increasing the chip's bandwidth, reducing interface dark current and defects, reducing chip light emission loss, and increasing chip light emission power.

[0054] Referring to Figure 3, in some embodiments, the first active region 203 includes a first lower confinement layer 2031, a first quantum well region 2032, and a first upper confinement layer 2033, arranged sequentially from bottom to top. The first lower confinement layer 2031 is made of InGaAsP, the first quantum well region 2032 is a quantum well region formed by alternating layers of InGaAsP barrier material and InGaAsP well material, and the first upper confinement layer 2033 is made of InGaAsP. Specifically, in one example, the first lower confinement layer 2031 has a thickness of 20 nm, a fluorescence wavelength of 1.2 μm, and a strain of 0; the first upper confinement layer 2033 has a thickness of 20 nm; the first quantum well region 2032 is formed by alternating layers of 11 layers of InGaAsP barrier material, 6 nm thick, with a fluorescence wavelength of 1.25 μm and a strain of 0.3% tensile strain, and 10 layers of InGaAsP well material, 8 nm thick, with a fluorescence wavelength of 1.54 μm and a strain of 1% compressive strain.

[0055] Referring to Figure 4, in some embodiments, the semiconductor laser DFB 3 includes a second substrate 301, a second active region 302, and a second upper waveguide region 303 arranged sequentially from bottom to top. The second substrate 301 shares the same substrate as the chip substrate 1; that is, the second substrate 301 also includes a first InP layer 101, a first InGaAsP layer 102, a second InP layer 103, a second InGaAsP layer 104, and a third InP layer 105 arranged sequentially from bottom to top. In some embodiments, the second active region 302 is an unintentionally doped region, the second substrate 301 is an N-type doped region, and the second upper waveguide region 303 is a P-type doped region.

[0056] Referring to Figure 5, in some embodiments, the second active region 302 includes a second lower confinement layer 3031, a second quantum well region 3032, and a second upper confinement layer 3033, arranged sequentially from bottom to top. The second lower confinement layer 3031 is made of InGaAsP, the second quantum well region 3032 is a quantum well region formed by alternating layers of InGaAsP barrier material and InGaAsP well material, and the second upper confinement layer 3033 is made of InGaAsP. Specifically, in one example, the second lower confinement layer 3031 has a thickness of 50 nm, a fluorescence wavelength of 1.2 μm, and a strain of 0; the second upper confinement layer 3033 has a thickness of 50 nm; the second quantum well region 3032 is formed by alternating layers of 7 layers of InGaAsP barrier material (8 nm thick, fluorescence wavelength 1.25 μm, tensile strain 0.3%) and 6 layers of InGaAsP well material (5.5 nm thick, fluorescence wavelength 1.58 μm, compressive strain 1%).

[0057] In summary, this application provides a semiconductor chip in which the width of the support pillars and upper waveguide region in the electro-absorption modulator (EAM) is smaller than the width of the active region. This limits the junction area width of the active region's reverse PN junction to the upper waveguide region and support pillars, preventing it from widening. Simultaneously, because the width of the active region is much larger than the width of the reverse PN junction limited by the upper waveguide region and support pillars, exposed sidewall interface dangling bonds and defects in the active region are less likely to effectively enter the reverse PN junction, significantly reducing dark current. Furthermore, the transverse optical field of the waveguide is limited by the upper waveguide region and support pillars, and the mode edge is far from the sidewalls. Therefore, interface roughness has little impact on optical field transmission, reducing waveguide transmission loss. This solution effectively suppresses the degradation of electrical and optical performance by sidewalls while reducing the reverse PN junction area, improving chip bandwidth, reducing interface dark current and defects, reducing chip output loss, and increasing chip output power.

[0058] Example 2

[0059] Referring to Figure 6, this embodiment provides a method for manufacturing a semiconductor chip, applied to the semiconductor chip described in Embodiment 1. The main purpose of this method is to fabricate the support pillar 202 of the electro-absorption modulator EAM 2 in Embodiment 1, so as to effectively suppress the degradation of electrical and optical performance by the sidewalls, improve the chip bandwidth, reduce interface dark current and defects, reduce chip light output loss, and improve chip light output power. The method mainly includes the following steps.

[0060] Step 100: Using photolithography and etching methods, holes are made on both sides of the first upper waveguide region 204 to form a first etched hole 205 and a second etched hole 206. The first etched hole 205 and the second etched hole 206 penetrate the third InP layer 105 and remain on the second InGaAsP layer 104. The distance between the first etched hole 205 and the second etched hole 206 is W2, so that the width of the first active region 203 is W2 and the width of the first upper waveguide region 204 is W3, where W2 is greater than W3.

[0061] Specifically, referring to Figure 7, before fabricating the electroabsorption modulator (EAM), the first upper waveguide region 204 and the first active region 203 are located above a shared chip substrate 1. The chip substrate 1 includes a first InP layer 101, a first InGaAsP layer 102, a second InP layer 103, a second InGaAsP layer 104, and a third InP layer 105, arranged sequentially from bottom to top. After opening holes on both sides of the first upper waveguide region 204, the first etched hole 205 and the second etched hole 206, as shown in Figure 8, are formed. At this time, the width of the first active region 203 is the distance W2 between the first etched hole 205 and the second etched hole 206.

[0062] Step 200: Mask the chip surface with photoresist 207, and photolithographically etch a first etched hole 2051 in the first etched hole 205, and photolithographically etch a second etched hole 2061 in the second etched hole 206. A schematic diagram after this step is completed is shown in Figure 9.

[0063] Step 300: Laterally etch the second InGaAsP layer 104 using a first selective etchant to form a sacrificial layer 2022 with a width of W1; wherein, the first selective etchant is only corrosive to InGaAsP. A schematic diagram after this step is completed is shown in Figure 10, at which point the sacrificial layer 2022 has a width of W1.

[0064] Step 400: The third InP layer 105 and the second InP layer 103 are etched using a second selective etching solution to form an upper InP support pillar layer 2023 and a lower InP support pillar layer 2021 with a width of W1. The upper InP support pillar layer 2023, the sacrificial layer 2022, and the lower InP support pillar layer 2021 combine to form a support pillar 202 with a width of W1, where W2 is greater than W1. The second selective etching solution is only corrosive to InP. A schematic diagram after this step is completed is shown in Figure 11. At this point, the support pillar 202 is complete, with a width of W1. Finally, the photoresist is removed to obtain the cross-section of the electroabsorption modulator EAM 2 as shown in Figure 12. At this time, the first InP layer 101 and the first InGaAsP layer 102 correspond to the InP buffer layer 2011 and the InGaAsP anti-etching layer 2012, respectively, forming the first substrate 201 of the electroabsorption modulator EAM 2. On the first substrate 201, there are support pillars 202, a first active region 203 and a first upper waveguide region 204 arranged sequentially from bottom to top. The width W1 of the support pillars 202 and the width W3 of the first upper waveguide region 204 are both smaller than the width W2 of the first active region 203.

[0065] In the above process, the width W1 of the support column 202 is determined by the etching time of the first selective etchant. By controlling the etching time of the first selective etchant, W1 can be made much smaller than W2. Using this manufacturing method, the cross-section of the electro-absorption modulator EAM 2 shown in Figure 2 can be formed.

[0066] In summary, this application provides a method for fabricating a semiconductor chip, where the width of the support pillars and upper waveguide region in the electro-absorption modulator (EAM) is smaller than the width of the active region. This limits the junction area width of the active region's reverse PN junction to the upper waveguide region and support pillars, preventing it from widening. Simultaneously, because the active region's width is much larger than the width of the reverse PN junction limited by the upper waveguide region and support pillars, exposed sidewall interface dangling bonds and defects in the active region are less likely to effectively enter the reverse PN junction, significantly reducing dark current. Furthermore, the transverse optical field of the waveguide is limited by the upper waveguide region and support pillars, and the mode edge is far from the sidewalls. Therefore, interface roughness has little impact on optical field transmission, reducing waveguide transmission loss. This solution effectively suppresses the degradation of electrical and optical performance by sidewalls while reducing the reverse PN junction area, improving chip bandwidth, reducing interface dark current and defects, lowering chip output loss, and increasing chip output power.

[0067] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of this application as described above. For the sake of brevity, they are not provided in detail; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A semiconductor chip, characterized in that, The device includes a chip substrate (1) and an electroabsorption modulator (EAM) (2) disposed on the chip substrate (1); the electroabsorption modulator (EAM) (2) includes a first substrate (201), a support pillar (202), a first active region (203) and a first upper waveguide region (204) disposed sequentially from bottom to top; the width of the support pillar (202) and the width of the first upper waveguide region (204) are both smaller than the width of the first active region (203).

2. The semiconductor chip according to claim 1, characterized in that, The width of the support column (202) is smaller than the width of the first upper waveguide region (204).

3. The semiconductor chip according to claim 2, characterized in that, The width of the support column (202) is between 1-3 μm, the width of the first upper waveguide region (204) is between 1.2-3.5 μm, and the width of the first active region (203) is between 4-10 μm.

4. The semiconductor chip according to claim 1, characterized in that, The first substrate (201) includes an InP buffer layer (2011) and an InGaAsP etch-resistant layer (2012) arranged sequentially from bottom to top; the support pillar (202) includes an InP lower support pillar layer (2021), a sacrificial layer (2022), and an InP upper support pillar layer (2023) arranged sequentially from bottom to top, wherein the material of the sacrificial layer (2022) includes InGaAsP; the first active region (203) includes a first lower confinement layer (2031), a first quantum well region (2032), and a first upper confinement layer (2033) arranged sequentially from bottom to top; wherein the material of the first lower confinement layer (2031) includes InGaAsP, the first quantum well region (2032) includes a quantum well region formed by alternating layers of InGaAsP barrier material and multiple layers of InGaAsP well material, and the material of the first upper confinement layer (2033) includes InGaAsP.

5. The semiconductor chip according to claim 4, characterized in that, The first active region (203) is an unintentionally doped region, the first substrate (201) and the support pillar (202) are N-type doped regions, and the first upper waveguide region (204) is a P-type doped region.

6. The semiconductor chip according to claim 1, characterized in that, It also includes a semiconductor laser DFB (3) disposed on the chip substrate (1), wherein the electroabsorption modulator EAM (2) and the semiconductor laser DFB (3) are arranged sequentially from front to back starting from the light emission direction; the semiconductor laser DFB (3) includes a second substrate (301), a second active region (302) and a second upper waveguide region (303) disposed sequentially from bottom to top.

7. The semiconductor chip according to claim 6, characterized in that, The second active region (302) includes a second lower confinement layer (3031), a second quantum well region (3032), and a second upper confinement layer (3033) arranged sequentially from bottom to top; wherein, the material of the second lower confinement layer (3031) includes InGaAsP, the second quantum well region (3032) includes a quantum well region formed by alternating layers of InGaAsP barrier material and InGaAsP well material, and the material of the second upper confinement layer (3033) includes InGaAsP.

8. The semiconductor chip according to claim 6, characterized in that, The second active region (302) is an unintentionally doped region, the second substrate (301) is an N-type doped region, and the second upper waveguide region (303) is a P-type doped region.

9. The semiconductor chip according to any one of claims 1-8, characterized in that, The chip substrate (1) includes a first InP layer (101), a first InGaAsP layer (102), a second InP layer (103), a second InGaAsP layer (104), and a third InP layer (105) arranged sequentially from bottom to top.

10. The semiconductor chip according to any one of claims 1-8, characterized in that, The width of the first active region (203) is greater than the width of the reverse PN junction, which is limited by the first upper waveguide region (204) and the support pillar (202).

11. The semiconductor chip according to any one of claims 1-8, characterized in that, The transverse optical field of the waveguide is limited by the first upper waveguide region (204) and the support column (202), and the edge of the mode spot is far away from the sidewall.

12. A method for manufacturing a semiconductor chip, applied to the semiconductor chip according to any one of claims 1-11, characterized in that, include: Using photolithography and etching methods, openings are made on both sides of the first upper waveguide region (204) to form a first etched hole (205) and a second etched hole (206). The first etched hole (205) and the second etched hole (206) penetrate the third InP layer (105) and remain on the second InGaAsP layer (104). The first etched hole (205) and the second etched hole (206) are spaced apart by W2, so that the width of the first active region (203) is W2 and the width of the first upper waveguide region (204) is W3, where W2 is greater than W3. The chip surface is masked with photoresist, and a first etched hole (2051) is photolithographically formed in the first etched hole (205), and a second etched hole (2061) is photolithographically formed in the second etched hole (206). The second InGaAsP layer (104) is laterally etched using a first selective etchant to form a sacrificial layer (2022) with a width of W1; wherein the first selective etchant is only corrosive to InGaAsP. The third InP layer (105) and the second InP layer (103) are etched using a second selective etchant to form an upper InP support pillar layer (2023) and a lower InP support pillar layer (2021) with a width of W1. The upper InP support pillar layer (2023), the sacrificial layer (2022), and the lower InP support pillar layer (2021) are combined to form a support pillar (202) with a width of W1, where W2 is greater than W1. The second selective etchant is only corrosive to InP.

13. The method for manufacturing a semiconductor chip according to claim 12, characterized in that, The first selective etching solution is only corrosive to InGaAsP.

14. The method for manufacturing a semiconductor chip according to claim 12, characterized in that, The second selective etchant is corrosive only to InP.

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