Method and apparatus for achieving compatibility of multiple PHY chips, and communication system

Abstract

The present invention relates to the technical field of communications. Provided are a method and apparatus for achieving compatibility of multiple PHY chips, and a communication system. The method comprises: connecting a configuration module between a MAC module and a PHY chip, and pre-storing configuration rules for various operating modes in the configuration module; the configuration module reading a connection state identifier of a first preset register location in the PHY chip at intervals of a preset period; and when the read connection state identifier indicates a disconnected state, according to a configuration rule for the next operating mode, switching the PHY chip to the next operating mode until the read connection state identifier indicates a connected state, and then stopping the switching, wherein during initialization, according to a configuration rule for a first operating mode, the PHY chip is configured to be in the first operating mode. In the present invention, a configuration module is provided, and the configuration module is enabled to periodically read a connection state identifier and perform operating mode switching on the basis of the connection state identifier, thereby solving the problem of compatibility between different PHY chips in the same switch system.

Description

A method, apparatus and communication system compatible with multiple PHY chips

[0001] Cross-reference of related applications

[0002] This application claims priority to the following patent application:

[0003] (1) A Chinese patent application filed on January 16, 2025, with application number 202510068433.9 and titled “A method, apparatus and communication system compatible with multiple PHY chips”. Technical Field

[0004] This invention relates to the field of communication technology, and in particular to a method, apparatus and communication system compatible with multiple PHY chips. Background Technology

[0005] In modern communication systems, Ethernet modules offer high-speed transmission capabilities. They support various transmission speeds, allowing for the selection of different modules to meet diverse needs. Especially in scenarios involving large-scale data transmission and processing, the high-speed transmission capabilities of Ethernet modules can satisfy the demands of rapid communication.

[0006] Currently, most small factor pluggable (SFP) modules from various manufacturers utilize highly integrated physical layer (PHY) chips as their development solution. Many functions are integrated within the PHY chip, requiring minimal intervention from designers or users. For example, the most common Marvell 88E1111 chip solution only requires designers to perform simple peripheral circuit design and provide an Inter-Integrated Circuit (I2C) interface, allowing the host to read some register information via the gold fingers. All register configuration information is embedded within the PHY chip. This approach has lower requirements for circuit design, reducing development difficulty. However, only a few registers within the PHY chip are accessible via the I2C interface. Therefore, the above design limits host access to the PHY chip and results in poor versatility.

[0007] Early switch systems extensively used Marvell's 88E1111 PHY chip for gigabit Ethernet modules. With advancements in chip technology, domestic manufacturers developed PHY chips such as the RTL8211FSI and YT8531SH-CA. While registers Reg_0 to Reg_15 are defined according to the 802.3 communication protocol, Reg_16 to Reg_31 can be defined by the chip manufacturer. This resulted in incompatibility between modules from different solutions within a given switch system. Introducing other solutions required maintaining the entire switch system's instruction set, leading to high costs and a significant workload.

[0008] Therefore, overcoming the shortcomings of the existing technology is an urgent problem to be solved in this technical field.

[0009] Application content

[0010] The technical problem to be solved by the present invention is to provide a method, apparatus and communication system compatible with multiple PHY chips, so as to solve the compatibility problem between different PHY chips in the same switch system.

[0011] The present invention adopts the following technical solution:

[0012] In a first aspect, the present invention provides a method for compatibility with multiple PHY chips, wherein a configuration module is connected between a MAC module and a PHY chip, and configuration rules for various operating modes are pre-stored in the configuration module; the method includes:

[0013] The configuration module reads the connection status identifier of the first preset register position in the PHY chip at preset intervals.

[0014] If the connection status identifier is read as not connected, the PHY chip is switched to the next working mode according to the configuration rules of the next working mode, until the connection status identifier is read as connected.

[0015] During initialization, the PHY chip is configured to the first working mode according to the configuration rules of the first working mode.

[0016] Preferably, the next operating mode is determined based on the current operating mode of the PHY chip, specifically including:

[0017] Read the mode identifier at the location of the second preset register in the PHY chip, and determine the current operating mode of the PHY chip based on the mode identifier;

[0018] After configuring the PHY chip to the next operating mode, the mode identifier corresponding to the next operating mode is stored in the second preset register position.

[0019] Preferably, the various working modes include SERDES mode and SGMII mode; the configuration rules corresponding to SERDES are as follows:

[0020] Write the value 0x0001 to register location 0x16 of the PHY chip, write the value 0x9088 to register location 0x1B of the PHY chip, write the value 0x9140 to register location 0x00 of the PHY chip, and write the value 0x0000 to register location 0x16 of the PHY chip.

[0021] Preferably, the configuration rules corresponding to the SGMII mode are as follows:

[0022] Write the value 0x9084h to the 0x1Bh register of the PHY chip, write the value 0x9140h to the 0x00h register of the PHY chip, write the value 0x0000h to the 0x16h register of the PHY chip, write the value 0x0F00h to the 0x09h register of the PHY chip, write the value 0x0DE1h to the 0x04h register of the PHY chip, and write the value 0x9140h to the 0x00h register of the PHY chip.

[0023] Preferably, the instructions that the MAC module needs to send to the PHY chip are forwarded via the configuration module, and the method further includes:

[0024] When the configuration module receives an instruction from the MAC module, it determines whether the current type of the PHY chip is a preset type. If the current type of the PHY chip is a preset type, the configuration module directly sends the instruction to the PHY chip. The MAC module sends the instruction according to the preset type.

[0025] Otherwise, the instruction is mapped to the current type instruction according to the preset instruction mapping rules, and the current type instruction is sent to the PHY chip.

[0026] Preferably, the step of mapping the instruction to a current type instruction according to a preset instruction mapping rule and sending the current type instruction to the PHY chip specifically includes:

[0027] The instruction is passed to the preset instruction sending interface host_write_to_phy_a(), and the preset instruction sending interface host_write_to_phy_a() is called to send the instruction;

[0028] In the preset instruction sending interface host_write_to_phy_a(), if it is determined that the current type of the PHY chip is different from the preset type, the corresponding type branch is entered, specifically including:

[0029] If it is determined that the current type of the PHY chip is the first type, then the first type branch is entered. In the first type branch, the Value_PhyA_To_PhyB() interface is used to map the instruction to the first type instruction, and the first type instruction is passed to the first type instruction sending interface host_write_to_phy_b(). The first type instruction sending interface host_write_to_phy_b() is called to send the first type instruction to the first type of PHY chip.

[0030] Preferably, when the preset type is Marvell chip type and the current type is RTL8211F chip type, mapping the instruction to the current type instruction according to the preset instruction mapping rule specifically includes:

[0031] Map the Marvell chip's MDIX setting instructions to the RTL8211F chip's MDIX reading instructions;

[0032] Map the SGMII and GBIC mode switching instructions of the Marvell chip to the SGMII and SERDES mode switching instructions of the RTL8211F chip.

[0033] In a second aspect, the present invention provides a device compatible with multiple PHY chips, including a MAC module, a PHY chip, a network transformer, a connector, and a configuration module;

[0034] The configuration module is connected between the MAC module and the PHY chip, and the configuration module is used to execute the method for compatibility with multiple PHY chips as described in the first aspect.

[0035] The PHY chip is one or more of MARVELL, RTL8211FSI, and YT8531SH-CA chips.

[0036] Thirdly, the present invention provides a communication system compatible with multiple PHY chips, including a local end and a remote end, wherein the apparatus for compatibility with multiple PHY chips described in the second aspect is used in the local end and / or the remote end.

[0037] Fourthly, the present invention also provides an apparatus compatible with multiple PHY chips, used to implement the method for compatible with multiple PHY chips described in the first aspect. In practical use, the apparatus is the configuration module, and the apparatus includes:

[0038] At least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor for performing the method for compatible multi-PHY chips as described in the first aspect.

[0039] Fifthly, the present invention also provides a non-volatile computer storage medium storing computer-executable instructions that are executed by one or more processors to perform the method described in the first aspect.

[0040] In a sixth aspect, a chip is provided, comprising: a processor and an interface for calling and running a computer program stored in a memory, performing the method as described in the first aspect.

[0041] In a seventh aspect, a computer program product comprising instructions is provided, which, when executed on a computer or processor, cause the computer or processor to perform the method as described in the first aspect.

[0042] This invention solves the compatibility problem between different PHY chips in the same switch system by setting up a configuration module that periodically reads the connection status identifier and switches the working mode according to the connection status identifier. Attached Figure Description

[0043] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments of the present invention will be briefly described below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0044] Figure 1 is a flowchart illustrating a method for compatibility with multiple PHY chips provided in an embodiment of the present invention;

[0045] Figure 2 is a flowchart illustrating a method for compatibility with multiple PHY chips provided in an embodiment of the present invention;

[0046] Figure 3 is a flowchart illustrating a method for compatibility with multiple PHY chips provided in an embodiment of the present invention;

[0047] Figure 4 is a flowchart illustrating a method for compatibility with multiple PHY chips provided in an embodiment of the present invention;

[0048] Figure 5 is a schematic diagram of the architecture of a device compatible with multiple PHY chips provided in an embodiment of the present invention;

[0049] Figure 6 is a schematic diagram of the architecture of a communication system compatible with multiple PHY chips provided in an embodiment of the present invention;

[0050] Figure 7 is a flowchart illustrating a method for compatibility with multiple PHY chips provided in an embodiment of the present invention;

[0051] Figure 8 is a flowchart illustrating a method for compatibility with multiple PHY chips provided in an embodiment of the present invention;

[0052] Figure 9 is a schematic diagram of a method for compatibility with multiple PHY chips provided in an embodiment of the present invention;

[0053] Figure 10 is a schematic diagram of a method for compatibility with multiple PHY chips provided in an embodiment of the present invention;

[0054] Figure 11 is a schematic diagram of a method for compatibility with multiple PHY chips provided in an embodiment of the present invention;

[0055] Figure 12 is a schematic diagram of a method for compatibility with multiple PHY chips provided in an embodiment of the present invention;

[0056] Figure 13 is a schematic diagram of a method for compatibility with multiple PHY chips provided in an embodiment of the present invention;

[0057] Figure 14 is a schematic diagram of a method for compatibility with multiple PHY chips provided in an embodiment of the present invention;

[0058] Figure 15 is a schematic diagram of a method for compatibility with multiple PHY chips provided in an embodiment of the present invention;

[0059] Figure 16 is a schematic diagram of the architecture of a device compatible with multiple PHY chips provided in an embodiment of the present invention. Detailed Implementation

[0060] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0061] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as openly inclusive, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples; that is, although they may be incorporated into embodiments or examples using the above terms for reasons such as order and position, it does not limit them to be incorporated in combination by a single embodiment or example.

[0062] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more. Furthermore, for example, the description may use the prefix "A" or "B" to describe the same type of nouns as two independent entities. In this case, the corresponding features defined with "A" and "B" are used only to distinguish between similar entities and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.

[0063] In the description of this invention, the expression “A and / or B” (where A and B are used to formally represent specific features) will be used. The corresponding expression includes the following three combinations: only A, only B, and a combination of A and B.

[0064] As used in this invention, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from a particular value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0065] Furthermore, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0066] Example 1:

[0067] Embodiment 1 of the present invention provides a method for compatibility with multiple PHY chips, wherein a configuration module is connected between the MAC module and the PHY chip, and configuration rules for various working modes are pre-stored in the configuration module; as shown in Figure 1, the method includes:

[0068] In step 201, the configuration module reads the connection status identifier of the first preset register position in the PHY chip at preset intervals. In actual use, the configuration module can be a microcontroller unit (MCU). The first preset register position can be bit2 of reg_0x01. When bit2 = 1, it can be considered that the PHY chip has been successfully connected to the PHY chip on the other end. When bit2 = 0, the PHY chip is not connected to the PHY chip on the other side.

[0069] In step 202, if the connection status identifier is read as "not connected," the PHY chip is switched to the next working mode according to the configuration rules of the next working mode, until the connection status identifier is read as "connected." Here, the next working mode is relative to the current working mode in a single working mode switch (i.e., the working mode the PHY chip was in before the working mode switch). For example, assuming there are three working modes, in a preset order of working mode A, working mode B, and working mode C, if the connection status identifier is read as "not connected" during a single reading, the PHY chip's current working mode... If the operating mode is operating mode A, then the PHY chip is switched to operating mode B. If the connection status identifier is read as not connected, and the current operating mode of the PHY chip is operating mode B, then the PHY chip is switched to operating mode C. If the connection status identifier is read as not connected, and the current operating mode of the PHY chip is operating mode C, then the PHY chip is switched back to operating mode A, and so on. All operating modes are tried in this way until the local PHY chip and the remote PHY chip are operating in the same operating mode. At this point, they will connect successfully, and the connection status identifiers will be updated to "connected," stopping the mode switching. The preset period is obtained by those skilled in the art based on experience. In a specific application scenario, the preset period is longer than the time required for two PHY chips to connect successfully in the same operating mode, and the multiple PHY chips that need to connect to each other execute steps 201-202 at staggered times. During initialization, the PHY chip is configured to the first operating mode according to the configuration rules of the first operating mode. The first operating mode is obtained by those skilled in the art based on requirements analysis, such as using operating mode A as the first operating mode.

[0070] This embodiment solves the compatibility problem between different PHY chips in the same switch system by setting up a configuration module that periodically reads the connection status identifier and switches the working mode according to the connection status identifier.

[0071] In practical use, the next operating mode is determined based on the current operating mode of the PHY chip, as shown in Figure 2, and specifically includes:

[0072] In step 301, the mode identifier of the second preset register position in the PHY chip is read, and the current working mode of the PHY chip is determined according to the mode identifier.

[0073] In step 302, after configuring the PHY chip to the next working mode, the mode identifier corresponding to the next working mode is stored in the second preset register position so that when the second preset register position is read again, the current working mode configured this time is used as the current working mode for the next read.

[0074] In practical use, the second preset register position can be the byte 127 position of the A2 table of the EEPROM. Taking the working modes including SERDES mode and SGMII mode as an example, when byte 127 = 00, it means that the current working mode is SERDES mode, and when byte 127 = 01, it means that the current working mode is SGMII mode.

[0075] In a practical application scenario, the various working modes include SERDES mode and SGMII mode; the configuration rules corresponding to SERDES are as follows: write the value 0x0001 to the 0x16 register position of the PHY chip, write the value 0x9088 to the 0x1B register position of the PHY chip, write the value 0x9140 to the 0x00 register position of the PHY chip, and write the value 0x0000 to the 0x16 register position of the PHY chip.

[0076] The configuration rules corresponding to the SGMII mode are as follows: write the value 0x9084h to the 0x1Bh register position of the PHY chip, write the value 0x9140h to the 0x00h register position of the PHY chip, write the value 0x0000h to the 0x16h register position of the PHY chip, write the value 0x0F00h to the 0x09h register position of the PHY chip, write the value 0x0DE1h to the 0x04h register position of the PHY chip, and write the value 0x9140h to the 0x00h register position of the PHY chip.

[0077] In practical use, there are not only compatibility issues between PHY chips, but also compatibility issues between the MAC module and different PHY chips. To solve this problem, this embodiment also provides a preferred implementation method, in which the instructions that the MAC module needs to send to the PHY chip are forwarded through the configuration module. That is, the configuration module acts as an instruction relay station, and all instructions sent to the PHY chip pass through the configuration module so that the configuration module can process the instructions, as shown in Figure 3. The method also includes:

[0078] In step 401, when the configuration module receives an instruction from the MAC module, it determines whether the current type of the PHY chip is a preset type. If the current type of the PHY chip is a preset type, the instruction is directly sent to the PHY chip. The MAC module sends the instruction according to the preset type.

[0079] In step 402, otherwise, the instruction is mapped to a current type instruction according to a preset instruction mapping rule, and the current type instruction is sent to the PHY chip. The preset instruction mapping rule is obtained by those skilled in the art through instruction analysis of various types of chips. The preset type can be understood as a PHY chip type pre-defined by those skilled in the art during the design phase of the switch system. The MAC module sends instructions to the PHY chip according to this type. The current type instruction is an instruction applicable to the current PHY chip. The current type of the PHY chip can be referred to as the current type, i.e., the actual chip type used.

[0080] In some application scenarios, when designing a switch system, those skilled in the art may choose to use a Marvell-type PHY chip and design the MAC module's instructions accordingly to make the instructions compatible with the Marvell-type PHY chip. In this case, the default type is Marvell. However, in actual use, the RTL8211F chip type is used, so the current type is RTL8211F, and the corresponding instructions for the current type are the instructions applicable to the RTL8211F chip.

[0081] Specifically, mapping the instruction to a current type instruction according to a preset instruction mapping rule and sending the current type instruction to the PHY chip includes:

[0082] The instruction is passed to the preset instruction sending interface host_write_to_phy_a(), and the preset instruction sending interface host_write_to_phy_a() is called to send the instruction.

[0083] In the preset instruction sending interface host_write_to_phy_a(), if it is determined that the current type of the PHY chip is different from the preset type, the corresponding type branch is entered, specifically including:

[0084] If it is determined that the current type of the PHY chip is the first type, then the first type branch (i.e. the branch corresponding to the first type) is entered. In the first type branch, the Value_PhyA_To_PhyB() interface is used to map the instruction to the first type instruction, and the first type instruction is passed to the first type instruction sending interface host_write_to_phy_b(). The first type instruction sending interface host_write_to_phy_b() is called to send the first type instruction to the first type of PHY chip.

[0085] If the current type of the PHY chip is determined to be a preset type, then the instruction is issued directly.

[0086] The first type refers to the current type of the PHY chip. The first type instructions are those applicable to PHY chips of the first type.

[0087] In practical applications, instruction mapping can be implemented using the following code:

[0088] In other words, instructions are generated according to the method of PHY chip A, and the host_write_to_phy_a() interface is called to write values ​​to the PHY chip (i.e., issue instructions). In the host_write_to_phy_a() interface, the actual PHY chip type used is obtained. If the actual PHY chip type (i.e., the current type) is PHY chip B, the Value_PhyA_To_PhyB() interface is used to map the instructions to obtain the instructions of the current type. Then, the host_write_to_phy_b() interface is called inside the host_write_to_phy_a() interface. The instructions of the current type are passed to the host_write_to_phy_b() interface to issue the instructions to PHY chip B.

[0089] In practical application scenarios, the preset type can be the Marvell chip type, i.e., the chip type widely used in early switch system layouts. For example, when the preset type is the Marvell chip type and the current type is the RTL8211F chip type, mapping the instruction to the current type instruction according to the preset instruction mapping rules, as shown in Figure 4, specifically includes:

[0090] In step 501, the Marvell chip's MDIX setting instruction (i.e., the 0x10 instruction in Figure 15) is mapped to the RTL8211F chip's MDIX reading instruction.

[0091] In step 502, the SGMII and GBIC mode switching instructions of the Marvell chip (i.e., the 0x1B instruction in Figure 15) are mapped to the SGMII and SERDES mode switching instructions of the RTL8211F chip.

[0092] It should be noted that steps 501 and 502 above are merely examples of two instructions corresponding to the preset instruction mapping rules. In actual use, there are some instructions that can be applied to multiple chips. These instructions do not require mapping and can be used directly. The current type of the PHY chip is read from the chip's third preset register location. The location of the third preset register is determined by those skilled in the art based on experience and can be understood as follows: each chip has a fixed location storing its type.

[0093] This embodiment solves the compatibility problem between the MAC module and different chips in the same switch system by setting up a configuration module between the MAC module and the PHY chip and using the configuration module for instruction mapping.

[0094] Example 2:

[0095] Based on Embodiment 1, this embodiment also provides a device compatible with multiple PHY chips, as shown in Figure 5, including a MAC module, a PHY chip, a network transformer, a connector, and a configuration module; the device is also referred to as an electrical port module in actual use.

[0096] The configuration module is connected between the MAC module and the PHY chip, and the configuration module is used to execute the method for compatibility with multiple PHY chips described in Embodiment 1.

[0097] In practical use, the configuration module is an MCU. One end of the PHY chip is connected to the configuration module, and the other end is connected to one end of the network transformer. The other end of the network transformer is connected to the connector. In a specific application scenario, the MAC module is connected to a gold finger, and the configuration module and the gold finger are connected via an integrated circuit bus (I2C). The PHY chip is one or more of the following: MARVELL, RTL8211FSI, and YT8531SH-CA.

[0098] Based on this, this embodiment also provides a communication system compatible with multiple PHY chips, as shown in FIG6, including a local end and a remote end, wherein the above-mentioned device compatible with multiple PHY chips is used in the local end and / or the remote end.

[0099] Example 3:

[0100] Based on the method described in Embodiment 1, this invention combines specific application scenarios and uses technical descriptions in relevant scenarios to illustrate the implementation process of the features of this invention in those scenarios.

[0101] To address the incompatibility issue between different PHY chips in a given switch system, this embodiment uses the RTL8211FSI chip as an example. The RTL8211FSI chip is used to achieve compatibility with the 88E1111 chip, thus achieving mutual compatibility between different PHY chips.

[0102] The compatibility here mainly includes two aspects. The first aspect is the compatibility between PHY chips connected via copper cables (i.e., the compatibility between electrical port modules). When transmitting data between modules, incompatibility may occur due to different operating modes, and switching operating modes requires additional operations, which is quite cumbersome. The second aspect is the compatibility between the MAC module and different PHY chips (i.e., whether the MAC module in an electrical port module can use different PHY chips).

[0103] To address compatibility issues, this embodiment introduces an MCU as an intermediary within the module, based on register mapping. This ensures that modules with different PHY chip solutions can respond identically when the switch issues the same command. Simultaneously, after the module powers on, a polling mechanism is established during the handshake phase. This mechanism automatically matches the appropriate SGMII or SERDES mode, memorizes the mode, and sets the matched mode as the default mode for the next power-on, as shown in Figures 7 and 8. Specifically:

[0104] After the module completes power-on initialization, it handshakes with the MAC-side host. At this time, the MCU reads the register value corresponding to the PHY's link status (i.e., the connection status identifier obtained in Example 1). If the corresponding register is not set within 300ms, it means that the PHY and the MAC-side switch are not linked. Polling is then performed, corresponding to the PHY chip's mode configuration register, to complete the mode switch from the default SERDES mode to SGMII mode. If the switch and PHY successfully link up, 01 is written to byte 127 of EEPROM A2 and saved. Users can manually change the default power-on initialization value by writing to byte 127 of A2; 00 corresponds to SERDES mode, and 01 corresponds to SGMII mode.

[0105] According to the IEEE 802.3 protocol, in 1000BASE-T mode, setting bit 2 of the PHY register reg_0x01 can determine the module's link status. When bit 2 = 1, the module is successfully linked; when bit 2 = 0, the module is not linked. The internal MCU of the module can read host instructions sent by the switch via I2C and assign values ​​to the corresponding registers according to the host instructions to configure them to the corresponding operating mode. For example, writing the value shown in Figure 9 to the corresponding register address configures the PHY chip to SERDES mode, or writing the value shown in Figure 10 to the corresponding register address configures the PHY chip to SGMII mode.

[0106] The above method is to achieve compatibility between the local PHY chip and the remote PHY chip, so as to ensure that the two chips can be successfully connected. As shown in Figure 11 or Figure 12, the two chips can be successfully connected when both the local and remote PHY chips are in SGMII working mode or when both the local and remote PHY chips are in SERDES mode.

[0107] However, in practical use, in order to make a switch system compatible with different PHY chips, it is also necessary to handle the compatibility between the MAC chip and PHY chip on the same side. For example, for MAC1 and PHY1 in Figure 11, or for MAC2 and PHY2 in Figure 11, that is, between two switches, they need to be in SGMII mode or SERDES mode. If one side is SGMII and the other side is SERDES, the link cannot be linked, and the MAC and PHY connections need to be symmetrical. To address this issue, this embodiment introduces an MCU module, as shown in Figure 5, and uses the MCU for instruction mapping. For example, there are two modules, using "PHY chip A" and "PHY chip B" respectively. The host can achieve the desired effect by operating reg0x00 on "PHY chip A", but it needs to operate reg0x01 on "PHY chip B" to achieve the same effect. This makes the corresponding operations within a switch quite complex and confusing. In this case, the MCU inside the "PHY chip B" module can, after recognizing the host's instruction to operate on "PHY chip A", map the registers of "PHY chip B", configure reg0x01, and return the value of register reg0x00 of "PHY chip A" that achieves the desired effect to the host. In this way, the switch host will consider the "PHY chip B" module to be equivalent to the "PHY chip A" module, and both can work normally.

[0108] Figures 13 and 14 show the data link diagrams of the 88E1111 PHY chip in different operating modes. To achieve compatibility between the MAC chip and different PHY chips, the MCU inside the electrical port module communicates with the switch via I2C through the gold fingers, corresponding to different register operations according to the differences in the module's PHY chip. For example, if the switch host instruction is an operation instruction made for "PHY chip A", no additional register mapping is needed when targeting "PHY chip A" module; the corresponding register can be operated directly. When targeting "PHY chip B" module, the corresponding register mapping for "PHY chip B" needs to be followed before operating the registers of "PHY chip B". What remains the same is that after the module MCU completes the required operation, the return value to the host is the same. In this way, the compatibility of different PHY chip modules on the same switch system is achieved.

[0109] This embodiment uses Realtek as "PHY chip B" and Marvell as "PHY chip A". In the default instructions of the switch system, the default working mode of the Marvell solution is SERDES when it is powered on. Therefore, during power-on initialization, the Realtek solution also needs to be configured to SERDES mode.

[0110] After power-on initialization, the host reads the registers of the Marvell PHY to ensure its operating state is SERDES, corresponding to register reg0x1B = 9088. After configuring the Realtek PHY to operate in SERDES mode, the MCU's return value to the switch is also set to reg0x1B = 9088. This ensures the Realtek PHY is successfully compatible with the default Marvell switch system. For the RTL8211F PHY chip, instruction mapping is performed internally by the MCU as shown in Figure 15. The mapped instructions are then sent to the PHY chip, enabling the electrical port module to adaptively switch between SERDES and SGMII modes after power-on initialization. Furthermore, the MCU firmware ensures compatibility between different PHY chip modules with existing switch systems and communication links.

[0111] Example 4:

[0112] Figure 16 shows a schematic diagram of the architecture of a multi-PHY chip compatible device (i.e., configuration module) according to an embodiment of the present invention. The multi-PHY chip compatible device of this embodiment includes one or more processors 21 and a memory 22. Figure 16 uses one processor 21 as an example.

[0113] The processor 21 and the memory 22 can be connected via a bus or other means. Figure 16 shows an example of a connection via a bus.

[0114] The memory 22, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs and non-volatile computer-executable programs, such as the method for compliant multi-PHY chips in Embodiment 1. The processor 21 executes the method for compliant multi-PHY chips by running the non-volatile software programs and instructions stored in the memory 22.

[0115] Memory 22 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 22 may optionally include memory remotely located relative to processor 21, which can be connected to processor 21 via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0116] The program instructions / modules are stored in the memory 22 and, when executed by one or more processors 21, perform the method for compatible multi-PHY chips described in Embodiment 1 above.

[0117] It is worth noting that the information interaction and execution process between the modules and units in the above-mentioned device and system are based on the same concept as the processing method embodiment of the present invention. For details, please refer to the description in the method embodiment of the present invention, and will not be repeated here.

[0118] Those skilled in the art will understand that all or part of the steps in the various methods of the embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, which may include: read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, etc.

[0119] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method compatible with multiple PHY chips, characterized in that, A configuration module is connected between the MAC module and the PHY chip, and configuration rules for various working modes are pre-stored in the configuration module; the method includes: the configuration module reads the connection status identifier of the first preset register position in the PHY chip at preset intervals; If the connection status identifier is read as not connected, the PHY chip is switched to the next working mode according to the configuration rules of the next working mode, until the connection status identifier is read as connected. During initialization, the PHY chip is configured to the first working mode according to the configuration rules of the first working mode.

2. The method for compatibility with multiple PHY chips according to claim 1, characterized in that, The next operating mode is determined based on the current operating mode of the PHY chip, and specifically includes: Read the mode identifier at the location of the second preset register in the PHY chip, and determine the current operating mode of the PHY chip based on the mode identifier; After configuring the PHY chip to the next operating mode, the mode identifier corresponding to the next operating mode is stored in the second preset register position.

3. The method for compatibility with multiple PHY chips according to claim 1, characterized in that, The various working modes include SERDES mode and SGMII mode; the configuration rules corresponding to SERDES are as follows: write the value 0x0001 to the 0x16 register position of the PHY chip, write the value 0x9088 to the 0x1B register position of the PHY chip, write the value 0x9140 to the 0x00 register position of the PHY chip, and write the value 0x0000 to the 0x16 register position of the PHY chip.

4. The method for compatibility with multiple PHY chips according to claim 3, characterized in that, The configuration rules corresponding to the SGMII mode are as follows: Write the value 0x9084h to the 0x1Bh register of the PHY chip, write the value 0x9140h to the 0x00h register of the PHY chip, write the value 0x0000h to the 0x16h register of the PHY chip, write the value 0x0F00h to the 0x09h register of the PHY chip, write the value 0x0DE1h to the 0x04h register of the PHY chip, and write the value 0x9140h to the 0x00h register of the PHY chip.

5. The method for compatibility with multiple PHY chips according to claim 1, characterized in that, The instructions that the MAC module needs to send to the PHY chip are forwarded through the configuration module. The method also includes: When the configuration module receives an instruction from the MAC module, it determines whether the current type of the PHY chip is a preset type. If the current type of the PHY chip is a preset type, the configuration module directly sends the instruction to the PHY chip. The MAC module sends the instruction according to the preset type. Otherwise, the instruction is mapped to the current type instruction according to the preset instruction mapping rules, and the current type instruction is sent to the PHY chip.

6. The method for compatibility with multiple PHY chips according to claim 5, characterized in that, The step of mapping the instruction to a current type instruction according to a preset instruction mapping rule and sending the current type instruction to the PHY chip specifically includes: The instruction is passed to the preset instruction sending interface host_write_to_phy_a(), and the preset instruction sending interface host_write_to_phy_a() is called to send the instruction; In the preset instruction sending interface host_write_to_phy_a(), if it is determined that the current type of the PHY chip is different from the preset type, the corresponding type branch is entered, specifically including: If it is determined that the current type of the PHY chip is the first type, then the first type branch is entered. In the first type branch, the Value_PhyA_To_PhyB() interface is used to map the instruction to the first type instruction, and the first type instruction is passed to the first type instruction sending interface host_write_to_phy_b(). The first type instruction sending interface host_write_to_phy_b() is called to send the first type instruction to the first type of PHY chip.

7. The method for compatibility with multiple PHY chips according to claim 5, characterized in that, When the preset type is Marvell chip type and the current type is RTL8211F chip type, mapping the instruction to the current type instruction according to the preset instruction mapping rule specifically includes: Map the Marvell chip's MDIX setting instructions to the RTL8211F chip's MDIX reading instructions; Map the SGMII and GBIC mode switching instructions of the Marvell chip to the SGMII and SERDES mode switching instructions of the RTL8211F chip.

8. A device compatible with multiple PHY chips, characterized in that, Includes MAC module, PHY chip, network transformer, connectors and configuration module; The configuration module is connected between the MAC module and the PHY chip, and the configuration module is used to execute the method of compatibility with multiple PHY chips as described in any one of claims 1-7.

9. The device compatible with multiple PHY chips according to claim 8, characterized in that, The PHY chip is one or more of MARVELL, RTL8211FSI, and YT8531SH-CA chips.

10. A communication system compatible with multiple PHY chips, characterized in that, The apparatus includes a local end and a remote end, wherein the local end and / or the remote end uses a multi-PHY compatible chip as described in any of claims 8-9.

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