Communication method and apparatus

Abstract

A communication method and apparatus, which relate to the technical field of communications, and can improve a base matrix so as to improve the coding performance of an LDPC code and reduce the decoding complexity. The method comprises: on the basis of a base matrix, a transmitter device performing LDPC coding on an information bit sequence, so as to obtain a coded bit sequence, and outputting the coded bit sequence. The base matrix comprises a first row region and a second row region, wherein the first row region corresponds to a first code rate range, and the second row region corresponds to a second code rate range; or, the first row region corresponds to a non-orthogonal region in the base matrix, and the second row region corresponds to one or more of a quasi-orthogonal region in the base matrix and an orthogonal region in the base matrix; column indices of non-zero elements in a pth row of the first row region comprise column indices of non-zero elements, which are located in a first column region, among the first x rows of the second row region; and an element in a yth column of the pth row of the first row region is a zero element, there is at least one non-zero element in the yth column among the first x rows of the second row region, and elements in the yth column among rows other than the first x rows of the second row region are zero elements.

Description

Communication methods and devices

[0001] This application claims priority to Chinese patent application filed on January 17, 2025, with application number 202510082087.X and entitled "Communication Method and Apparatus", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communication technology, and in particular to communication methods and apparatus. Background Technology

[0003] Low-density parity-check (LDPC) codes are a class of linear block codes with sparse parity-check matrices, characterized by flexible structure and low decoding complexity. Because they employ a partially parallel iterative decoding algorithm, they achieve higher throughput than traditional Turbo codes. LDPC codes can be used as error-correcting codes in communication systems, thereby improving the reliability and power efficiency of channel transmission.

[0004] The transmitting device can perform LDPC encoding on the information bit sequence based on the basis matrix, and similarly, the receiving device can decode the information to be decoded based on the basis matrix. How to improve the basis matrix to enhance the encoding performance of LDPC codes while reducing decoding complexity is a pressing issue. Summary of the Invention

[0005] This application provides a communication method and apparatus that can improve the basis matrix to enhance the encoding performance of LDPC codes while reducing decoding complexity.

[0006] Firstly, this application provides a communication method that can be applied to a transmitting device, such as the transmitting device itself or a communication module and / or computing module within the transmitting device, or circuits or chips in the transmitting device responsible for communication functions (e.g., modem chips, also known as baseband chips, or system-on-chip (SoC) chips containing modem cores, or system-in-package (SIP) chips), or circuits or chips in the transmitting device responsible for communication and / or computing functions (e.g., graphics processing units (GPUs), artificial intelligence (AI) processors, or application-specific integrated circuits (ASICs)), or logic nodes, logic modules, or software capable of implementing all or part of the functions of the transmitting device. Taking the application of this method to a transmitting device as an example, in this method, the transmitting device performs LDPC encoding on the information bit sequence according to the base matrix to obtain an encoded bit sequence; and outputs the encoded bit sequence. The base matrix includes a first row region and a second row region, and the intersection of the rows of the first row region and the second row region is an empty set; the first row region corresponds to a first code rate interval, and the second row region corresponds to a second code rate interval; or, the first row region corresponds to a non-orthogonal region in the base matrix, and the second row region corresponds to one or more of the following: a quasi-orthogonal region in the base matrix, or an orthogonal region in the base matrix; the first row region and the second row region satisfy any of the following conditions: the first condition or the second condition; the first condition is that the column index of the non-zero element in the p-th row of the first row region includes the column index of the non-zero element in the first column region of the first x rows of the second row region; the second condition is that the y-th column of the p-th row of the first row region is a zero element, there is at least one non-zero element in the y-th column of the first x rows of the second row region, and the y-th column of the other rows in the second row region other than the first x rows is a zero element; y is an integer less than the number of columns of the base matrix and greater than or equal to 0; p is an integer less than the number of rows of the first row region and greater than or equal to 0, and x is a positive integer less than or equal to the number of rows of the second row region.

[0007] Based on the first aspect, the base matrix can include a first row region and a second row region. Based on the first condition, the column index of the non-zero element in the p-th row of the first row region can include the column index of the non-zero element in the first column region of the first x rows of the second row region. By changing the edge relationships in the base matrix, any row of the first x rows of the second row region is orthogonal to the last row of the base matrix, thereby improving coding performance. Based on the second condition, the y-th column of the p-th row of the first row region is a zero element, there is at least one non-zero element in the y-th column of the first x rows of the second row region, and the y-th column of all rows other than the first x rows of the second row region is a zero element. By changing the edge relationships in the base matrix, any row of the first x rows of the second row region is orthogonal to the last row of the base matrix, thereby improving coding performance.

[0008] Furthermore, based on the first or second condition, since the 0th row of the basis matrix is ​​orthogonal to the last row, and any row in the first x rows of the second row region is orthogonal to the last row of the basis matrix, the order in which the non-zero elements of the last row of the basis matrix are read remains unchanged regardless of the number of iterations or the scheduling method (i.e., the order in which the non-zero elements of the last row of the basis matrix are read can remain constant), thus improving communication reliability. Moreover, since the order in which the non-zero elements of the last row of the basis matrix are read remains constant, multiple rows of the basis matrix can be read simultaneously, thereby reducing communication latency and improving overall communication performance.

[0009] Secondly, this application provides a communication method that can be applied to a receiving device, such as the receiving device itself or its communication and / or computing modules, or circuits or chips responsible for communication functions within the receiving device, or circuits or chips responsible for communication and / or computing functions (such as GPUs, AI processors, or ASICs) within the receiving device, or logic nodes, logic modules, or software capable of implementing all or part of the functions of the receiving device. Taking the application of this method to a receiving device as an example, in this method, the receiving device receives information to be decoded; and decodes the information to be decoded according to a basis matrix to obtain a decoding result. The base matrix includes a first row region and a second row region, and the intersection of the rows of the first row region and the second row region is an empty set; the first row region corresponds to a first code rate interval, and the second row region corresponds to a second code rate interval; or, the first row region corresponds to a non-orthogonal region in the base matrix, and the second row region corresponds to one or more of the following: a quasi-orthogonal region in the base matrix, or an orthogonal region in the base matrix; the first row region and the second row region satisfy any of the following conditions: the first condition or the second condition; the first condition is that the column index of the non-zero element in the p-th row of the first row region includes the column index of the non-zero element in the first column region of the first x rows of the second row region; the second condition is that the y-th column of the p-th row of the first row region is a zero element, there is at least one non-zero element in the y-th column of the first x rows of the second row region, and the y-th column of the other rows in the second row region other than the first x rows is a zero element; y is an integer less than the number of columns of the base matrix and greater than or equal to 0; p is an integer less than the number of rows of the first row region and greater than or equal to 0, and x is a positive integer less than or equal to the number of rows of the second row region.

[0010] Based on the second aspect, the basis matrix can include a first row region and a second row region. Based on the first condition, the column index of the non-zero element in the p-th row of the first row region can include the column index of the non-zero element in the first column region of the first x rows of the second row region. By changing the edge relationships in the basis matrix, any row of the first x rows of the second row region is orthogonal to the last row of the basis matrix, thereby improving decoding performance (e.g., reducing the bit error rate). Based on the second condition, the y-th column of the p-th row of the first row region is a zero element, there is at least one non-zero element in the y-th column of the first x rows of the second row region, and the y-th column of all rows other than the first x rows of the second row region is a zero element. By changing the edge relationships in the basis matrix, any row of the first x rows of the second row region is orthogonal to the last row of the basis matrix, thereby improving decoding performance (e.g., reducing the bit error rate).

[0011] In addition, based on the first or second condition, since the 0th row of the basis matrix is ​​orthogonal to the last row, and any row in the first x rows of the second row region is orthogonal to the last row of the basis matrix, the order of reading the non-zero elements of the last row of the basis matrix during the decoding process does not change with the number of iterations or the scheduling method (i.e., the order of reading the non-zero elements of the last row of the basis matrix can remain fixed), which can reduce the hardware burden and reduce the complexity of decoding.

[0012] Furthermore, based on the first or second condition, since the order in which the non-zero elements of the last row of the base matrix are read can remain fixed during the decoding process, multiple rows of the base matrix can be read simultaneously during the decoding process, which can reduce the decoding latency and thus improve communication performance.

[0013] Combining the first and second aspects, one possible implementation is that the first column region includes the information column and the core verification column in the base matrix; or, the first column region includes the information column in the base matrix; or, the first column region includes all columns in the base matrix except for the punched column; or, the first column region includes columns 0 to t0 in the base matrix, where t0 is greater than or equal to a first threshold; or, the first column region includes columns t1 to t2 in the base matrix, where t2 is the number of information columns in the base matrix; or, the first column region includes columns t1 to t3 in the base matrix, where t3 is the sum of the number of information columns and the number of core verification columns in the base matrix; wherein, t1 is greater than or equal to a second threshold.

[0014] Based on this possible implementation, the sending or receiving device can determine the first column region according to the actual communication scenario or situation to better meet communication needs and thus improve communication performance. Furthermore, the fewer elements included in the first column region, the simpler the hardware implementation and the less latency during decoding; conversely, the more elements included in the first column region, the larger the design space for the edge relationships of the basis matrix, leading to a better degree distribution and a better decoding threshold, thereby improving decoding performance.

[0015] Here, the degree can refer to the degree of a variable (i.e., the number of edges connecting the variable, or the number of check nodes connected to the variable), or the degree of the check equation (i.e., the number of edges connecting the check equation, or the number of variables connected to the check equation). For a variable, the more edges it has, the higher its degree, allowing it to obtain information from more check nodes and more accurately estimate the information to be decoded. For a check equation, the fewer edges it has, the lower its degree, and the more accurate the estimation of the variable's state. Therefore, the degree distribution can be determined jointly by the edges of the variable and the check equation to achieve a better degree distribution.

[0016] In this context, the degree of a variable can be understood as the row weight of the basis matrix, and the degree of a verification equation can be understood as the column weight of the basis matrix.

[0017] Combining the first and second aspects, one possible implementation is that the first threshold can be 10; or, the first threshold can be 9.

[0018] Based on this possible implementation, the elements in the extended parity region of the base matrix in the first x rows of the second row region can remain unchanged, which can reduce the impact on encoding or decoding performance and thus improve communication performance.

[0019] Combining the first and second aspects, one possible implementation is that the second threshold can be 3; or, the second threshold can be 2.

[0020] Based on this possible implementation, on the one hand, changes to the elements in the punched column can be avoided, reducing the impact on encoding or decoding performance and thus improving communication performance. On the other hand, with a smaller second threshold, the number of elements included in the first column region can be larger, and the design space for the edge relationships of the basis matrix can be larger, resulting in a better degree distribution and a better decoding threshold, thereby improving decoding performance.

[0021] Combining the first and second aspects, one possible implementation is that the first and second row regions are continuous.

[0022] Based on this possible implementation, the first row region can include consecutive rows in the basis matrix, the second row region can include consecutive rows in the basis matrix, and the row numbers corresponding to the end row in the first row region and the start row in the second row region in the basis matrix can be consecutive. This can reduce the design of the edge relationships in the basis matrix, reduce the implementation complexity, and simplify the implementation.

[0023] Combining the first and second aspects, one possible implementation is that p is 0.

[0024] Based on this possible implementation, the 0th row of the basis matrix can be orthogonal to the last row, and each row in the first x rows of the second row region can be orthogonal to the last row of the basis matrix. This allows the order in which the non-zero elements of the last row of the basis matrix are read during the decoding process to remain unchanged regardless of the number of iterations or the scheduling method (i.e., the order in which the non-zero elements of the last row of the basis matrix are read can remain fixed). This can reduce the hardware burden and the complexity of decoding.

[0025] Combining the first and second aspects, one possible implementation is that x is 1, or x is 2, or x is 3.

[0026] Based on this possible implementation, several feasible solutions are provided for the value of x. The value of x can be determined according to actual communication needs, thereby improving communication reliability. At the same time, it can increase the flexibility and diversity of x's value. In addition, a smaller value for x can reduce hardware implementation complexity and simplify implementation.

[0027] Combining the first and second aspects, one possible implementation is that the first row region includes rows 0 to P-1 of the base matrix, and the second row region includes rows P to the last row of the base matrix; where P is the sum of the number of rows in the core verification region of the base matrix and t6, and t6 is an integer greater than or equal to 0.

[0028] Based on this possible implementation, the first and second row regions can be determined according to the number of rows in the core parity region of the base matrix, which can improve the overall communication performance.

[0029] Combining the first and second aspects, one possible implementation is that t6 is 0; or t6 is 1; or t6 is 2.

[0030] Based on this possible implementation, several feasible schemes are provided for the value of t6. The value of t6 can be determined according to the actual communication needs, thereby improving the reliability of communication. At the same time, the flexibility and diversity of the value of t6 can be improved.

[0031] Combining the first and second aspects, one possible implementation is that the number of non-zero elements in the punched column of the basis matrix is ​​a first preset value.

[0032] Based on this possible implementation, the elements of the punched column can remain unchanged, thereby reducing the impact on decoding performance.

[0033] Optionally, the elements in the punched columns of the base matrix remain fixed.

[0034] Combining the first and second aspects, one possible implementation is that the row weight of the z-th row in the basis matrix is ​​Nz; where z = 0, 1, ..., Z-1, Z is the row number of the basis matrix, and Nz is a preset value.

[0035] Optionally, the row weight of the z-th row in the basis matrix is ​​fixed.

[0036] Based on this possible implementation, the degree distribution in the basis matrix can remain unchanged, which can result in a better decoding threshold.

[0037] Combining the first and second aspects, one possible implementation is that the maximum value of the row number corresponding to the first row region in the base matrix is ​​associated with the minimum value of the first code rate interval; wherein, the minimum value of the first code rate interval is the ratio of the maximum number of information columns supported by the base matrix to the first difference; the first difference is the difference between the first value and the number of punched columns in the base matrix, and the first value is the sum of the maximum number of information columns supported by the base matrix and the maximum value of the row number corresponding to the first row region in the base matrix.

[0038] Combining the first and second aspects, one possible implementation is that the maximum value of the row number corresponding to the second row region in the base matrix is ​​associated with the minimum value of the second code rate interval; wherein, the minimum value of the second code rate interval is the ratio of the maximum number of information columns supported by the base matrix to the second difference; the second difference is the difference between the second value and the number of punched columns in the base matrix, and the second value is the sum of the maximum number of information columns supported by the base matrix and the maximum value of the row number corresponding to the second row region in the base matrix.

[0039] Based on this possible implementation, the row number of the first row (or second row) in the base matrix can be determined according to the minimum bit rate supported by the first row (or second row), so that the determined first row (or second row) can better meet the communication requirements and improve the reliability of communication.

[0040] Thirdly, this application provides a communication method that can be applied to a transmitting device, such as a transmitting device or a communication module and / or computing module within the transmitting device, or a circuit or chip in the transmitting device responsible for communication functions, or a circuit or chip in the transmitting device responsible for communication and / or computing functions (such as a GPU, AI processor, or ASIC), or a logic node, logic module, or software capable of implementing all or part of the functions of the transmitting device. Taking the application of this method to a transmitting device as an example, in this method, the transmitting device performs LDPC encoding on the information bit sequence according to the basis matrix to obtain an encoded bit sequence; and outputs the encoded bit sequence. The basis matrix includes the following non-zero elements (i, j), where i is the row number and j is the column number:

[0041] i=0, j=0, 1, 2, 3, 6, 9, 10, 11;

[0042] i=1, j=0, 3, 4, 5, 6, 7, 8, 9, 11, 12;

[0043] i=2, j=0, 1, 3, 4, 8, 10, 12, 13;

[0044] i=3, j=1, 2, 4, 5, 6, 7, 8, 9, 10, 13;

[0045] i=4, j=0, 1, 11, 14;

[0046] i=5, j=0,1,2,6,9,15.

[0047] All other elements in the above row are zero elements.

[0048] Based on the third aspect, the column index of the non-zero element in the 0th row of the basis matrix can include the column index of the non-zero element in the first column region of the 5th row of the basis matrix. By changing the connection relationship in the basis matrix, the 5th row of the basis matrix is ​​made orthogonal to the last row of the basis matrix, thereby improving the encoding performance.

[0049] Furthermore, since the 0th row and the last row of the basis matrix are orthogonal, and the 5th row and the last row of the basis matrix are also orthogonal, the order in which the non-zero elements of the last row of the basis matrix are read remains unchanged regardless of the number of iterations or the scheduling method (i.e., the order in which the non-zero elements of the last row of the basis matrix are read can remain constant), thus improving communication reliability. Moreover, because the order in which the non-zero elements of the last row of the basis matrix are read remains constant, multiple rows of the basis matrix can be read simultaneously, thereby reducing communication latency and improving overall communication performance.

[0050] Fourthly, this application provides a communication method that can be applied to a receiving device, such as a receiving device or a communication module and / or computing module within the receiving device, or a circuit or chip in the receiving device responsible for communication functions, or a circuit or chip in the receiving device responsible for communication and / or computing functions (such as a GPU, AI processor, or ASIC), or a logic node, logic module, or software capable of implementing all or part of the functions of the receiving device. Taking the application of this method to a receiving device as an example, in this method, the receiving device receives information to be decoded; the information to be decoded is decoded according to a basis matrix to obtain a decoding result. The basis matrix includes the following non-zero elements (i, j), where i is the row number and j is the column number:

[0051] i=0, j=0, 1, 2, 3, 6, 9, 10, 11;

[0052] i=1, j=0, 3, 4, 5, 6, 7, 8, 9, 11, 12;

[0053] i=2, j=0, 1, 3, 4, 8, 10, 12, 13;

[0054] i=3, j=1, 2, 4, 5, 6, 7, 8, 9, 10, 13;

[0055] i=4, j=0, 1, 11, 14;

[0056] i=5, j=0,1,2,6,9,15.

[0057] All other elements in the above row are zero elements.

[0058] Based on the fourth aspect, the column index of the non-zero element in the 0th row of the basis matrix can include the column index of the non-zero element in the first column region of the 5th row of the basis matrix. By changing the connection relationship in the basis matrix, the 5th row of the basis matrix can be orthogonal to the last row of the basis matrix, which can improve the decoding performance.

[0059] In addition, since the 0th row of the basis matrix is ​​orthogonal to the last row, and the 5th row of the basis matrix is ​​orthogonal to the last row of the basis matrix, the order in which the non-zero elements of the last row of the basis matrix are read during the decoding process does not change with the number of iterations or the scheduling method (that is, the order in which the non-zero elements of the last row of the basis matrix are read can remain fixed), which can reduce the hardware burden and reduce the complexity of decoding.

[0060] Furthermore, since the order in which the non-zero elements of the last row of the base matrix are read can remain fixed during the decoding process, multiple rows of the base matrix can be read simultaneously during the decoding process, which can reduce the decoding latency and thus improve communication performance.

[0061] Fifthly, this application provides a communication method that can be applied to a transmitting device, such as a transmitting device or a communication module and / or computing module within the transmitting device, or a circuit or chip in the transmitting device responsible for communication functions, or a circuit or chip in the transmitting device responsible for communication and / or computing functions (such as a GPU, AI processor, or ASIC), or a logic node, logic module, or software capable of implementing all or part of the functions of the transmitting device. Taking the application of this method to a transmitting device as an example, in this method, the transmitting device performs LDPC encoding on the information bit sequence according to the basis matrix to obtain an encoded bit sequence; and outputs the encoded bit sequence. The basis matrix includes the following non-zero elements (i, j), where i is the row number and j is the column number:

[0062] i=0, j=0, 1, 2, 3, 6, 9, 10, 11;

[0063] i=1, j=0, 3, 4, 5, 6, 7, 8, 9, 11, 12;

[0064] i=2, j=0, 1, 3, 4, 8, 10, 12, 13;

[0065] i=3, j=1, 2, 4, 5, 6, 7, 8, 9, 10, 13;

[0066] i=4, j=0, 1, 11, 14;

[0067] i=5, j=0,1,2,6,9,11,15.

[0068] All other elements in the above row are zero elements.

[0069] Based on the fifth aspect, the column index of the non-zero element in the 0th row of the basis matrix can include the column index of the non-zero element in the first column region of the 5th row of the basis matrix. By changing the connection relationship in the basis matrix, the 5th row of the basis matrix is ​​made orthogonal to the last row of the basis matrix, thereby improving the coding performance.

[0070] Furthermore, since the 0th row and the last row of the basis matrix are orthogonal, and the 5th row and the last row of the basis matrix are also orthogonal, the order in which the non-zero elements of the last row of the basis matrix are read remains unchanged regardless of the number of iterations or the scheduling method (i.e., the order in which the non-zero elements of the last row of the basis matrix are read can remain constant), thus improving communication reliability. Moreover, because the order in which the non-zero elements of the last row of the basis matrix are read remains constant, multiple rows of the basis matrix can be read simultaneously, thereby reducing communication latency and improving overall communication performance.

[0071] Sixthly, this application provides a communication method that can be applied to a receiving device, such as a receiving device or a communication module and / or computing module within the receiving device, or a circuit or chip in the receiving device responsible for communication functions, or a circuit or chip in the receiving device responsible for communication and / or computing functions (such as a GPU, AI processor, or ASIC), or a logic node, logic module, or software capable of implementing all or part of the functions of the receiving device. Taking the application of this method to a receiving device as an example, in this method, the receiving device receives information to be decoded; and decodes the information to be decoded according to a basis matrix to obtain a decoding result. The basis matrix includes the following non-zero elements (i, j), where i is the row number and j is the column number:

[0072] i=0, j=0, 1, 2, 3, 6, 9, 10, 11;

[0073] i=1, j=0, 3, 4, 5, 6, 7, 8, 9, 11, 12;

[0074] i=2, j=0, 1, 3, 4, 8, 10, 12, 13;

[0075] i=3, j=1, 2, 4, 5, 6, 7, 8, 9, 10, 13;

[0076] i=4, j=0, 1, 11, 14;

[0077] i=5, j=0,1,2,6,9,11,15.

[0078] All other elements in the above row are zero elements.

[0079] Based on the sixth aspect, the column index of the non-zero element in the 0th row of the basis matrix can include the column index of the non-zero element in the first column region of the 5th row of the basis matrix. By changing the connection relationship in the basis matrix, the 5th row of the basis matrix is ​​made orthogonal to the last row of the basis matrix, thereby improving the decoding performance.

[0080] In addition, since the 0th row of the basis matrix is ​​orthogonal to the last row, and the 5th row of the basis matrix is ​​orthogonal to the last row of the basis matrix, the order in which the non-zero elements of the last row of the basis matrix are read during the decoding process does not change with the number of iterations or the scheduling method (that is, the order in which the non-zero elements of the last row of the basis matrix are read can remain fixed), which can reduce the hardware burden and reduce the complexity of decoding.

[0081] Furthermore, since the order in which the non-zero elements of the last row of the base matrix are read can remain fixed during the decoding process, multiple rows of the base matrix can be read simultaneously during the decoding process, which can reduce the decoding latency and thus improve communication performance.

[0082] Seventhly, this application provides a communication method that can be applied to a transmitting device, such as a transmitting device or a communication module and / or computing module within the transmitting device, or a circuit or chip in the transmitting device responsible for communication functions, or a circuit or chip in the transmitting device responsible for communication and / or computing functions (such as a GPU, AI processor, or ASIC), or a logic node, logic module, or software capable of implementing all or part of the functions of the transmitting device. Taking the application of this method to a transmitting device as an example, in this method, the transmitting device performs LDPC encoding on the information bit sequence according to the basis matrix to obtain an encoded bit sequence; and outputs the encoded bit sequence. The basis matrix includes the following non-zero elements (i, j), where i is the row number and j is the column number:

[0083] i=0, j=0, 1, 2, 3, 6, 9, 10, 11;

[0084] i=1, j=0, 3, 4, 5, 6, 7, 8, 9, 11, 12;

[0085] i=2, j=0, 1, 3, 4, 8, 10, 12, 13;

[0086] i=3, j=1, 2, 4, 5, 6, 7, 8, 9, 10, 13;

[0087] i=4, j=0, 1, 11, 14;

[0088] i=5,j=0,1,5,7,11,15;

[0089] i=6, j=0, 6, 9, 11, 16.

[0090] All other elements in the above row are zero elements.

[0091] Based on the seventh aspect, the column index of the non-zero element in the 0th row of the basis matrix can include the column index of the non-zero element in the first column region of the 6th row of the basis matrix. By changing the connection relationship in the basis matrix, the 6th row of the basis matrix is ​​made orthogonal to the last row of the basis matrix, thereby improving the coding performance.

[0092] Furthermore, since the 0th row and the last row of the basis matrix are orthogonal, and the 6th row and the last row of the basis matrix are also orthogonal, the order in which the non-zero elements of the last row of the basis matrix are read remains unchanged regardless of the number of iterations or the scheduling method (i.e., the order in which the non-zero elements of the last row of the basis matrix are read can remain constant), thus improving communication reliability. Moreover, because the order in which the non-zero elements of the last row of the basis matrix are read remains constant, multiple rows of the basis matrix can be read simultaneously, thereby reducing communication latency and improving overall communication performance.

[0093] Eighthly, this application provides a communication method that can be applied to a receiving device, such as a receiving device or a communication module and / or computing module within the receiving device, or a circuit or chip in the receiving device responsible for communication functions, or a circuit or chip in the receiving device responsible for communication and / or computing functions (such as a GPU, AI processor, or ASIC), or a logic node, logic module, or software capable of implementing all or part of the functions of the receiving device. Taking the application of this method to a receiving device as an example, in this method, the receiving device receives information to be decoded; the information to be decoded is decoded according to a basis matrix to obtain a decoding result. The basis matrix includes the following non-zero elements (i, j), where i is the row number and j is the column number:

[0094] i=0, j=0, 1, 2, 3, 6, 9, 10, 11;

[0095] i=1, j=0, 3, 4, 5, 6, 7, 8, 9, 11, 12;

[0096] i=2, j=0, 1, 3, 4, 8, 10, 12, 13;

[0097] i=3, j=1, 2, 4, 5, 6, 7, 8, 9, 10, 13;

[0098] i=4, j=0, 1, 11, 14;

[0099] i=5,j=0,1,5,7,11,15;

[0100] i=6, j=0, 6, 9, 11, 16.

[0101] All other elements in the above row are zero elements.

[0102] Based on the eighth aspect, the column index of the non-zero element in the 0th row of the basis matrix can include the column index of the non-zero element in the first column region of the 6th row of the basis matrix. By changing the connection relationship in the basis matrix, the 6th row of the basis matrix is ​​made orthogonal to the last row of the basis matrix, thereby improving the decoding performance.

[0103] In addition, since the 0th row of the basis matrix is ​​orthogonal to the last row, and the 6th row of the basis matrix is ​​orthogonal to the last row of the basis matrix, the order in which the non-zero elements of the last row of the basis matrix are read during the decoding process does not change with the number of iterations or the scheduling method (that is, the order in which the non-zero elements of the last row of the basis matrix are read can remain fixed), which can reduce the hardware burden and reduce the complexity of decoding.

[0104] Furthermore, since the order in which the non-zero elements of the last row of the base matrix are read can remain fixed during the decoding process, multiple rows of the base matrix can be read simultaneously during the decoding process, which can reduce the decoding latency and thus improve communication performance.

[0105] Ninthly, this application provides a communication method that can be applied to a transmitting device, such as a transmitting device or a communication module and / or computing module within the transmitting device, or a circuit or chip in the transmitting device responsible for communication functions, or a circuit or chip in the transmitting device responsible for communication and / or computing functions (such as a GPU, AI processor, or ASIC), or a logic node, logic module, or software capable of implementing all or part of the functions of the transmitting device. Taking the application of this method to a transmitting device as an example, in this method, the transmitting device performs LDPC encoding on the information bit sequence according to the basis matrix to obtain an encoded bit sequence; and outputs the encoded bit sequence. The basis matrix includes the following non-zero elements (i, j), where i is the row number and j is the column number:

[0106] i=0, j=0, 1, 2, 3, 6, 9, 10, 11;

[0107] i=1, j=0, 3, 4, 5, 6, 7, 8, 9, 11, 12;

[0108] i=2, j=0, 1, 3, 4, 8, 10, 12, 13;

[0109] i=3, j=1, 2, 4, 5, 6, 7, 8, 9, 10, 13;

[0110] i=4, j=0, 1, 11, 14;

[0111] i=5,j=0,1,5,7,11,15;

[0112] i=6, j=0, 2, 3, 9, 11, 16.

[0113] All other elements in the above row are zero elements.

[0114] Based on the ninth aspect, the column index of the non-zero element in the 0th row of the basis matrix can include the column index of the non-zero element in the first column region of the 6th row of the basis matrix. By changing the connection relationship in the basis matrix, the 6th row of the basis matrix is ​​made orthogonal to the last row of the basis matrix, thereby improving the coding performance.

[0115] Furthermore, since the 0th row and the last row of the basis matrix are orthogonal, and the 6th row and the last row of the basis matrix are also orthogonal, the order in which the non-zero elements of the last row of the basis matrix are read remains unchanged regardless of the number of iterations or the scheduling method (i.e., the order in which the non-zero elements of the last row of the basis matrix are read can remain constant), thus improving communication reliability. Moreover, because the order in which the non-zero elements of the last row of the basis matrix are read remains constant, multiple rows of the basis matrix can be read simultaneously, thereby reducing communication latency and improving overall communication performance.

[0116] Tenthly, this application provides a communication method that can be applied to a receiving device, such as a receiving device or a communication module and / or computing module within the receiving device, or a circuit or chip in the receiving device responsible for communication functions, or a circuit or chip in the receiving device responsible for communication and / or computing functions (such as a GPU, AI processor, or ASIC), or a logic node, logic module, or software capable of implementing all or part of the functions of the receiving device. Taking the application of this method to a receiving device as an example, in this method, the receiving device receives information to be decoded; the information to be decoded is decoded according to a basis matrix to obtain a decoding result. The basis matrix includes the following non-zero elements (i, j), where i is the row number and j is the column number:

[0117] i=0, j=0, 1, 2, 3, 6, 9, 10, 11;

[0118] i=1, j=0, 3, 4, 5, 6, 7, 8, 9, 11, 12;

[0119] i=2, j=0, 1, 3, 4, 8, 10, 12, 13;

[0120] i=3, j=1, 2, 4, 5, 6, 7, 8, 9, 10, 13;

[0121] i=4, j=0, 1, 11, 14;

[0122] i=5,j=0,1,5,7,11,15;

[0123] i=6, j=0, 2, 3, 9, 11, 16.

[0124] All other elements in the above row are zero elements.

[0125] Based on the tenth aspect, the column index of the non-zero element in the 0th row of the basis matrix can include the column index of the non-zero element in the first column region of the 6th row of the basis matrix. By changing the connection relationship in the basis matrix, the 6th row of the basis matrix is ​​orthogonal to the last row of the basis matrix, thereby improving the decoding performance.

[0126] In addition, since the 0th row of the basis matrix is ​​orthogonal to the last row, and the 6th row of the basis matrix is ​​orthogonal to the last row of the basis matrix, the order in which the non-zero elements of the last row of the basis matrix are read during the decoding process does not change with the number of iterations or the scheduling method (that is, the order in which the non-zero elements of the last row of the basis matrix are read can remain fixed), which can reduce the hardware burden and reduce the complexity of decoding.

[0127] Furthermore, since the order in which the non-zero elements of the last row of the base matrix are read can remain fixed during the decoding process, multiple rows of the base matrix can be read simultaneously during the decoding process, which can reduce the decoding latency and thus improve communication performance.

[0128] In the eleventh aspect, this application provides a communication device that has the function of implementing any one of the first, third, fifth, seventh, and ninth aspects. For example, the communication device includes a module, unit, or means corresponding to the operation involved in any one of the first, third, fifth, seventh, and ninth aspects. The module, unit, or means can be implemented by software, hardware, or a combination of software and hardware.

[0129] In a twelfth aspect, this application provides a communication device that has the function of implementing any one of the second, fourth, sixth, eighth, and tenth aspects described above. For example, the communication device includes a module, unit, or means corresponding to the operation involved in any one of the second, fourth, sixth, eighth, and tenth aspects described above. The module, unit, or means can be implemented by software, hardware, or a combination of software and hardware.

[0130] In a thirteenth aspect, this application provides a communication device including an interface circuit and one or more processors. The one or more processors are coupled to a memory. The memory stores part or all of the computer program or instructions necessary to implement the functions described in the first aspect. The one or more processors can execute the computer program or instructions, which, when executed, cause the communication device to implement the methods in any possible design or implementation of any of the first, third, fifth, seventh, and ninth aspects. The interface circuit is used to implement communication functions within the communication device and / or communication functions between the communication device and other devices or components.

[0131] In one possible design, the communication device further includes one or more memories coupled to one or more processors, the memories used to store the aforementioned computer programs or instructions. In one possible implementation, the memories are located outside the communication device. In another possible implementation, the memories are located inside the communication device. In embodiments of this application, the processor and memory may also be integrated into a single device, i.e., the processor and memory may be integrated together. In one possible implementation, the communication device further includes a transceiver for receiving and / or transmitting information.

[0132] In one possible design, the communication device further includes one or more communication interfaces coupled to one or more processors, and the communication interfaces are used to communicate with other modules outside the communication device.

[0133] The aforementioned communication device may be a transmitting device, or a communication and / or computing module in a transmitting device, or a chip in a transmitting device that is responsible for communication functions, such as a modem chip (also known as a baseband chip) or a SoC or SIP chip containing a modem module, or a circuit or chip in a transmitting device that is responsible for communication and / or computing functions (such as a GPU, AI processor, or ASIC), or a logic node or logic module that can implement all or part of the functions of the transmitting device.

[0134] In a fourteenth aspect, this application provides a communication device including an interface circuit and one or more processors. The one or more processors are coupled to a memory. The memory stores part or all of the necessary computer program or instructions for implementing the functions described in the first aspect. The one or more processors can execute the computer program or instructions, which, when executed, cause the communication device to implement the methods in any possible design or implementation of any of the second, fourth, sixth, eighth, and tenth aspects described above. The interface circuit is used to implement communication functions within the communication device and / or communication functions between the communication device and other devices or components.

[0135] In one possible design, the communication device further includes one or more memories coupled to one or more processors, the memories used to store the aforementioned computer programs or instructions. In one possible implementation, the memories are located outside the communication device. In another possible implementation, the memories are located inside the communication device. In embodiments of this application, the processor and memory may also be integrated into a single device, i.e., the processor and memory may be integrated together. In one possible implementation, the communication device further includes a transceiver for receiving and / or transmitting information.

[0136] In one possible design, the communication device further includes one or more communication interfaces coupled to one or more processors, and the communication interfaces are used to communicate with other modules outside the communication device.

[0137] The aforementioned communication device may be a receiving device, or a communication and / or computing module in a receiving device, or a chip in a receiving device that is responsible for communication functions, such as a modem chip (also known as a baseband chip) or a SoC or SIP chip containing a modem module, or a circuit or chip in a receiving device that is responsible for communication and / or computing functions (such as a GPU, AI processor, or ASIC), or a logic node or logic module that can implement all or part of the functions of the receiving device.

[0138] In a fifteenth aspect, embodiments of this application provide a computer-readable storage medium storing computer instructions or programs that, when executed on a computer, cause the communication method described in any one of the first to tenth aspects to be performed.

[0139] In a sixteenth aspect, embodiments of this application provide a computer program product containing computer instructions that, when run on a computer, cause the communication method described in any one of the first to tenth aspects to be executed.

[0140] In a seventeenth aspect, embodiments of this application provide a computer program that, when run on a computer, causes the communication method described in any one of the first to tenth aspects to be executed.

[0141] In an eighteenth aspect, embodiments of this application provide a chip, including: a processor coupled to a memory for storing programs or instructions, wherein when the program or instructions are executed by the processor, a communication method as described in any one of the first to tenth aspects is executed.

[0142] The technical effects of any of the design methods in aspects eleven to eighteen can be found in the technical effects of any of the aspects one to ten mentioned above, and will not be elaborated upon further.

[0143] In a nineteenth aspect, embodiments of this application provide a communication system that may include communication means for performing the communication described in the first aspect or any possible design of the first aspect, and communication means for performing the communication described in the second aspect or any possible design of the second aspect; or, the communication system may include communication means for performing the communication described in the third aspect or any possible design of the third aspect, and communication means for performing the communication described in the fourth aspect or any possible design of the fourth aspect; or, the communication system may include communication means for performing the communication described in the fifth aspect or any possible design of the fifth aspect, and communication means for performing the communication described in the sixth aspect or any possible design of the sixth aspect; or, the communication system may include communication means for performing the communication described in the seventh aspect or any possible design of the seventh aspect, and communication means for performing the communication described in the eighth aspect or any possible design of the eighth aspect; or, the communication system may include communication means for performing the communication described in the ninth aspect or any possible design of the ninth aspect, and communication means for performing the communication described in the tenth aspect or any possible design of the tenth aspect. Attached Figure Description

[0144] Figure 1 is a schematic diagram of the structure of a basis matrix provided in an embodiment of this application;

[0145] Figure 2 is a schematic diagram of a verification matrix provided in an embodiment of this application;

[0146] Figure 3 is a schematic diagram of two adjacent rows of a basis matrix provided in an embodiment of this application;

[0147] Figure 4 is a schematic diagram of a scheduling base matrix provided in an embodiment of this application;

[0148] Figure 5 is a schematic diagram of reading the non-zero elements of the last row of a base matrix according to an embodiment of this application;

[0149] Figure 6 is a schematic diagram of a communication system provided in an embodiment of this application;

[0150] Figures 7 and 8 are schematic diagrams of the application framework provided in the embodiments of this application;

[0151] Figure 9 is a schematic diagram of encoding and decoding performed by a transmitting end device and a receiving end device according to an embodiment of this application;

[0152] Figure 10 is a flowchart illustrating a communication method provided in an embodiment of this application;

[0153] Figures 11 and 12 are schematic diagrams of reading the non-zero elements of the last row of the base matrix provided in the embodiments of this application;

[0154] Figure 13 is a schematic diagram of a simulation result provided by an embodiment of this application;

[0155] Figure 14 is a schematic diagram of a cyclic shift matrix provided in an embodiment of this application;

[0156] Figures 15–18 are schematic diagrams of the basis matrix provided in the embodiments of this application;

[0157] Figure 19 is a schematic diagram of the communication device provided in an embodiment of this application;

[0158] Figure 20 is a schematic diagram of the structure of a terminal device provided in an embodiment of this application. Detailed Implementation

[0159] Before describing the embodiments of this application, the technical terms involved in the embodiments of this application will be described.

[0160] LDPC codes: LDPC codes are a channel coding scheme that is very close to the Shannon limit. They have the characteristics of good coding performance and low complexity. They have been selected by the 3rd generation partnership project (3GPP) as the channel coding scheme for the 5th generation (5G) mobile communication system.

[0161] Among them, LDPC code decoding algorithms can be min-sum (MS) decoding and belief propagation (BP) decoding. BP decoding has better decoding performance, but it requires more information storage and has higher computational complexity, making it less suitable for hardware implementation. MS decoding has poorer decoding performance, but its computational complexity is lower and it is easier to implement in hardware. Therefore, in practical communication systems, offset MS decoding and normalized MS decoding algorithms are commonly used.

[0162] Among them, LDPC codes can achieve channel coding through generator matrices. The mainstream LDPC codes are quasi-cyclic (QC) structures, that is, by setting the shift amount of each block, bad structures such as short cycles can be avoided as much as possible, thereby improving the code distance.

[0163] The generator matrix of the QC-LDPC code can be determined by the basis matrix. For example, the transmitting device can determine the generator matrix based on the basis matrix (which can be denoted as H). BG The parity check matrix is ​​determined, and then the generator matrix can be determined based on the parity check matrix.

[0164] Basis Matrix: The basis matrix has a common basis matrix structure. For example, as shown in Figure 1, the basis matrix can include parts A, B, C, D, and E. Part A corresponds to information bits (or information digits, system bits, etc.), such as a high-bitrate information column region. Part B is a square matrix corresponding to core parity bits (or core parity bits). Core parity bits can be the parity bits corresponding to the highest bitrate (or can be described as a high-bitrate core parity region), or parity bits with a degree greater than or equal to 2, or parity bits corresponding to the row with the highest row weight (or a row weight significantly higher than other rows) (row weight is the number of 1s in a row). Part C can be a zero matrix, Part D can be the incremental redundancy region of the basis matrix (corresponding to a low-bitrate matrix), and Part E can be the extended parity region of the basis matrix. Part E can be used for hybrid automatic repeat request (HARQ). The degrees mentioned above can refer to the degree of variables or the degree of parity nodes; please refer to the description of degrees below.

[0165] Part B and Part E are both verification parts. Part B is defined as the core verification region. One possible feature is a non-lower triangular encoding part (i.e., the values ​​of elements above the diagonal are not all 0), or an encoding part with a column weight (the number of 1s in a column) greater than 1. Part E is defined as the extended verification region. One possible feature is a lower triangular encoding part (i.e., the values ​​of elements above the diagonal are all 0), or a diagonal matrix.

[0166] It is understandable that the columns of the base matrix can include information columns and check columns.

[0167] Among them, the information column corresponds to the information bit (or information bit, system bit, etc.), that is, the information column can be the column corresponding to part A.

[0168] In this context, the check column corresponds to the check bit (or check position, etc.). That is, the check column can be the column corresponding to part B and part C. The check column can include a core check column and extended check columns. The core check column can be the column corresponding to part B, and the extended check column can be the column corresponding to part C or part E. The extended check column can also be called a raptor-like region column. Alternatively, the core check column can be the check column in part B with a column weight greater than 1 (part B has 1 element above and below the diagonal), and the extended check column can be the remaining columns in the check column excluding the core check column.

[0169] In addition, the base matrix contains core columns, which can include all information columns and all core check columns. That is, core columns are the columns corresponding to high bitrate regions, or the columns corresponding to parts A and B. Similarly, the base matrix contains core rows, which can be the rows corresponding to the core check bits of the base matrix. That is, core rows are the rows corresponding to high bitrate regions, or the rows corresponding to parts A, B, or C. Likewise, the base matrix contains a kernel matrix, which is a matrix region composed of all core rows and all core columns of the base matrix. That is, the kernel matrix is ​​the high bitrate region of the base matrix, or the portion composed of parts A and B.

[0170] It is understood that the high bit rate in the embodiments can also be referred to as a higher bit rate, and the low bit rate can also be referred to as a lower bit rate.

[0171] In Figure 1, the area within the dashed box represents the punctured columns. The first two columns of the base matrix are also punctured columns, which have a relatively high column weight. During transmission, the punctured columns do not participate in the transmission process, but they are involved in both encoding and decoding.

[0172] The graph model of the basis matrix (which can be simply called the base graph (BG)) can be represented as: BG = (X, Y, F); where X corresponds to the variable, Y corresponds to the check equation associated with the variable, and F corresponds to the edge relationship between the variable and the check equation associated with the variable.

[0173] It is understandable that the elements in the basis matrix can be 0 or 1. A value of 0 represents an empty element, a value of 1 represents the relationship between the verification equation and the variable, or it can represent the connection of the basis graph.

[0174] The parity check matrix can be obtained by expanding the base matrix according to the expansion factor (which can be denoted as Zc). For example, the transmitting device can expand the 0s in the base matrix into a Zc×Zc all-zero matrix and expand the 1s in the base matrix into a Zc×Zc cyclic shift matrix to obtain the parity check matrix.

[0175] The expansion factor can also be called the boosting factor, expansion value, expansion coefficient, or boosting size, and there is no restriction on its usage.

[0176] The graph model of the verification matrix (which can be simply called the Tanner graph or a bipartite graph) can be represented as: G = (V, C, E), where V corresponds to the variable node, C corresponds to the verification node, and E corresponds to the edge relationship between the variable node and the verification node.

[0177] It is understandable that the number of columns N in the parity check matrix can be represented as: N = |V| = Zc|X|, the number of rows M in the parity check matrix can be represented as: M = |C| = Zc|Y|, and the number of non-zero elements in the parity check matrix is: |E| = Zc|F|. Here, |·| can be understood as the size of the set corresponding to (·). For example, in |V|, V can be understood as the set of columns in the parity check matrix, and |V| is the size of the set of columns in the parity check matrix.

[0178] For example, the common matrix structure of the parity check matrix can be as shown in Figure 2. The parity check matrix can include a high-rate region, an all-zero region, an incremental redundancy region, and a Lapt-like region. Specifically, the high-rate region can include parts A and B as shown in Figure 1; the all-zero region can include part C as shown in Figure 1, which is an all-zero matrix; the incremental redundancy region can include part D as shown in Figure 1; and the Lapt-like region can include part E as shown in Figure 1, which can be an identity matrix corresponding to the parity bits of the low-rate extension.

[0179] It is understandable that the aforementioned parity-check matrix and base matrix are designed according to the lowest possible bit rate (i.e., capable of encoding the information bit sequence at the lowest possible bit rate). When the bit rate changes, the upper left part of the parity-check matrix can be truncated for encoding (equivalent to truncating the upper left part of the base matrix for encoding). As the bit rate decreases, one or more rows, one or more columns (as shown by the dotted lines in Figure 2) can be added as matrix regions for encoding. For the base matrix, taking part A as an example with 22 information columns, part B with 4 core parity columns, and 2 punched columns, the bit rate supported by regions A and B can be 22 / (22+4-2)=11 / 12≈0.917.

[0180] In other words, the transmitting device can extract the first F rows and first G columns of the parity check matrix for encoding based on the bit rate. As the bit rate increases, the values ​​of F and G also increase. Here, F and G are both positive integers.

[0181] Based on the above description of LDPC codes, the transmitting device can encode the information bit sequence according to the basis matrix; correspondingly, the receiving device can decode the information to be decoded according to the basis matrix.

[0182] In this matrix, adjacent rows can be orthogonal (i.e., the intersection of the column indices of the non-zero elements in adjacent rows is an empty set). For example, adjacent rows in the basis matrix can be as shown in Figure 3(a), where the intersection of the column indices of the non-zero elements in the upper row and the lower row is an empty set. Alternatively, adjacent rows in the basis matrix can be quasi-orthogonal (i.e., the intersection of the column indices of the non-zero elements in adjacent rows, excluding the perforated columns, is an empty set). For example, adjacent rows in the basis matrix can be as shown in Figure 3(b), assuming the perforated columns are the first two columns of the basis matrix, where the intersection of the column indices of the non-zero elements in the upper row and the lower row, excluding the perforated columns, is an empty set.

[0183] The receiving device can perform decoding by sequentially scheduling the base matrix (i.e., decoding the rows of the base matrix sequentially) or by reversing the scheduling of the base matrix (i.e., reading the rows of the base matrix in reverse order). For example, the base matrix can be as shown in Figure 4. The receiving device can start from row 0 of the base matrix and sequentially decode each row (i.e., read rows 0, 1, 2, ..., 7). Furthermore, it can return to row 0 and repeat the sequential decoding until successful decoding. Alternatively, the receiving device can start from the last row of the base matrix and read each row in reverse order (i.e., read rows 7, 6, 5, ..., 0). Furthermore, it can return to the last row and repeat the reverse reading until successful decoding.

[0184] In this application, the row and column numbers of the matrix start from 0, merely for ease of explanation. For example, column number 0 represents the first column of the matrix, column number 1 represents the second column, row number 0 represents the first row, row number 1 represents the second row, and so on. It is understood that the row and column numbers can also start from 1, in which case the corresponding row and column numbers are increased by 1. For example, if the row or column numbers start from 1, then column number 1 represents the first column, column number 2 represents the second column, row number 1 represents the first row, row number 2 represents the second row, and so on.

[0185] Since adjacent rows in the basis matrix are orthogonal, the receiving device can read non-zero elements in different rows in the same order, thus allowing multiple rows of the basis matrix to be read simultaneously to reduce latency.

[0186] Optionally, the receiving device can schedule the base matrix in other orders. For example, the receiving device can first read some rows of the base matrix, and then read all rows of the base matrix. For instance, as shown in Figure 4, the receiving device can read rows 7, 6, and 5 of the base matrix, and then return to row 7 to repeat the reading; further, the receiving device can read rows 7, 6, 5, ..., 0 of the base matrix, and then return to row 7 to repeat the reading, until decoding is successful. Alternatively, the receiving device can read rows 4, 3, 2, 1, and 0 of the base matrix, and then return to row 5 to repeat the reading; further, the receiving device can read rows 7, 6, 5, ..., 0 of the base matrix, and then return to row 7 to repeat the reading, until decoding is successful. Alternatively, the receiving device can read rows 7, 6, and 5 of the base matrix, then return to row 7 and repeat the reading. At the same time, it can read rows 4, 3, 2, 1, and 0 of the base matrix, then return to row 4 and repeat the reading. Furthermore, the receiving device can read rows 7, 6, 5, ..., and 0 of the base matrix, then return to row 7 and repeat the reading.

[0187] During the process of the receiving device scheduling the base matrix in a different order, the order in which the receiving device reads the non-zero elements of one row of the base matrix may change. For example, when returning from row 0 to the last row of the base matrix, the reading order of the non-zero elements of the last row can be as shown in Figure 5(a); when returning from row 5 to the last row, the reading order of the non-zero elements of the last row can be as shown in Figure 5(b). That is, the 0th row and the last row of the base matrix are orthogonal, while the 5th row and the last row are not orthogonal, causing the reading order of the non-zero elements of the last row to change.

[0188] Since the order in which non-zero elements in a row of the basis matrix are read changes depending on the scheduling method, the receiving device needs to support multiple scheduling methods, which increases the hardware burden and the complexity of decoding.

[0189] Therefore, how to improve the basis matrix to enhance the decoding performance of LDPC codes while reducing hardware burden and decoding complexity has become an urgent problem to be solved.

[0190] This application provides a communication method, which includes: a transmitting device performing LDPC encoding on an information bit sequence according to a base matrix to obtain an encoded bit sequence; and outputting the encoded bit sequence. The base matrix includes a first row region and a second row region, and the intersection of the rows of the first row region and the second row region is an empty set; the first row region corresponds to a first code rate interval, and the second row region corresponds to a second code rate interval; or, the first row region corresponds to a non-orthogonal region in the base matrix, and the second row region corresponds to one or more of the following: a quasi-orthogonal region in the base matrix, or an orthogonal region in the base matrix; the first row region and the second row region satisfy any of the following conditions: the first condition or the second condition; the first condition is that the column index of the non-zero element in the p-th row of the first row region includes the column index of the non-zero element in the first column region of the first x rows of the second row region; the second condition is that the y-th column of the p-th row of the first row region is a zero element, there is at least one non-zero element in the y-th column of the first x rows of the second row region, and the y-th column of the other rows in the second row region other than the first x rows is a zero element; y is an integer less than the number of columns of the base matrix and greater than or equal to 0; p is an integer less than the number of rows of the first row region and greater than or equal to 0, and x is a positive integer less than or equal to the number of rows of the second row region.

[0191] In this embodiment, the base matrix may include a first row region and a second row region. Based on a first condition, the column index of the non-zero element in the p-th row of the first row region may include the column index of the non-zero element in the first column region of the first x rows of the second row region. By changing the edge relationships in the base matrix, any row of the first x rows of the second row region is orthogonal to the last row of the base matrix, thereby improving coding performance. Based on a second condition, the y-th column of the p-th row of the first row region is a zero element, there is at least one non-zero element in the y-th column of the first x rows of the second row region, and the y-th column of all rows other than the first x rows of the second row region is a zero element. By changing the edge relationships in the base matrix, any row of the first x rows of the second row region is orthogonal to the last row of the base matrix, thereby improving coding performance.

[0192] Furthermore, based on the first or second condition, since the 0th row of the basis matrix is ​​orthogonal to the last row, and any row in the first x rows of the second row region is orthogonal to the last row of the basis matrix, the order in which the non-zero elements of the last row of the basis matrix are read during the decoding process does not change with the number of iterations or the scheduling method (i.e., the order in which the non-zero elements of the last row of the basis matrix are read can remain fixed), which can reduce the hardware burden and the complexity of decoding; at the same time, it can improve the reliability of communication.

[0193] Furthermore, based on the first or second condition, since the order in which the non-zero elements of the last row of the base matrix are read can remain fixed during the decoding process, multiple rows of the base matrix can be read simultaneously during the decoding process, which can reduce the decoding waiting delay and communication latency, thereby improving communication performance.

[0194] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0195] The communication method provided in this application can be used in any communication system, such as a 3GPP communication system, for example, a long term evolution (LTE) system, a 5G mobile communication system (or a new radio (NR) communication system), a hybrid LTE and 5G network system, a vehicle-to-everything (V2X) system, a device-to-device (D2D) communication system, a machine-to-machine (M2M) communication system, an Internet of Things (IoT) system, a narrow band Internet of Things (NB-IoT) system, enhanced mobile broadband (eMBB), ultra-reliable and low-latency communication (URLLC), enhanced machine-type communication (eMTC), and various types of future communication systems. It can also be a non-terrestrial network (NTN) system (such as a satellite communication system), a non-3GPP communication system, etc., without limitation.

[0196] The communication system provided in the embodiments of this application will be described below with reference to Figure 6.

[0197] Figure 6 illustrates a possible, non-limiting system diagram. As shown in Figure 6, the communication system 10 includes a radio access network (RAN) 100 and a core network (CN) 200. RAN 100 includes at least one RAN node (110a and 110b in Figure 6, collectively referred to as 110) and at least one terminal (120a-120j in Figure 6, collectively referred to as 120). RAN 100 may also include other RAN nodes, such as wireless relay devices and / or wireless backhaul devices (not shown in Figure 6). Terminal 120 is wirelessly connected to RAN node 110. RAN node 110 is wirelessly or wired connected to core network 200. The core network equipment in core network 200 and RAN node 110 in RAN 100 can be different physical devices, or they can be the same physical device integrating core network logical functions and radio access network logical functions.

[0198] RAN 100 can be a 3GPP-related cellular system, such as a 4G or 5G mobile communication system, or a future-oriented evolution system. RAN 100 can also be an open RAN (O-RAN or ORAN), a cloud RAN (CRAN), a virtualized RAN (vRAN), an artificial intelligence radio access network (AI RAN), or a wireless fidelity (Wi-Fi) system. RAN 100 can also be a communication system that integrates two or more of the above systems.

[0199] RAN node 110, sometimes referred to as access network equipment, RAN entity, or access node, constitutes part of the communication system and assists terminals in achieving wireless access. Multiple RAN nodes 110 in communication system 10 can be of the same type or different types. In some scenarios, the roles of RAN node 110 and terminal 120 are relative. For example, network element 120i in Figure 6 can be a helicopter or drone, which can be configured as a mobile base station. For terminals 120j accessing RAN 100 through network element 120i, network element 120i is a base station; however, for base station 110a, network element 120i is a terminal. RAN node 110 and terminal 120 are sometimes both referred to as communication devices. For example, network elements 110a and 110b in Figure 6 can be understood as communication devices with base station functions, and network elements 120a-120j can be understood as communication devices with terminal functions.

[0200] In one possible scenario, the RAN node can be a base station, an evolved NodeB (eNodeB), an access point (AP), a transmission reception point (TRP), a next-generation NodeB (gNB), a base station in a future mobile communication system, or an access node in a Wi-Fi system. The RAN node can be a macro base station (as shown in Figure 6, 110a), a micro base station or indoor station (as shown in Figure 6, 110b), a relay node or donor node, or a radio controller in a CRAN scenario. Optionally, the RAN node can also be a server, wearable device, vehicle, or in-vehicle equipment. For example, the access network equipment in vehicle-to-everything (V2X) technology can be a roadside unit (RSU). All or part of the functions of the RAN node in this application can also be implemented through software functions running on hardware, or through virtualization functions instantiated on a platform (e.g., a cloud platform). The RAN node can also be equipped with communication modules, circuits, or chips that perform corresponding communication functions. The RAN node can also be configured with program instructions for performing corresponding communication functions, as well as corresponding program instructions. The RAN node in this application can also be a logical node, logical module, or software capable of implementing all or part of the access node's functions, or a circuit or chip (such as a GPU, AI processor, or ASIC) responsible for communication and / or computing functions within the access node.

[0201] In another possible scenario, multiple RAN nodes collaborate to assist terminals in achieving wireless access, with different RAN nodes implementing some of the base station's functions. For example, RAN nodes can be central units (CUs), distributed units (DUs), CU-control plane (CPs), CU-user plane (UPs), or radio units (RUs). CUs and DUs can be separate entities or included in the same network element, such as a baseband unit (BBU). RUs can be included in radio frequency equipment or radio frequency units, such as remote radio units (RRUs), active antenna units (AAUs), or remote radio heads (RRHs). Furthermore, RAN nodes can also be computing units, providing computational power for tasks such as model inference and / or model training, and can also be used to implement one or more of the following: task partitioning, scheduling, and orchestration. The functionality of a computing unit can be implemented by a separate module independent of other units (e.g., CU, DU, RU), or by one or more other units (e.g., one or more of CU, DU, RU).

[0202] In different systems, CU (or CU-CP and CU-UP), DU, computing unit, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an ORAN system, CU can also be called O-CU (open CU), DU can also be called O-DU, CU-CP can also be called O-CU-CP, CU-UP can also be called O-CU-UP, and RU can also be called O-RU. For ease of description, this application uses CU, CU-CP, CU-UP, DU, computing unit, and RU as examples. Any of the units among CU (or CU-CP, CU-UP), DU, computing unit, and RU in this application can be implemented through software modules, hardware modules, or a combination of software modules and hardware modules.

[0203] The terminal in Figure 6 can be a device with wireless transceiver capabilities or a chip or chip system that can be installed on the device. It can be used to access the aforementioned communication system and is a device or module with corresponding communication functions. The terminal device can also be called user equipment (UE), subscriber unit, terminal, mobile station (MS), or mobile terminal (MT), etc. Terminals can be widely used in various scenarios, such as device-to-device (D2D), vehicle-to-everything (V2X) communication, machine-type communication (MTC), Internet of Things (IoT), virtual reality, augmented reality, industrial control, autonomous driving, telemedicine, smart grids, smart furniture, smart offices, smart wearables, smart transportation, smart cities, etc. Terminals can be mobile phones, tablets, computers with wireless transceiver capabilities, wearable devices, vehicles, drones, helicopters, airplanes, ships, robots, robotic arms, smart home devices, transportation vehicles with wireless communication capabilities, communication modules, etc. The embodiments of this application do not limit the device form of the terminal. The terminal typically contains communication modules, circuits, or chips that perform corresponding communication functions. Furthermore, it may also contain modules, circuits, or chips (such as GPUs, AI processors, or ASICs) that perform corresponding communication and / or computing functions. The terminal can also be configured with program instructions for performing these communication and / or computing functions.

[0204] Optionally, in order to enable the above communication system to support AI technology, the above communication system may also introduce AI nodes.

[0205] The AI ​​node can be deployed in one or more of the following locations within the aforementioned communication system: RAN nodes (such as access network nodes), terminals, or core network equipment. Alternatively, the AI ​​node can be deployed independently, for example, in a location other than any of the aforementioned devices, such as in the host or cloud server of an over-the-top (OTT) system. The AI ​​node can communicate with other devices in the communication system, which can be one or more of the following: access network equipment, terminal equipment, or core network elements.

[0206] It is understood that this application does not limit the number of AI nodes. For example, when there are multiple AI nodes, these nodes can be divided based on function, such as different AI nodes being responsible for different functions.

[0207] It can also be understood that AI nodes can be independent devices, or they can be integrated into the same device to achieve different functions. Alternatively, they can be network elements in hardware devices, software functions running on dedicated hardware, or virtualization functions instantiated on a platform (e.g., a cloud platform). This application does not limit the specific form of the aforementioned AI nodes.

[0208] Optionally, the AI ​​node can be an AI network element or an AI module.

[0209] Figure 7 is a schematic diagram of a possible application framework in a communication system. As shown in Figure 7, network elements in the communication system are connected through interfaces (e.g., NG, Xn, or Fn) or air interfaces. For example, a terminal can connect to a RAN node through an air interface, a RAN node can connect to core network equipment through an NG interface, a CU in a RAN node can connect to a CU through an Xn interface, and a CU in a RAN node can connect to a DU through an Fn interface.

[0210] One or more AI modules are configured in one or more devices within a network element node (e.g., core network equipment, RAN node, terminal, or operations administration and maintenance (OAM)). (For clarity, only one is shown in Figure 7.) A RAN node can be a single RAN node or can include multiple RAN nodes, such as CUs and DUs. The CU and / or DU can also be configured with one or more AI modules. A CU can also be split into CU-CP and CU-UP, with one or more AI modules configured in the CU-CP and / or CU-UP.

[0211] AI modules are used to implement corresponding AI functions. AI modules deployed in different network elements can be the same or different. The models of AI modules can achieve different functions depending on the parameter configurations. The models of AI modules can be configured based on one or more of the following parameters: structural parameters (e.g., at least one of the following: number of neural network layers, neural network width, inter-layer connections, neuron weights, neuron activation function, or biases in the activation function), input parameters (e.g., the type and / or dimension of the input parameters), or output parameters (e.g., the type and / or dimension of the output parameters). The biases in the activation function can also be referred to as the biases of the neural network.

[0212] In one example, the neural network mentioned above can be a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), or a generative adversarial network (GAN).

[0213] Deep Neural Networks (DNNs) are artificial neural network architectures with multiple layers of nonlinear transformation units stacked in a hierarchical structure to form deep computational models. Compared to shallow neural networks, deep neural networks have more hidden layers, allowing the network model to capture more complex data structures and higher-level abstract features.

[0214] CNN is a type of deep neural network with convolutional structures. A CNN contains a feature extractor consisting of convolutional layers and subsampling layers. This feature extractor can be viewed as a filter, and the convolution process can be seen as performing convolution between a trainable filter and an input image or a convolutional feature map.

[0215] RNN is a type of recursive neural network that takes sequence data as input, recurses in the direction of sequence evolution, and connects all nodes (recurrent units) in a chain-like manner.

[0216] GAN is a deep learning model consisting of a generator and a discriminator, trained through adversarial learning. Its purpose is to estimate the potential distribution of data samples and generate new data samples.

[0217] An AI module can have one or more models. A model can infer an output, which includes one or more parameters. The learning, training, or inference processes of different models can be deployed on different nodes or devices, or they can be deployed on the same node or device.

[0218] Figure 8 illustrates another possible application framework in a communication system. As shown in Figure 8, the communication system includes a RAN intelligent controller (RIC). For example, the RIC can be the AI ​​module shown in Figure 7, used to implement AI-related functions. RICs include near-real-time RICs (near-RT RICs) and non-real-time RICs (non-RT RICs). Non-real-time RICs primarily process non-real-time information, such as data that is not sensitive to latency, with latency in the order of seconds. Real-time RICs primarily process near-real-time information, such as data that is relatively sensitive to latency, with latency in the order of tens of milliseconds.

[0219] Near real-time (NRT) RICs are used for model training and inference. For example, they are used to train AI models and then use those models for inference. NRT RICs can obtain network-side and / or terminal-side information from RAN nodes (e.g., CUs, CU-CPs, CU-UPs, DUs, compute nodes, and / or RUs) and / or terminals. This information can be used as training data or inference data. NRT RICs can deliver inference results to RAN nodes and / or terminals. Inference results can be exchanged between CUs and DUs, and / or between DUs and RUs. For example, a NRT RIC delivers an inference result to a DU, which then forwards it to an RU.

[0220] Non-real-time RICs are also used for model training and inference. For example, they are used to train AI models and then use those models for inference. Non-real-time RICs can obtain network-side and / or terminal-side information from RAN nodes (e.g., CUs, CU-CPs, CU-UPs, DUs, compute nodes, and / or RUs) and / or terminals. This information can be used as training data or inference data, and the inference results can be delivered to RAN nodes and / or terminals. Inference results can be exchanged between CUs and DUs, and / or between DUs and RUs; for example, a non-real-time RIC delivers inference results to a DU, which then forwards them to an RU.

[0221] Understandably, near real-time RICs and non-real-time RICs can be configured as separate network elements. Near real-time RICs and non-real-time RICs can also be part of other devices. For example, near real-time RICs can be set in RAN nodes (e.g., CU, DU, compute nodes), while non-real-time RICs can be set in OAM, cloud servers, core network devices, or other network devices.

[0222] Optionally, in this embodiment of the application, the transmitting device (or source) and the receiving device (or sink) can be encoded and decoded using the process shown in Figure 9 below. The transmitting device can be any terminal or RAN node in the communication system shown in Figure 6, and the receiving device can also be any terminal or RAN node in the communication system shown in Figure 6.

[0223] In this process, the transmitting device performs source coding on its generated bits to obtain a source bit stream. Then, it performs channel coding on the source bit stream, modulates it, and transmits the modulated symbols to the receiving device through a noisy channel. When the receiving device receives the modulated symbols through the noisy channel, it demodulates them, performs channel decoding to recover the source bit stream, and then performs source decoding to obtain the decoded result.

[0224] The actions, terms, etc., involved in the various embodiments of this application can be referenced interchangeably without limitation. The message names or parameter names in the messages exchanged between the various devices in the embodiments of this application are just examples, and other names may be used in specific implementations without limitation.

[0225] The communication method and apparatus will be further described below with reference to the accompanying drawings. It is understood that this application uses a transmitting device and a receiving device as examples to illustrate the execution of this interaction, but this application does not limit the execution entities of the interaction. For example, the method executed by the transmitting device in this application can also be implemented by a module (e.g., circuit, chip, or chip system) in the transmitting device, or a logic node, logic module, or software that can implement all or part of the functions of the transmitting device, or a circuit or chip (e.g., GPU, AI processor, or ASIC) in the transmitting device responsible for communication and / or computing functions. Similarly, the method executed by the receiving device in this application can also be implemented by a communication and / or computing module in the receiving device, or a circuit or chip (e.g., modem chip (also known as baseband chip), or a SoC chip / SIP chip containing a modem core, or GPU / AI processor / ASIC) in the receiving device responsible for communication and / or computing functions, or a logic node, logic module, or software that can implement all or part of the functions of the receiving device, or a circuit or chip (e.g., GPU, AI processor, or ASIC) in the receiving device responsible for communication and / or computing functions.

[0226] The communication method provided in the embodiments of this application will be described below with reference to the communication system shown in Figure 6 and Figure 10 below. The transmitting device can be any terminal device or network device in the communication system shown in Figure 6, and the receiving device can also be any terminal device or network device in the communication system shown in Figure 6.

[0227] It is understood that, in addition, "sending information" in this application can be understood as one device sending information to another device, or it can also be understood as one logic module within a device sending information to another logic module. For example, "sending device sending information" can be understood as the sending device sending information to the receiving device, or it can be understood as logic module 1 in the sending device sending information to logic module 2 in the sending device.

[0228] Similarly, in this application, "receiving information (such as information to be decoded)" can be understood as one device receiving information from another device, or it can also be understood as a logic module within a device receiving information from another logic module. For example, "receiving information by the receiving device" can be understood as the receiving device receiving information from the sending device, or it can be understood as logic module 1 in the receiving device receiving information from logic module 2 in the receiving device.

[0229] Furthermore, the phrase "sending information to... (e.g., a terminal)" in this application, or the related illustrations in the accompanying drawings, can be understood as the destination of the information being the terminal. This can include sending information directly or indirectly to the terminal. Similarly, "receiving information from... (e.g., a terminal)," "receiving information from... (e.g., a terminal)," or "receiving information sent (e.g., by a terminal)," or the related illustrations in the accompanying drawings, can be understood as the source of the information being the terminal, and can include receiving information directly or indirectly from the terminal. Information may undergo necessary processing between the source and destination, such as format changes, but the destination can understand the valid information from the source. Similar expressions in this application can be interpreted similarly, and will not be elaborated further here.

[0230] Figure 10 is a flowchart of a communication method provided in an embodiment of this application. As shown in Figure 10, the method may include:

[0231] Step 1001: The transmitting device performs LDPC encoding on the information bit sequence according to the base matrix to obtain the encoded bit sequence.

[0232] It is understandable that the encoding of information bit sequences based on the basis matrix in this application can be interpreted in at least the following ways:

[0233] (1) Encode the information bit sequence according to the base matrix T. At this time, the transmitting device can encode the information bit sequence according to the parity check matrix corresponding to the base matrix T; that is, the transmitting device determines the parity check matrix according to the base matrix T, and then encodes the information bit sequence according to the parity check matrix.

[0234] (2) Encode the information bit sequence according to T' obtained by transforming the base matrix T. Here, the base matrix T' is obtained by transforming the base matrix T. At this time, the transmitting device encodes the information bit sequence according to the parity check matrix corresponding to the base matrix T', that is, the transmitting device determines the parity check matrix according to the base matrix T', and then encodes the information bit sequence according to the parity check matrix.

[0235] For example, the basis matrix T' is obtained by performing row transformations on the basis matrix T, that is, by performing row swaps on the basis matrix T to obtain the basis matrix T'; or, the basis matrix T' is obtained by performing column transformations on the basis matrix T, that is, by performing column swaps on the basis matrix T to obtain the basis matrix T'; or, the basis matrix T' is obtained by performing both row and column transformations on the basis matrix T, that is, by performing both row and column swaps on the basis matrix T to obtain the basis matrix T'; this application does not impose any restrictions.

[0236] Wherein, the basis matrix T can be any basis matrix that satisfies the first condition or the second condition in this application, or it can be any basis matrix exemplified in this application (as shown in Figures 15-18), without limitation.

[0237] Specifically, the transmitting device can expand the base matrix according to the expansion factor (or it can be described as the transmitting device expanding the base matrix T according to the expansion factor, or it can be described as the transmitting device expanding the base matrix T' according to the expansion factor) to obtain the parity check matrix, and then perform LDPC encoding on the information bit sequence according to the parity check matrix to obtain the encoded bit sequence.

[0238] Alternatively, the transmitting device can extend the base matrix according to the extension factor (or it can be described as the transmitting device extending the base matrix T according to the extension factor, or it can be described as the transmitting device extending the base matrix T' according to the extension factor) to obtain the parity check matrix; further, the transmitting device can determine the generator matrix according to the parity check matrix, and then perform LDPC encoding on the information bit sequence according to the generator matrix to obtain the encoded bit sequence.

[0239] The generator matrix G and the parity check matrix H can satisfy the following formula: HG Τ =0; or, the generating matrix and the parity check matrix can satisfy the following formula: GH Τ =0.

[0240] The length of the information bit sequence can be K, where K is a positive integer. For example, the information bit sequence may include information bits and cyclic redundancy check (CRC) bits, where K can be the sum of the number of information bits and the number of CRC bits in the information bit sequence. Alternatively, the information bit sequence may include only the information bits themselves without CRC bits, where K can be the number of information bits.

[0241] The basis matrix includes a first row region and a second row region, and the intersection of the rows of the first row region and the second row region is an empty set.

[0242] Specifically, the first row region can include one or more rows of the basis matrix, and similarly, the second row region can include one or more rows of the basis matrix. The intersection of the row indices of the first row region and the row indices of the second row region in the basis matrix is ​​an empty set. For example, the first row region can include rows 0 to 4 of the basis matrix, and the second row region can include rows 5 to the last row of the basis matrix; or, taking a second row region with more than or equal to 12 rows as an example, the first row region can include rows 0 to 4 of the basis matrix, and the second row region can include rows 5 to 10 of the basis matrix.

[0243] It is understood that the transmitting device can divide the base matrix by rows to determine the first row region and the second row region. For details, please refer to the description of the first row region and the second row region below, which will not be repeated here. Furthermore, in this application, unless otherwise specified, any row region (such as the first row region or the second row region) can include either consecutive rows in the base matrix or discontinuous rows. Discontinuous rows can be understood as any two rows being completely discontinuous (i.e., completely discontinuous); or as at least two rows being partially discontinuous (i.e., partially discontinuous).

[0244] The first and second row regions satisfy either of the following conditions: either the first condition or the second condition:

[0245] The first condition is that the column index of the non-zero element in the p-th row of the first row region includes the column index of the non-zero element in the first column region of the first x rows of the second row region.

[0246] The second condition is that the p-th row and y-th column of the first row region is a zero element, there is at least one non-zero element in the y-th column of the first x rows of the second row region, and the y-th column of the other rows in the second row region excluding the first x rows is a zero element.

[0247] The first condition is described in detail below:

[0248] Where p is a positive integer less than the number of rows in the first row region and greater than or equal to 0. For example, if the number of rows in the first row region is 4, p can be 0; or p can be 1; or p can be 2; or p can be 3.

[0249] Optionally, the column index of the non-zero element in row 0 of the first row region includes the column index of the non-zero element in the first column region of the first x rows of the second row region.

[0250] In this application, the number of rows in any region (such as the first row region) can be understood as the number of rows included in that region; similarly, the number of columns in any region (such as the first row region) can be understood as the number of columns included in that region.

[0251] Where x is a positive integer less than or equal to the number of rows in the second row region. For example, if the number of rows in the second row region is 6, x can be 1 (corresponding to the 0th row of the second row region); or x can be 2 (corresponding to the 0th and 1st rows of the second row region); or x can be 3 (corresponding to the 0th to 2nd rows of the second row region); or x can be 4 (corresponding to the 0th to 3rd rows of the second row region); or x can be 5 (corresponding to the 0th to 4th rows of the second row region); or x can be 6 (corresponding to the 0th to 5th rows of the second row region).

[0252] Understandably, the sending device can dynamically determine the value of x based on the actual communication scenario, allowing the value of x to better meet communication needs. This improves coding performance while increasing the diversity and flexibility of x values. Furthermore, the rows of the basis matrix differ for different code rates, and x can be determined based on the code rate to ensure optimal coding performance for each code rate.

[0253] Furthermore, x can be 1, or x can be 2, or x can be 3. A smaller value for x can reduce the complexity of hardware implementation and simplify the implementation.

[0254] For example, taking p as 0 and x as 2, the column number of the non-zero element in the 0th row of the first row region can include the column number of the non-zero element in the first column region of the first 2 rows of the second row region. That is, the column number of the non-zero element in the 0th row of the first row region can include the column number of the non-zero element in the first column region of the 0th row of the second row region and the column number of the non-zero element in the first column region of the 1st row of the second row region.

[0255] The first column region may include one or more columns of the basis matrix. For details, please refer to the description of the first column region below, which will not be repeated here.

[0256] For example, taking the first column region as an example that includes the 0th to vth columns of the base matrix, the column index of the non-zero element in the first column region in the first x rows of the second row region can be understood as the column index of the non-zero element in the first v+1 columns of the first x rows of the second row region.

[0257] Optionally, the column number of the non-zero element in the p-th row of the first row region may include the column number of the non-zero element in the first column region of the 0-th row of the second row region, the column number of the non-zero element in the first column region of the 1-th row of the second row region, ..., the column number of the non-zero element in the first column region of the (x-1)-th row of the second row region.

[0258] Alternatively, it can be described as follows: the column index of the non-zero element in the first column of the 0th row of the second row region can be included in the column index of the non-zero element in the pth row of the first row region, which can be expressed by the formula: Where N2(0) is the column index of the non-zero element in the first column of the 0th row of the second row region, and N1(p) is the column index of the non-zero element in the pth row of the first row region; similarly, the column index of the non-zero element in the first column of the 1st row of the second row region can be included in the column index of the non-zero element in the pth row of the first row region, which can be expressed by the formula: Where N2(1) is the column index of the non-zero element in the first column region of the first row of the second row region; ...; Similarly, the column index of the non-zero element in the first column region of the (x-1)th row of the second row region can be included in the column index of the non-zero element in the pth row of the first row region, which can be expressed by the formula: Where N2(x-1) is the column index of the non-zero element in the first column region of the (x-1)th row of the second row region.

[0259] It is understandable that the sending device can determine the column indices of the non-zero elements in the first x rows of the second row based on the column indices of the non-zero elements in the p-th row of the first row, and thus determine the elements in the first x rows of the second row.

[0260] For example, taking the column indices of the non-zero elements in the p-th row of the first row region as 0, 1, 2, 3, 4, and 5 (that is, the elements in columns 0, 1, 2, 3, 4, and 5 of the p-th row of the first row region are all 1, and the elements in all columns except columns 0 to 5 of the p-th row of the first row region are all 0), assuming x is 2, and the first column region includes columns 0 to 5 of the base matrix, then it can be determined that one or more of the columns 0, 1, 2, 3, 4, and 5 of the 0th row of the second row region are... The elements of a column are 1. For example, the elements of columns 0, 1, and 2 in row 0 of the second row area are 1, and the elements of all columns in row 0 of the second row area except for columns 0, 1, and 2 are 0. Similarly, it can be determined that the elements of one or more columns in columns 0, 1, 2, 3, 4, and 5 of row 1 of the second row area are 1. For example, the elements of columns 1, 3, and 4 in row 1 of the second row area are 1, and the elements of all columns in row 1 of the second row area except for columns 1, 3, and 4 are 0.

[0261] In the second row region, the column numbers of the non-zero elements in any two rows can be the same or different, and this application does not impose any restrictions on this.

[0262] The second condition is described in detail below:

[0263] The second condition is that the p-th row and y-th column of the first row region is a zero element, there is at least one non-zero element in the y-th column of the first x rows of the second row region, and the y-th column of the other rows in the second row region excluding the first x rows is a zero element.

[0264] The descriptions of x and p above are not repeated here.

[0265] Where y is an integer less than the number of columns of the basis matrix and greater than or equal to 0.

[0266] The existence of at least one non-zero element in the y-th column of the first x rows of the second row region can be described as the existence of one or more rows in the second row region where the element in the y-th column is 0; or it can be described as the existence of at least one row in the second row region where the element in the y-th column is 0.

[0267] For example, the element in the y-th column of the 0th row of the second row region is 0; or, the element in the y-th column of the 1st row of the second row region is 0; or, the element in the y-th column of the 2nd row of the second row region is 0; ..., or, the element in the y-th column of the (x-1)th row of the second row region is 0.

[0268] For example, the elements in the y-th column of row 0 to row x-1 of the second row region are all 0; or, the elements in the y-th column of row 0 and row 1 of the second row region are all 0; or, the elements in the y-th column of row 0 and row x-1 of the second row region are all 0.

[0269] For example, taking a first row region comprising rows 0 to 4 of the base matrix and a second row region comprising rows 5 to 7 of the base matrix, assuming p = 0 and x = 1, then the y-th column of row 0 in the first row region is a zero element, the y-th column of row 0 in the second row region is a non-zero element, and the y-th column of all rows in the second row region except row 0 is a zero element. For instance, if y = 4, the element in the 4th column of row 5 of the base matrix can be 1, the element in the 4th column of row 0 of the base matrix can be 0, and the elements in the 4th columns of rows 6 and 7 of the base matrix can be 0.

[0270] Understandably, y can take one or more distinct values. Specifically, in the first row region, the y0th column of the p-th row is zero; in the second row region, the y0th column of the first x rows contains at least one non-zero element, and the y0th column of all rows except the first x rows in the second row region is zero; in the first row region, the y1th column of the p-th row is zero; in the second row region, the y1th column of the first x rows contains at least one non-zero element, and the y1th column of all rows except the first x rows in the second row region is zero; ... Here, y can be y0; or y can be y1, ...

[0271] Based on the description of the first and second conditions, the first and second row regions can satisfy either the first or the second condition, such that the 0th row of the basis matrix is ​​orthogonal to the last row, and any row in the first x rows of the second row region is orthogonal to the last row of the basis matrix, thereby improving coding performance.

[0272] Step 1002: The transmitting device outputs the encoded bit sequence; correspondingly, the receiving device receives the decoding information from the transmitting device.

[0273] Optionally, the transmitting device can perform rate matching on the encoded bit sequence to obtain a rate-matched bit sequence.

[0274] Optionally, the transmitting device can modulate the rate-matched bit sequence to obtain a modulated symbol sequence; or, the transmitting device can interleave the rate-matched bit sequence to obtain an interleaved bit sequence, and then modulate the interleaved bit sequence to obtain a modulated symbol sequence.

[0275] It is understandable that the modulation symbol sequence sent by the transmitting device to the receiving device may be affected by noise and other interference when transmitted through the channel. The demodulated information received by the receiving device is a modulation symbol sequence affected by noise and other interference.

[0276] Optionally, the receiving device can demodulate the information to be demodulated to obtain the information to be decoded.

[0277] Step 1003: The receiving device decodes the information to be decoded according to the base matrix to obtain the decoding result.

[0278] It is understandable that the decoding of information to be decoded based on the basis matrix in this application can be interpreted in at least the following ways:

[0279] (1) Decode the information to be decoded according to the base matrix T. For example, the receiving device can decode the information to be decoded by scheduling the base matrix T.

[0280] (2) Decode the information to be decoded based on T' obtained by transforming the basis matrix T. The basis matrix T' is obtained by transforming the basis matrix T. For example, the receiving device can decode the information to be decoded by scheduling the basis matrix T'.

[0281] Optionally, the receiving device can implement decoding using different scheduling methods. This application provides several possible embodiments:

[0282] In a first possible embodiment, the receiving device can schedule the base matrix for decoding in a sequential manner. For example, the receiving device can read row 0, row 1, row 2, ..., row Z-1 of the base matrix, and then return to row 0, repeating the sequential decoding of the base matrix. Here, Z is the row number of the base matrix.

[0283] In a second possible embodiment, the receiving device can schedule the base matrix for decoding in reverse order. For example, the receiving device can read the (Z-1)th row, (Z-2)th row, (Z-3)th row, ..., the 0th row of the base matrix, and then return to the (Z-1)th row of the base matrix, repeatedly reading the base matrix in reverse order.

[0284] In a third possible embodiment, the receiving device can decode a portion of the rows of the base matrix. For example, the receiving device can schedule the first row region and the second row region separately. For instance, the receiving device can read rows 0, 1, 2, ..., P-1 of the first row region, and then return to row 0 of the first row region, repeating the sequential decoding of the first row region; similarly, the receiving device can read rows 0, 1, 2, ..., X-1 of the second row region, and then return to row 0 of the second row region, repeating the sequential decoding of the second row region. For example, the receiving device can read rows P-1, P-2, P-3, ..., 0 of the first row area, and then return to row P-1 of the first row area, repeating the reverse reading of the first row area. Similarly, the receiving device can read rows X-1, X-2, X-3, ..., 0 of the second row area, and then return to row X-1 of the second row area, repeating the reverse reading of the second row area. Here, P is the row number of the first row area, and X is the row number of the second row area.

[0285] Based on the three possible implementations described above, the receiving device can schedule the base matrix in different scheduling orders to achieve decoding. Since the first row region and the second row region satisfy the first condition or the second condition, the 0th row of the base matrix can be orthogonal to the last row, and any row in the first x rows of the second row region can be orthogonal to the last row of the base matrix. Thus, no matter which scheduling order the receiving device adopts, the order in which the non-zero elements of the last row of the base matrix are read is fixed, which can reduce the hardware burden and reduce the complexity of decoding.

[0286] It is understood that the receiving device can determine the first line area and the second line area by referring to the description of the sending device in this application, which will not be repeated here.

[0287] Optionally, if the transmitting device interleaves the rate-matched bit sequence, the receiving device can deinterleave the information to be decoded to obtain a deinterleaved bit sequence, and then de-rate-match the deinterleaved bit sequence to obtain a de-rate-matched bit sequence; otherwise, the receiving device can de-rate-match the information to be decoded to obtain a de-rate-matched bit sequence.

[0288] Optionally, the receiving device can decode the rate-matched bit sequence based on the basis matrix to obtain the decoding result.

[0289] Based on the communication method shown in Figure 10, the base matrix can include a first row region and a second row region. Based on a first condition, the column index of the non-zero element in the p-th row of the first row region can include the column index of the non-zero element in the first column region of the first x rows of the second row region. By changing the edge relationships in the base matrix, any row of the first x rows of the second row region is orthogonal to the last row of the base matrix, thereby improving coding performance. Based on a second condition, the y-th column of the p-th row of the first row region is a zero element, at least one non-zero element exists in the y-th column of the first x rows of the second row region, and the y-th column of all rows other than the first x rows of the second row region is a zero element. By changing the edge relationships in the base matrix, any row of the first x rows of the second row region is orthogonal to the last row of the base matrix, thereby improving coding performance.

[0290] Furthermore, based on the first or second condition, since the 0th row of the basis matrix is ​​orthogonal to the last row, and any row in the first x rows of the second row region is orthogonal to the last row of the basis matrix, the order in which the non-zero elements of the last row of the basis matrix are read during the decoding process does not change with the number of iterations or the scheduling method (i.e., the order in which the non-zero elements of the last row of the basis matrix are read can remain fixed), which can reduce the hardware burden and the complexity of decoding; at the same time, it can improve the reliability of communication.

[0291] Furthermore, based on the first or second condition, since the order in which the non-zero elements of the last row of the base matrix are read can remain fixed during the decoding process, multiple rows of the base matrix can be read simultaneously during the decoding process, which can reduce the decoding waiting delay and communication latency, thereby improving communication performance.

[0292] Based on the description of the first and second row regions in Figure 10, the determination of the first and second row regions can refer to the following two possible designs:

[0293] In the first possible design, the transmitting device can determine the first and second row regions based on the bit rate. The first row region can correspond to a first bit rate interval, and the second row region can correspond to a second bit rate interval.

[0294] The minimum value of the first bitrate interval can be greater than or equal to the maximum value of the second bitrate interval. For example, the first bitrate interval can be [8 / 9, 9 / 10], and the second bitrate interval can be [3 / 4, 8 / 9].

[0295] Optionally, the minimum value of any bitrate interval can be associated with the row region corresponding to that bitrate interval. For example, the minimum value of the first bitrate interval can be associated with the maximum value of the row number corresponding to the first row region in the base matrix, or the minimum value of the second bitrate interval can be associated with the maximum value of the row number corresponding to the second row region in the base matrix.

[0296] The maximum value of the row number corresponding to the first (or second) row region in the base matrix can be understood as the row number corresponding to the last row of the first row region in the base matrix. For example, if the first row region includes rows 0 to P-1 of the base matrix, the maximum value of the row number corresponding to the first row region in the base matrix can be P-1.

[0297] In one example, taking the association between the minimum value of the first bit rate interval and the maximum value of the row number corresponding to the first row region in the base matrix as an example, the minimum value of the first bit rate interval is the ratio of the maximum number of information columns supported by the base matrix to the first difference. Here, the first difference is the difference between the first value and the number of punched columns in the base matrix, and the first value is the sum of the maximum number of information columns supported by the base matrix and the maximum value of the row number corresponding to the first row region in the base matrix.

[0298] For example, the minimum value of the first code rate interval and the row number of the first row region in the basis matrix can satisfy the following formula: Where R1 is the minimum value of the first code rate interval, row1 is the row number of the first row region in the basis matrix, kb is the maximum number of information columns supported by the basis matrix, and punc is the number of punched columns in the basis matrix.

[0299] In another example, taking the association between the minimum value of the second bitrate interval and the maximum value of the row number corresponding to the second row region in the base matrix as an example, the minimum value of the second bitrate interval is the ratio of the maximum number of information columns supported by the base matrix to the second difference. Here, the second difference is the difference between the second value and the number of punched columns in the base matrix, and the second value is the sum of the maximum number of information columns supported by the base matrix and the maximum value of the row number corresponding to the second row region in the base matrix.

[0300] For example, the minimum value of the second code rate interval and the row number of the second row region in the basis matrix can satisfy the following formula: Where R2 is the minimum value of the first code rate interval, and row2 is the row number of the first row region in the base matrix.

[0301] It is understood that the punched columns in this application are fixed punched columns in the base matrix, that is, the punched columns can be the first U columns with the largest column weight in the base matrix, where U is a positive integer. For example, the punched columns of the base matrix can be the first to second columns of the base matrix.

[0302] Column weight can be understood as the number of non-zero elements in a column of any region (such as the first row region, the second row region, or the basis matrix). For example, if the elements in column 0 of the first column region are [0 1 1 1 1 1 1], the column weight of column 0 can be 6. Similarly, row weight can be understood as the number of non-zero elements in a row of any region (such as the first row region, the second row region, or the basis matrix). For example, if the elements in row 0 of the first row region are [0 0 1 1 0 1 1], the row weight of column 0 can be 4.

[0303] In this context, the column U with the largest column weight in the base matrix can be understood as follows: If there exists a column U1 in the base matrix with the largest and equal column weight, then if U1 is greater than or equal to U, column U can be determined from this U1 column as the column U with the largest column weight in the base matrix. If U1 is less than U, the column weights of the base matrix can be arranged in descending order, and the columns corresponding to the first U column weights can be determined as the column U with the largest column weight in the base matrix. Therefore, any two columns in the column U with the largest column weight in the base matrix can have the same column weight, or at least two columns in the column U with the largest column weight in the base matrix can have different column weights, or any two columns in the column U with the largest column weight in the base matrix can have different column weights; there are no restrictions.

[0304] Based on the first possible design, this application provides two possible embodiments:

[0305] In a first possible embodiment, the first row region and the second row region can be continuous. For example, the first row region can include the 0th row to the (P-1th row)th row of the base matrix, and the first row region can correspond to the first code rate interval; the second row region can include the Pth row to the (P+X-1th row)th row of the base matrix, and the second row region can correspond to the second code rate interval.

[0306] In one example, P can be 3, or P can be 4, or P can be 5, or P can be 6.

[0307] In another example, P can be the sum of the row number of the core check region in the base matrix and t6, where t6 is an integer greater than or equal to 0. That is, the first row region includes row 0 to row P-1 of the base matrix (or it can be understood that the first row region can include the (t6-1)th row in parts A, B, C, D and E of Figure 1, i.e., the row number of parts A, B and C is P), and the second row region includes row P to the last row in the base matrix (or it can be described as the second row region can include the t6th row to the last row in parts D and E of Figure 1).

[0308] For example, t6 is an integer greater than or equal to 0. For example, t6 can be 1; or t6 can be 2.

[0309] It is understandable that the smaller the value of P, the fewer elements the first row region contains, the simpler the hardware implementation, and the less latency during decoding; the more elements the first row region contains, the larger the design space of the edge relationships of the basis matrix, which can make the degree distribution better and the decoding threshold better, thereby improving the decoding performance.

[0310] In a second possible embodiment, the first and second row regions can be determined according to the blocks of the base matrix. For example, the first row region may include parts A, B, and C in Figure 1, and the first row region may correspond to the first bit rate interval (at this time, the first bit rate interval can be replaced with the maximum bit rate supported by the base matrix); the second row region may include parts D and E in Figure 1, and the second row region may correspond to the second bit rate interval (at this time, the minimum value of the second bit rate interval can be the minimum bit rate supported by the base matrix, and the maximum value of the second bit rate interval can be less than the maximum bit rate supported by the base matrix).

[0311] In a second possible design, the transmitting device can determine the first and second row regions based on the orthogonality between rows in the basis matrix. The first row region can correspond to a non-orthogonal region in the basis matrix, and the second row region can correspond to one or more of the following: a quasi-orthogonal region in the basis matrix, or an orthogonal region in the basis matrix.

[0312] In the non-orthogonal regions of the basis matrix, there is no obvious orthogonality between adjacent rows. That is, the intersection of the column indices of adjacent rows in the non-orthogonal regions of the basis matrix may not be an empty set.

[0313] In the quasi-orthogonal region of the basis matrix, adjacent rows of columns other than the punched columns are completely orthogonal. That is, the intersection of the column indices of adjacent rows of columns other than the punched columns in the quasi-orthogonal region of the basis matrix is ​​an empty set.

[0314] In this case, adjacent rows in the orthogonal region of the basis matrix are completely orthogonal, meaning that the intersection of the column indices of adjacent rows in the orthogonal region of the basis matrix is ​​an empty set.

[0315] For example, the first row region may include some or all rows of the non-orthogonal region in the basis matrix, and the second row region may include some or all rows of the quasi-orthogonal region in the basis matrix; or, the first row region may include some or all rows of the non-orthogonal region in the basis matrix, and the second row region may include some or all rows of the orthogonal region in the basis matrix; or, the first row region may include some or all rows of the non-orthogonal region in the basis matrix, and the second row region may include some or all rows of the quasi-orthogonal region in the basis matrix, as well as some or all rows of the orthogonal region in the basis matrix.

[0316] Based on the two possible designs mentioned above, the transmitting device can determine the first and second row regions according to the code rate or the orthogonality between rows in the base matrix, so that the determined first and second row regions can better meet the communication requirements and improve the reliability of communication.

[0317] Optionally, the base matrix may include a third row in addition to the first and second row regions.

[0318] In one example, the first row region may include rows 0 to P-1 of the basis matrix, the second row region may include rows P to P+X-1 of the basis matrix, and the third row region may include rows P+X to the last row of the basis matrix.

[0319] In another example, the first row of regions can correspond to non-orthogonal regions in the basis matrix, the second row of regions can correspond to quasi-orthogonal regions in the basis matrix, and the third row of regions can correspond to orthogonal regions in the basis matrix. For example, the first row of regions can include some or all rows of non-orthogonal regions in the basis matrix, the second row of regions can include some or all rows of quasi-orthogonal regions in the basis matrix, and the third row of regions can include some or all rows of orthogonal regions in the basis matrix.

[0320] Among them, the first row area and the third row area can satisfy either the first condition or the second condition, or the second row area and the third row area can satisfy either the first condition or the second condition.

[0321] The first and third row regions satisfying the first or second condition can be referred to the above description of the first and second row regions satisfying the first or second condition; similarly, the second and third row regions satisfying the first or second condition can be referred to the above description of the first and second row regions satisfying the first or second condition, and will not be repeated here.

[0322] It is understandable that the basis matrix can also include the fourth row region, the fifth row region, and so on. For details, please refer to the description of the third row region, which will not be repeated here.

[0323] Based on the above description of the first row region and the second row region, the column index of the non-zero element in the p-th row of the first row region can include the column index of the non-zero element located in the first column region from the first x rows of the second row region. The first column region can include a portion of the columns of the base matrix. This application provides six possible embodiments for determining the first column region:

[0324] In one possible embodiment, the first column region may include the information column and the core verification column in the base matrix. Alternatively, the first column region may include parts A and B in Figure 1.

[0325] For example, taking the sum of the number of information columns and the number of core verification columns in the base matrix as t3, and the number of rows corresponding to the information columns (or core verification columns) as t4, the first column region can include columns 0 to t3-1 of the base matrix, and rows 0 to t4-1. Here, t3 and t4 are both positive integers.

[0326] In a second possible embodiment, the first column region may include information columns from the base matrix. Alternatively, it can be understood that the first column region may include part A in Figure 1.

[0327] For example, taking a base matrix with information column number t2 and corresponding row number t4, the first column region can include column 0 to column t2-1 and row 0 to row t4-1 of the base matrix. Here, t2 is a positive integer.

[0328] In a third possible embodiment, the first column region may include columns other than the punched columns in the base matrix. For example, taking columns 0 to 1 of the base matrix as the punched columns, the first column region may include columns 2 to the last column of the base matrix.

[0329] In a fourth possible embodiment, the first column region may include columns 0 to t0 of the base matrix, where t0 is a positive integer.

[0330] Optionally, t0 can be greater than or equal to a first threshold. The first threshold can be predefined, or it can be determined based on the actual communication scenario or situation, without restriction. For example, the first threshold can be 9; or, the first threshold can be 10.

[0331] For example, taking a first threshold of 10 as an example, the first column region may include columns 0 to 10 in the base matrix, or the first column region may include columns 0 to 11 in the base matrix, or the first column region may include columns 0 to 12 in the base matrix.

[0332] In a fifth possible embodiment, the first column region may include columns t1 to t2 of the base matrix, where t2 is the column number of the information column in the base matrix. Here, t1 is a positive integer.

[0333] Optionally, t1 can be greater than or equal to the second threshold. The second threshold can be predefined, or it can be determined based on the actual communication scenario or situation, without restriction. For example, the second threshold can be 2; or the first threshold can be 3.

[0334] For example, if the second threshold is 2, t1 can be 2, then the first column region can include the 2nd column to the t2nd column in the base matrix; or, t1 can be 3, then the first column region can include the 3rd column to the t2nd column in the base matrix; or, t1 can be 4, then the first column region can include the 4th column to the t2nd column in the base matrix.

[0335] In a sixth possible embodiment, the first column region may include columns t1 to t3 in the base matrix, where column t3 is the sum of the number of information columns and the number of core verification columns in the base matrix.

[0336] For example, if the second threshold is 2, t1 can be 2, then the first column region can include the 2nd to t3rd columns in the base matrix; or, t1 can be 3, then the first column region can include the 3rd to t3rd columns in the base matrix; or, t1 can be 4, then the first column region can include the 4th to t3rd columns in the base matrix.

[0337] Based on the six possible embodiments described above, the transmitting device can determine the first column region in one of the embodiments according to the actual communication scenario or communication situation to better meet communication requirements and thus improve communication performance. Furthermore, the fewer elements included in the first column region, the simpler the hardware implementation and the less latency during decoding; conversely, the more elements included in the first column region, the larger the design space for the edge relationships of the basis matrix, resulting in a better degree distribution and a better decoding threshold, thereby improving decoding performance.

[0338] Here, the degree can refer to the degree of a variable (i.e., the number of edges connecting the variable, or the number of check nodes connected to the variable), or the degree of the check equation (i.e., the number of edges connecting the check equation, or the number of variables connected to the check equation). For a variable, the more edges it has, the higher its degree, allowing it to obtain information from more check nodes and more accurately estimate the information to be decoded. For a check equation, the fewer edges it has, the lower its degree, and the more accurate the estimation of the variable's state. Therefore, the degree distribution can be determined jointly by the edges of the variable and the check equation to achieve a better degree distribution.

[0339] In this context, the degree of a variable can be understood as the row weight of the basis matrix, and the degree of the verification equation can be understood as the column weight of the basis matrix. Based on the above description of the basis matrix, this application provides two possible embodiments. The basis matrix may include a first row region and a second row region. Taking the first row region including rows 0 to 4 of the basis matrix and the second row region including rows 5 to 7 of the basis matrix as an example, assuming p is 0 and x is 1, the first column region includes columns 0 to 13 of the basis matrix, and the column number of the 0th row in the first row region can be {0, 1, 2, 3, 6, 9, 10, 11}.

[0340] In a first possible embodiment, the column number of the non-zero element in the 0th row of the first row region may include the column number of the non-zero element in the 0th row of the second row region located in the first column region. Then, the column number of the non-zero element in the 0th row of the second row region located in the first column region may be {0,1,2,3,6,9,11}.

[0341] For example, the column numbers of the non-zero elements in the 0th row of the second row region can be {0,1,2,3,6,9,11,13}. The element in the 13th column of the 0th row of the second row region is located in part E in Figure 1, and part E corresponds to the identity matrix.

[0342] In a first possible embodiment, taking the column numbers of the non-zero elements in the last row of the base matrix as {1,5,7,11,13,17} as an example, the receiving device can return to the last row of the base matrix from the 0th row of the first row region and read the non-zero elements of the last row of the base matrix in the following order as shown in Figure 11(a); the receiving device can return to the last row of the base matrix from the 0th row of the second row region and read the non-zero elements of the last row of the base matrix in the following order as shown in Figure 11(b). That is, the reading order of the non-zero elements of the last row of the base matrix can be the same based on different scheduling orders, thereby reducing the hardware burden and the complexity of decoding.

[0343] In the second possible embodiment, taking y as 5 as an example, the 5th column of the 0th row of the first row region is a zero element, the 5th column of the 0th row of the second row region has at least one non-zero element, and the 5th column of each row other than the 0th row of the second row region is a zero element.

[0344] In a second possible embodiment, taking the column numbers of the non-zero elements in the last row of the base matrix as {1,3,4,11,13,17} and the column numbers of the non-zero elements in the 0th row of the second row region as {0,1,5,7,11,15} as an example, the order in which the receiving device returns from the 0th row of the first row region to the last row of the base matrix and reads the non-zero elements of the last row of the base matrix can be as shown in Figure 12(a); the order in which the receiving device returns from the 0th row of the second row region to the last row of the base matrix and reads the non-zero elements of the last row of the base matrix can be as shown in Figure 12(b). That is, the order in which the non-zero elements of the last row of the base matrix are read can be the same based on different scheduling orders, thereby reducing the hardware burden and the complexity of decoding.

[0345] Optionally, the number of non-zero elements in the punched column of the base matrix can be a first preset value.

[0346] It is understandable that the elements in the punched columns of the base matrix can remain fixed. That is, the columns in the first and second rows, excluding the punched columns, can satisfy either the first or second condition mentioned above, which can reduce the impact on decoding performance.

[0347] Optionally, the row weight of the z-th row in the basis matrix is ​​Nz; where z = 0, 1, ..., Z-1, Z is the number of rows in the basis matrix, and Nz is a preset value.

[0348] For example, the row weight of the 0th row in the basis matrix can be N0, the row weight of the 1st row in the basis matrix can be N1, the row weight of the 2nd row in the basis matrix can be N2, ..., and the row weight of the Zth row in the basis matrix can be Nz.

[0349] It is understandable that the row weight of any column in the basis matrix can be fixed, which can keep the degree distribution in the basis matrix unchanged and make the decoding threshold better.

[0350] This application provides a simulation design, as shown in Figure 13. The horizontal axis represents the code rate, and the vertical axis represents the decoding complexity (or decoding delay). Curve 1 corresponds to the receiving device decoding the information to be decoded based on the basis matrix determined in this application (e.g., the basis matrix may include a first row region and a second row region, and the column index of the non-zero element in the 0th row of the first row region may include the column index of the non-zero element in the first column region of the 0th row of the second row region). Curve 2 corresponds to the receiving device decoding the information to be decoded based on the basis matrix corresponding to BG1 in 5G. As can be seen from Figure 13, for different code rates, the decoding complexity corresponding to Curve 1 is less than that of Curve 2; that is, the waiting delay for decoding corresponding to Curve 1 can be less than the waiting delay for decoding corresponding to Curve 2. In other words, the basis matrix determined in this application has a gain in complexity reduction compared to the basis matrix corresponding to BG1 in 5G.

[0351] In step 1001, the transmitting device can expand the base matrix according to the expansion factor to obtain the parity check matrix. For example, the expansion factor can be contained in an expansion factor list, as shown in Table 1. Different set indices in Table 1 correspond to different expansion factor sets, and each expansion factor set can include multiple expansion factors.

[0352] Table 1 List of expansion factors

[0353] Wherein, the set index i of the expansion factor set LS The corresponding element can be represented as a i It can be called the base. The set of natural numbers, The initial value is 1. For example, using set index i LS Taking 1 as an example, max(k1) is 7, k1∈{0,1,2,3,4,5,6,7}, a1=2, then the set index i LS The set of extended factors associated with 1 is {2, 4, 8, 16, 32, 64, 128, 256}. For example, using set index i... LS For example, if the value is 7, then max(k7) is 4, k7∈{0,1,2,3,4}, and a7=15, then the set index i LS The set of extended factors associated with 7 is {15,30,60,120,240}.

[0354] Specifically, the transmitting device can expand the 0s in the base matrix into a Zc×Zc all-zero matrix, and expand the 1s in the base matrix into a Zc×Zc cyclic shift matrix.

[0355] For example, the transmitting device can expand the 1 in the i-th row and j-th column of the base matrix into a Zc×Zc cyclic shift matrix, that is, it can cyclically shift the Zc×Zc identity matrix by P. i,j Next, P i,j SV is the shifting value (SV) corresponding to the i-th row and j-th column of the base matrix.

[0356] For example, taking a 4*4 identity matrix as an example, the result of shifting the identity matrix cyclically once can be shown in Figure 14(a), the result of shifting the identity matrix cyclically twice can be shown in Figure 14(b), the result of shifting the identity matrix cyclically three times can be shown in Figure 14(c), and the result of shifting the identity matrix cyclically 0 (or 4) times can be shown in Figure 14(d).

[0357] Optionally, the transmitting device can determine the set index (i.e., the index of the set containing the expansion factor) based on the determined expansion factor, and can expand the 1s in the basis matrix according to the translation value list corresponding to the determined set index. For example, the translation value lists corresponding to different set indices in the expansion factor list are different, and the translation value lists can be as shown in Table 2:

[0358] Table 2 lists the translation values ​​corresponding to set index 0.

[0359] Table 2 shows only the number of cyclic shifts corresponding to the elements in the first row of the base matrix.

[0360] For example, taking the set index of the expansion factor as 0, the 1 in the 1st row and 1st column of the base matrix can be expanded into a cyclic shift matrix of Zc×Zc, that is, the identity matrix of Zc×Zc can be cyclically shifted 250 times. The 1 in the 1st row and 2nd column of the base matrix can be expanded into a cyclic shift matrix of Zc×Zc, that is, the identity matrix of Zc×Zc can be cyclically shifted 69 times, ..., and the 1 in the 1st row and 24th column of the base matrix can be expanded into a cyclic shift matrix of Zc×Zc, that is, the identity matrix of Zc×Zc can be cyclically shifted 0 times.

[0361] For example, similar to the description in Release 15 of the 5G 3GPP standard, the basic code length *n* of LDPC encoding can be defined by the base matrix and the spreading factor *Zc*. When selecting the base matrix and spreading factor *Zc*, the choice between using the base matrix corresponding to BG1 or BG2 can be determined based on the transport block size and code rate conditions, ensuring that the encoded code length is as close as possible to the target code length. The target code length can be a preset value, such as 6144. Optionally, in this process, the spreading factor *Zc* can be determined from the aforementioned spreading factor list based on the number of information columns in the base matrix and the number of bits to be transmitted. Alternatively, the correspondence between the basic code length *n* and the spreading factor *Zc* and the transport block size and code rate conditions can be predefined.

[0362] It is understood that this application can be used to determine the base matrix, and the transmitting device can perform LDPC encoding based on the base matrix; correspondingly, the receiving device can perform decoding based on the base matrix, as shown in the communication method in Figure 10. The structure of the designed base matrix is ​​shown in Figures 15 to 18 below. To fully illustrate the design of the base matrix in the embodiments of this invention, it can be further explained by Tables 3-6 below.

[0363] As shown in Figure 15, the basis matrix can include a first row region and a second row region. The first row region can include rows 0 to 4 of the basis matrix and rows 5 to the last row of the second basis matrix. The column indices of the non-zero elements in row 0 of the first row region include the column indices of the non-zero elements in row 0 of the second row region located in the first column region (i.e., columns 0 to 13 of the basis matrix). The column indices of the non-zero elements in row 0 of the first row region (i.e., row 0 of the basis matrix) can be {0, 1, 2, 3, 6, 9, 10, 11}, and the column indices of the non-zero elements in row 0 of the second row region (i.e., row 5 of the basis matrix) can be {0, 1, 2, 6, 9, 15}. The non-zero elements in the basis matrix can be as shown in Table 3.

[0364] Table 3 Non-zero elements in the basis matrix

[0365] It is understandable that all elements in the basis matrix except those shown in Table 3 above are 0, or it can be described as all other elements in the above rows being zero elements.

[0366] As shown in Figure 16, the basis matrix can include a first row region and a second row region. The first row region can include rows 0 to 4 of the basis matrix and rows 5 to the last row of the second basis matrix. The column indices of the non-zero elements in row 0 of the first row region include the column indices of the non-zero elements in row 0 of the second row region located in the first column region (i.e., columns 0 to 13 of the basis matrix). The column indices of the non-zero elements in row 0 of the first row region (i.e., row 0 of the basis matrix) can be {0, 1, 2, 3, 6, 9, 10, 11}, and the column indices of the non-zero elements in row 0 of the second row region (i.e., row 5 of the basis matrix) can be {0, 1, 2, 6, 9, 11, 15}. The non-zero elements in the basis matrix can be as shown in Table 4.

[0367] Table 4 Non-zero elements in the basis matrix

[0368] It is understandable that all elements in the basis matrix except those shown in Table 4 above are 0, or it can be described as all other elements in the above rows being zero elements.

[0369] As shown in Figure 17, the basis matrix can include a first row region and a second row region. The first row region can include rows 0 to 5 of the basis matrix and rows 6 to the last row of the second basis matrix. The column indices of the non-zero elements in row 0 of the first row region include the column indices of the non-zero elements in row 0 of the second row region located in the first column region (i.e., columns 0 to 13 of the basis matrix). That is, the column indices of the non-zero elements in row 0 of the first row region (i.e., row 0 of the basis matrix) can be {0, 1, 2, 3, 6, 9, 10, 11}, and the column indices of the non-zero elements in row 0 of the second row region (i.e., row 6 of the basis matrix) can be {0, 6, 9, 11, 16}. The non-zero elements in the basis matrix can be as shown in Table 5.

[0370] Table 5 Non-zero elements in the basis matrix

[0371] It is understandable that all elements in the basis matrix except those shown in Table 5 above are 0, or it can be described as all other elements in the above rows being zero elements.

[0372] As shown in Figure 18, the basis matrix can include a first row region and a second row region. The first row region can include rows 0 to 5 of the basis matrix and rows 6 to the last row of the second basis matrix. The column indices of the non-zero elements in row 0 of the first row region include the column indices of the non-zero elements in row 0 of the second row region located in the first column region (i.e., columns 0 to 13 of the basis matrix). The column indices of the non-zero elements in row 0 of the first row region (i.e., row 0 of the basis matrix) can be {0, 1, 2, 3, 6, 9, 10, 11}, and the column indices of the non-zero elements in row 0 of the second row region (i.e., row 6 of the basis matrix) can be {0, 2, 3, 9, 11, 16}. The non-zero elements in the basis matrix can be as shown in Table 6.

[0373] Table 6 Non-zero elements in the basis matrix

[0374] It is understandable that all elements in the basis matrix except those shown in Table 6 above are 0, or it can be described as all other elements in the above rows being zero elements.

[0375] It is understandable that the basis matrices shown in Figures 15 to 18 can be the basis matrices corresponding to the basis graph 2.

[0376] The various embodiments of this application can be implemented independently or in combination, without limitation. Unless otherwise specified or in conflict of logic, the terminology and / or descriptions between the different embodiments provided in this application are consistent and can be referenced mutually. Technical features in different embodiments can be combined to form new embodiments based on their inherent logical relationships.

[0377] It is understood that in the embodiments of this application, the executing entity may perform some or all of the steps in the embodiments of this application. These steps or operations are merely examples, and the embodiments of this application may also perform other operations or variations thereof. Furthermore, the various steps may be executed in different orders as presented in the embodiments of this application, and it is not necessarily necessary to execute all the operations in the embodiments of this application.

[0378] The foregoing primarily describes the solutions provided in this application from the perspective of device-to-device interaction. It is understood that each device, in order to achieve the aforementioned functions, includes corresponding hardware structures and / or software modules for executing each function. Those skilled in the art will readily recognize that, based on the algorithmic steps of the examples described in conjunction with the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0379] This application embodiment can divide each device into functional modules according to the above method example. For example, each function can be divided into a separate functional module, or two or more functions can be integrated into one processing module. The integrated module can be implemented in hardware or as a software functional module. The module division in this application embodiment is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods.

[0380] With each functional module corresponding to a specific function, Figure 19 shows a possible exemplary block diagram of the communication device involved in the embodiments of this application. As shown in Figure 19, the communication device 1900 may include modules or units for implementing the methods described above. In one possible design, the communication device 1900 includes a processing unit 1902 and a communication unit 1903. Optionally, the communication device 1900 may also include a storage unit 1901 for storing device program code and / or data.

[0381] The communication device 1900 can be the transmitting end device in the above embodiments, such as the transmitting end device or the communication module in the transmitting end device, or the circuit or chip in the transmitting end device responsible for the communication function.

[0382] For example, the processing unit 1902 is used to perform LDPC encoding on the information bit sequence according to the basis matrix to obtain the encoded bit sequence; the communication unit 1903 is used to output the encoded bit sequence. The base matrix includes a first row region and a second row region, and the intersection of the rows of the first row region and the second row region is an empty set; the first row region corresponds to a first code rate interval, and the second row region corresponds to a second code rate interval; or, the first row region corresponds to a non-orthogonal region in the base matrix, and the second row region corresponds to one or more of the following: a quasi-orthogonal region in the base matrix, or an orthogonal region in the base matrix; the first row region and the second row region satisfy any of the following conditions: a first condition or a second condition; the first condition is that the column index of the non-zero element in the p-th row of the first row region includes the column index of the non-zero element in the first column region of the first x rows of the second row region; the second condition is that the y-th column of the p-th row of the first row region is a zero element, there is at least one non-zero element in the y-th column of the first x rows of the second row region, and the y-th column of the other rows of the second row region other than the first x rows is a zero element; y is a positive integer less than the number of columns of the base matrix; p is a positive integer less than the number of rows of the first row region.

[0383] In one possible design, when the communication device 1900 is a transmitting device or a communication module within a transmitting device, the function of the processing unit 1902 can be implemented by one or more processors. Specifically, the processor may include a modem chip, or a system-on-a-chip (SoC) chip or a SIP chip containing a modem core. The function of the communication unit 1903 can be implemented by transceiver circuitry.

[0384] In one possible design, when the communication device 1900 is a circuit or chip responsible for communication functions in a transmitting device, such as a modem chip or a system-on-a-chip (SoC) or SIP chip containing a modem core, the function of the processing unit 1902 can be implemented by a circuit system in the aforementioned chip that includes one or more processors or processor cores. The function of the communication unit 1903 can be implemented by interface circuitry or data transceiver circuitry on the aforementioned chip.

[0385] In one possible design, when the communication device 1900 is a transmitting device or a communication and / or computing module within a transmitting device, the functionality of the processing unit 1902 can be implemented by one or more processors. Specifically, the processor may include a GPU, or a system-on-a-chip (SoC) or SIP chip containing a GPU. Alternatively, the processor may include an AI processor, or a SoC or SIP chip containing an AI processor. Or, the processor may include an ASIC, or a SoC or SIP chip containing an ASIC. The functionality of the communication unit 1903 can be implemented by transceiver circuitry.

[0386] In one possible design, when the communication device 1900 is a circuit or chip in a transmitting device responsible for communication and / or computing functions, such as a GPU or a system-on-a-chip (SoC) or SIP chip containing a GPU, an AI processor or a SoC or SIP chip containing an AI processor, or an ASIC or a SoC or SIP chip containing an ASIC, the function of the processing unit 1902 can be implemented by a circuit system in the aforementioned chip that includes one or more processors or processor cores. The function of the communication unit 1903 can be implemented by interface circuitry or data transceiver circuitry on the aforementioned chip.

[0387] The communication device 1900 can be the receiving end device in the above embodiments, such as the receiving end device or the communication module in the receiving end device, or the circuit or chip in the receiving end device responsible for the communication function.

[0388] For example, the communication unit 1903 is used to receive the information to be decoded; the processing unit 1902 is used to decode the information to be decoded according to the basis matrix to obtain the decoding result. The base matrix includes a first row region and a second row region, and the intersection of the rows of the first row region and the second row region is an empty set; the first row region corresponds to a first code rate interval, and the second row region corresponds to a second code rate interval; or, the first row region corresponds to a non-orthogonal region in the base matrix, and the second row region corresponds to one or more of the following: a quasi-orthogonal region in the base matrix, or an orthogonal region in the base matrix; the first row region and the second row region satisfy any of the following conditions: the first condition or the second condition; the first condition is that the column index of the non-zero element in the p-th row of the first row region includes the column index of the non-zero element in the first column region of the first x rows of the second row region; the second condition is that the y-th column of the p-th row of the first row region is a zero element, there is at least one non-zero element in the y-th column of the first x rows of the second row region, and the y-th column of the other rows in the second row region other than the first x rows is a zero element; y is an integer less than the number of columns of the base matrix and greater than or equal to 0; p is an integer less than the number of rows of the first row region and greater than or equal to 0, and x is a positive integer less than or equal to the number of rows of the second row region.

[0389] In one possible design, when the communication device 1900 is a receiving device or a communication module within a receiving device, the function of the processing unit 1902 can be implemented by one or more processors. Specifically, the processor may include a modem chip, or a system-on-a-chip (SoC) or SIP chip containing a modem core. The function of the communication unit 1903 can be implemented by transceiver circuitry.

[0390] In one possible design, when the communication device 1900 is a circuit or chip responsible for communication functions in a receiving device, such as a modem chip or a system-on-a-chip (SoC) or SIP chip containing a modem core, the function of the processing unit 1902 can be implemented by a circuit system in the aforementioned chip that includes one or more processors or processor cores. The function of the communication unit 1903 can be implemented by interface circuitry or data transceiver circuitry on the aforementioned chip.

[0391] In one possible design, when the communication device 1900 is a receiving device or a communication and / or computing module within a receiving device, the functionality of the processing unit 1902 can be implemented by one or more processors. Specifically, the processor may include a GPU, or a system-on-a-chip (SoC) or SIP chip containing a GPU. Alternatively, the processor may include an AI processor, or a SoC or SIP chip containing an AI processor. Or, the processor may include an ASIC, or a SoC or SIP chip containing an ASIC. The functionality of the communication unit 1903 can be implemented by transceiver circuitry.

[0392] In one possible design, when the communication device 1900 is a circuit or chip in a receiving device responsible for communication and / or computing functions, such as a GPU or a system-on-a-chip (SoC) or SIP chip containing a GPU, an AI processor or a SoC or SIP chip containing an AI processor, or an ASIC or a SoC or SIP chip containing an ASIC, the function of the processing unit 1902 can be implemented by a circuit system in the aforementioned chip that includes one or more processors or processor cores. The function of the communication unit 1903 can be implemented by interface circuitry or data transceiver circuitry on the aforementioned chip.

[0393] It is understandable that the division of units in the above-mentioned device is merely a logical functional division. One function can correspond to one functional unit, or two or more functions can be integrated into one functional unit. In actual implementation, all or some units can be integrated into one physical entity, or they can be distributed across different physical entities. Furthermore, the above-mentioned functional units can be implemented in hardware, software, or a combination of both.

[0394] In one example, the functional unit in any of the above devices may be one or more integrated circuits configured to implement the above methods, such as: one or more ASICs, or one or more central processing units (CPUs), one or more microcontroller units (MCUs), one or more digital signal processors (DSPs), or one or more field programmable gate arrays (FPGAs), or a combination of at least two of these integrated circuit forms.

[0395] In one example, storage unit 1901 may include random access memory, flash memory, read-only memory, programmable read-only memory, or electrically erasable programmable memory and / or registers, etc.

[0396] This application embodiment also provides a schematic diagram of a terminal device, as shown in FIG20. The terminal device 2000 can correspond to the transmitting device shown in FIG10 and is used to implement the operation of the transmitting device in the above embodiments; or, the communication device 2000 can correspond to the receiving device shown in FIG10 and is used to implement the operation of the receiving device in the above embodiments. As shown in FIG20, the communication device includes: one or more antennas 2010, a radio frequency processing system 2020, and a processor system 2030.

[0397] The processor system 2030 can process the information from the communication device and send it to the radio frequency (RF) processing system 2020. The RF processing system 2020 processes the signal and then transmits it through the antenna 2010. Alternatively, the RF processing system 2020 can receive RF signals through the antenna 2010 and send the processed signals to the processor system 2030 for further processing.

[0398] In one example, the radio frequency (RF) processing system 2020 serves as the communication interface for external communication of the communication device and may include an RF front end (RFFE) 2021 and an RF transceiver 2022. The RFFE 2021 is primarily used for one or more processing operations, such as shaping, passband selection, or gain adjustment, on the RF signals received by the antenna or those to be transmitted through the antenna. It may include one or more components such as RF switches, duplexers, filters, power amplifiers, antenna tuners, and low-noise amplifiers. The RFFE 2021 can be a circuit system composed of multiple discrete components or integrated into one or more chips. The RF transceiver 2022 processes the RF signals received by the RFFE 2021 into baseband / IF signals for further processing by the processor system 2030, and processes the baseband / IF signals provided by the processor system 2030 into RF signals for transmission to the RFFE 2021. The baseband / IF signals transmitted between the RF transceiver 2022 and the processor system 2030 can be digital or analog signals. An RF transceiver 2022 can be implemented by one or more chips, which are commonly referred to as RF ICs.

[0399] In another example, processor system 2030 may include one or more processors for processing signals and executing one or more communication protocols. Optionally, processor system 2030 may also include memory 2036. In one example, the one or more processors include at least one baseband processor 2031 (also known as a modem processor). Memory 2036 is used to store data and / or computer program instructions. Optionally, processor system 2030 may also include one or more application processors 2032 for implementing processing of the communication device's operating system and application layer. Application processor 2032 may include, for example, a GPU, AI processor, or ASIC. Optionally, processor system 2030 may also include one or more of a voice subsystem 2033, a multimedia subsystem 2034, or an interface circuit 2035. The voice subsystem 2033 is used to process voice signals, the multimedia subsystem 2034 is used to handle multimedia-related operations, such as video encoding / decoding, image processing, etc., and the interface circuit 2035 is used to implement communication with other communication device components, such as a display 2040, an input device 2050, memory 2060, etc. The aforementioned components in the processor system 2030 can communicate with each other via a bus or communication interface circuit.

[0400] In another example, the processor system 2030 can be packaged as a single processor chip, such as a SoC chip or a SIP chip. In one example, the processor system 2030 can be a system composed of multiple chips; for example, the baseband processor 2031 can be packaged as a single chip, or packaged with part or all of the circuitry of the radio frequency processing system into a single chip.

[0401] In another example, memory 2036 can be on-chip memory, i.e., located on the processor system 2030 chip. In one example, memory 2060 can be off-chip memory, i.e., located outside the processor system 2030 chip.

[0402] In another example, the baseband processor 2031 may include one or more processor cores 20311 and interface circuitry 20314. The one or more processor cores 20311 are used to process signals and execute one or more communication protocols. Optionally, the baseband processor 2031 may also include a memory 20312 for storing at least a portion of the corresponding computer program instructions and / or data. In one example, the one or more processor cores 20311 execute the computer program instructions stored in the memory 20312 to perform the relevant operations in the above method embodiments (such as encoding information bit sequences or decoding information to be decoded). In this disclosure, memory 20312 is used to store corresponding computer program instructions and / or data. This can mean that memory 20312 stores all corresponding computer program instructions and / or data for execution by processor core 20311; or it can mean that memory 20312 stores a portion of corresponding computer program instructions and / or data, including the computer program instructions and / or data currently required to be executed by processor core 20311. Memory 20312 can store different portions of computer program instructions and / or data multiple times for execution by processor core 20311 to implement the relevant operations in the above method embodiments. Interface circuit 20314 serves as a communication interface for communication with other components, such as transmitting signals with radio frequency processing system 2020, communicating with other subsystems and related components of processor system 2030 via bus, such as transmitting data control signals with application processor 2032, and transmitting data or computer program instructions with memory 2036 or memory 2060. Optionally, in order to reduce the load on the processor core, a baseband signal processing circuit 20313 can be set to perform at least some baseband signal processing, including one or more of signal demodulation, modulation, encoding or decoding.

[0403] In another example, the communication device provided in this application may be a communication device 2000, including a communication module comprising a processor system 2030 and a radio frequency system 2020, or a baseband processor 2031.

[0404] The processor, processor system, application processor, baseband processor, processor circuit or processor core mentioned above can be collectively referred to as a processor. The processor may include one or more of the following: CPU, DSP, microprocessor unit (MPU), MCU, GPU, FPGA, ASIC, AI processor or neural processing unit (NPU).

[0405] The aforementioned memory may include one or more of the following storage media: random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), phase-change memory (PCM), resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), cache, register, read-only memory (ROM), flash memory, erasable programmable read-only memory (EPROM), hard disk, etc. For example, computer program instructions for executing the above embodiments may be stored on non-volatile memory, such as at least a portion of the aforementioned memory 2060 (e.g., one or more of ROM, flash memory, EPROM, or hard disk). When the communication device is running, the corresponding computer program instructions may be partially or wholly loaded onto a memory with a faster transmission speed than the processor, such as at least a portion of memory 2036 and / or memory 20312 (e.g., one or more of RAM, SRAM, DRAM, PCM, ReRAM, MRAM, FRAM, cache, or register), for the processor to execute in order to implement the steps in the above method embodiments.

[0406] It is understandable that the RF transceiver 2022 and the RF front-end 2021 can also be packaged in a single chip. Alternatively, the RF transceiver 2022, the RF front-end 2021, and the baseband processor 2031 can also be packaged in a single chip.

[0407] This application also provides a computer program product that, when executed by a computer, can implement the functions of any of the above method embodiments.

[0408] This application also provides a computer program that, when executed by a computer, can implement the functions of any of the above method embodiments.

[0409] This application also provides a computer-readable storage medium. All or part of the processes in the above method embodiments can be implemented by a computer program instructing related hardware. This program can be stored in the computer-readable storage medium, and when executed, it can include the processes of the above method embodiments. The computer-readable storage medium can be an internal storage unit of the communication device (including a data transmitter and / or a data receiver) of any of the foregoing embodiments, such as the hard disk or memory of the communication device. The computer-readable storage medium can also be an external storage device of the communication device, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc., equipped on the communication device. Further, the computer-readable storage medium can include both internal storage units and external storage devices of the communication device. The computer-readable storage medium is used to store the computer program and other programs and data required by the communication device. The computer-readable storage medium can also be used to temporarily store data that has been output or will be output.

[0410] The terms "system" and "network" in this application embodiment are used interchangeably. "At least one" refers to one or more, and "multiple" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, "at least one of A, B, or C" includes A, B, C, AB, AC, BC, or ABC; "at least one of A, B, and C" can also be understood as including A, B, C, AB, AC, BC, or ABC. Furthermore, unless otherwise specified, the ordinal numbers such as "first" and "second" mentioned in this application embodiment are used to distinguish multiple objects and are not used to limit the order, sequence, priority, or importance of multiple objects.

[0411] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, etc.) containing computer-usable program code.

[0412] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or one or more blocks of the block diagrams.

[0413] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0414] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

Claims

1. A communication method, characterized in that, include: The information bit sequence is encoded by low-density parity-check (LDPC) encoding based on the basis matrix to obtain the encoded bit sequence. Output the encoded bit sequence; The basis matrix includes a first row region and a second row region, and the intersection of the rows of the first row region and the second row region is an empty set. The first row region corresponds to a first code rate interval, and the second row region corresponds to a second code rate interval; or, the first row region corresponds to a non-orthogonal region in the base matrix, and the second row region corresponds to one or more of the following: a quasi-orthogonal region in the base matrix, or an orthogonal region in the base matrix. The first row region and the second row region satisfy either of the following conditions: the first condition or the second condition; The first condition is that the column index of the non-zero element in the p-th row of the first row region includes the column index of the non-zero element in the first column region in the first x rows of the second row region; The second condition is that the p-th row and y-th column of the first row region is a zero element, there is at least one non-zero element in the first x rows and y-th column of the second row region, and the y-th column of the other rows in the second row region excluding the first x rows is a zero element. y is an integer less than the number of columns of the base matrix and greater than or equal to 0; p is an integer less than the number of rows in the first row region and greater than or equal to 0; and x is a positive integer less than or equal to the number of rows in the second row region.

2. A communication method, characterized in that, include: Receive the information to be decoded; The information to be decoded is decoded according to the basis matrix to obtain the decoding result; The basis matrix includes a first row region and a second row region, and the intersection of the rows of the first row region and the second row region is an empty set. The first row region corresponds to a first code rate interval, and the second row region corresponds to a second code rate interval; or, the first row region corresponds to a non-orthogonal region in the base matrix, and the second row region corresponds to one or more of the following: a quasi-orthogonal region in the base matrix, or an orthogonal region in the base matrix. The first row region and the second row region satisfy either of the following conditions: the first condition or the second condition; The first condition is that the column index of the non-zero element in the p-th row of the first row region includes the column index of the non-zero element in the first column region in the first x rows of the second row region; The second condition is that the p-th row and y-th column of the first row region is a zero element, there is at least one non-zero element in the first x rows and y-th column of the second row region, and the y-th column of the other rows in the second row region excluding the first x rows is a zero element. y is an integer less than or equal to the number of columns of the base matrix and greater than or equal to 0; p is an integer less than or equal to the number of rows in the first row region and greater than or equal to 0; and x is a positive integer less than or equal to the number of rows in the second row region.

3. The method according to claim 1 or 2, characterized in that, The first column region includes the information columns in the base matrix and the core verification columns; or The first column region includes the information columns in the base matrix; or The first column region includes all columns in the base matrix except for the punched columns; or The first column region includes columns 0 to t0 of the base matrix, where t0 is greater than or equal to a first threshold; or The first column region includes columns t1 to t2 of the base matrix, where t2 is the column number of the information column in the base matrix; or The first column region includes columns t1 to t3 in the base matrix, where column t3 is the sum of the number of information columns and the number of core verification columns in the base matrix; Wherein, t1 is greater than or equal to the second threshold.

4. The method according to any one of claims 1-3, characterized in that, The value of p is 0.

5. The method according to any one of claims 1-4, characterized in that, The x is 1; or The x is 2; or The value of x is 3.

6. The method according to any one of claims 1-5, characterized in that, The first row area and the second row area are continuous.

7. The method according to any one of claims 1-6, characterized in that, The first row region includes rows 0 to P-1 of the base matrix, and the second row region includes rows P to the last row of the base matrix; wherein, P is the sum of the row number of the core verification region in the base matrix and t6, and t6 is an integer greater than or equal to 0.

8. The method according to claim 7, characterized in that, The t6 is 0; or The t6 is 1; or The value of t6 is 2.

9. The method according to any one of claims 1-8, characterized in that, The maximum value of the row number corresponding to the first row region in the base matrix is ​​associated with the minimum value of the first code rate interval; wherein, the minimum value of the first code rate interval is the ratio of the maximum number of information columns supported by the base matrix to the first difference; the first difference is the difference between the first value and the number of punched columns of the base matrix, and the first value is the sum of the maximum number of information columns supported by the base matrix and the maximum value of the row number corresponding to the first row region in the base matrix.

10. The method according to any one of claims 1-9, characterized in that, The maximum value of the row number corresponding to the second row region in the base matrix is ​​associated with the minimum value of the second code rate interval; wherein, the minimum value of the second code rate interval is the ratio of the maximum number of information columns supported by the base matrix to the second difference; the second difference is the difference between the second value and the number of punched columns of the base matrix, and the second value is the sum of the maximum number of information columns supported by the base matrix and the maximum value of the row number corresponding to the second row region in the base matrix.

11. A communication method, characterized in that, include: The information bit sequence is encoded using low-density parity-check (LDPC) encoding based on the basis matrix to obtain the encoded bit sequence; the encoded bit sequence is then output. or Receive the information to be decoded; The information to be decoded is decoded based on the basis matrix to obtain the decoding result; The basis matrix includes the following non-zero elements (i, j), where i is the row number and j is the column number: i=0, j=0, 1, 2, 3, 6, 9, 10, 11; i=1, j=0, 3, 4, 5, 6, 7, 8, 9, 11, 12; i=2, j=0, 1, 3, 4, 8, 10, 12, 13; i=3, j=1, 2, 4, 5, 6, 7, 8, 9, 10, 13; i=4, j=0, 1, 11, 14; i=5, j=0, 1, 2, 6, 9, 15; All other elements in the above row are zero elements.

12. A communication method, characterized in that, include: The information bit sequence is encoded using low-density parity-check (LDPC) encoding based on the basis matrix to obtain the encoded bit sequence; the encoded bit sequence is then output. or Receive the information to be decoded; The information to be decoded is decoded based on the basis matrix to obtain the decoding result; The basis matrix includes the following non-zero elements (i, j), where i is the row number and j is the column number: i=0, j=0, 1, 2, 3, 6, 9, 10, 11; i=1, j=0, 3, 4, 5, 6, 7, 8, 9, 11, 12; i=2, j=0, 1, 3, 4, 8, 10, 12, 13; i=3, j=1, 2, 4, 5, 6, 7, 8, 9, 10, 13; i=4, j=0, 1, 11, 14; i=5, j=0, 1, 2, 6, 9, 11, 15; All other elements in the above row are zero elements.

13. A communication method, characterized in that, include: The information bit sequence is encoded using low-density parity-check (LDPC) encoding based on the basis matrix to obtain the encoded bit sequence; the encoded bit sequence is then output. or Receive the information to be decoded; The information to be decoded is decoded based on the basis matrix to obtain the decoding result; The basis matrix includes the following non-zero elements (i, j), where i is the row number and j is the column number: i=0, j=0, 1, 2, 3, 6, 9, 10, 11; i=1, j=0, 3, 4, 5, 6, 7, 8, 9, 11, 12; i=2, j=0, 1, 3, 4, 8, 10, 12, 13; i=3, j=1, 2, 4, 5, 6, 7, 8, 9, 10, 13; i=4, j=0, 1, 11, 14; i=5,j=0,1,5,7,11,15; i=6, j=0, 6, 9, 11, 16; All other elements in the above row are zero elements.

14. A communication method, characterized in that, include: The information bit sequence is encoded using low-density parity-check (LDPC) encoding based on the basis matrix to obtain the encoded bit sequence; the encoded bit sequence is then output. or Receive the information to be decoded; The information to be decoded is decoded based on the basis matrix to obtain the decoding result; The basis matrix includes the following non-zero elements (i, j), where i is the row number and j is the column number: i=0, j=0, 1, 2, 3, 6, 9, 10, 11; i=1, j=0, 3, 4, 5, 6, 7, 8, 9, 11, 12; i=2, j=0, 1, 3, 4, 8, 10, 12, 13; i=3, j=1, 2, 4, 5, 6, 7, 8, 9, 10, 13; i=4, j=0, 1, 11, 14; i=5,j=0,1,5,7,11,15; i=6, j=0, 2, 3, 9, 11, 16; All other elements in the above row are zero elements.

15. A communication device, characterized in that, The communication device includes a unit for performing the communication method as described in any one of claims 1, 3-10, or includes a unit for performing the communication method as described in any one of claims 2-10, or includes a unit for performing the communication method as described in claim 11, or includes a unit for performing the communication method as described in claim 12, or includes a unit for performing the communication method as described in claim 13, or includes a unit for performing the communication method as described in claim 14.

16. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions or programs that, when executed, cause the communication method as described in any one of claims 1, 3-10, or any one of claims 2-10, or the communication method as described in claim 11, or the communication method as described in claim 12, or the communication method as described in claim 13, or the communication method as described in claim 14 to be executed.

17. A computer program product, characterized in that, The computer program product includes computer instructions; when some or all of the computer instructions are executed, the communication method as described in any one of claims 1, 3-10 is executed, or the communication method as described in any one of claims 2-10 is executed, or the communication method as described in claim 11 is executed, or the communication method as described in claim 12 is executed, or the communication method as described in claim 13 is executed, or the communication method as described in claim 14 is executed.

18. A communication device, characterized in that, The device includes one or more processors and interface circuitry, wherein the one or more processors are coupled to a memory for storing computer programs or instructions that, when executed by the one or more processors, cause the device to perform the method as claimed in any one of claims 1, 3-10, or any one of claims 2-10, or any one of claims 11, or any one of claims 12, or any one of claims 13, or any one of claims 14.

19. The apparatus according to claim 18, characterized in that, The interface circuit is used to implement communication functions within the device and / or communication functions between the device and other devices or components.

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