Circuit board and method for forming same, circuit board assembly and electronic device
By placing thicker electronic components across layers and embedding thinner components within them, combined with an add-on structure, the problem of vias caused by excessive frame board thickness was solved, enabling a compact wiring design and miniaturized packaging of the circuit board.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- HUAWEI TECH CO LTD
- Filing Date
- 2025-10-13
- Publication Date
- 2026-07-23
AI Technical Summary
The thickness difference of different electronic components results in a larger frame board thickness, which increases the difficulty of manufacturing chip vias, affects subsequent layer addition wiring design, and hinders the realization of miniaturized packaging structures.
Thicker electronic components are placed across multiple layers, while thinner electronic components are embedded in the inner frame board. Electrical connections are achieved through the layering structure, which reduces the overall thickness of the circuit board and makes it easier to form vias.
By using cross-layer configurations and layer-addition structures, the overall thickness of the circuit board is reduced, the via forming process is simplified, and the flexibility of wiring design and the compactness of the packaging structure are improved.
Smart Images
Figure CN2025127281_23072026_PF_FP_ABST
Abstract
Description
A circuit board and its molding method, a circuit board assembly, and an electronic device.
[0001] This application claims priority to Chinese Patent Application No. 202510060585.4, filed on January 14, 2025, entitled "A Circuit Board and a Method for Molding the Circuit Board Thereof, Circuit Board Assembly, Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field
[0002] This application relates to the field of circuit board technology, and in particular to a circuit board and its forming method, circuit board assembly and electronic device. Background Technology
[0003] Miniaturization of electronic components (such as chips, capacitors, and resistors) is a development trend in the semiconductor industry. Embedding chips, capacitors, and resistors within a substrate (such as a frame board) is a relatively novel packaging method that can make full use of vertical space for layout packaging and achieve a high-density miniaturized packaging structure.
[0004] However, different electronic components have different thicknesses, and the appropriate frame board is usually selected based on the size of the thicker electronic component. For example, the thickness of a resistor or capacitor is much greater than the thickness of a chip. Therefore, in order to embed the resistor or capacitor and the chip within the same frame board, the frame board is selected based on the size of the resistor or capacitor. This results in a larger frame board thickness, which is not conducive to the realization of miniaturized packaging structures. It also results in a larger gap between the chip's thickness-direction surface and the frame board's thickness-direction surface, increasing the difficulty of fabricating chip vias and affecting subsequent layer-addition wiring design. Summary of the Invention
[0005] To address the aforementioned issues, embodiments of this application provide a circuit board and its molding method, a circuit board assembly, and an electronic device.
[0006] In a first aspect, embodiments of this application provide a circuit board, comprising: an inner frame board having a first surface and a second surface along its thickness direction; a first add-in structure and a second add-in structure, the first add-in structure being disposed on the first surface and the second add-in structure being disposed on the second surface, the add-in structure including a wiring layer and a dielectric layer; a first element embedded in the inner frame board, the first element having a third surface and a fourth surface along its thickness direction, the third surface and the fourth surface being located between the first surface and the second surface along the thickness direction; and a second element located in a slot inside the circuit board, wherein the slot penetrates at least one dielectric layer, at least one wiring layer and the inner frame board along the thickness direction, the second element having a fifth surface and a sixth surface along the thickness direction, at least one of the first surface and the second surface being located between the fifth surface and the sixth surface along the thickness direction.
[0007] It is understood that the first component and the second component are electronic components with different thicknesses, and the thickness of the first component can be less than the thickness of the second component. In the circuit board of this application embodiment, only the thinner first component is embedded in the inner frame board, while the thicker second component is disposed across layers. For example, the second component penetrates the inner frame board and at least one dielectric layer and at least one wiring layer along its thickness direction. In this way, the frame board is no longer limited by the thicker second component, and only the thinner first component needs to be considered, thereby reducing the overall thickness of the circuit board and reducing the distance between the surface of the first component and the surface of the inner frame board, thereby reducing the difficulty of forming the vias communicating with the first component.
[0008] It should be noted that this application does not limit the types of the first element and the second element. For example, the first element may be a chip, and the second element may be a resistor or a capacitor.
[0009] In some possible implementations of the first aspect described above, the first layer addition structure includes a first dielectric layer and a first wiring layer, wherein the first dielectric layer is stacked on the first surface along the thickness direction, and the first wiring layer is stacked on the side of the first dielectric layer opposite to the first surface along the thickness direction.
[0010] In some possible embodiments of the first aspect described above, the first layer addition structure further includes a second dielectric layer and a second wiring layer, wherein the second dielectric layer is stacked on the first wiring layer along the thickness direction, and the second wiring layer is stacked on the side of the second dielectric layer opposite to the first wiring layer along the thickness direction.
[0011] It should be noted that this application does not limit the specific number of dielectric and wiring layers in the added-layer structure, but sets them according to actual wiring requirements.
[0012] In some possible embodiments of the first aspect described above, the fifth surface is flush with the surface of the first wiring layer facing away from the first dielectric layer. That is, the second element penetrates at least through the first dielectric layer and the first wiring layer in the first layered structure along the thickness direction.
[0013] In some possible embodiments of the first aspect described above, the fifth surface is flush with the surface of the second wiring layer facing away from the second dielectric layer. That is, the second element penetrates at least the first dielectric layer, the first wiring layer, the second dielectric layer, and the second wiring layer in the first layered structure along the thickness direction.
[0014] It is understood that the number of layers spanned by the second element is determined based on its thickness, but this application does not impose any limitation on this.
[0015] In some possible implementations of the first aspect described above, the first element includes a first connection structure located on a third surface, the first dielectric layer having a first via, and the first connection structure being electrically connected to the first via.
[0016] It is understood that the first component is electrically connected to the first wiring layer through the first connection structure and the first via, thus achieving external output through the first layer addition structure.
[0017] In some possible implementations of the first aspect described above, the second layer addition structure includes a third dielectric layer and a third wiring layer, wherein the third dielectric layer is stacked on the second surface along the thickness direction, and the third wiring layer is stacked on the side of the third dielectric layer facing away from the second surface along the thickness direction.
[0018] In some possible embodiments of the first aspect described above, the first element further includes a second connection structure located on the fourth surface, the third dielectric layer having a second via, and the second connection structure being electrically connected to the second via.
[0019] It is understandable that the first component is electrically connected to the third wiring layer through the second connection structure and the second via, thus enabling external routing through the second layer addition structure.
[0020] In some possible implementations of the first aspect described above, the circuit board has multiple slots extending through the inner frame plate along the thickness direction, with the first element and the second element located in different slots.
[0021] It is understandable that different slots have different depths in the thickness direction, which are specifically related to the thickness of each component.
[0022] In some possible embodiments of the first aspect described above, the plurality of slots includes a first slot, the first element is located in the first slot, and the two ends of the first slot along the thickness direction are flush with the first surface and the second surface, respectively. In this way, the first element is embedded within the inner frame plate.
[0023] In some possible embodiments of the first aspect described above, the plurality of slots includes a second slot, the second element is located in the second slot, and the second slot penetrates at least one dielectric layer, at least one wiring layer, and the inner frame board along the thickness direction. This achieves a cross-layer arrangement of the second element.
[0024] In some possible implementations of the first aspect described above, the inner frame plate includes at least two wiring layers, wherein one of the at least two wiring layers is located on a first surface and the other of the at least two wiring layers is located on a second surface.
[0025] It should be noted that this application does not limit the number of wiring layers within the inner frame board; the specific number can be set according to the actual application. For example, the inner frame board can be a two-layer wiring layer structure, a four-layer wiring layer structure, a six-layer wiring layer structure, or an eight-layer wiring layer structure, etc.
[0026] Secondly, embodiments of this application provide a circuit board forming method, including: obtaining an inner frame board; embedding a first component in the inner frame board; performing a layering process on the surface of the inner frame board along its thickness direction to form at least one wiring layer and at least one dielectric layer; performing a slotting process on the inner frame board after the layering process, and placing a second component in the slot; continuing the layering process to form a layered structure, thereby obtaining a circuit board.
[0027] Thirdly, embodiments of this application provide a circuit board assembly, including the circuit board of the first aspect described above, and an electronic device disposed on at least one side of the circuit board along the thickness direction, the electronic device being electrically connected to a first element or a second element.
[0028] Fourthly, embodiments of this application provide an electronic device, including a circuit board assembly and a housing as described in the third aspect above, wherein the circuit board assembly is disposed within the housing.
[0029] The technical effects of the second to fourth aspects can be referred to the technical effects of the first aspect, and will not be repeated here. Attached Figure Description
[0030] Figure 1 shows a cross-sectional schematic diagram of a first type of circuit board 1 according to some embodiments of this application;
[0031] Figure 2 shows a cross-sectional schematic diagram of a second type of circuit board 1 according to some embodiments of this application;
[0032] Figure 3 shows a cross-sectional schematic diagram of a third type of circuit board 1 according to some embodiments of this application;
[0033] Figure 4 shows a schematic flowchart of a method for forming a circuit board 1 according to some embodiments of this application;
[0034] Figures 5A to 5N illustrate a forming process of a circuit board 1 according to some embodiments of this application. Detailed Implementation
[0035] The illustrative embodiments of this application include, but are not limited to, a circuit board and a method for forming the same, a circuit board assembly, and an electronic device.
[0036] It should be noted that the circuit board in this embodiment of the application adopts embedded packaging technology, which directly embeds electronic components (such as chips, capacitors, and resistors) into the substrate (frame board). By adding circuits around the frame board, the electronic components are interconnected and fan-out with the frame board, forming a highly integrated and high-density packaging structure.
[0037] The solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.
[0038] It should be noted that in the figures of this application, the Z-axis direction can represent the thickness direction of the circuit board / frame board, and the X-axis direction can represent the length or width direction of the circuit board / frame board. The X-axis direction and the Z-axis direction are perpendicular to each other.
[0039] Please refer to Figure 1, which shows a schematic cross-sectional view of the circuit board 1 in the XZ plane in some embodiments. It should be noted that the cross-section of the circuit board 1 in the XZ plane is not limited to the portions shown in the figures of this application, and may also include other portions not shown in the figures.
[0040] As shown in Figure 1, the circuit board 1 includes an inner frame board 10, and a first element 20 and a second element 30 embedded in the inner frame board 10. For example, the inner frame board 10 includes a first slot 10a that extends through itself along the Z-axis direction, the first element 20 and the second element 30 are placed in the first slot 10a, and the gaps are filled with a dielectric material.
[0041] The inner frame plate 10 includes a first surface 101 and a second surface 102 opposite to each other along the Z-axis. The first element 20 includes a third surface 201 and a fourth surface 202 opposite to each other along the Z-axis. The second element 30 includes a fifth surface 301 and a sixth surface 302 opposite to each other along the Z-axis. The first surface 101, the third surface 201, and the fifth surface 301 are approximately flush, i.e., they are in the same plane (perpendicular to the XZ plane). The second surface 102, the fourth surface 202, and the sixth surface 302 are not in the same plane and have a height difference between them.
[0042] In some embodiments, the dimensions z1 (thickness of the first element 20) along the Z-axis of the first element 20, z2 (thickness of the second element 30) along the Z-axis of the second element 30, and z3 (thickness of the inner frame plate 10) along the Z-axis of the inner frame plate 10 can gradually increase, i.e., z1 < z2 < z3. Therefore, the height difference between the second surface 102 and the fourth surface 202 can be z3 - z1. The height difference between the sixth surface 302 and the second surface 102 can be z2 - z1. In other words, both the fourth surface 202 and the sixth surface 302 are located between the first surface 101 and the second surface 102.
[0043] For example, the first element 20 may be a chip, and the second element 30 may be a resistor or a capacitor. This application does not limit the types of the first element 20 and the second element 30.
[0044] Referring again to Figure 1, the circuit board 1 also includes a first layer addition structure 40 and a second layer addition structure 50, which are located on opposite sides of the inner frame plate 10 along the Z-axis. For example, the first layer addition structure 40 is disposed on the first surface 101, and the second layer addition structure 50 is disposed on the second surface 102.
[0045] It is understood that the add-on structure includes a wiring layer and a dielectric layer. For example, the first add-on structure 40 includes a dielectric layer 410 and a wiring layer 420, and the second add-on structure 50 includes a dielectric layer 510 and a wiring layer 520. The dielectric layer 410 is stacked on the first surface 101, and the wiring layer 420 is stacked on the side of the dielectric layer 410 facing away from the first surface 101. The dielectric layer 510 is stacked on the second surface 102, and the wiring layer 520 is stacked on the side of the dielectric layer 510 facing away from the second surface 102. It should be noted that the embodiments of this application do not limit the number of wiring layers and dielectric layers in the add-on structure.
[0046] The wiring layers 420 / 520 are mainly used to realize the electrical connection between the inner frame board 10, the first component 20, and the second component 30. The dielectric layers 410 / 510 serve as insulating or isolating layers to prevent short circuits between different parts. The dielectric layers 410 / 510 may include one or more through-holes extending through themselves along the Z-axis direction. The through-holes are filled with conductive dielectric to facilitate electrical connections between different layers or different components within the same layer.
[0047] In some application scenarios, the first component 20 requires double-sided power delivery. For example, when the first component 20 is a power chip, it needs to provide vertical power to electronic devices located on both sides of the circuit board 1 along the Z-axis. Therefore, the first component 20 includes a first connection structure 210 located on its third surface 201 and a second connection structure 220 located on its fourth surface 202. The first connection structure 210 is electrically connected to the first via 411, and through the first via 411, the first component 20 is electrically connected to the wiring layer 420. The second connection structure 220 is electrically connected to the second via 511, and through the second via 511, the first component 20 is electrically connected to the wiring layer 520. In this way, the first component 20 can achieve double-sided power delivery through the wiring layer 420 and the wiring layer 520.
[0048] However, as mentioned earlier, since both the first element 20 and the second element 30 are embedded within the inner frame plate 10, and the thickness of the frame plate 30 is adapted to the relatively thick second element 30, the height difference (z3-z1) between the fourth surface 202 of the first element 20 and the second surface 102 of the inner frame plate 10 is relatively large. This not only makes the overall thickness of the circuit board 1 relatively large, but also makes the dimension of the second via 511 along the Z-axis (the sum of the height difference between the fourth surface 202 and the second surface 102 and the thickness of the dielectric layer 510) relatively large, increasing the difficulty of forming the second via 511.
[0049] Based on this, embodiments of this application provide a circuit board in which only a thinner first component is embedded within the frame board, while a thicker second component is disposed across multiple layers. For example, the second component penetrates the frame board and at least one dielectric layer and at least one wiring layer along the Z-axis. In this way, the frame board is no longer limited by the thicker second component; only the thinner first component needs to be considered. This reduces the overall thickness of the circuit board and the distance between the surface of the first component and the surface of the frame board, thereby reducing the difficulty of forming the vias communicating with the first component.
[0050] The following describes specific embodiments of the circuit board of this application with reference to the accompanying drawings.
[0051] Figure 2 shows a cross-sectional schematic diagram of circuit board 1 in some embodiments. The difference from the circuit board 1 shown in Figure 1 is that the first element 20 and the second element 30 are located in different slots, and only the first element 20 is embedded in the inner frame plate 10, while the second element 30 is arranged across layers in the Z-axis direction. For example, the second element 30 penetrates the inner frame plate 10 and at least one dielectric layer and at least one wiring layer.
[0052] Specifically, as shown in Figure 2, the circuit board 1 includes an inner frame board 10, a first add-on structure 40, and a second add-on structure 50. The positional relationship between the inner frame board 10, the first add-on structure 40, and the second add-on structure 50 can be referred to the description above, and will not be repeated here.
[0053] The circuit board 1 includes multiple slots extending through the inner frame board 10 along the Z-axis, such as a first slot 10a and a second slot 10b. The first slot 10a has its two ends flush with the first surface 101 and the second surface 102 of the inner frame board 10 along the Z-axis, respectively. The second slot 10b extends through the inner frame board 10, at least one dielectric layer, and at least one wiring layer along the Z-axis.
[0054] The first element 20 is embedded in the inner frame plate 10, and the first element 20 is located in the first slot 10a. Thus, the third surface 201 and the fourth surface 202 of the first element 20 are located between the first surface 101 and the second surface 102 of the inner frame plate 10.
[0055] It should be noted that, in the embodiments of this application, any surface located between two surfaces includes the case where any surface is flush with one of the two surfaces (i.e., on the same plane). For example, as shown in Figure 2, the third surface 201 is flush with the first surface 101, and it can be considered that the third surface 201 is located between the first surface 101 and the second surface 102.
[0056] The second element 30 is located in the second slot 10b. At least one of the first surface 101 and the second surface 102 of the inner frame plate 10 is located between the fifth surface 301 and the sixth surface 302 of the second element 30.
[0057] For example, as shown in Figure 2, the second slot 10b sequentially penetrates the wiring layer 420 (an example of the first wiring layer in this application), the dielectric layer 410 (an example of the first dielectric layer in this application), the inner frame plate 10, the dielectric layer 510 (an example of the third dielectric layer in this application), and the wiring layer 520 (an example of the third wiring layer in this application) along the Z-axis direction. Correspondingly, the first surface 101 and the second surface 102 of the inner frame plate 10 are both located between the fifth surface 301 and the sixth surface 302 of the second element 30.
[0058] In some embodiments, as shown in FIG2, the fifth surface 301 of the second element 30 is flush with the surface of the wiring layer 420 facing away from the dielectric layer 410. The sixth surface 302 of the second element 30 may be located between the first surface 101 and the second surface 102, or substantially flush with the second surface 102.
[0059] In this embodiment, the thickness z1 of the first element 20, the thickness z3 of the inner frame plate 10, and the thickness z2 of the second element 30 can gradually increase, that is, z1 < z3 < z2. Thus, by placing the second element 30 across layers and not embedding it in the inner frame plate 10 together with the first element 20, the thickness of the inner frame plate 10 is no longer limited by the thickness of the second element 30, which can reduce the required thickness of the inner frame plate 10, thereby helping to reduce the overall thickness of the circuit board 1.
[0060] Compared to the circuit board 1 shown in Figure 1, the circuit board 1 shown in Figure 2 of this embodiment can have an additional wiring layer 420 when it has the same thickness (for example, when the thickness of the circuit board 1 is z2), which is beneficial to the wiring design of the circuit board 1.
[0061] Furthermore, since the thickness of the inner frame plate 10 is no longer limited by the thickness of the second element 30, only the thickness of the first element 20 needs to be considered. For example, without considering the tolerances of the inner frame plate 10 and the first element 20, the thickness of the inner frame plate 10 can be equal to the thickness of the first element 20, making the height difference between the fourth surface 202 and the second surface 102 zero. As a result, the size of the second through hole 511 along the Z-axis direction can be greatly reduced, thereby reducing the molding difficulty of the second through hole 511.
[0062] It is understandable that when the thickness of the inner frame plate 10 and the first component 20 is small, the thickness tolerance caused by measurement or process is also small and can be ignored. However, when the thickness of the inner frame plate 10 is large, the thickness tolerance caused by measurement or process is large. That is, due to tolerance factors, the actual size of the second via 511 along the Z-axis of the inner frame plate 10 in the circuit board 1 shown in Figure 1 may be larger than the theoretical value (the sum of the height difference between the fourth surface 202 and the second surface 102 and the thickness of the dielectric layer 510), which will further increase the molding difficulty of the second via 511.
[0063] Therefore, in comparison, in this embodiment, since the thickness of the inner frame plate 10 is no longer limited by the thickness of the second element 30, the required thickness of the inner frame plate 10 can be greatly reduced, avoiding the actual size of the second through hole 511 from not matching the theoretical value due to tolerance, thereby affecting the forming of the second through hole 511.
[0064] Referring again to Figure 2, in some embodiments, the first add-on structure 40 further includes a dielectric layer 430 (an example of the second dielectric layer in this application), a wiring layer 440 (an example of the second wiring layer in this application), a dielectric layer 450, and a wiring layer 460, which are sequentially stacked on the surface of the wiring layer 420 facing away from the inner frame plate 10. The second add-on structure 50 further includes a dielectric layer 530, a wiring layer 540, a dielectric layer 550, and a wiring layer 560, which are sequentially stacked on the surface of the wiring layer 520 facing away from the inner frame plate 10. This application does not limit the specific number of dielectric layers and wiring layers in the add-on structure, and sets them according to actual wiring requirements. It can be understood that each of the dielectric layers 430 / 450 / 530 / 550 is provided with one or more through holes to electrically connect each wiring layer.
[0065] In some embodiments, the third surface 201 of the first element 20 is provided with at least one first connection structure 210, and the at least one first connection structure 210 corresponds to at least one first via 411. Figure 2 shows an example with two first connection structures 210 and two first vias 411. The first element 20 can be electrically connected to the wiring layer 420 through the first connection structure 210 and the first via 411, and then exited from the front side of the circuit board 1 (e.g., the side facing the negative Z-axis) through the wiring layers 440 and 460. Additionally, the fourth surface of the first element 20 is provided with at least one second connection structure 220, and the at least one second connection structure 220 corresponds to at least one second via 511. Figure 2 shows an example with one first connection structure 220 and one second via 511. The first element 20 can be electrically connected to the wiring layer 520 through the second connection structure 220 and the second via 511, and then exited from the back side of the circuit board 1 (e.g., the side facing the positive Z-axis) through the wiring layers 540 and 560. Thus, the first element 20 can be exported from both sides.
[0066] It should be noted that the connection structure in the embodiments of this application may include electrical connection structures such as conductive sheets, electrodes, or pads, and this application is not limited thereto. Furthermore, each connection structure in the embodiments of this application has a corresponding via to enable electrical connection between the corresponding electronic component and the adjacent wiring layer.
[0067] For example, the first element 20 can be a power chip. In fields such as computing, networking, and automotive, the amount of data processed by power chips is increasing dramatically, the chip size and the number of peripheral devices are increasing, and the corresponding power supply module layout space is decreasing. Therefore, the power chip adopts the solution shown in Figure 2, which is embedded in the inner frame board 10, and can achieve double-sided output, thereby supplying power to electronic devices located on at least one side of the circuit board 1 along the Z-axis direction, that is, vertical power supply, which can provide greater power density, while achieving higher conversion efficiency and lower loss.
[0068] In some embodiments, the fifth surface 301 of the second element 30 is electrically connected to the wiring layer 440 and the wiring layer 460 through the third via 431, thereby enabling it to be exposed from the front side of the circuit board 1.
[0069] It should be noted that this application does not limit the types of the first element 20 and the second element 30. Generally, the thickness of the first element 20 is less than the thickness of the second element 30. For example, the first element 20 can be a power supply chip or other types of chips. The second element 30 can be an electronic component such as a resistor or capacitor.
[0070] Referring again to Figure 2, in some embodiments, the inner frame board 10 has a two-layer wiring layer structure. For example, the inner frame board 10 includes two wiring layers opposite each other along the Z-axis and an intermediate dielectric layer located between the two wiring layers. The inner frame board 10 also includes at least one conductive via 10A penetrating the intermediate dielectric layer along the Z-axis. Figure 2 uses three conductive vias 10A as an example. The conductive vias 10A connect the two wiring layers opposite each other along the Z-axis of the inner frame board 10.
[0071] It is understood that in the embodiments of this application, the first element 20 may be located between two wiring layers opposite each other along the Z-axis direction of the inner frame plate 10, and the second element 30 may be located between wiring layer 420 and wiring layer 520 in the added-layer structure.
[0072] In some embodiments, the circuit board 1 further includes a third element 60, which is located in a different slot from the second element 30 and the first element 20. The arrangement of the third element 60 can refer to the arrangement of the first element 20. For example, the third element 60 is embedded in the inner frame plate 10. That is, the thickness of the third element 60 is less than or equal to the thickness of the inner frame plate 10. Exemplarily, the third element 60 can be a chip.
[0073] For example, the third element 60 is a single-sided via. For instance, either surface 601 or surface 602 of the third element 60, which are opposite each other along the Z-axis, has a connection structure. In Figure 2, taking the surface 602 of the third element 60 having a third connection structure 610 as an example, the third element 60 can be electrically connected to the wiring layer 520 through the third connection structure 610 and the third via 512, and then be led out from the back side of the circuit board 1 (e.g., the side facing the positive Z-axis direction) through the wiring layers 440 and 460.
[0074] Referring again to Figure 2, in some embodiments, the circuit board 1 further includes a fourth element 70, which is located in a different slot from the third element 60, the second element 30, and the first element 20. The arrangement of the fourth element 70 can refer to the arrangement of the second element 30, and will not be repeated here.
[0075] It is understandable that the fourth element 70, the third element 60, the second element 30, and the first element 20 can be electrically connected through the inner frame plate 10 and the layered structure 40 / 50.
[0076] In addition, in some embodiments, the outermost layers of the circuit board 1 on opposite sides along the Z-axis may also be provided with a solder mask layer 120 and a solder mask layer 130, wherein the solder mask layer 120 is stacked on the side of the wiring layer 460 facing away from the inner frame plate 10, and the solder mask layer 130 is stacked on the side of the wiring layer 560 facing away from the inner frame plate 10. That is, the solder mask layer 120, wiring layer 460, dielectric layer 450, wiring layer 440, dielectric layer 430, wiring layer 420, dielectric layer 410, inner frame plate 10, dielectric layer 510, wiring layer 520, dielectric layer 530, wiring layer 540, dielectric layer 550, wiring layer 560, and solder mask layer 130 are stacked sequentially along the Z-axis. It can be understood that the solder mask layer may have a patterned design to expose the portion of the adjacent wiring layer used for electrical connection with external devices.
[0077] It should be noted that in other embodiments of this application, the circuit board 1 may have more or fewer dielectric layers / wiring layers, and the embodiments of this application are only examples.
[0078] Figure 3 shows a cross-sectional schematic diagram of circuit board 1 in some other embodiments. The difference between the circuit board 1 shown in Figure 2 and the circuit board 1 shown in Figure 2 is that the second element 30 is different from the inner frame board 10.
[0079] As shown in Figure 3, in some embodiments, the inner frame plate 10 has a four-layer wiring structure. For example, the inner frame plate 10 includes four wiring layers spaced apart along the Z-axis, and the four wiring layers are electrically connected through conductive vias 10B. It can be understood that two of the four wiring layers are located on the first surface 101 and the second surface 102, respectively, and the other two wiring layers are located inside the inner frame plate 10. Adjacent wiring layers are filled with a dielectric material.
[0080] It should be noted that this application does not limit the wiring layer structure of the inner frame board 10, and the specific structure can be set according to the actual application. For example, in addition to the two-layer wiring layer structure shown in Figure 2 and the four-layer wiring layer structure shown in Figure 3, the inner frame board 10 can also be a six-layer wiring layer structure or an eight-layer wiring layer structure, etc.
[0081] As shown in Figure 3, in some embodiments, the fifth surface 301 of the second element 30 may be flush with the surface of the wiring layer 440 facing away from the dielectric layer 430. The sixth surface 302 of the second element 30 may be flush with the surface of the dielectric layer 530 facing away from the wiring layer 520. That is, the second element 30 penetrates the wiring layer 440, the dielectric layer 430, the inner frame plate 10, the dielectric layer 510, the wiring layer 520, and the dielectric layer 530 along the Z-axis direction.
[0082] It is understandable that in practical applications, the number of layers spanned by the second element 30 can be determined based on its dimensions along the Z-axis direction, but this application does not impose any limitations on this.
[0083] In this embodiment, the thickness of the second element 30 differs significantly from that of the first element 20. If both are embedded within the inner frame plate 10 as shown in Figure 1, the required thickness of the inner frame plate 10 would be large. After subsequent layer addition processing, the overall thickness of the circuit board 1 would be substantial, hindering miniaturization of the package. Furthermore, the second via 511 of the first element 20 has an excessively large dimension along the Z-axis, making molding difficult. Therefore, by using the thicker second element 30 across layers as shown in Figure 3, the aforementioned problems caused by the thickness of the second element 30 can be resolved.
[0084] Furthermore, compared to the circuit board 1 shown in Figure 1, the circuit board 1 shown in Figure 3 of this embodiment can have an additional wiring layer 420 and a wiring layer 112 laid out with the same thickness, which is beneficial to the wiring design of the circuit board 1.
[0085] Furthermore, other descriptions of the circuit board 1 shown in Figure 3 can be found in the relevant descriptions of the circuit board 1 shown in Figure 2, and will not be repeated here.
[0086] The following describes a method for molding circuit board 1 according to an embodiment of this application. Figure 4 shows a schematic flowchart of a method for molding circuit board 1. As shown in Figure 4, the method includes the following steps:
[0087] S41: Obtain inner frame plate 10.
[0088] S42: Embed the first element 20 within the inner frame plate 10.
[0089] For example, in the molding process of the circuit board 1 shown in Figure 2 or Figure 3, an inner frame board 10 is first obtained, and a groove is made in the inner frame board 10 to obtain a first groove 10a. Then, a first component 20 with a relatively small thickness is placed in the first groove 10a, and then a dielectric material is filled to wrap the first component 20, so that the first component 20 is embedded in the inner frame board 10.
[0090] S43: The inner frame plate 10 is subjected to a layering process along its thickness direction to form at least one wiring layer and at least one dielectric layer.
[0091] For example, as shown in FIG2 or FIG3, a dielectric layer 410 and a wiring layer 420 are formed on a first surface 101, and a dielectric layer 510 and a wiring layer 520 are formed on a second surface.
[0092] S44: The inner frame plate after the layering process is slotted, and the second component is placed in the slot.
[0093] For example, as shown in Figure 2, the inner frame plate 10 after the layering process is slotted to obtain a second slot 10b. The second slot 10b penetrates the inner frame plate 10, the dielectric layer 410, and the wiring layer 420. Then, the relatively thick second component 30 is placed in the second slot 10b, and the second slot 10b is filled with dielectric material to wrap the second component 30.
[0094] Alternatively, as shown in Figure 3, after forming the dielectric layer 410, wiring layer 420, dielectric layer 430, and wiring layer 440 on the first surface 101, a grooving process is performed to obtain a second groove 10b. Then, a second component 30 with a relatively large thickness is placed in the second groove 10b, and dielectric material is filled into the second groove 10b to wrap the second component 30.
[0095] S45: Continue the layering process to form a layered structure and obtain circuit board 1.
[0096] For example, as shown in FIG2, a dielectric layer 430, a wiring layer 440, a dielectric layer 450, and a wiring layer 460 are sequentially stacked on the surface of wiring layer 420. And, a dielectric layer 530, a wiring layer 540, a dielectric layer 550, and a wiring layer 560 are sequentially stacked on the surface of wiring layer 520.
[0097] In some embodiments, a solder resist layer 120 / 130 is formed after the layering process, and a circuit board 1 is obtained after surface treatment.
[0098] It is understood that if more components are needed, this can be achieved in the corresponding steps. For example, in step S42, the third component 60 is also embedded in the inner frame plate 10. In step S44, the fourth component 70 is placed in another slot.
[0099] The molding process of circuit board 1 shown in Figure 2 is described in detail below. Figures 5A to 5N show a molding process of circuit board 1.
[0100] As shown in Figure 5A, the inner frame plate 10 is obtained and processed. The inner frame plate 10 has two opposing surfaces along the Z-axis: a first surface 101 and a second surface 102. The thickness of the inner frame plate 10 can be designed based on the thicknesses of the first element 20 and the third element 60 to be placed.
[0101] Specifically, the inner frame plate 10 is perforated to form a conductive hole 10A, and the inner frame plate 10 is slotted to form a first slot 10a and a third slot 10c. In some embodiments, conductive material can be plated on the sidewalls of the hole to form the conductive hole 10A.
[0102] The openings at both ends of the first slot 10a and the third slot 10c along the Z-axis are flush with the first surface 101 and the second surface 102 of the inner frame plate 10, respectively.
[0103] As shown in Figure 5B, the inner frame plate 10 is inverted and attached to the carrier film 100 (e.g., adhesive tape). For example, the carrier film 100 is attached to the first surface 101.
[0104] As shown in Figure 5C, the first element 20 is placed in the first slot 10a, and the third element 60 is placed in the third slot 10c.
[0105] As shown in Figure 5D, dielectric material is filled into the first slot 10a and the third slot 10c, and a dielectric layer 510 is formed on the second surface 102. Then, a wiring layer 520 is formed by laminating the dielectric layer 510.
[0106] As shown in Figure 5E, remove the carrier film 100.
[0107] As shown in Figure 5F, a dielectric layer 410 is formed on the first surface 101. Then, a wiring layer 420 is formed by laminating on the dielectric layer 410.
[0108] As shown in Figure 5G, blind holes are formed by laser drilling and then filled to form through holes in the dielectric layer 410 / 510, such as the first through hole 411 and the second through hole 511. The wiring layer 420 / 520 is then processed by electroplating and pattern processing.
[0109] It is understandable that since the thickness of the inner frame plate 10 can be determined by the first element 20, the thickness of the dielectric layer 510 can be thinner, which reduces the difficulty of forming the second through hole 511.
[0110] As shown in Figure 5H, the inner frame plate 10 after the addition of layers is further slotted to form a second slot 10b and a fourth slot 10d.
[0111] The second slot 10b and the fourth slot 10d pass through the wiring layer 420, the dielectric layer 410, the inner frame plate 10, the dielectric layer 510 and the wiring layer 520 in sequence along the Z-axis direction.
[0112] As shown in Figure 5I, the inner frame plate 10 after the addition of layers is inverted and attached to the carrier film 200 (e.g., adhesive tape). For example, the carrier film 200 is attached to the surface of the dielectric layer 410. The second element 30 is placed in the second slot 10b, and the fourth element 70 is placed in the fourth slot 10d.
[0113] As shown in Figure 5J, the layer addition process continues, and a dielectric layer 530 is formed on the side of the wiring layer 520 facing away from the dielectric layer 510. Then, a wiring layer 540 is formed by laminating the dielectric layer 530 on the side facing away from the wiring layer 520.
[0114] As shown in Figure 5K, the carrier film 200 is removed.
[0115] As shown in Figure 5L, the layer addition process continues, and a dielectric layer 430 is formed on the side of the wiring layer 420 facing away from the dielectric layer 410. Then, a wiring layer 440 is formed by laminating the dielectric layer 430 on the side facing away from the wiring layer 420.
[0116] As shown in Figure 5M, blind holes are formed by laser drilling and then filled to form conductive holes in dielectric layers 430 / 530. Wiring layers 440 / 540 are then processed by electroplating and patterning processes.
[0117] As shown in Figure 5N, the layer addition process continues, forming a dielectric layer 450 on the side of the wiring layer 440 facing away from the dielectric layer 430. A wiring layer 460 is formed by laminating the dielectric layer 450 on the side facing away from the wiring layer 440. A dielectric layer 550 is formed on the side of the wiring layer 540 facing away from the dielectric layer 530. A wiring layer 560 is formed by laminating the dielectric layer 550 on the side facing away from the wiring layer 540. Furthermore, a solder mask layer 120 is formed on the surface of the wiring layer 460, and a solder mask layer 130 is formed on the surface of the wiring layer 560.
[0118] Finally, surface treatment, such as surface cleaning, is performed to obtain circuit board 1.
[0119] For example, the conductive material and wiring layer mentioned in the embodiments of this application can be metallic materials, such as gold, silver, aluminum, zinc, copper, chromium, nickel, palladium, etc., and the dielectric material and dielectric layer can be epoxy resin and other materials. This application does not limit them.
[0120] In summary, the circuit board 1 provided in this application embodiment embeds a thinner first component 20 (e.g., a chip) and a thicker second component 30 (e.g., a resistor / capacitor) in different layers. The thin chip is embedded in the inner frame board 10. After adding layers to the inner frame board 10, slots are made to embed the thick resistor / capacitor within the slots after adding layers, thus achieving the embedding of the thin chip and the thick resistor / capacitor. Because the thin chip is embedded, the inner frame board 10 is thin and has a small thickness tolerance, resulting in a small thickness tolerance for the dielectric layer on the back of the chip, which is beneficial for forming and filling vias on the back of the chip.
[0121] Furthermore, this application also provides a circuit board assembly, including a circuit board 1 according to this application embodiment, and an electronic device disposed on at least one side of the circuit board 1 along the Z-axis direction. The electronic device is electrically connected to a first element 20 or a second element 30. Exemplary examples include, but are not limited to, circuit boards, power supply circuits, microcontroller units (MCUs), central processing units (CPUs), graphics processing units (GPUs), baseband chips, or system-on-chip (SoC) chips, etc., and this application does not limit the scope of the application to these categories.
[0122] This application also provides an electronic device, including a circuit board assembly and a housing, wherein the circuit board assembly is disposed inside the housing.
[0123] The electronic devices described in this application include, but are not limited to, mobile stations (MS) and mobile terminals (MT). For example, electronic devices may be mobile phones, smart TVs, wearable devices, tablets, desktop computers, laptops, virtual reality (VR) devices, augmented reality (AR) devices, terminals in industrial control, terminals in self-driving vehicles, terminals in remote medical surgery, terminals in smart grids, terminals in transportation safety, terminals in smart cities, terminals in smart homes, and so on. This application does not limit the specific form of the electronic devices described in its embodiments.
[0124] It should be noted that in the embodiments of this application, the concept of "being on the same plane" does not mean being on the same plane in a strict sense. During the circuit board forming process, due to the influence of the forming process and forming equipment, there may be situations where they are not strictly on the same plane. This situation is caused by the specific forming process and does not mean that the situation of not being strictly on the same plane is outside the scope of protection of this application.
[0125] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. As used in the specification and appended claims of this application, the singular expressions “a,” “an,” “the,” “the,” “the,” and “this” are intended to also include expressions such as “one or more,” unless the context clearly indicates otherwise. It should also be understood that in the embodiments of this application, “one or more” means one, two, or more.
[0126] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.
[0127] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.
[0128] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.
Claims
1. A circuit board, characterized by, include: An inner frame plate having a first surface and a second surface along its thickness direction; A first add-in structure and a second add-in structure, wherein the first add-in structure is disposed on the first surface and the second add-in structure is disposed on the second surface, and the add-in structure includes a wiring layer and a dielectric layer; A first element is embedded in the inner frame plate. The first element has a third surface and a fourth surface along the thickness direction. The third surface and the fourth surface are located between the first surface and the second surface along the thickness direction. The second element is located in a slot inside the circuit board, wherein the slot extends through at least one dielectric layer, at least one wiring layer and the inner frame board along the thickness direction, and the second element has a fifth surface and a sixth surface along the thickness direction, wherein at least one of the first surface and the second surface is located between the fifth surface and the sixth surface along the thickness direction.
2. The circuit board of claim 1, wherein The first layer addition structure includes a first dielectric layer and a first wiring layer. Wherein, the first dielectric layer is stacked on the first surface along the thickness direction, and the first wiring layer is stacked on the side of the first dielectric layer opposite to the first surface along the thickness direction.
3. The circuit board of claim 2, wherein, The fifth surface is flush with the surface of the first wiring layer facing away from the first dielectric layer.
4. The circuit board of claim 2, wherein The first layer addition structure also includes a second dielectric layer and a second wiring layer. Wherein, the second dielectric layer is stacked on the first wiring layer along the thickness direction, and the second wiring layer is stacked on the side of the second dielectric layer opposite to the first wiring layer along the thickness direction.
5. The circuit board of claim 4, wherein, The fifth surface is flush with the surface of the second wiring layer facing away from the second dielectric layer.
6. The circuit board according to any one of claims 2-5, characterized in that, The first element includes a first connection structure located on the third surface, the first dielectric layer has a first via, and the first connection structure is electrically connected to the first via.
7. The circuit board of claim 6, wherein The second layer addition structure includes a third dielectric layer and a third wiring layer. The third dielectric layer is stacked on the second surface along the thickness direction, and the third wiring layer is stacked on the side of the third dielectric layer facing away from the second surface along the thickness direction.
8. The circuit board according to claim 7, characterized in that, The first element further includes a second connection structure located on the fourth surface, the third dielectric layer having a second via, and the second connection structure being electrically connected to the second via.
9. The circuit board according to claim 3 or 5, characterized by The circuit board has multiple slots inside that penetrate the inner frame plate along the thickness direction, and the first element and the second element are located in different slots.
10. The circuit board of claim 9, wherein, The plurality of slots includes a first slot, and the first element is located in the first slot. Furthermore, the openings at both ends of the first groove along the thickness direction are flush with the first surface and the second surface, respectively.
11. The circuit board of claim 10, wherein, The plurality of slots includes a second slot, and the second element is located in the second slot. Furthermore, the second slot penetrates at least one dielectric layer, at least one wiring layer, and the inner frame plate along the thickness direction.
12. The circuit board of any of claims 1-11, wherein, The inner frame board includes at least two wiring layers. Wherein, one of the at least two wiring layers is located on the first surface, and the other of the at least two wiring layers is located on the second surface.
13. A method of forming a circuit board, characterized by, include: Obtain the inner frame board; The first component is embedded within the inner frame plate; The inner frame plate is subjected to a layering process along its thickness direction to form at least one wiring layer and at least one dielectric layer. The inner frame plate after the layering process is slotted, and the second component is placed in the slot. Continue the layering process to form a layered structure, resulting in a circuit board.
14. A circuit board assembly comprising a circuit board according to any one of claims 1-12, and an electronic device disposed on at least one side of the circuit board along the thickness direction, the electronic device being electrically connected to the first element or the second element.
15. An electronic device comprising a circuit board assembly as claimed in claim 14 and a housing, the circuit board assembly being disposed within the housing.