Encoding method and apparatus

Abstract

The embodiments of present application relate to the technical field of communications. Provided are an encoding method and apparatus, which can improve the encoding and decoding performance. The method comprises: a sending end device encoding an information bit sequence on the basis of a base matrix, in order to obtain and output an encoded bit sequence, wherein the base matrix comprises P matrix regions, each of the P matrix regions comprises some or all rows of the base matrix, and the P matrix regions do not overlap, P being an integer greater than or equal to 1; and there are T rows in each matrix region, the row weight of any one of the T rows is less than or equal to a first threshold, and at least one row among the T rows is associated with a punctured column in the base matrix, T being an integer greater than or equal to 1.

Description

Encoding method and apparatus

[0001] This application claims priority to Chinese patent application filed on January 17, 2025, with application number 202510081847.5 and entitled "Encoding Method and Apparatus", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communication technology, and in particular to coding methods and apparatus. Background Technology

[0003] Low-density parity check (LDPC) codes are a channel coding scheme. Transmitting equipment can encode information bit sequences based on LDPC codes, and correspondingly, receiving equipment can decode the information to be decoded based on LDPC codes. LDPC codes can be represented using a basis matrix. Specifically, the basis matrix can be used to generate the parity check matrix to achieve channel encoding and decoding.

[0004] Typically, the parity-check matrix (PCM) is designed according to the lowest possible bit rate (i.e., it can encode the information bit sequence at the lowest possible bit rate). When the bit rate changes, the upper left part of the PCM can be used for encoding and decoding. However, under this PCM acquisition mechanism, the reliability of the PCM corresponding to certain bit rates is low, which can easily lead to a decrease in encoding and decoding performance (such as an increase in the bit error rate).

[0005] Therefore, improving compilation and decoding performance is an urgent problem to be solved. Summary of the Invention

[0006] This application provides an encoding method and apparatus that can improve the encoding and decoding performance of LDPC codes.

[0007] Firstly, embodiments of this application provide an encoding method that can be applied to a transmitting device, such as a transmitting end device. For example, the transmitting end device can be a terminal or a communication / computing module within a terminal, or a circuit or chip in the terminal responsible for communication functions (such as a modem chip, also known as a baseband chip, or a system-on-chip (SoC) chip containing a modem core, or a system-in-package (SIP) chip), or a circuit or chip in the terminal responsible for computing and / or communication functions (such as a graphics processing unit (GPU), artificial intelligence (AI) processor, or application-specific integrated circuit (ASIC)). Alternatively, the transmitting end device can be a network-side access network device, a module (e.g., a circuit, chip, or chip system) within the access network device, or a logical node, logical module, or software capable of implementing all or part of the access network device's functions. Taking the application of this method to a transmitting end device as an example, in this method, the transmitting end device encodes the information bit sequence according to a base matrix to obtain and output the encoded bit sequence. The base matrix comprises P matrix regions, each of which includes some or all of the rows of the base matrix. There is no overlap between the P matrix regions, where P is an integer greater than or equal to 1. Each matrix region contains T rows, where the row weight of any row in the T rows is less than or equal to a first threshold, and at least one row in the T rows is associated with a punched column in the base matrix, where T is an integer greater than or equal to 1.

[0008] Using the above method, the transmitting device can encode the information bit sequence based on the base matrix to obtain and output the encoded bit sequence. The base matrix can be divided into P matrix regions (i.e., the base matrix includes P matrix regions, each of which includes some or all rows of the base matrix, and there is no overlap between the P matrix regions, where P is an integer greater than or equal to 1). Within each matrix region, at least one row in the smaller row weight is associated with a punched column in the base matrix (i.e., each matrix region has T rows, where the row weight (the row weight is the number of 1s (or non-zero elements) in a row) is less than or equal to a first threshold, and at least one row in the T rows is associated with a punched column in the base matrix, where T is an integer greater than or equal to 1).

[0009] It is understandable that the smaller the row weight of the row associated with a punched column in the base matrix, the higher the reliability of the parity check matrix corresponding to the base matrix. Therefore, in the base matrix provided in this application, having the row with the smaller row weight associated with only one punched column can improve the reliability of the parity check matrix corresponding to the base matrix, thereby improving the encoding and decoding performance.

[0010] Secondly, embodiments of this application provide a decoding method that can be applied to a receiving side, such as a receiving device. For example, the receiving device can be a terminal or a communication / computing module within the terminal, or a circuit or chip in the terminal responsible for communication functions (such as a modem chip, also known as a baseband chip, or a SoC chip or SIP chip containing a modem core), or a circuit or chip in the terminal responsible for computing and / or communication functions (such as a GPU, AI processor, or ASIC). Alternatively, the receiving device can be an access network device on the network side, a module (e.g., a circuit, chip, or chip system) within the access network device, or a logic module capable of implementing all or part of the functions of the access network device. Points, logic modules, or software. Taking the application of this method to a receiving device as an example, in this method, the receiving device acquires the bit sequence to be decoded; and decodes the bit sequence to be decoded according to the basis matrix to obtain the decoded bit sequence. The basis matrix includes P matrix regions, each of the P matrix regions includes some or all rows of the basis matrix, and there is no overlap between the P matrix regions, where P is an integer greater than or equal to 1; each matrix region contains T rows, the row weight of any row in the T rows is less than or equal to a first threshold, and at least one row in the T rows is associated with a punched column in the basis matrix, where T is an integer greater than or equal to 1.

[0011] Using the above method, the receiving device can encode the bit sequence to be decoded based on the base matrix to obtain the decoded bit sequence. The base matrix can be divided into P matrix regions (i.e., the base matrix includes P matrix regions, each of which includes some or all rows of the base matrix, and there is no overlap between the P matrix regions, where P is an integer greater than or equal to 1). Within each matrix region, at least one row in the smaller row weight is associated with a punched column in the base matrix (i.e., each matrix region has T rows, where the row weight (the row weight is the number of 1s (or non-zero elements) in a row) is less than or equal to a first threshold, and at least one row in the T rows is associated with a punched column in the base matrix, where T is an integer greater than or equal to 1).

[0012] It is understandable that the smaller the row weight of the row associated with a punched column in the base matrix, the higher the reliability of the parity check matrix corresponding to the base matrix. Therefore, in the base matrix provided in this application, having the row with the smaller row weight associated with only one punched column can improve the reliability of the parity check matrix corresponding to the base matrix, thereby improving the encoding and decoding performance.

[0013] Based on the first or second aspect, in one possible design, the first threshold is equal to the minimum row weight in each matrix region, and at least one row in the T rows includes the row with the minimum row weight in each matrix region.

[0014] Since the lower the row weight of the row associated with a punched column in the base matrix, the higher the reliability of the parity check matrix corresponding to that base matrix, the row with the lowest row weight in each matrix region can be associated with only one punched column. This facilitates improving the reliability of the parity check matrix corresponding to that base matrix, thereby improving the encoding and decoding performance.

[0015] Based on the first or second aspect, in one possible design, each matrix region also contains L rows, where the row weight of any row in the L rows is greater than or equal to the second threshold, and at least one row in the L rows is associated with multiple punched columns in the base matrix, where L is an integer greater than or equal to 1.

[0016] Since the lower the row weight of the row associated with a punched column in the base matrix, the higher the reliability of the parity check matrix corresponding to that base matrix, the above method can be used to associate rows with larger row weights (such as L rows with a row weight greater than or equal to the second threshold) with multiple punched columns in each matrix region. This avoids the problem of rows with larger row weights being associated with only one punched column, which would reduce the reliability of the parity check matrix corresponding to the base matrix and facilitates improved encoding and decoding performance.

[0017] Based on the first or second aspect, in one possible design, the second threshold is equal to the maximum row weight in each matrix region, and at least one row in the L rows includes the row with the maximum row weight in each matrix region.

[0018] Since the lower the row weight of the row associated with a punched column in the base matrix, the higher the reliability of the parity check matrix corresponding to that base matrix, the above method allows the row with the highest row weight in each matrix region to be associated with multiple punched columns. This avoids the row with the highest row weight being associated with only one punched column, which would reduce the reliability of the parity check matrix corresponding to the base matrix and thus improve the encoding and decoding performance.

[0019] Based on the first or second aspect, in one possible design, P equals 1, and each matrix region includes some or all of the rows of the base matrix.

[0020] Based on the first or second aspect, in one possible design, P is greater than 1, and each matrix region includes a portion of the rows of the base matrix.

[0021] Based on the first or second aspect, in one possible design, the first matrix region within the P matrix regions includes the first X rows of the incremental redundant region of the base matrix, where X takes the value of 1 or 2.

[0022] It is understandable that the first few rows of the incremental redundancy region of the base matrix usually include the row with the smallest row weight in the base matrix. Therefore, when dividing the matrix region, we can consider dividing these rows into the same matrix region. Thus, the row with the smallest row weight in this matrix region is also the row with the smallest row weight in the base matrix. This allows the row with the smallest row weight in the matrix region to be associated with only one punched column, thereby improving the reliability of the parity check matrix corresponding to the base matrix and thus improving the encoding and decoding performance.

[0023] Thirdly, embodiments of this application provide an encoding method that can be applied to a transmitting device, such as a transmitting end device. For example, the transmitting end device can be a terminal or a communication / computing module within a terminal, or a circuit or chip in the terminal responsible for communication functions (such as a modem chip, also known as a baseband chip, or a SoC chip or SIP chip containing a modem core), or a circuit or chip in the terminal responsible for computing and / or communication functions (such as a GPU, AI processor, or ASIC). Alternatively, the transmitting end device can be a network-side access network device, a module (e.g., a circuit, chip, or chip system) within the access network device, or a logical node, logical module, or software capable of implementing all or part of the access network device's functions. Taking the application of this method to a transmitting end device as an example, in this method, the transmitting end device encodes the information bit sequence according to the base matrix to obtain and output the encoded bit sequence. The basis matrix contains multiple non-zero elements (i,j), where i is the row number and j is the column number; i = 1, j = 1, 2, 3, 4, 6, 7, 10, 11, 12, 13, 14, 16, 17, 19, 20, 21, 22, 23, 24; i = 2, j = 1, 3, 4, 5, 6, 8, 9, 10, 12, 13, 15, 16, 17, 18, 20, 2 2, 23, 24, 25; i = 3, j = 1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 14, 15, 16, 18, 19, 20, 21, 25, 26; i = 4, j = 1, 2, 4, 5, 7, 8, 9, 11, 12, 13, 14, 15, 17, 18, 19, 21, 22, 23, 26; i = 5, j = 2, 27. The other elements in the above rows are zero elements.

[0024] Understandably, the smaller the row weight of the row associated with a punched column in the base matrix, the higher the reliability of the parity-check matrix corresponding to that base matrix. Typically, the punched columns are the first two columns of the base matrix, and a row being associated with a punched column means that the elements in that column are non-zero. Therefore, by using the above method, rows with smaller row weights can be associated with only one punched column (e.g., the second column of row 5 has non-zero elements), thereby improving the reliability of the parity-check matrix corresponding to that base matrix, thus reducing the bit error rate and improving encoding / decoding performance.

[0025] Fourthly, embodiments of this application provide an encoding method that can be applied to a transmitting device, such as a transmitting end device. For example, the transmitting end device can be a terminal or a communication / computing module within a terminal, or a circuit or chip in the terminal responsible for communication functions (such as a modem chip, also known as a baseband chip, or a SoC chip or SIP chip containing a modem core), or a circuit or chip in the terminal responsible for computing and / or communication functions (such as a GPU, AI processor, or ASIC). Alternatively, the transmitting end device can be a network-side access network device, a module (e.g., a circuit, chip, or chip system) within the access network device, or a logical node, logical module, or software capable of implementing all or part of the access network device's functions. Taking the application of this method to a transmitting end device as an example, in this method, the transmitting end device encodes the information bit sequence according to the base matrix to obtain and output the encoded bit sequence. The basis matrix contains multiple non-zero elements (i,j), where i is the row number and j is the column number; i = 1, j = 1, 2, 3, 4, 6, 7, 10, 11, 12, 13, 14, 16, 17, 19, 20, 21, 22, 23, 24; i = 2, j = 1, 3, 4, 5, 6, 8, 9, 10, 12, 13, 15, 16, 17, 18, 20, 2 2, 23, 24, 25; i = 3, j = 1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 14, 15, 16, 18, 19, 20, 21, 25, 26; i = 4, j = 1, 2, 4, 5, 7, 8, 9, 11, 12, 13, 14, 15, 17, 18, 19, 21, 22, 23, 26; i = 5, j = 1, 27. The other elements in the above rows are zero elements.

[0026] Understandably, the smaller the row weight of the row associated with a punched column in the base matrix, the higher the reliability of the parity-check matrix corresponding to that base matrix. Typically, the punched columns are the first two columns of the base matrix, and a row being associated with a punched column means that the elements in that column of that row are non-zero. Therefore, by using the above method, rows with smaller row weights can be associated with only one punched column (e.g., the first column of row 5 is non-zero), thereby improving the reliability of the parity-check matrix corresponding to that base matrix, thus reducing the bit error rate and improving encoding / decoding performance.

[0027] Fifthly, embodiments of this application provide an encoding method that can be applied to a transmitting device, such as a transmitting end device. For example, the transmitting end device can be a terminal or a communication / computing module within a terminal, or a circuit or chip in the terminal responsible for communication functions (such as a modem chip, also known as a baseband chip, or a SoC chip or SIP chip containing a modem core), or a circuit or chip in the terminal responsible for computing and / or communication functions (such as a GPU, AI processor, or ASIC). Alternatively, the transmitting end device can be a network-side access network device, a module (e.g., a circuit, chip, or chip system) within the access network device, or a logical node, logical module, or software capable of implementing all or part of the access network device's functions. Taking the application of this method to a transmitting end device as an example, in this method, the transmitting end device encodes the information bit sequence according to a base matrix to obtain and output the encoded bit sequence. The basis matrix includes multiple non-zero elements (i,j), where i is the row number and j is the column number; i = 1, j = 1, 2, 3, 4, 6, 7, 10, 11, 12, 13, 14, 16, 17, 19, 20, 21, 22, 23, 24; i = 2, j = 1, 3, 4, 5, 6, 8, 9, 10, 12, 13, 15, 16, 17, 18, 20, 22, 2 3, 24, 25; i = 3, j = 1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 14, 15, 16, 18, 19, 20, 21, 25, 26; i = 4, j = 1, 2, 4, 5, 7, 8, 9, 11, 12, 13, 14, 15, 17, 18, 19, 21, 22, 23, 26; i = 5, j = 2, 24, 25, 27. The other elements in the above rows are zero elements.

[0028] Understandably, the smaller the row weight of the row associated with a punched column in the base matrix, the higher the reliability of the parity-check matrix corresponding to that base matrix. Typically, the punched columns are the first two columns of the base matrix, and a row being associated with a punched column means that the elements in that column are non-zero. Therefore, by using the above method, rows with smaller row weights can be associated with only one punched column (e.g., the second column of row 5 has non-zero elements), thereby improving the reliability of the parity-check matrix corresponding to that base matrix, thus reducing the bit error rate and improving encoding / decoding performance.

[0029] Sixthly, embodiments of this application provide an encoding method that can be applied to a transmitting device, such as a transmitting end device. For example, the transmitting end device can be a terminal or a communication / computing module within a terminal, or a circuit or chip in the terminal responsible for communication functions (such as a modem chip, also known as a baseband chip, or a SoC chip or SIP chip containing a modem core), or a circuit or chip in the terminal responsible for computing and / or communication functions (such as a GPU, AI processor, or ASIC). Alternatively, the transmitting end device can be a network-side access network device, a module (e.g., a circuit, chip, or chip system) within the access network device, or a logical node, logical module, or software capable of implementing all or part of the access network device's functions. Taking the application of this method to a transmitting end device as an example, in this method, the transmitting end device encodes the information bit sequence according to a base matrix to obtain and output the encoded bit sequence. The basis matrix contains multiple non-zero elements (i,j), where i is the row number and j is the column number; i = 1, j = 1, 2, 3, 4, 6, 7, 10, 11, 12, 13, 14, 16, 17, 19, 20, 21, 22, 23, 24; i = 2, j = 1, 3, 4, 5, 6, 8, 9, 10, 12, 13, 15, 16, 17, 18, 20, 22, 23. 24, 25; i = 3, j = 1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 14, 15, 16, 18, 19, 20, 21, 25, 26; i = 4, j = 1, 2, 4, 5, 7, 8, 9, 11, 12, 13, 14, 15, 17, 18, 19, 21, 22, 23, 26; i = 5, j = 1, 24, 25, 26, 27. The other elements in the above rows are zero elements.

[0030] Understandably, the smaller the row weight of the row associated with a punched column in the base matrix, the higher the reliability of the parity-check matrix corresponding to that base matrix. Typically, the punched columns are the first two columns of the base matrix, and a row being associated with a punched column means that the elements in that column of that row are non-zero. Therefore, by using the above method, rows with smaller row weights can be associated with only one punched column (e.g., the first column of row 5 is non-zero), thereby improving the reliability of the parity-check matrix corresponding to that base matrix, thus reducing the bit error rate and improving encoding / decoding performance.

[0031] Seventhly, embodiments of this application provide an encoding method that can be applied to a transmitting device, such as a transmitting end device. For example, the transmitting end device can be a terminal or a communication / computing module within a terminal, or a circuit or chip in the terminal responsible for communication functions (such as a modem chip, also known as a baseband chip, or a SoC chip or SIP chip containing a modem core), or a circuit or chip in the terminal responsible for computing and / or communication functions (such as a GPU, AI processor, or ASIC). Alternatively, the transmitting end device can be a network-side access network device, a module (e.g., a circuit, chip, or chip system) within the access network device, or a logical node, logical module, or software capable of implementing all or part of the access network device's functions. Taking the application of this method to a transmitting end device as an example, in this method, the transmitting end device encodes the information bit sequence according to a base matrix to obtain and output the encoded bit sequence. The basis matrix includes multiple non-zero elements (i,j), where i is the row number and j is the column number; i = 1, j = 1, 2, 3, 4, 6, 7, 10, 11, 12, 13, 14, 16, 17, 19, 20, 21, 22, 23, 24; i = 2, j = 1, 3, 4, 5, 6, 8, 9, 10, 12, 13, 15, 16, 17, 18, 20, 22, 23, 24, 25; i = 3, j = 1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 14, 15, 16, 18, 19, 20, 21, 25, 26; i = 4, j = 1, 2, 4, 5, 7, 8, 9, 11, 12, 13, 14, 15, 17, 18, 19, 21, 22, 23, 26; i = 5, j = 2, 27; i = 6, j = 1, 4, 13, 17, 22, 13, 28. All other elements in the above rows are zero elements.

[0032] Understandably, the smaller the row weight of the row associated with a punched column in the base matrix, the higher the reliability of the parity-check matrix corresponding to that base matrix. Typically, the punched columns are the first two columns of the base matrix, and a row being associated with a punched column means that the elements in that column of that row are non-zero. Therefore, by using the above method, rows with smaller row weights can be associated with only one punched column (e.g., the first column of row 5 and the first column of row 6 both have non-zero elements), thereby improving the reliability of the parity-check matrix corresponding to that base matrix, thus reducing the bit error rate and improving encoding / decoding performance.

[0033] Eighthly, this application provides a communication device that has the function of implementing any one of the first, third to seventh aspects. For example, the communication device includes a module, unit or means corresponding to the operation involved in any one of the first, third to seventh aspects. The module, unit or means can be implemented by software, or by hardware, or by a combination of software and hardware.

[0034] Ninthly, this application provides a communication device that has the functions of the second aspect described above. For example, the communication device includes modules, units, or means that perform the operations involved in the second aspect described above. These modules, units, or means can be implemented by software, hardware, or a combination of software and hardware.

[0035] Tenthly, this application provides a communication device including an interface circuit and one or more processors. The one or more processors are coupled to a memory. The memory stores part or all of the necessary computer program or instructions for implementing the functions involved in any of the first, third, to seventh aspects described above. The one or more processors can execute the computer program or instructions, causing the communication device to implement the methods in any possible design or implementation of any of the first, third, to seventh aspects described above when the computer program or instructions are executed. The interface circuit is used to implement the communication functions within the communication device and / or the communication functions between the communication device and other devices or components.

[0036] In one possible design, the processor is used to communicate with other devices or components through the interface circuit.

[0037] In one possible design, the communication device may also include the memory.

[0038] The aforementioned communication device may be a terminal, or a communication / computing module in the terminal, or a chip in the terminal responsible for communication functions such as a modem chip (also known as a baseband chip) or a SoC or SIP chip containing a modem module, or a circuit or chip in the terminal responsible for computing and / or communication functions (such as a GPU, AI processor, or ASIC).

[0039] Alternatively, the aforementioned communication device may be an access network device, a module (e.g., a circuit, chip, or chip system) within the access network device, or a logical node, logical module, or software capable of implementing all or part of the functions of the access network device.

[0040] Eleventhly, this application provides a communication device including an interface circuit and one or more processors. The one or more processors are coupled to a memory. The memory stores part or all of the necessary computer program or instructions for implementing the functions described in the second aspect above. The one or more processors can execute the computer program or instructions, causing the communication device to implement the methods in any possible design or implementation of the second aspect above when executed. The interface circuit is used to implement the communication functions within the communication device and / or the communication functions between the communication device and other devices or components.

[0041] In one possible design, the processor is used to communicate with other devices or components through the interface circuit.

[0042] In one possible design, the communication device may also include the memory.

[0043] The aforementioned communication device may be a terminal, or a communication / computing module in the terminal, or a chip in the terminal responsible for communication functions such as a modem chip (also known as a baseband chip) or a SoC or SIP chip containing a modem module, or a circuit or chip in the terminal responsible for computing and / or communication functions (such as a GPU, AI processor, or ASIC).

[0044] Alternatively, the aforementioned communication device may be an access network device, a module (e.g., a circuit, chip, or chip system) within the access network device, or a logical node, logical module, or software capable of implementing all or part of the functions of the access network device.

[0045] In a twelfth aspect, this application provides a communication system comprising units of the encoding method described in any one of the first, third to seventh aspects, and units of the decoding method described in the second aspect.

[0046] In a thirteenth aspect, this application provides a computer-readable storage medium storing computer-readable instructions that, when read and executed by a computer, cause the computer to perform any of the possible designs in the first to seventh aspects described above.

[0047] In a fourteenth aspect, this application provides a computer program product that, when read and executed by a computer, causes the computer to perform any of the possible designs in the first to seventh aspects described above. Attached Figure Description

[0048] Figure 1 shows a possible, non-limiting system schematic diagram;

[0049] Figures 2 and 3 illustrate possible application frameworks in a communication system;

[0050] Figure 4 shows a schematic diagram of an information transmission method provided in an embodiment of this application;

[0051] Figure 5 shows a schematic diagram of a parity-check array structure provided in an embodiment of this application;

[0052] Figure 6 shows a schematic diagram of a base matrix structure provided in an embodiment of this application;

[0053] Figure 7 shows a schematic diagram illustrating the correspondence between a parity check matrix and a code rate according to an embodiment of this application;

[0054] Figure 8 shows a flowchart of an encoding method provided in an embodiment of this application;

[0055] Figures 9 to 16 show schematic diagrams of the basis matrix provided in the embodiments of this application;

[0056] Figure 17 shows a possible exemplary block diagram of the communication device involved in the embodiments of this application;

[0057] Figure 18 shows a possible exemplary block diagram of the terminal involved in the embodiments of this application. Detailed Implementation

[0058] In this application, "sending information" can be understood as one device sending information to another device, or it can also be understood as one logical module within a device sending information to another logical module. For example, "access network device sending information" can be understood as the access network device sending information to another device (such as a terminal), or it can be understood as logical module 1 in the access network device sending information to logical module 2 in the access network device.

[0059] In this application, "receiving information" can be understood as one device receiving information from another device, or it can also be understood as a logical module within a device receiving information from another logical module. For example, "access network device receiving information" can be understood as the access network device receiving information from another device (such as a terminal), or it can be understood as logical module 1 in the access network device receiving information from logical module 2 in the access network device.

[0060] In this application, phrases such as "sending information to... (e.g., a terminal)" or related illustrations in the accompanying drawings can be understood as indicating that the destination of the information is a terminal. This can include sending information directly or indirectly to a terminal. Similarly, phrases such as "receiving information from... (e.g., a terminal)," "receiving information from... (e.g., a terminal)," or "receiving information sent by (e.g., a terminal)," or related illustrations in the accompanying drawings, can be understood as indicating that the source of the information is a terminal. This can include receiving information directly or indirectly from a terminal. Information may undergo necessary processing between the source and destination, such as format changes, but the destination can understand the valid information from the source. Similar expressions in this application can be interpreted similarly and will not be elaborated further here.

[0061] Figure 1 illustrates a possible, non-limiting system diagram. As shown in Figure 1, the communication system 10 includes a radio access network (RAN) 100 and a core network (CN) 200. RAN 100 includes at least one RAN node (110a and 110b in Figure 1, collectively referred to as 110) and at least one terminal (120a-120j in Figure 1, collectively referred to as 120). RAN 100 may also include other RAN nodes, such as wireless relay devices and / or wireless backhaul devices (not shown in Figure 1). Terminal 120 is wirelessly connected to RAN node 110. RAN node 110 is wirelessly or wired connected to core network 200. The core network equipment in core network 200 and RAN node 110 in RAN 100 can be different physical devices, or they can be the same physical device integrating core network logical functions and radio access network logical functions.

[0062] RAN 100 can be a cellular system related to the 3rd Generation Partnership Project (3GPP), such as 4G, 5G mobile communication systems, or future-oriented evolution systems. RAN 100 can also be an open RAN (O-RAN or ORAN), a cloud radio access network (CRAN), or a wireless fidelity (WiFi) system. RAN 100 can also be a communication system that integrates two or more of the above systems.

[0063] RAN node 110, sometimes also referred to as access network equipment, RAN entity, or access node, constitutes part of the communication system and is used to help terminals achieve wireless access. Multiple RAN nodes 110 in communication system 10 can be of the same type or different types. In some scenarios, the roles of RAN node 110 and terminal 120 are relative. For example, network element 120i in Figure 1 can be a helicopter or drone, which can be configured as a mobile base station. For terminals 120j accessing RAN 100 through network element 120i, network element 120i is a base station; but for base station 110a, network element 120i is a terminal. RAN node 110 and terminal 120 are sometimes both referred to as communication devices. For example, network elements 110a and 110b in Figure 1 can be understood as communication devices with base station functions, and network elements 120a-120j can be understood as communication devices with terminal functions.

[0064] In one possible scenario, the RAN node can be a base station, an evolved NodeB (eNodeB), an access point (AP), a transmission reception point (TRP), a next-generation NodeB (gNB), a base station in a future mobile communication system, or an access node in a WiFi system. The RAN node can be a macro base station (as shown in Figure 1, 110a), a micro base station or indoor station (as shown in Figure 1, 110b), a relay node or donor node, or a radio controller in a CRAN scenario. Optionally, the RAN node can also be a server, wearable device, vehicle, or in-vehicle equipment. For example, the access network equipment in vehicle-to-everything (V2X) technology can be a roadside unit (RSU). All or part of the functions of the RAN node in this application can also be implemented through software functions running on hardware, or through virtualization functions instantiated on a platform (e.g., a cloud platform). The RAN node can also be equipped with communication modules, circuits, or chips that perform corresponding communication functions. The RAN node can also be configured with program instructions for performing corresponding communication functions, as well as corresponding program instructions. The RAN node in this application can also be a logical node, logical module, or software capable of implementing all or part of the RAN node's functions.

[0065] In another possible scenario, multiple RAN nodes collaborate to assist the terminal in achieving wireless access, with each RAN node performing a portion of the base station's functions. For example, RAN nodes can be central units (CUs), distributed units (DUs), CU-control plane (CPs), CU-user plane (UPs), or radio units (RUs), etc. CUs and DUs can be separate entities or included in the same network element, such as a baseband unit (BBU). RUs can be included in radio frequency equipment or radio frequency units, such as remote radio units (RRUs), active antenna units (AAUs), or remote radio heads (RRHs).

[0066] In different systems, CU (or CU-CP and CU-UP), DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an ORAN system, CU can also be called O-CU (open CU), DU can also be called O-DU, CU-CP can also be called O-CU-CP, CU-UP can also be called O-CU-UP, and RU can also be called O-RU. For ease of description, this application uses CU, CU-CP, CU-UP, DU, and RU as examples. Any of the units among CU (or CU-CP, CU-UP), DU, and RU in this application can be implemented through software modules, hardware modules, or a combination of software and hardware modules.

[0067] A terminal can be a device or module that accesses the aforementioned communication system and has corresponding communication functions. A terminal can also be called a terminal device, user equipment (UE), mobile station, mobile terminal, etc. Terminals can be widely used in various scenarios, such as device-to-device (D2D), vehicle-to-everything (V2X) communication, machine-type communication (MTC), Internet of Things (IoT), virtual reality, augmented reality, industrial control, autonomous driving, telemedicine, smart grids, smart furniture, smart offices, smart wearables, smart transportation, smart cities, etc. Terminals can be mobile phones, tablets, computers with wireless transceiver capabilities, wearable devices, vehicles, drones, helicopters, airplanes, ships, robots, robotic arms, smart home devices, transportation vehicles with wireless communication capabilities, communication modules, etc. The embodiments of this application do not limit the device form of the terminal. A terminal typically contains a communication module, circuit, or chip that performs the corresponding communication function. The terminal can also be configured with program instructions for performing the corresponding communication function.

[0068] To support artificial intelligence (AI) technology in wireless networks, AI nodes may also be introduced into the network.

[0069] AI nodes can be deployed in one or more of the following locations within the communication system: access network nodes (RAN nodes), terminals, or core network equipment, etc. Alternatively, AI nodes can be deployed independently, for example, in a location other than any of the above-mentioned devices, such as in the host or cloud server of an over-the-top (OTT) system. AI nodes can communicate with other devices in the communication system, which can be one or more of the following: network devices, terminal devices, or core network elements, etc.

[0070] It is understood that this application does not limit the number of AI nodes. For example, when there are multiple AI nodes, these nodes can be divided based on function, such as different AI nodes being responsible for different functions.

[0071] It can also be understood that AI nodes can be independent devices, or they can be integrated into the same device to achieve different functions. Alternatively, they can be network elements in hardware devices, software functions running on dedicated hardware, or virtualization functions instantiated on a platform (e.g., a cloud platform). This application does not limit the specific form of the aforementioned AI nodes.

[0072] AI nodes can be AI network elements or AI modules.

[0073] Figure 2 illustrates a possible application framework in a communication system. As shown in Figure 2, network elements in the communication system are connected via interfaces (e.g., NG, Xn) or air interfaces. These network element nodes, such as core network equipment, access network nodes (RAN nodes), terminals, or one or more devices in operations administration and maintenance (OAM), are equipped with one or more AI modules (only one is shown in Figure 2 for clarity). A radio access network node can be a single RAN node or can include multiple RAN nodes, for example, including CU and DU. The CU and / or DU can also be equipped with one or more AI modules. A CU can also be split into CU-CP and CU-UP, with one or more AI modules configured in the CU-CP and / or CU-UP.

[0074] AI modules are used to implement corresponding AI functions. AI modules deployed in different network elements can be the same or different. The models of AI modules can achieve different functions depending on the parameter configurations. The models of AI modules can be configured based on one or more of the following parameters: structural parameters (e.g., at least one of the following: number of neural network layers, neural network width, inter-layer connections, neuron weights, neuron activation function, or biases in the activation function), input parameters (e.g., the type and / or dimension of the input parameters), or output parameters (e.g., the type and / or dimension of the output parameters). The biases in the activation function can also be referred to as the biases of the neural network.

[0075] In one example, the neural network mentioned above can be a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), or a generative adversarial network (GAN).

[0076] Deep Neural Networks (DNNs) are artificial neural network architectures with multiple layers of nonlinear transformation units stacked in a hierarchical structure to form deep computational models. Compared to shallow neural networks, deep neural networks have more hidden layers, allowing the network model to capture more complex data structures and higher-level abstract features.

[0077] A CNN is a deep neural network with a convolutional structure. A CNN contains a feature extractor consisting of convolutional layers and subsampling layers. This feature extractor can be viewed as a filter, and the convolution process can be seen as performing convolution between a trainable filter and an input image or a convolutional feature map.

[0078] RNN is a type of recursive neural network that takes sequence data as input, recursively moves along the direction of sequence evolution, and connects all nodes (recurrent units) in a chain-like manner.

[0079] GAN is a deep learning model. It consists of a generator and a discriminator, and is trained through adversarial learning. Its purpose is to estimate the potential distribution of data samples and generate new data samples.

[0080] An AI module can have one or more models. A model can infer an output, which includes one or more parameters. The learning, training, or inference processes of different models can be deployed on different nodes or devices, or they can be deployed on the same node or device.

[0081] Figure 3 illustrates another possible application framework in a communication system. As shown in Figure 3, the communication system includes a RAN intelligent controller (RIC). For example, the RIC can be the AI ​​module shown in Figure 2, used to implement AI-related functions. RICs include near-real-time RICs (near-RT RICs) and non-real-time RICs (non-RT RICs). Non-real-time RICs primarily process non-real-time information, such as data that is not sensitive to latency, with latency in the order of seconds. Real-time RICs primarily process near-real-time information, such as data that is relatively sensitive to latency, with latency in the order of tens of milliseconds.

[0082] Near real-time (NRT) RICs are used for model training and inference. For example, they are used to train AI models and then use those models for inference. NRT RICs can obtain network-side and / or terminal-side information from RAN nodes (e.g., CUs, CU-CPs, CU-UPs, DUs, and / or RUs) and / or terminals. This information can be used as training data or inference data. NRT RICs can deliver inference results to RAN nodes and / or terminals. Inference results can be exchanged between CUs and DUs, and / or between DUs and RUs. For example, a NRT RIC delivers an inference result to a DU, which then forwards it to an RU.

[0083] Non-real-time RICs are also used for model training and inference. For example, they are used to train AI models and then use those models for inference. Non-real-time RICs can obtain network-side and / or terminal-side information from RAN nodes (e.g., CUs, CU-CPs, CU-UPs, DUs, and / or RUs) and / or terminals. This information can be used as training data or inference data, and the inference results can be delivered to RAN nodes and / or terminals. Inference results can be exchanged between CUs and DUs, and / or between DUs and RUs; for example, a non-real-time RIC delivers inference results to a DU, which then forwards them to an RU.

[0084] Near real-time RICs and non-real-time RICs can also be configured as separate network elements. Near real-time RICs and non-real-time RICs can also be part of other devices. For example, near real-time RICs can be set in RAN nodes (e.g., CU, DU), while non-real-time RICs can be set in OAM, cloud servers, core network devices, or other network devices.

[0085] To facilitate understanding of the technical solutions of the embodiments of this application, a brief introduction to the relevant technologies of this application is given below.

[0086] 1) Signal transmission:

[0087] In a communication system, as shown in Figure 4, the information sent by the source can be processed through source coding, channel coding, and modulation to form a signal. After being transmitted through the channel, the sink receives the signal. The signal then undergoes demodulation, channel decoding, and source recovery to become information, thus enabling signal transmission between the sink and the source.

[0088] The main types of channel coding include: linear block codes, convolutional codes, concatenated codes, and low-density parity check (LDPC) codes.

[0089] 2) LDPC code:

[0090] Among them, LDPC code is a low-density parity-check code, which is a channel coding scheme that is very close to Shannon line. It has the characteristics of good coding performance and low complexity, and has been selected by the 3rd generation partnership project (3GPP) as the channel coding scheme for the 5th generation (5G) mobile communication system.

[0091] LDPC codes can be used to implement channel coding through generator matrices or parity check matrices. The mainstream LDPC codes are quasi-cyclic (QC) structures, which avoid bad structures such as short cycles as much as possible by setting the shift amount of each block, thereby improving the code distance.

[0092] The base graph model of QC-LDPC code can be represented as: BG=(X,Y,F); where X is the corresponding variable, Y is the check equation associated with the corresponding variable, and F is the edge relationship between the corresponding variable and the check equation associated with the corresponding variable.

[0093] Optionally, the base graph of the QC-LDPC code can be extended into a cyclic shift matrix. That is, after the QC base graph is extended by a boost factor of Z, a Tanner graph is obtained (the Tanner graph corresponds one-to-one with the parity check matrix).

[0094] The Tanner graph can be represented as: G = (V, C, E); V is the variable node, C is the check node, and E is the connection between the variable node and the check node.

[0095] Optionally, based on the Tanner plot and the lifting factor Z, the number of columns in the parity check matrix can be determined as: |V|=Z|X|, and the number of non-zero elements in the parity check matrix is: |E|=Z|F|.

[0096] As shown in Figure 5, the parity check matrix can include a high-rate region, an all-zero region, an incremental redundancy region, and a raptor-like region. The high-rate region can include parts A and B as shown in Figure 6. Part A corresponds to information bits (or information digits, system bits, etc.), and part B is a square matrix corresponding to the core parity bits (or core parity digits). The core parity can be the parity corresponding to the highest bit rate, or it can be a parity with a degree greater than or equal to 2, or it can be the parity node corresponding to the row set with the largest row weight (row weight significantly higher than other rows). The all-zero region can correspond to part C in Figure 6 and is an all-zero matrix. The incremental redundancy region can correspond to part D in Figure 6. The raptor-like region can correspond to part E in Figure 6 and can be an identity matrix, corresponding to the parity bits of the low-rate extension. Part B and Part E are both verification parts. Part B is defined as the core verification region, and its features can be non-lower triangular coding parts (i.e., values ​​above the diagonal are not all 0) or coding parts with column weight greater than 1. Part E is defined as the extended verification region, and its features can be lower triangular coding parts (i.e., values ​​above the diagonal are all 0) or diagonal matrices.

[0097] The parity-check matrix of the LDPC code shown in Figure 5 adopts a "raptor-like" structure, which can be gradually extended to low bitrates from a high-bitrate core matrix. In actual use, as shown in Figure 5, the first X rows and the first Y columns of the parity-check matrix can be extracted. As the bitrate decreases, X and Y gradually increase, and the area of ​​the matrix used also gradually expands.

[0098] For example, taking a high-throughput scenario of a 5G mobile communication system (the code length of the information bit sequence is 1k to 2k bits or greater than 8k bits, and / or the code rate is greater than a preset threshold) as an example, in this scenario, the encoding of the information bit sequence can be achieved through base map 1. The number of information columns in part A of base map 1 is 22, the number of information columns in part B is 4, and the number of punched columns is 2. Then, the code rate supported by base map 1 is 22 / (22+4-2)=11 / 12≈0.917.

[0099] In 5G mobile communication systems, data channels can support information bit sequences of lengths ranging from 1 to 8448 bits. Different information bit sequences correspond to different base maps (such as base map 1 (BG1) and base map 2 (BG2)). The same base map can be adapted to rate matching of information bit sequences of different lengths through different boosting factors.

[0100] Base graph 1 and base graph 2 share a common base matrix structure, as shown in Figure 6. The columns of the base matrix consist of information columns and check columns.

[0101] Information column: Corresponding to information bits (or information bits, system bits, etc.), it is the column corresponding to part A.

[0102] Check columns: Corresponding to check bits (or check digits, etc.), these are the columns corresponding to parts B and C, and can include core check columns and extended check columns. The core check columns are those corresponding to part B, while the extended check columns are those corresponding to parts C or E. Extended check columns can also be called raptor-like columns. Alternatively, the core check columns are the check columns in part B with a column weight greater than 1 (part B has 1 elements both above and below its diagonal), and the extended check columns are the remaining check columns excluding the core check columns.

[0103] Core rows: The core rows of the base matrix correspond to the core parity bits. In other words, the core rows are the rows corresponding to high bitrate regions, or the rows corresponding to parts A, B, or C.

[0104] Core columns: These can include all information columns and all core check columns. In other words, core columns are the columns corresponding to high bitrate areas, or the columns corresponding to part A plus part B.

[0105] The kernel matrix is ​​a matrix region consisting of all the kernel rows and all the kernel columns of the base matrix. In other words, the kernel matrix is ​​the high-bitrate region of the base matrix, or the part composed of part A and part B.

[0106] In this matrix, the values ​​are either 0 or 1; a value of 0 represents an empty element, which is sometimes called a zero element. A value of 1 represents an edge in the base graph, or a value of 1 represents the association between the corresponding check and the corresponding variable; an element with a value of 1 is sometimes called a non-zero element.

[0107] In Figure 6, the area within the dashed box represents the punched columns. The first two columns of the base matrix are both punched columns, and the column weight (the number of 1s (or non-zero elements) in a column) is relatively large. During transmission, the punched columns do not participate in the transmission process, but they participate in both encoding and decoding.

[0108] 3) Decoding algorithm for LDPC codes:

[0109] Optionally, the decoding algorithm for LDPC codes can be the min-sum (MS) decoding algorithm or the belief propagation (BP) decoding algorithm.

[0110] Among them, the BP decoding algorithm has good decoding performance, but it requires a large amount of information storage and has high computational complexity, which is not conducive to hardware implementation.

[0111] Among them, the MS decoding algorithm has poor decoding performance, but lower computational complexity and is easier to implement in hardware. In practical communication systems, the Offset-MS decoding algorithm and the Normalized MS decoding algorithm are commonly used.

[0112] Since the punctured columns do not participate in transmission, during the decoding process of LDPC codes, the receiving device needs to recover the information bits located in the punctured columns based on the parity check matrix, and then decode the received information based on these information bits to obtain the complete information bit sequence. In other words, the reliability of the parity check matrix can affect the decoding performance of LDPC codes during the decoding process. For example, a highly reliable parity check matrix can recover reliable information bits, thus enabling decoding based on these highly reliable information bits and improving decoding performance.

[0113] Typically, a high number of decoding iterations can reduce the impact of the parity check matrix's reliability on decoding performance, thereby improving decoding performance. However, in high-throughput scenarios (such as scenarios with high code rates and / or large code lengths), the number of decoding iterations and complexity are extremely low. Therefore, a decrease in the reliability of the parity check matrix will lead to a decrease in the decoding performance of LDPC codes.

[0114] Taking a 5-round iteration as an example, for the parity check matrix acquisition mechanism shown in Figure 3, the corresponding bit error rates after encoding the parity check matrices obtained under different code rates are shown in Figure 7. As can be seen from Figure 7, the bit error rate is higher for some code rates (such as higher code rates), which leads to a decrease in decoding performance. In other words, under the current parity check matrix acquisition mechanism (i.e., the parity check matrix acquisition mechanism shown in Figure 3), the reliability of the parity check matrix corresponding to some code rates is low, which can easily lead to a decrease in decoding performance (such as an increase in the bit error rate).

[0115] Furthermore, since encoding is based on a parity check matrix, the reliability of the parity check matrix also affects encoding performance (e.g., improved parity check matrix reliability leads to improved encoding performance). Therefore, improving encoding and decoding performance is an urgent problem to be solved.

[0116] In view of this, this application provides an encoding method and apparatus, in which a transmitting device can encode an information bit sequence based on a base matrix to obtain and output an encoded bit sequence. The base matrix can be divided into P matrix regions (i.e., the base matrix includes P matrix regions, each of the P matrix regions includes some or all of the rows of the base matrix, and there is no overlap between the P matrix regions, where P is an integer greater than or equal to 1). Within each matrix region, at least one row in the row with the smaller row weight is associated with a punched column in the base matrix (i.e., each matrix region has T rows, the row weight (row weight is the number of 1s (or non-zero elements) in a row) of any of the T rows is less than or equal to a first threshold, and at least one row in the T rows is associated with a punched column in the base matrix, where T is an integer greater than or equal to 1).

[0117] It is understandable that the smaller the row weight of the row associated with a punched column in the base matrix, the higher the reliability of the parity check matrix corresponding to that base matrix. Therefore, in the base matrix provided in this application, having the row with the smaller row weight associated with only one punched column can improve the reliability of the parity check matrix corresponding to that base matrix, thereby reducing the bit error rate and improving the encoding and decoding performance.

[0118] The encoding method and apparatus will be further described below with reference to the accompanying drawings. It is understood that this application uses the transmitting side and the receiving side as examples to illustrate the interaction. The transmitting side can be any terminal or access network device in the communication system shown in Figure 1, and correspondingly, the receiving side can be the access network device or any terminal in the communication system shown in Figure 1.

[0119] This application does not limit the subject of execution in the interactive illustrations. For example, the method executed by the access network device in this application can also be implemented by a module (e.g., circuit, chip, or chip system) in the access network device, or a logical node, logical module, or software that can implement all or part of the functions of the access network device. Alternatively, it can be implemented by a communication and / or computing module in the access network device, or a circuit or chip (e.g., a modem chip (also known as a baseband chip), or a system-on-a-chip (SoC) chip / system-in-a-package (SIP) chip containing a modem core, or a graphics processing unit (GPU) / AI processor / application-specific integrated circuit (ASIC)) in the access network device. Similarly, the method executed by the terminal in this application can also be implemented by a communication and / or computing module in the terminal, or a circuit or chip (e.g., a modem chip (also known as a baseband chip), or a SoC chip / SIP chip containing a modem core, or a GPU / AI processor / ASIC) in the terminal.

[0120] Referring to Figure 8, a flowchart illustrating an encoding method provided in an embodiment of this application is shown. As shown in Figure 8, taking the sending-side execution entity as the sending device and the receiving-side execution entity as the receiving device as an example, the method may include:

[0121] S801. The transmitting device encodes the information bit sequence according to the base matrix to obtain the encoded bit sequence.

[0122] The base matrix consists of P matrix regions. Each of the P matrix regions includes some or all of the rows of the base matrix. There is no overlap between the P matrix regions, and P is an integer greater than or equal to 1.

[0123] Each matrix region contains T rows, and at least one row in these T rows is associated with a punched column in the base matrix, where T is an integer greater than or equal to 1.

[0124] In one possible implementation, the row weight of any row in the T rows is less than or equal to a first threshold.

[0125] For example, in this possible implementation, each matrix region includes the following features: each matrix region contains T rows, the row weight of any row in the T rows is less than or equal to a first threshold, and at least one row in the T rows is associated with a punched column in the base matrix.

[0126] Each matrix region contains T rows, where the row weight of any row in the T rows is less than or equal to a first threshold, and at least one row in the T rows is associated with a punched column in the base matrix. This can also be understood as: each matrix region consists of at least one row of the base matrix, where at least one row contains T rows with a row weight less than or equal to the first threshold, and at least one row in the T rows is associated with a punched column in the base matrix.

[0127] It is understandable that for a row of elements, if the elements in the punched column of that row contain only one non-zero element (e.g., 1), then that row is associated with a punched column. For example, taking a base matrix with the first two punched columns as the first two columns and the base matrix having n columns as an example, for any row in the base matrix, the first two elements of that row are the elements in the punched column of the base matrix. Therefore, if a row is associated with a punched column in the base matrix, then the first two elements contain only one non-zero element (i.e., the first two elements include one non-zero element and one non-zero element); for example, the first two elements can be "10" or "01". Therefore, the existence of at least one row in rows T that is associated with a punched column in the base matrix can be understood as: at least one row in rows T contains only one non-zero element (e.g., 1) in the punched column of the base matrix.

[0128] Specifically, the first threshold includes, but is not limited to, any one of the following: 3, 4, 5, or 6.

[0129] In another possible implementation, the row weight of any row in the T rows is less than a first threshold.

[0130] For example, in this possible implementation, each matrix region includes the following features: each matrix region has T rows, the row weight of any row in the T rows is less than a first threshold, and at least one row in the T rows is associated with a punched column in the base matrix.

[0131] Each matrix region contains T rows, where the row weight of any row in the T rows is less than a first threshold, and at least one row in the T rows is associated with a punched column in the base matrix. This can also be understood as: each matrix region consists of at least one row of the base matrix, where at least one row contains T rows with a row weight less than the first threshold, and at least one row in the T rows is associated with a punched column in the base matrix.

[0132] For example, the implementation of "at least one row is associated with a punched column in the base matrix" and the first threshold can be found in the relevant description in one of the possible implementations above, and will not be repeated here.

[0133] For ease of description, the implementation of the basis matrix will be introduced below using the example of "the row weight of any row in row T is less than or equal to the first threshold". This will be explained uniformly here and will not be repeated.

[0134] For example, each of the P matrix regions includes some or all of the rows of the base matrix. There is no overlap between the P matrix regions. It can be understood that the base matrix can be divided by rows to obtain P matrix regions. When P is greater than 1, any two matrix regions in the P matrix regions contain completely different rows, and the row numbers of the rows contained in the two matrix regions in the base matrix are also completely different.

[0135] As an example, P is greater than 1, and each matrix region includes a portion of the rows of the base matrix.

[0136] Specifically, when P is greater than 1, taking a base matrix containing m rows as an example, the (p-1)th matrix region among the P matrix regions includes the m-th row in the base matrix. A Reaching the mth B The p-th matrix region includes the m-th matrix in the base matrix. C Reaching the mth D Line, where m A <m B <m C <m D And m D m is less than or equal to the row number of the last row of the basis matrix. A The row number is greater than or equal to the row number of the first row of the base matrix. That is, each matrix region includes a subset of rows from the base matrix. Where p = 1, 2, ..., P.

[0137] Taking a case where m is greater than 5 and the basis matrix can be divided into two regions by rows as an example, such that one region includes the first 4 rows of the basis matrix, and the other region includes the 5th to the last row of the basis matrix. In this case, P matrix regions are these two regions (i.e., P is greater than 1 and P equals 2).

[0138] As another example, P equals 1, and each matrix region includes some or all of the rows of the base matrix.

[0139] Specifically, when P equals 1, taking a basis matrix containing m rows as an example, the basis matrix can be divided into one region by rows, and this one region contains the basis matrix; that is, this one region is the basis matrix. In this case, the P matrix regions are this one region. Alternatively, the basis matrix can be divided into Q regions by rows, where each of the Q-1 regions consists of multiple rows with the same row weight (the row weight is the number of 1s (or non-zero elements) in a row); in this case, the P matrix regions are the remaining one region in the Q regions excluding the Q-1 regions.

[0140] Taking a case where m is greater than 5 and the basis matrix can be divided into two regions by rows as an example, where one region includes the first 4 rows of the basis matrix, and the other region includes the 5th to the last row of the basis matrix. If the first 4 rows of the basis matrix have the same row weight, then P matrix regions constitute the other region, and in this case, P equals 1.

[0141] Combining the two examples above, optionally, there exists a matrix region (such as the first matrix region) within the P matrix regions that includes the first X rows of the D part of the base matrix (or, it can also be considered as an incremental redundant region), where X takes the value of 1 or 2.

[0142] For example, taking base graph 1 as an example, the first two rows of the D part of its base matrix are the 5th and 6th rows; therefore, when the value of X is 1, the matrix region includes, but is not limited to, the 5th row; when the value of X is 2, the matrix region includes, but is not limited to, the 5th and 6th rows. Specifically, the implementation of the D part and the incremental redundancy region can be found in the description in the relevant technology, and will not be repeated here.

[0143] It is understandable that the first few rows of the incremental redundancy region of the base matrix usually include the row with the smallest row weight in the base matrix. Therefore, when dividing the matrix region, we can consider dividing these rows into the same matrix region. Thus, the row with the smallest row weight in this matrix region is also the row with the smallest row weight in the base matrix. This allows the row with the smallest row weight in the matrix region to be associated with only one punched column, thereby improving the reliability of the parity check matrix corresponding to the base matrix and thus improving the encoding and decoding performance.

[0144] Optionally, the transmitting device encodes the information bit sequence according to the base matrix to obtain an encoded bit sequence, including: the transmitting device encodes the information bit sequence according to the parity check matrix corresponding to the base matrix to obtain an encoded bit sequence.

[0145] For example, the implementation of determining the parity check matrix based on the base matrix and encoding the information bit sequence according to the parity check matrix can be found in the aforementioned introduction to LDPC codes, and will not be implemented here.

[0146] It should be noted that the phrase "encoding the information bit sequence based on the basis matrix" in this application can be interpreted in at least the following ways:

[0147] (1) Encode the information bit sequence according to the base matrix A. At this time, the transmitting device can encode the information bit sequence according to the parity check matrix corresponding to the base matrix A; that is, the transmitting device determines the parity check matrix according to the base matrix A, and then encodes the information bit sequence according to the parity check matrix.

[0148] (2) Encode the information bit sequence based on A' obtained by transforming the base matrix A. Here, the base matrix A' is obtained by transforming the base matrix A. At this time, the transmitting device encodes the information bit sequence according to the parity check matrix corresponding to the base matrix A', that is, the transmitting device determines the parity check matrix according to the base matrix A', and then encodes the information bit sequence according to the parity check matrix.

[0149] For example, basis matrix A' is obtained by performing row operations on basis matrix A, i.e., by exchanging rows in basis matrix A; or, basis matrix A' is obtained by performing column operations on basis matrix A, i.e., by exchanging columns in basis matrix A; or, basis matrix A' is obtained by performing both row and column operations on basis matrix A, i.e., by exchanging rows and columns in basis matrix A; this application does not impose any restrictions. Specifically, the aforementioned basis matrix A can be any basis matrix that satisfies the design principles described in this application, or, basis matrix A can be any basis matrix shown in the embodiments of this application (as shown in any one of Figures 9 to 16), this application does not impose any restrictions.

[0150] S802, The transmitting device outputs the encoded bit sequence; correspondingly, the receiving device obtains the bit sequence to be decoded.

[0151] Optionally, the transmitting device outputs an encoded bit sequence, including: modulating the encoded bit sequence to obtain a modulated symbol sequence, and outputting the modulated symbol sequence. Correspondingly, the receiving device acquires a bit sequence to be decoded, including: receiving a symbol sequence to be demodulated from the transmitting device, and demodulating the symbol sequence to be demodulated to obtain a bit sequence to be decoded.

[0152] The modulation symbol sequence output by the transmitting device may be affected by noise and other interference when transmitted through the channel, and the demodulated symbol sequence received by the receiving device is the modulation symbol sequence affected by noise and other interference.

[0153] S803. The receiving device decodes the bit sequence to be decoded according to the basis matrix to obtain the decoded bit sequence.

[0154] Optionally, the receiving device decodes the bit sequence to be decoded based on the base matrix to obtain a decoded bit sequence, including: the receiving device obtaining the information bits located in the punched column of the base matrix according to the parity check matrix corresponding to the base matrix; and decoding the bit sequence to be decoded based on the information bits and the parity check matrix to obtain the decoded bit sequence.

[0155] For example, step S803 is the decoding step corresponding to step S801; therefore, the decoded bit sequence obtained in step S803 corresponds to the information bit sequence. Specifically, the implementation of step S803 can be found in the relevant description of step S801, and will not be repeated here.

[0156] This application provides an encoding method and apparatus. A transmitting device can encode an information bit sequence based on a base matrix to obtain and output the encoded bit sequence. The base matrix can be divided into P matrix regions (i.e., the base matrix includes P matrix regions, each of the P matrix regions includes some or all rows of the base matrix, and there is no overlap between the P matrix regions, where P is an integer greater than or equal to 1). Within each matrix region, at least one row in the row with the smaller row weight is associated with a punched column in the base matrix (i.e., each matrix region has T rows, the row weight (the row weight is the number of 1s (or non-zero elements) in a row) of any of the T rows is less than or equal to a first threshold, and at least one row in the T rows is associated with a punched column in the base matrix, where T is an integer greater than or equal to 1).

[0157] It is understandable that the smaller the row weight of the row associated with a punched column in the base matrix, the higher the reliability of the parity check matrix corresponding to that base matrix. Therefore, in the base matrix provided in this application, having the row with the smaller row weight associated with only one punched column can improve the reliability of the parity check matrix corresponding to that base matrix, thereby reducing the bit error rate and improving the encoding and decoding performance.

[0158] The above is a general description of the encoding method provided in this application. The "base matrix" involved in step S801 above will be described in detail below.

[0159] Optionally, the T rows present in each matrix region can be determined based on the row weights of the rows contained within that matrix region. The value of T can include the following two possible implementations:

[0160] In one possible implementation, the value of T can be pre-agreed upon between the sending and receiving devices.

[0161] For example, in this possible implementation, the value of T can be predetermined by the sending device and informed to the receiving device, or it can be informed by the receiving device and the sending device, or it can be predefined by the protocol. This application does not limit this.

[0162] Optionally, in this possible implementation, the T rows existing in each matrix region can be the top T rows with the smallest row weight in that matrix region.

[0163] For example, the p-th matrix region among P matrix regions includes m p OK m p For example, if T > If the row weights are arranged in ascending order, then the T rows existing in the p-th matrix region are r1, r2, ..., r T At this point, the first threshold is greater than or equal to r. T The row weight. That is, in this possible implementation, the first threshold is determined based on the value of T.

[0164] In another possible implementation, the value of T can be determined based on a first threshold.

[0165] For example, in this possible implementation, the first threshold may be predetermined by the sending device and communicated to the receiving device, or it may be communicated by the receiving device and communicated to the sending device, or it may be predefined by the protocol, which is not limited in this application.

[0166] Optionally, in this possible implementation, the T rows existing in each matrix region can be some or all of the rows in the matrix region whose row weight is less than or equal to the first threshold.

[0167] For example, the p-th matrix region among P matrix regions includes mp rows. Taking mp > T as an example, if The rows with weights in ascending order, and the rows with weights less than or equal to the first threshold include r1, r2, ..., r W If W < mp, then the T rows existing in the p-th matrix region can be r1, r2, ..., r W Any T rows in the p-th matrix region can be r1, r2, ..., r W The first T rows with the smallest weight (i.e., r1, r2, ..., r) T (T≤W).

[0168] Combining the two possible implementations described above, optionally, the T rows in each matrix region include the row with the smallest row weight within that matrix region; for example, the T rows in each matrix region are the first T rows with the smallest row weight within that matrix region. In this case, the first threshold can be equal to the maximum row weight in those T rows.

[0169] For example, at least one row in the T rows can include all of the T rows; in this case, it can also be considered that each of the T rows is associated with a punched column in the basis matrix.

[0170] Optionally, the at least one row in the T rows includes the row with the smallest row weight in each matrix region. Since the at least one row is associated with a punched column in the base matrix, it can also be understood that the row in the T rows associated with a punched column in the base matrix (i.e., the at least one row) includes the row with the smallest row weight in the matrix region.

[0171] Optionally, each matrix region also contains L rows, and at least one row in these L rows is associated with multiple punched columns in the base matrix, where L is an integer greater than or equal to 1.

[0172] In one possible implementation, the row weight of any row in the L rows is greater than or equal to the second threshold.

[0173] For example, in this possible implementation, each matrix region also includes the following features: each matrix region has L rows, the row weight of any row in the L rows is greater than or equal to a second threshold, and at least one row in the L rows is associated with multiple punched columns in the base matrix.

[0174] Each matrix region also contains L rows, where the row weight of any row in the L rows is greater than or equal to the second threshold, and at least one row in the L rows is associated with multiple punched columns in the base matrix. This can also be understood as: each matrix region consists of at least one row of the base matrix, where at least one row contains L rows with a row weight greater than or equal to the second threshold, and at least one row in the L rows is associated with multiple punched columns in the base matrix.

[0175] It is understandable that for a row of elements, if there are multiple non-zero elements (e.g., 1) in the punched columns, then that row is associated with multiple punched columns. For example, taking a base matrix with the first two punched columns as the first two columns and the base matrix having n columns as an example, for any row in the base matrix, the first two elements of that row are the elements in the punched columns of the base matrix. Therefore, if that row is associated with multiple punched columns in the base matrix, then the first two elements include two non-zero elements; for example, the first two elements could be "11". Therefore, the existence of at least one row in L rows that is associated with multiple punched columns in the base matrix can be understood as: at least one row in L rows has multiple non-zero elements (e.g., 1) in the punched columns of the base matrix.

[0176] For example, the second threshold is greater than the first threshold. And the sum of L and T is less than or equal to the number of rows contained in the matrix region.

[0177] Specifically, the second threshold includes, but is not limited to, any one of the following: 9, 10, or 11.

[0178] In another possible implementation, the row weight of any row in the L rows is greater than the second threshold.

[0179] For example, in this possible implementation, each matrix region also includes the following features: each matrix region has L rows, the row weight of any row in the L rows is greater than the second threshold, and at least one row in the L rows is associated with multiple punched columns in the base matrix.

[0180] Each matrix region also contains L rows, where the row weight of any row in the L rows is greater than the second threshold, and at least one row in the L rows is associated with multiple punched columns in the base matrix. This can also be understood as: each matrix region consists of at least one row of the base matrix, where at least one row contains L rows with a row weight greater than the second threshold, and at least one row in the L rows is associated with multiple punched columns in the base matrix.

[0181] For example, the implementation of "at least one row is associated with multiple punched columns in the base matrix" and the second threshold can be found in the relevant description of one possible implementation above, and will not be repeated here.

[0182] For ease of description, the implementation of the basis matrix will be introduced below using the example of "the row weight of any row in L rows is greater than or equal to the second threshold". This will be explained uniformly here and will not be repeated.

[0183] For example, the value of T can be the same as or different from the value of L; similarly, the number of rows in row T that are associated with a punched column in the base matrix (i.e., at least one row in row T) can be the same as or different from the number of rows in row L that are associated with a punched column in the base matrix (i.e., at least one row in row L), and this application does not limit this.

[0184] Optionally, the L rows existing within each matrix region can be determined based on the row weights of the rows contained within that matrix region. The value of L can include the following two possible implementations:

[0185] In one possible implementation, the value of L can be pre-agreed upon between the sending and receiving devices.

[0186] For example, in this possible implementation, the value of L can be predetermined by the sending device and informed to the receiving device, or it can be informed by the receiving device and the sending device, or it can be predefined by the protocol. This application does not limit this.

[0187] Optionally, in this possible implementation, the L rows existing in each matrix region can be the top L rows with the largest row weight in that matrix region.

[0188] For example, the p-th matrix region among P matrix regions includes m p OK m p For example, if T > If the row weights are ordered from smallest to largest, then the L rows existing in the p-th matrix region are... At this point, the second threshold is less than or equal to The row weight. That is, in this possible implementation, the second threshold is determined based on the value of L.

[0189] In another possible implementation, the value of L can be determined based on a second threshold.

[0190] For example, in this possible implementation, the second threshold may be predetermined by the sending device and communicated to the receiving device, or it may be communicated by the receiving device and communicated to the sending device, or it may be predefined by the protocol; this application does not limit this.

[0191] Optionally, in this possible implementation, the L rows existing in each matrix region can be some or all of the rows in the matrix region whose row weight is greater than or equal to the second threshold.

[0192] For example, the p-th matrix region among P matrix regions includes mp rows. Taking mp > L as an example, if The row weights are ordered from smallest to largest, and the rows that are greater than or equal to the second threshold include... If Z > 1, then the L rows existing in the p-th matrix region can be... Any L rows in the p-th matrix region can be... The first L rows with the largest weight (i.e.) L≥Z).

[0193] Combining the two possible implementations described above, optionally, the L rows in each matrix region include the row with the highest row weight within that matrix region; for example, the L rows in each matrix region are the top L rows with the highest row weight within that matrix region. In this case, the second threshold can be equal to the minimum row weight among those L rows.

[0194] For example, at least one row in the L rows can include all of the L rows; in this case, it can also be considered that the L rows are all associated with multiple punched columns in the basis matrix.

[0195] Optionally, the at least one row in the L rows includes the row with the largest row weight in each matrix region. Since the at least one row is associated with multiple punched columns in the base matrix, it can also be understood that the row in the L rows associated with multiple punched columns in the base matrix (i.e., the at least one row) includes the row with the largest row weight in the matrix region.

[0196] In some embodiments, the basis matrix of this application can be obtained by adjusting the matrix of the current base graph 1. For example, the matrix of base graph 1 is divided into rows to obtain a matrix region, which is the matrix of base graph 1. Further, the T rows with smaller row weights in the matrix of base graph 1 are associated with one punched column in the matrix of base graph 1 to obtain the basis matrix; or, the T rows with smaller row weights in the matrix of base graph 1 are associated with one punched column in the matrix of base graph 1, and the L rows with larger row weights in the matrix of base graph 1 are associated with multiple punched columns in the matrix of base graph 1 to obtain the basis matrix.

[0197] It is understandable that in the matrix of base graph 1, the punched columns are the first two columns, and the row with the smallest row weight is the fifth row. Furthermore, the sixth row also has a relatively small row weight. Therefore, the base matrix can include several possible implementations, such as:

[0198] In the first possible implementation, T equals 1, and in this case, the 5th row of the basis matrix is ​​associated with only one punched column in the basis matrix.

[0199] Optionally, since the 5th row of base graph 1 is associated with the two punched columns, the connection in the 5th row and 1st column of the matrix of base graph 1 (i.e., the association between the element in the 5th row and 1st column and the parity check matrix) can be deleted, for example, by setting the value of the element in the 5th row and 1st column to 0, to obtain the base matrix; or, the connection in the 5th row and 2nd column of the matrix of base graph 1 (i.e., the association between the element in the 5th row and 2nd column and the parity check equation) can be deleted, for example, by setting the value of the element in the 5th row and 2nd column to 0, to obtain the base matrix.

[0200] Specifically, when the edge in the 5th row and 1st column is deleted, the basis matrix can be as shown in Figure 9. The row weight of each row in the basis matrix and the position of the non-zero element in that row are shown in Table 1.

[0201] Table 1

[0202] When the edge in row 5 and column 2 is deleted, the basis matrix can be as shown in Figure 10. The row weight of each row in the basis matrix and the position of the non-zero element in that row are shown in Table 2.

[0203] Table 2

[0204] For example, to further improve decoding performance, row weights in the 5th row of the matrix in base graph 1 can be increased. For instance, edges can be added to some columns in the 5th row, such as adding edges to one or more columns in the 24th, 25th, and 26th columns of the 5th row (e.g., setting the element value of one or more columns in the 24th, 25th, and 26th columns of the 5th row to 1).

[0205] Specifically, when adding the edge between the 24th and 25th columns of the 5th row, the basis matrix can be as shown in Figure 11. The row weight of each row in the basis matrix and the position of the non-zero element in that row are shown in Table 3.

[0206] Table 3

[0207] When adding the edge in the 5th row and columns 24, 25, and 26, the basis matrix can be as shown in Figure 12. The row weight of each row in the basis matrix and the position of the non-zero element in that row are shown in Table 4.

[0208] Table 4

[0209] In the second possible implementation, T equals 2, and in this case, the 5th and 6th rows of the basis matrix are each associated with only one punched column in the basis matrix.

[0210] Optionally, since rows 5 and 6 of base graph 1 are both associated with two punched columns, the edges connecting rows 5 and 1 and rows 6 and 1 of the matrix of base graph 1 can be deleted to obtain the base matrix; or, the edges connecting rows 5 and 2 and rows 6 and 2 of the matrix of base graph 1 can be deleted to obtain the base matrix; or, the edges connecting rows 5 and 1 and rows 6 and 2 of the matrix of base graph 1 can be deleted to obtain the base matrix; or, the edges connecting rows 5 and 2 and rows 6 and 1 of the matrix of base graph 1 can be deleted to obtain the base matrix.

[0211] Specifically, when the edge in row 5, column 1 is deleted, and the edge in row 6, column 2 is deleted, the basis matrix can be as shown in Figure 13. The row weight of each row in the basis matrix and the position of the non-zero element in that row are shown in Table 5.

[0212] Table 5

[0213] For example, to further improve decoding performance, row weights in rows 5 and / or 6 of the matrix in base graph 1 can be increased. For instance, edges can be added to some columns in row 5, such as adding edges to one or more columns in rows 24, 25, and 26 (e.g., setting the element value of one or more columns in rows 24, 25, and 26 to 1), to obtain the base matrix. Alternatively, edges can be added to some columns in row 6, such as adding edges to columns 3-26 in row 6 (e.g., setting the element value of one or more columns in rows 3-26 to 1), to obtain the base matrix. Or, edges can be added to both rows 5 and rows 6 to obtain the base matrix.

[0214] Specifically, when deleting the edge in row 5, column 2, deleting the edge in row 6, column 1, and adding the edge in row 5, column 26, the basis matrix can be as shown in Figure 14. The row weight of each row in the basis matrix and the position of the non-zero element in that row are shown in Table 6.

[0215] Table 6

[0216] Specifically, when deleting the edge in row 5, column 1, deleting the edge in row 6, column 2, and adding the edge in row 6, columns 25 and 26, the basis matrix can be as shown in Figure 15. The row weight of each row in the basis matrix and the position of the non-zero element in that row are shown in Table 7.

[0217] Table 7

[0218] When the edge in row 5, column 2 is deleted, the edge in row 6, column 1 is deleted, and the edge in row 5, columns 24, 25, and 26 is added, and the edge in row 6, column 10 is added, the basis matrix can be as shown in Figure 16. The row weight of each row in the basis matrix and the position of the non-zero element in that row are shown in Table 8.

[0219] Table 8

[0220] It is understandable that the above example only shows the positions of non-zero elements in the basis matrix, and the positions not shown are the zero elements in the basis matrix.

[0221] It should be noted that the above example uses a 46-row, 68-column matrix to illustrate a partial implementation of the base matrix described in this application. This does not mean that the base matrix described in this application only includes the content shown in the above example. In fact, the base matrix described in this application can have any other possible implementation besides the above example. For example, the number of rows in the base matrix described in this application can be greater than 46 or less than 46. Similarly, the number of rows in the base matrix described in this application can be greater than 68 or less than 68. This application does not impose any restrictions.

[0222] Furthermore, in the example above, the row number of the first row is 1, so the row numbers of the Y-row basis matrix are 1 to Y. In fact, the row number of the first row in the basis matrix described in this application can also be other values ​​W, so the row numbers of the Y-row basis matrix are W to Y+W-1; where Y is a positive integer and W is a natural number. For example, W can be 0, in which case the row numbers of the Y-row basis matrix are 0 to Y-1, such as the row numbers of the 46-row basis matrix being 0-45.

[0223] Similarly, in the example above, the column number of the first column is 1, so the column numbers of the M-column basis matrix are 1 to M. In fact, the column number of the first column in the basis matrix described in this application can also be other values ​​N, so the column numbers of the M-column basis matrix are N to M+N-1; where M is a positive integer and N is a natural number. For example, N can be 0, in which case the row numbers of the M-column basis matrix are 0 to N-1, such as the column numbers of a 68-column basis matrix being 0-67.

[0224] Figure 17 illustrates a possible exemplary block diagram of the communication device involved in the embodiments of this application. As shown in Figure 17, the communication device 1700 may include modules or units for implementing the method embodiments described above. In one possible design, the communication device 1700 includes a processing unit 1702 and a communication unit 1703. Optionally, the communication device 1700 may further include a storage unit 1701 for storing device program code and / or data.

[0225] The communication device 1700 can be the transmitting side device in the above embodiments, such as a transmitting end device (such as a terminal or access network device) or a communication module in the transmitting end device, or a circuit or chip in the transmitting end device responsible for communication functions.

[0226] For example, in one embodiment, processing unit 1702 is used to: encode the information bit sequence according to the base matrix to obtain an encoded bit sequence. Communication unit 1703 is used to: output the encoded bit sequence. The base matrix includes P matrix regions, each of the P matrix regions includes some or all rows of the base matrix, and there is no overlap between the P matrix regions, where P is an integer greater than or equal to 1; each matrix region contains T rows, the row weight of any row in the T rows is less than or equal to a first threshold, and at least one row in the T rows is associated with a punched column in the base matrix, where T is an integer greater than or equal to 1.

[0227] In one possible design, the first threshold is equal to the minimum row weight in each matrix region, and at least one row in the T rows includes the row with the minimum row weight in each matrix region.

[0228] In one possible design, each matrix region also contains L rows, where the row weight of any row in the L rows is greater than or equal to a second threshold, and at least one row in the L rows is associated with multiple punched columns in the base matrix, where L is an integer greater than or equal to 1.

[0229] In one possible design, the second threshold is equal to the maximum row weight in each matrix region, and at least one row in the L rows includes the row with the maximum row weight in each matrix region.

[0230] In one possible design, P equals 1, and each matrix region includes some or all of the rows of the base matrix.

[0231] In one possible design, P is greater than 1, and each matrix region includes a portion of the rows of the base matrix.

[0232] In one possible design, the first matrix region within the P matrix regions includes the first X rows of the incremental redundant region of the base matrix, where X takes the value of 1 or 2.

[0233] The communication device 1700 can be the receiving side device in the above embodiments, such as a receiving end device (such as a terminal or access network device) or a communication module in the receiving end device, or a circuit or chip in the receiving end device responsible for communication functions.

[0234] For example, in one embodiment, the processing unit 1702 is used to obtain the bit sequence to be decoded; and decode the bit sequence to be decoded according to the basis matrix to obtain the decoded bit sequence. The basis matrix includes P matrix regions, each of the P matrix regions includes some or all rows of the basis matrix, and there is no overlap between the P matrix regions, where P is an integer greater than or equal to 1; each matrix region contains T rows, the row weight of any row in the T rows is less than or equal to a first threshold, and at least one row in the T rows is associated with a punched column in the basis matrix, where T is an integer greater than or equal to 1.

[0235] In one possible design, the first threshold is equal to the minimum row weight in each matrix region, and at least one row in the T rows includes the row with the minimum row weight in each matrix region.

[0236] In one possible design, each matrix region also contains L rows, where the row weight of any row in the L rows is greater than or equal to a second threshold, and at least one row in the L rows is associated with multiple punched columns in the base matrix, where L is an integer greater than or equal to 1.

[0237] In one possible design, the second threshold is equal to the maximum row weight in each matrix region, and at least one row in the L rows includes the row with the maximum row weight in each matrix region.

[0238] In one possible design, P equals 1, and each matrix region includes some or all of the rows of the base matrix.

[0239] In one possible design, P is greater than 1, and each matrix region includes a portion of the rows of the base matrix.

[0240] In one possible design, the first matrix region within the P matrix regions includes the first X rows of the incremental redundant region of the base matrix, where X takes the value of 1 or 2.

[0241] Combining the two implementations of the communication device 1700 described above, in one possible design, when the communication device 1700 is a terminal or a communication module within a terminal, the function of the processing unit 1702 can be implemented by one or more processors. Specifically, the processor may include a modem chip, or a system-on-a-chip (SoC) chip or a SIP chip containing a modem core. The function of the communication unit 1703 can be implemented by a transceiver circuit.

[0242] In one possible design, when the communication device 1700 is a circuit or chip in a terminal responsible for communication functions, such as a modem chip or a system-on-a-chip (SoC) or SIP chip containing a modem core, the function of the processing unit 1702 can be implemented by a circuit system in the aforementioned chip that includes one or more processors or processor cores. The function of the communication unit 1703 can be implemented by an interface circuit or data transceiver circuit on the aforementioned chip.

[0243] In one possible design, when the communication device 1700 is a terminal or a computing module within a terminal, the functionality of the processing unit 1702 can be implemented by one or more processors. Specifically, the processor may include a GPU, or a system-on-a-chip (SoC) or SIP chip containing a GPU. Alternatively, the processor may include an AI processor, or a SoC or SIP chip containing an AI processor. Or, the processor may include an ASIC, or a SoC or SIP chip containing an ASIC. The functionality of the communication unit 1703 can be implemented by transceiver circuitry.

[0244] In one possible design, when the communication device 1700 is a circuit or chip in a terminal responsible for computing functions, such as a GPU or a system-on-a-chip (SoC) or SIP chip containing a GPU, an AI processor or a SoC or SIP chip containing an AI processor, or an ASIC or a SoC or SIP chip containing an ASIC, the function of the processing unit 1702 can be implemented by a circuit system in the aforementioned chip that includes one or more processors or processor cores. The function of the communication unit 1703 can be implemented by interface circuitry or data transceiver circuitry on the aforementioned chip.

[0245] It is understood that the division of units in the above-described device is merely a logical functional division. One function can correspond to one functional unit, or two or more functions can be integrated into one functional unit. In actual implementation, all or some units can be integrated onto a single physical entity, or distributed across different physical entities. Furthermore, the aforementioned functional units can be implemented in hardware, software, or a combination of both. Whether a function is executed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for specific applications, but such implementations should not be considered beyond the scope of this application.

[0246] In one example, the functional unit in any of the above devices may be one or more integrated circuits configured to implement the above methods, such as: one or more ASICs, or one or more central processing units (CPUs), one or more microcontroller units (MCUs), one or more digital signal processors (DSPs), or one or more field programmable gate arrays (FPGAs), or a combination of at least two of these integrated circuit forms.

[0247] In one example, storage unit 1701 may include random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory and / or registers, etc.

[0248] Optionally, when the transmitting device and / or receiving device is a terminal, its structural diagram can be as shown in Figure 18. The terminal 1800 in Figure 18 can correspond to any of the terminals shown in Figures 1 to 3, and is used to implement the operation of the terminal in the above embodiments. As shown in Figure 18, the terminal includes: one or more antennas 1810, a radio frequency processing system 1820, and a processor system 1830.

[0249] In the downlink or sidelink direction, the RF processing system 1820 receives RF signals through the antenna 1810 and sends the RF-processed signals to the processor system 1830 for further processing. In the uplink or sidelink direction, the processor system 1830 processes the terminal-side information and sends it to the RF processing system 1820, which then processes the signal and transmits it through the antenna 1810.

[0250] In one example, the radio frequency (RF) processing system 1820 serves as the communication interface for external communication of the terminal and may include an RF front end (RFFE) 1821 and an RF transceiver 1822. The RFFE 1821 is primarily used for one or more processing operations, such as shaping, passband selection, or gain adjustment, on the RF signals received by the antenna or those to be transmitted through the antenna. It may include one or more components such as RF switches, duplexers, filters, power amplifiers, antenna tuners, and low-noise amplifiers. The RFFE 1821 can be a circuit system composed of multiple discrete components or integrated into one or more chips. The RF transceiver 1822 processes the RF signals received by the RFFE into baseband / IF signals for further processing by the processor system 1830, and processes the baseband / IF signals provided by the processor system 1830 into RF signals for transmission to the RFFE 1821. The baseband / IF signals transmitted between the RF transceiver 1822 and the processor system 1830 can be digital or analog signals. The 1822 radio frequency transceiver can be implemented by one or more chips, which are usually referred to as radio frequency integrated circuits (RFICs).

[0251] In one example, processor system 1830 may include one or more processors for processing signals and executing one or more communication protocols. Optionally, processor system 1830 may also include memory 1836. In one example, the one or more processors include at least one baseband processor 1831 (also known as a modem processor). Memory 1836 is used to store data and / or computer program instructions. Optionally, processor system 1830 may also include one or more application processors 1832 for implementing processing of the terminal operating system and application layer. Application processor 1832 may include, for example, a GPU, AI processor, or ASIC. Optionally, processor system 1830 may also include one or more of a voice subsystem 1833, a multimedia subsystem 1834, or an interface circuit 1835. The voice subsystem 1833 is used to process voice signals, the multimedia subsystem 1834 is used to handle multimedia-related operations, such as video encoding / decoding, image processing, etc., and the interface circuit 1835 is used to implement communication with other terminal components, such as a display 1840, an input device 1850, memory 1860, etc. The aforementioned components in the processor system 1830 can communicate with each other via a bus or communication interface circuit.

[0252] In one example, the processor system 1830 can be packaged as a single processor chip, such as a SoC chip or a SIP chip. In another example, the processor system 1830 can be a system composed of multiple chips; for example, the baseband processor 1831 can be packaged as a single chip, or packaged with part or all of the circuitry of the radio frequency processing system into a single chip.

[0253] In one example, memory 1836 can be on-chip memory, i.e., located on the processor system 1830 chip. In another example, memory 1860 can be off-chip memory, i.e., located outside the processor system 1830 chip.

[0254] In one example, the baseband processor 1831 may include one or more processor cores 18311 and interface circuitry 18314. The one or more processor cores 18311 are used to process signals and execute one or more communication protocols. Optionally, the baseband processor 1831 may also include a memory 18312 for storing at least a portion of the corresponding computer program instructions and / or data. In one example, the one or more processor cores 18311 implement the relevant operations in the above method embodiments (such as the encoding method shown in FIG8) by executing the computer program instructions stored in the memory 18312. In this disclosure, memory 18312 is used to store corresponding computer program instructions and / or data. This can mean that memory 18312 stores all corresponding computer program instructions and / or data for execution by processor core 18311; or it can mean that memory 18312 stores a portion of corresponding computer program instructions and / or data, including the computer program instructions and / or data currently required to be executed by processor core 18311. Memory 18312 can store different portions of computer program instructions and / or data multiple times for execution by processor core 18311 to implement the relevant operations in the above method embodiments. Interface circuit 18314 serves as a communication interface for communication with other components, such as transmitting signals with radio frequency processing system 1820, communicating with other subsystems and related components of processor system 1830 via a bus, such as transmitting data control signals with application processor 1832, and transmitting data or computer program instructions with memory 1836 or memory 1860. Optionally, in order to reduce the load on the processor core, a baseband signal processing circuit 18313 can be set to perform at least some baseband signal processing, including one or more of signal demodulation, modulation, encoding or decoding.

[0255] In one example, the communication device provided in this application may be a terminal 1800, a communication module including a processor system 1830 and a radio frequency system 1820, or a baseband processor 1831.

[0256] The processor, processor system, application processor, baseband processor, processor circuit or processor core mentioned above can be collectively referred to as a processor. The processor may include one or more of the following: CPU, DSP, microprocessor unit (MPU), MCU, GPU, FPGA, ASIC, artificial intelligence processor (AI processor) or neural processing unit (NPU).

[0257] The aforementioned memory may include one or more of the following storage media: random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), phase-change memory (PCM), resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), cache, register, read-only memory (ROM), flash memory, erasable programmable read-only memory (EPROM), hard disk, etc. In one example, computer program instructions for executing the above embodiments may be stored on non-volatile memory, such as at least a portion of the aforementioned memory 1860 (e.g., one or more of ROM, flash memory, EPROM, or hard disk). When the terminal is running, the corresponding computer program instructions may be partially or wholly loaded onto a memory with a faster transfer speed than the processor, such as at least a portion of memory 1836 and / or memory 18312 (e.g., one or more of RAM, SRAM, DRAM, PCM, RERAM, MRAM, FRAM, cache, or register), for the processor to execute in order to implement the steps in the above method embodiments.

[0258] In one example, the RF transceiver 1822 and the RF front-end 1821 can also be packaged in a single chip. In another example, the RF transceiver 1822, the RF front-end 1821, and the baseband processor 1831 can also be packaged in a single chip.

[0259] The terms "system" and "network" in this application embodiment are used interchangeably. "At least one" refers to one or more, and "multiple" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, "at least one of A, B, or C" includes A, B, C, AB, AC, BC, or ABC; "at least one of A, B, and C" can also be understood as including A, B, C, AB, AC, BC, or ABC. Furthermore, unless otherwise specified, the ordinal numbers such as "first" and "second" mentioned in this application embodiment are used to distinguish multiple objects and are not used to limit the order, sequence, priority, or importance of multiple objects.

[0260] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, etc.) containing computer-usable program code.

[0261] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or one or more blocks of the block diagrams.

[0262] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0263] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

[0264] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. An encoding method, characterized in that, The method includes: The information bit sequence is encoded using the basis matrix to obtain the encoded bit sequence. Output the encoded bit sequence; Wherein, the base matrix includes P matrix regions, each of the P matrix regions includes some or all of the rows of the base matrix, and there is no overlap between the P matrix regions, where P is an integer greater than or equal to 1; Each matrix region contains T rows, the row weight of any row in the T rows is less than or equal to a first threshold, and at least one row in the T rows is associated with a punched column in the base matrix, where T is an integer greater than or equal to 1.

2. A decoding method, characterized in that, The method includes: Obtain the bit sequence to be decoded; The bit sequence to be decoded is decoded according to the basis matrix to obtain the decoded bit sequence; Wherein, the base matrix includes P matrix regions, each of the P matrix regions includes some or all of the rows of the base matrix, and there is no overlap between the P matrix regions, where P is an integer greater than or equal to 1; Each matrix region contains T rows, the row weight of any row in the T rows is less than or equal to a first threshold, and at least one row in the T rows is associated with a punched column in the base matrix, where T is an integer greater than or equal to 1.

3. The method according to claim 1 or 2, characterized in that, The first threshold is equal to the minimum row weight in each matrix region, and the at least one row in the T rows includes the row with the minimum row weight in each matrix region.

4. The method according to any one of claims 1-3, characterized in that, Each matrix region also contains L rows, where the row weight of any row in the L rows is greater than or equal to the second threshold, and at least one row in the L rows is associated with multiple punched columns in the base matrix, where L is an integer greater than or equal to 1.

5. The method according to claim 4, characterized in that, The second threshold is equal to the maximum row weight in each matrix region, and the at least one row in the L rows includes the row with the maximum row weight in each matrix region.

6. The method according to any one of claims 1-5, characterized in that, The P is equal to 1, and each matrix region includes some or all of the rows of the base matrix.

7. The method according to any one of claims 1-5, characterized in that, Where P is greater than 1, each matrix region includes a portion of the rows of the base matrix.

8. The method according to any one of claims 1-7, characterized in that, The first matrix region within the P matrix regions includes the first X rows of the incremental redundant region of the base matrix, where X takes the value of 1 or 2.

9. An encoding method, characterized in that, The method includes: The information bit sequence is encoded using the basis matrix to obtain the encoded bit sequence. Output the encoded bit sequence; The basis matrix includes multiple non-zero elements (i,j), where i is the row number and j is the column number; i=1, j=1, 2, 3, 4, 6, 7, 10, 11, 12, 13, 14, 16, 17, 19, 20, 21, 22, 23, 24; i=2, j=1, 3, 4, 5, 6, 8, 9, 10, 12, 13, 15, 16, 17, 18, 20, 22, 23, 24, 25; i=3, j=1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 14, 15, 16, 18, 19, 20, 21, 25, 26; i=4, j=1, 2, 4, 5, 7, 8, 9, 11, 12, 13, 14, 15, 17, 18, 19, 21, 22, 23, 26; i = 5, j = 2, 27; The other elements in the above row are zero elements.

10. An encoding method, characterized in that, The method includes: The information bit sequence is encoded using the basis matrix to obtain the encoded bit sequence. Output the encoded bit sequence; The basis matrix includes multiple non-zero elements (i,j), where i is the row number and j is the column number; i=1, j=1, 2, 3, 4, 6, 7, 10, 11, 12, 13, 14, 16, 17, 19, 20, 21, 22, 23, 24; i=2, j=1, 3, 4, 5, 6, 8, 9, 10, 12, 13, 15, 16, 17, 18, 20, 22, 23, 24, 25; i=3, j=1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 14, 15, 16, 18, 19, 20, 21, 25, 26; i=4, j=1, 2, 4, 5, 7, 8, 9, 11, 12, 13, 14, 15, 17, 18, 19, 21, 22, 23, 26; i = 5, j = 1, 27; The other elements in the above row are zero elements.

11. An encoding method, characterized in that, The method includes: The information bit sequence is encoded using the basis matrix to obtain the encoded bit sequence. Output the encoded bit sequence; The basis matrix includes multiple non-zero elements (i,j), where i is the row number and j is the column number; i=1, j=1, 2, 3, 4, 6, 7, 10, 11, 12, 13, 14, 16, 17, 19, 20, 21, 22, 23, 24; i=2, j=1, 3, 4, 5, 6, 8, 9, 10, 12, 13, 15, 16, 17, 18, 20, 22, 23, 24, 25; i=3, j=1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 14, 15, 16, 18, 19, 20, 21, 25, 26; i=4, j=1, 2, 4, 5, 7, 8, 9, 11, 12, 13, 14, 15, 17, 18, 19, 21, 22, 23, 26; i=5, j=2, 24, 25, 27; The other elements in the above row are zero elements.

12. An encoding method, characterized in that, The method includes: The information bit sequence is encoded using the basis matrix to obtain the encoded bit sequence. Output the encoded bit sequence; The basis matrix includes multiple non-zero elements (i,j), where i is the row number and j is the column number; i=1, j=1, 2, 3, 4, 6, 7, 10, 11, 12, 13, 14, 16, 17, 19, 20, 21, 22, 23, 24; i=2, j=1, 3, 4, 5, 6, 8, 9, 10, 12, 13, 15, 16, 17, 18, 20, 22, 23, 24, 25; i=3, j=1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 14, 15, 16, 18, 19, 20, 21, 25, 26; i=4, j=1, 2, 4, 5, 7, 8, 9, 11, 12, 13, 14, 15, 17, 18, 19, 21, 22, 23, 26; i = 5, j = 2, 27; i=6, j=1, 4, 13, 17, 22, 13, 28; The other elements in the above row are zero elements.

13. A communication device, characterized in that, The communication device includes a unit for performing the method of any one of claims 1, 3-8; or, the communication device includes a unit for performing the method of any one of claims 2-8; or, the communication device includes a unit for performing the method of claim 9; or, the communication device includes a unit for performing the method of claim 10; or, the communication device includes a unit for performing the method of claim 11; or, the communication device includes a unit for performing the method of claim 12.

14. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions or programs that, when executed, cause the method as described in any one of claims 1, 3-8, or the method as described in any one of claims 2-8, or the method as described in claim 9, or the method as described in claim 10, or the method as described in claim 11, or the method as described in claim 12 to be executed.

15. A computer program product, characterized in that, The computer program product includes computer instructions; when some or all of the computer instructions are executed, they cause the method as described in any one of claims 1, 3-8 to be performed, or the method as described in any one of claims 2-8 to be performed, or the method as described in claim 9 to be performed, or the method as described in claim 10 to be performed, or the method as described in claim 11 to be performed, or the method as described in claim 12 to be performed.

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