Control circuit, hard disk startup circuit, electronic device, and staggered startup control method

Abstract

The present application provides a control circuit, a hard disk startup circuit, an electronic device, and a staggered startup control method, which can be applied to the technical field of hard disk staggered power-on. The control circuit comprises: a backplane execution circuit and a backplane control circuit. The backplane execution circuit is connected to the backplane control circuit and is used to control the backplane control circuit to be powered on and operate. The backplane control circuit comprises at least two groups of signal transmission ends, which are separately connected to corresponding hard disks. Any of the groups of signal transmission ends is used for sending a startup signal to the corresponding hard disk, and when a hard disk signal fed back by the corresponding hard disk indicates that the hard disk has started up, any of the remaining groups of signal transmission ends is used for sending a startup signal to the corresponding hard disk, until all of the hard disks have performed a startup procedure. Hence, in the present application, during the process of controlling the hard disks to be powered on and start up, the startup signal is first sent to any of the hard disks, and after the hard disk has started up, the startup signal is sent to any of the remaining hard disks, thereby reducing the design costs of a staggered circuit.

Description

Control circuit, hard disk boot circuit, electronic equipment and peak-shaving boot control method

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. CN202510067504.3, filed on January 16, 2025, entitled "Control Circuit, Hard Disk Startup Circuit, Electronic Device and Off-Peak Startup Control Method", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of hard disk staggered power-on technology, and in particular to control circuits, hard disk boot circuits, electronic devices, and staggered boot control methods. Background Technology

[0004] With the development of big data technology, electronic devices (such as storage servers) have rapidly advanced, and their performance is becoming increasingly higher. As a primary component of storage systems, the performance of hard drives is particularly important, and the reliability of hard drive power supply is a fundamental condition for their normal operation. In storage servers, to prevent large inrush currents during hard drive startup, multiple hard drives are typically required to be started at staggered times.

[0005] In recent years, in order to achieve staggered startup of multiple hard drives in storage servers, a separate startup circuit has been configured for each hard drive on the hard drive backplane. This practice has greatly increased the cost of storage servers.

[0006] It is evident that the staggered startup circuit for controlling hard drives in related technologies suffers from the technical problem of high design costs. Summary of the Invention

[0007] The purpose of this application is to provide a control circuit, a hard disk boot circuit, an electronic device, and a staggered boot control method, which can solve the cost problem caused by configuring a boot circuit for each hard disk in order to achieve staggered boot of hard disks in related technologies.

[0008] To solve the above-mentioned technical problems, according to a first aspect, this application provides a control circuit applied to a hard disk backplane, including: a backplane execution circuit and a backplane control circuit;

[0009] The backplane execution circuit is connected to the backplane control circuit and is used to control the power-on operation of the backplane control circuit.

[0010] The backplane control circuit includes at least two sets of signal transmission terminals, which are connected to the corresponding hard drives respectively. A start signal is sent to the corresponding hard drive through any one set of signal transmission terminals. When the hard drive signal fed back by the corresponding hard drive indicates that the hard drive is starting, a start signal is sent to the corresponding hard drive through the remaining set of signal transmission terminals until all hard drives have started the startup process.

[0011] In some embodiments, a boot signal is sent to the corresponding hard drive through any of the remaining set of signal transmission terminals until all hard drives initiate the boot process, including:

[0012] A boot signal is sent to the corresponding hard drive from any set of signal transmission terminals that has not sent a boot signal before, until the hard drives start the boot process in the order in which the boot signals are received.

[0013] In some embodiments, the backplane execution circuitry is a first programmable memory;

[0014] The output of the first programmable memory is connected to the first end of each hard disk.

[0015] The status signal terminal of the first programmable memory is connected to the first terminal of the backplane control circuit.

[0016] The enable signal terminal of the first programmable memory is connected to the second terminal of the backplane control circuit.

[0017] The input terminal of the first programmable memory is connected to the power supply.

[0018] In some embodiments, the backplane execution circuit further includes: a first resistor, a second resistor, a third resistor, a first capacitor, and a second capacitor;

[0019] The first end of the first resistor is connected to the output terminal of the first programmable memory, and the second end of the first resistor is connected to the status signal terminal of the first programmable memory, the first end of the second resistor, and the first end of the first capacitor.

[0020] The second terminal of the second resistor is connected to the first terminal of the first capacitor and grounded;

[0021] The first terminal of the third resistor is connected to the enable signal terminal of the first programmable memory and the first terminal of the second capacitor.

[0022] The second terminal of the third resistor is connected to the second terminal of the second capacitor and grounded.

[0023] In some embodiments, the backplane control circuit is a complex programmable logic device;

[0024] The status signal input terminal of the complex programmable logic device is connected to the status signal terminal of the first programmable memory as the first terminal of the backplane control circuit.

[0025] The enable signal input terminal of the complex programmable logic device is connected to the enable signal terminal of the first programmable memory as the second terminal of the backplane control circuit.

[0026] Each enable signal detection terminal of the complex programmable logic device is connected to the second terminal of the corresponding hard disk;

[0027] Each in-situ signal detection terminal of the complex programmable logic device is connected to the third terminal of the corresponding hard disk;

[0028] Each state signal detection terminal of the complex programmable logic device is connected to the fourth terminal of the corresponding hard disk; wherein, each enable signal detection terminal, each in-situ signal detection terminal, and each state signal detection terminal of the complex programmable logic device constitute each group of signal transmission terminals of the backplane control circuit.

[0029] According to the second aspect, this application also provides a hard disk boot circuit, applied to a hard disk, including: a hard disk execution circuit and a hard disk control circuit;

[0030] The hard drive control circuit is connected to the hard drive backplane and is used to determine the boot time based on the boot signal sent by the hard drive backplane, and to determine the drive signal based on the boot signal.

[0031] The hard disk execution circuit is connected to the hard disk control circuit and the hard disk backplane respectively. It is used to determine the corresponding hard disk signal based on the drive signal and send the hard disk signal to the hard disk backplane so that when the hard disk backplane determines that the hard disk signal indicates that the hard disk is starting, it sends a start signal to the other hard disk start circuits.

[0032] In some embodiments, the hard disk execution circuit is a second programmable memory;

[0033] The input terminal of the second programmable memory is connected to the first terminal of the hard disk control circuit and the first terminal of the hard disk backplane.

[0034] The status signal terminal of the second programmable memory is connected to the second terminal of the hard disk backplane.

[0035] The enable signal terminal of the second programmable memory is connected to the second terminal of the hard disk control circuit.

[0036] In some embodiments, the hard disk execution circuit further includes: a fourth resistor, a fifth resistor, and a third capacitor;

[0037] The first end of the fourth resistor is connected to the output of the second programmable memory.

[0038] The second terminal of the fourth resistor is connected to the status signal terminal of the second programmable memory, the first terminal of the fifth resistor, and the first terminal of the third capacitor.

[0039] The second terminal of the fifth resistor is connected to the second terminal of the third capacitor and grounded.

[0040] In some embodiments, the hard disk control circuit includes: a comparator, an AND logic operation unit, a first metal-oxide-semiconductor field-effect transistor (MOSFET), a Zener diode, and a sixth resistor;

[0041] The non-inverting input of the comparator is connected to the first terminal of the sixth resistor, and together they serve as the first terminal of the hard disk control circuit connected to the input terminal of the second programmable memory.

[0042] The inverting input of the comparator is connected to the second terminal of the sixth resistor and the negative terminal of the Zener diode;

[0043] The pins of the comparator are connected to the clamping voltage source, and the output of the comparator is connected to the first terminal of the logic operation unit.

[0044] The gate of the first MOSFET is connected to the third terminal of the hard disk backplane as the third terminal of the hard disk control circuit, and is also connected to the fourth terminal of the hard disk backplane as the fourth terminal of the hard disk control circuit.

[0045] The drain of the first MOSFET is connected to the clamping voltage source and the second terminal of the logic unit;

[0046] The third terminal of the logic operation unit is connected to the enable signal terminal of the second programmable memory as the second terminal of the hard disk control circuit.

[0047] The source of the first MOSFET and the positive terminal of the Zener diode are grounded.

[0048] In some embodiments, the hard disk control circuit further includes: a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, and an eleventh resistor;

[0049] Among them, the first end of the seventh resistor is connected to the first end of the sixth resistor, and the second end of the seventh resistor is connected to the first end of the eighth resistor and the non-inverting input of the comparator.

[0050] The first terminal of the ninth resistor is connected to the second terminal of the sixth resistor and the negative terminal of the Zener diode; the second terminal of the ninth resistor is connected to the first terminal of the tenth resistor and the inverting input terminal of the comparator.

[0051] The second terminal of the tenth resistor is connected to the first terminal of the eleventh resistor;

[0052] The second terminal of the eleventh resistor is connected to the second terminal of the eighth resistor and grounded.

[0053] In some embodiments, the hard disk control circuit further includes: a second MOSFET;

[0054] The gate of the second MOS transistor is connected to the output of the comparator and the first terminal of the logic operation unit.

[0055] The source of the second MOSFET is connected to the second terminal of the eighth resistor and the second terminal of the eleventh resistor, and is grounded;

[0056] The drain of the second MOSFET is connected to the second terminal of the tenth resistor and the first terminal of the eleventh resistor.

[0057] In some embodiments, the hard disk control circuit further includes: a twelfth resistor and a fourth capacitor;

[0058] The first terminal of the twelfth resistor is connected to the output terminal of the comparator;

[0059] The second terminal of the twelfth resistor is connected to the first terminal of the fourth capacitor, the gate of the second MOS transistor, and the first terminal of the logic operation unit;

[0060] The second terminal of the fourth capacitor is grounded.

[0061] In some embodiments, the hard disk control circuit further includes: a thirteenth resistor, a fourteenth resistor, and a fifth capacitor;

[0062] The first terminal of the thirteenth resistor is connected to the clamping voltage source;

[0063] The second terminal of the thirteenth resistor is connected to the drain of the first MOSFET;

[0064] The first terminal of the fourteenth resistor is connected to the first terminal of the fifth capacitor, the gate of the first MOSFET, and the fourth terminal of the hard disk backplane.

[0065] The second terminal of the fifth capacitor is connected to the third terminal of the hard drive backplate;

[0066] The second terminal of the fourteenth resistor is grounded.

[0067] In some embodiments, the hard disk control circuit further includes: a fuse;

[0068] The first end of the fuse is connected to the input terminal of the second programmable memory;

[0069] The second end of the fuse is connected to the first end of the sixth resistor and the first end of the seventh resistor.

[0070] In some embodiments, the hard disk control circuit further includes: a first set of detection circuits, a second set of detection circuits, and a third set of detection circuits;

[0071] The first set of detection circuits is connected to the first end of the fuse and the output end of the comparator, and is used to detect the hard disk power supply signal and the first hard disk power supply enable signal.

[0072] The second set of detection circuits is connected to the gate and drain of the first MOSFET and is used to detect the hard disk boot control signal, the hard disk presence confirmation signal, and the second hard disk power supply enable signal.

[0073] The third set of detection circuits is connected to the first, second, and third terminals of the logic operation unit, and is used to detect the first hard disk power supply enable signal, the second hard disk power supply enable signal, and the hard disk boot control signal.

[0074] According to a third aspect, this application also provides an electronic device, including the control circuit and / or hard disk boot circuit described above.

[0075] According to the fourth aspect, this application also provides a peak-shaving start-up control method, applied to the above-mentioned control circuit, comprising:

[0076] A startup signal is sent to the corresponding hard disk boot control circuit based on any set of signal transmission terminals;

[0077] Obtain the hard drive signal fed back by the hard drive based on the boot signal;

[0078] When the hard drive signal indicates that the hard drive is starting, a start signal is sent to the corresponding hard drive through any of the remaining signal transmission terminals until all hard drives have started the startup process.

[0079] In some embodiments, when a hard disk signal indicates that the hard disk is starting, a startup signal is sent to the corresponding hard disk through any of the remaining sets of signal transmission terminals, including:

[0080] Determine whether the hard disk signal is a high-level signal within a preset time;

[0081] If the hard disk signal is high within the preset time, the hard disk signal indicates that the hard disk is starting up, and a start signal is sent to the corresponding hard disk start control circuit through any of the remaining signal transmission terminals.

[0082] If the hard disk signal is low for a preset time, indicating that the hard disk is not started, a shutdown signal is sent to the corresponding hard disk, and a start signal is sent to the corresponding hard disk through any of the remaining signal transmission terminals.

[0083] In some embodiments, after the hard disk signal indicates that the hard disk is not started, the method further includes:

[0084] Trigger the alarm system corresponding to the current hard drive so that the operator can determine the hard drive's boot status.

[0085] In some embodiments, after the hard disk signal indicates that the hard disk is not started, the method further includes:

[0086] The hard drive signal summary result is obtained by summarizing the hard drive signal through the backplane control circuit.

[0087] The display device connected to the backplane control circuitry displays the hard drive signal summary results.

[0088] According to the fifth aspect, this application also provides a peak-shaving start-up control device, comprising:

[0089] Memory, used to store computer programs;

[0090] A processor is used to execute computer programs to implement the steps of the above-described peak-shaving startup control method.

[0091] According to the sixth aspect, this application also provides a computer non-volatile readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the above-described staggered startup control method.

[0092] According to the seventh aspect, this application also provides a computer program product, including a computer program / instructions that, when executed by a processor, implement the steps of the above-described off-peak startup control method.

[0093] As can be seen from the above technical solution, this application provides a control circuit applied to a hard disk backplane, including: a backplane execution circuit and a backplane control circuit; wherein, the backplane execution circuit is connected to the backplane control circuit and is used to control the power-on operation of the backplane control circuit; the backplane control circuit includes at least two sets of signal transmission terminals, which are respectively connected to the corresponding hard disks. A start signal is sent to the corresponding hard disk through any one set of signal transmission terminals. When the hard disk signal fed back by the corresponding hard disk indicates that the hard disk has started, a start signal is sent to the corresponding hard disk through the remaining set of signal transmission terminals until all hard disks have started the boot process. Therefore, this application uses one control circuit to control the staggered power-on and booting of at least two hard disks. During the control of hard disk power-on and booting, a start signal is sent to any one hard disk first. After the hard disk starts, a start signal is sent to any one of the remaining hard disks, so that the hard disks start in staggered order according to the order in which they receive the start signal. Since the control circuit provided by this application has only one backplane execution circuit and one backplane control circuit, the design cost is reduced compared to the staggered booting circuits for controlling hard disks in related technologies. Attached Figure Description

[0094] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0095] Figure 1 is a structural diagram of a control circuit provided in an embodiment of this application;

[0096] Figure 2 is a circuit diagram of hard drive off-peak boot provided by related technologies;

[0097] Figure 3 is a circuit diagram of the backplane execution circuit and the backplane control circuit provided in the embodiment of this application;

[0098] Figure 4 is a structural diagram of a hard disk boot circuit provided in an embodiment of this application;

[0099] Figure 5 is a circuit diagram of the hard disk execution circuit and hard disk control circuit provided in the embodiments of this application;

[0100] Figure 6 is a structural diagram of an electronic device provided in an embodiment of this application;

[0101] Figure 7 is a flowchart of a staggered start-up control method provided in an embodiment of this application;

[0102] Figure 8 is a structural diagram of a staggered start-up control device provided in an embodiment of this application. Detailed Implementation

[0103] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0104] The terms "comprising" and "having," and any variations thereof, in the specification and accompanying drawings of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may include steps or units not listed.

[0105] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0106] Next, a control circuit provided in the embodiments of this application will be described in detail. Figure 1 is a structural diagram of a control circuit provided in an embodiment of this application. As shown in Figure 1, the control circuit is applied to a hard disk backplane 1 and includes a backplane execution circuit 11 and a backplane control circuit 12. In addition, a hard disk 2 is also included in Figure 1. The connection relationship of the control circuit is as follows: the backplane execution circuit 11 is connected to the backplane control circuit 12, and the backplane control circuit 12 includes at least two sets of signal transmission terminals, which are respectively connected to the corresponding hard disk 2.

[0107] In this embodiment, with the development of big data technology, electronic devices (such as storage servers) have rapidly evolved, and their performance has become increasingly advanced. As a primary component of storage systems, the performance of hard drives is particularly crucial, and the reliability of hard drive power supply is a fundamental condition for their normal operation. In storage servers, to prevent large inrush currents during hard drive startup, it is typically required that multiple hard drives in the storage server stagger their startup times. In recent years, to achieve staggered startup of multiple hard drives in storage servers, a separate backplane startup circuit (PU11-PU1N) is configured for each hard drive on the hard drive backplane, and a corresponding hard drive startup circuit (PU21-PU2N) is also configured within the hard drive itself. The enable signal of the backplane startup circuit on the hard drive backplane is controlled by a Complex Programmable Logic Device (CPLD) in the entire electronic device. The circuit diagram for implementing staggered hard drive startup in current electronic devices is shown in Figure 2. In the backplane startup circuits (PU11-PU1N), each backplane startup circuit includes a one-time programmable memory (Electrical Fuse (EFUSE)) and corresponding three resistors and two capacitors. In the hard drive startup circuits (PU21-PU2N), each hard drive startup circuit includes a one-time programmable memory (EFUSE) and corresponding three four-resistors and two capacitors. The hard drive enable signal EN is obtained by voltage division of its input voltage. When the input voltage is low, EFUSE will start working, supplying power to its downstream load, which can easily cause the hard drive EUFSE protection to activate, resulting in a power outage. In this design, the hard drive enable signals P12V_NVME1_EN-P12V_NVMEN_EN are obtained by voltage division of their corresponding input voltages P12V_NVME1_VIN-P12V_NVMEN_VIN. During power loss, the outputs P12V_NVME1-P12V_NVMEN will reappear. In situations where power loss is not monotonous, P12V_NVME1_PG-P12V_NVMEN_PG may even go high again, causing false detections. The one-time programmable memory (EFUSE) in the backplane startup circuit receives the power signal P12V_STBY and the enable signal P12V_NVME1_VIN_EN-P12V_NVMEN_VIN_EN. Therefore, the current design requires a large number of backplane startup circuits, leading to space constraints and increasing the cost of the hard drive backplane and the server.

[0108] Therefore, this application provides a control circuit. In the design of the control circuit provided in this application, only a backplane execution circuit 11 and a backplane control circuit 12 need to be designed on the hard disk backplane 1. In the circuit connection relationship of the control circuit shown in Figure 1, the backplane control circuit 12 includes at least two sets of signal transmission terminals, which are respectively connected to the corresponding hard disk 2. It mainly sends a start signal to the corresponding hard disk 2 through any one set of signal transmission terminals. After receiving the start signal, the hard disk 2 generates a corresponding hard disk signal and resends the hard disk signal to the backplane control circuit 12. At this time, the backplane control circuit 12 will judge the hard disk signal. If the current hard disk signal indicates that the hard disk is starting, then the backplane control circuit 12 sends a start signal to the corresponding hard disk 2 through the remaining set of signal transmission terminals until the hard disk 2 starts the startup process.

[0109] It should be noted that if the backplane control circuit 12 determines that the hard drive signal indicates that the hard drive has not started, then the backplane control circuit 12 needs to resend a shutdown signal to the corresponding hard drive 2 through the current signal transmission terminal. The main reason for this is that if the backplane control circuit 12 determines that the hard drive signal indicates that the hard drive has not started, it means that the current hard drive 2 may be malfunctioning, thus causing the hard drive 2 to fail to start. In order to prevent further damage to the hard drive 2, it is necessary to send a shutdown signal to the hard drive 2 to prevent the hard drive 2 from continuing the boot process.

[0110] For example, if the control circuit controls three hard drives (the first, second, and third hard drives) to power on sequentially, its backplane control circuit 12 includes three sets of signal transmission terminals: a first set, a second set, and a third set. The circuit connections are as follows: the first set of signal transmission terminals in the backplane control circuit 12 is connected to the first hard drive; the second set is connected to the second hard drive; and the third set is connected to the third hard drive.

[0111] The current control circuit design for achieving off-peak boot times for the hard drive includes the following steps:

[0112] Step 1: The backplane control circuit 12 sends a start signal to the first hard disk through the first group of signal transmission terminals, so that the first hard disk generates the first hard disk signal according to the start signal.

[0113] Step 2: The backplane control circuit 12 receives the first hard disk signal through the first set of signal transmission terminals. If the first hard disk signal indicates that the first hard disk is started, the backplane control circuit 12 sends a start signal to the second hard disk through the second set of signal transmission terminals so that the second hard disk generates a second hard disk signal according to the start signal. If the first hard disk signal indicates that the first hard disk is not started, the backplane control circuit 12 sends a shutdown signal to the first hard disk through the first set of signal transmission terminals, and then sends a start signal to the second hard disk through the second set of signal transmission terminals so that the second hard disk generates a second hard disk signal according to the start signal.

[0114] Step 3: The backplane control circuit 12 receives the second hard disk signal through the second set of signal transmission terminals. If the second hard disk signal indicates that the second hard disk is started, the backplane control circuit 12 sends a start signal to the third hard disk through the third set of signal transmission terminals so that the third hard disk generates a third hard disk signal based on the start signal. If the second hard disk signal indicates that the second hard disk is not started, the backplane control circuit 12 sends a shutdown signal to the second hard disk through the second set of signal transmission terminals, and then sends a start signal to the third hard disk through the third set of signal transmission terminals so that the third hard disk generates a third hard disk signal based on the start signal.

[0115] Step 4: The backplane control circuit 12 receives the third hard disk signal through the third group of signal transmission terminals. If the third hard disk signal indicates that the third hard disk is started, the control circuit under the current design completes the staggered start of the hard disk. If the third hard disk signal indicates that the third hard disk is not started, the backplane control circuit 12 sends a shutdown signal to the third hard disk through the third group of signal transmission terminals, and then the control circuit under the current design completes the staggered start of the hard disk.

[0116] Step 5: The backplane control circuit 12 summarizes the signals or data indicating that the hard drive is not started, and displays them through the connected display device for the operator to view.

[0117] It should be noted that step 5 is optional; it can be included in the hard drive's off-peak boot process or not. Users can configure it according to their actual needs.

[0118] It should also be noted that the specific process in the example provided in this application is to start the first hard drive, the second hard drive, and the third hard drive in that order. This is only one possible way to implement it, but it is not limited to this method. Users can adjust it according to their needs.

[0119] As can be seen from the above technical solution, this application provides a control circuit applied to a hard disk backplane, including: a backplane execution circuit and a backplane control circuit; wherein, the backplane execution circuit is connected to the backplane control circuit and is used to control the power-on operation of the backplane control circuit; the backplane control circuit includes at least two sets of signal transmission terminals, which are respectively connected to the corresponding hard disks. A start signal is sent to the corresponding hard disk through any one set of signal transmission terminals. When the hard disk signal fed back by the corresponding hard disk indicates that the hard disk has started, a start signal is sent to the corresponding hard disk through the remaining set of signal transmission terminals until all hard disks have started the boot process. Therefore, this application uses one control circuit to control the staggered power-on and booting of at least two hard disks. During the control of hard disk power-on and booting, a start signal is sent to any one hard disk first. After the hard disk starts, a start signal is sent to any one of the remaining hard disks, so that the hard disks start in staggered order according to the order in which they receive the start signal. Since the control circuit provided by this application has only one backplane execution circuit and one backplane control circuit, the design cost is reduced compared to the staggered booting circuits for controlling hard disks in related technologies.

[0120] In some embodiments, as shown in FIG3, the backplane execution circuit 11 is a first programmable memory EFUSE1. The output terminal (Voltage Output (VOUT)) of the first programmable memory EFUSE1 is connected to the first terminal of each hard disk 2 as the first terminal of the backplane execution circuit 11 to realize the transmission of the power supply signal P12V_NVME. The status signal terminal (Power Good (PG)) of the first programmable memory EFUSE1 is connected to the first terminal of the backplane control circuit 12 as the second terminal of the backplane execution circuit 11 to realize the transmission of the backplane power status signal P12V_NVME_PG. The enable signal terminal (EN) of the first programmable memory EFUSE1 is connected to the second terminal of the backplane control circuit 12 as the third terminal of the backplane execution circuit 11 to realize the transmission of the backplane enable signal P12V_NVME_EN. The input terminal (Voltage Input (VIN)) of the first programmable memory EFUSE1 is connected to the power supply as the fourth terminal of the backplane execution circuit 11 to obtain the power supply signal P12V_STBY required by itself.

[0121] In addition, to ensure normal signal transmission and prevent voltage from exceeding the threshold of electronic components, the backplane execution circuit 11 also includes: a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, and a second capacitor C2. The circuit connections are as follows: the first end of the first resistor R1 is connected to the output terminal (VOUT) of the first programmable memory EFUSE1; the second end of the first resistor R1 is connected to the status signal terminal (PG) of the first programmable memory EFUSE1; the first end of the second resistor R2 is connected to the first end of the first capacitor C1; the second end of the second resistor R2 is connected to the first end of the first capacitor C1 and grounded; the first end of the third resistor R3 is connected to the enable signal terminal (Enable, EN) of the first programmable memory EFUSE1 and the first end of the second capacitor C2; the second end of the third resistor R3 is connected to the second end of the second capacitor C2 and grounded.

[0122] In some embodiments, as shown in FIG3, the backplane control circuit 12 is a complex programmable logic device (CPLD). When the backplane control circuit 12 is a CPLD, its circuit connection relationship is as follows: the status signal input terminal of the CPLD is connected to the status signal terminal (PG) of the first programmable memory EFUSE1 as the first terminal of the backplane control circuit 12, and is used to realize the transmission of the backplane power status signal P12V_NVME_PG; the enable signal input terminal of the CPLD is connected to the enable signal terminal (EN) of the first programmable memory EFUSE1 as the second terminal of the backplane control circuit 12; and each enable signal detection terminal of the CPLD is connected to the second terminal of the corresponding hard disk 2, and is used to transmit the start signal (which can also be understood as the hard disk enable signal) P12V_NVME1 / 3_EN_N. Meanwhile, the enable signal detection terminals of the complex programmable logic device (CPLD) are also connected to the power supply to acquire the P3V3_STBY power signal; the presence signal detection terminals of the CPLD are respectively connected to the third terminal of the corresponding hard disk 2 to acquire the disk slot signal P12V_NVME1 / 3_INDEF_R_N representing the disk slot number in each hard disk 2. The presence signal detection terminals of the CPLD are also connected to the power supply to acquire the P3V3_STBY power signal; the status signal detection terminals of the CPLD are respectively connected to the fourth terminal of the corresponding hard disk to acquire the hard disk signal P12V_NVME1 / 3_PG output by hard disk 2 (which can also be understood as the current hard disk power status signal of hard disk 2).

[0123] In addition, to ensure normal signal transmission and prevent voltage from exceeding the threshold values ​​of electronic components, the circuit also includes resistors. These resistors are placed at the enable signal detection terminals and the presence signal detection terminals of the complex programmable logic device (CPLD). The resistors are R104, R105, R106, R107, R108, and R109.

[0124] It should be noted that in the embodiment shown in Figure 3, the Complex Programmable Logic Device (CPLD) includes three enable signal detection terminals, three presence signal detection terminals, and three status signal detection terminals. However, this is only one possible implementation method, and users can configure it according to their needs.

[0125] In the current embodiment, an enable signal detection terminal, an in-position signal detection terminal, and a status signal detection terminal constitute a set of signal transmission terminals for the backplane control circuit 12. Therefore, in the embodiment shown in Figure 3, the complex programmable logic device (CPLD) includes three sets of signal transmission terminals, meaning it can be connected to three hard disks 2 to achieve staggered startup of the three hard disks.

[0126] As can be seen from the above technical solution, this application uses a control circuit to control the staggered power-on startup of at least two hard drives. During the hard drive power-on startup process, a startup signal is first sent to any one of the hard drives. After that hard drive starts, a startup signal is then sent to any one of the remaining hard drives, so that the hard drives start sequentially in staggered order according to the order in which they receive the startup signals. Since the control circuit provided in this application only has one backplane execution circuit and one backplane control circuit, the design cost is reduced compared to the staggered startup circuits for controlling hard drives in related technologies.

[0127] On the other hand, this application provides a hard disk boot circuit, as shown in Figure 4. This hard disk boot circuit is applied to a hard disk 2 and includes a hard disk execution circuit 22 and a hard disk control circuit 21. In addition, the circuit shown in Figure 4 includes a hard disk backplane 1. The circuit connections are as follows: the hard disk control circuit 21 is connected to the hard disk backplane 1; the hard disk execution circuit 22 is connected to both the hard disk control circuit 21 and the hard disk backplane 1.

[0128] In this embodiment, the hard disk control circuit 21, connected to the hard disk backplane 1, receives the startup signal sent by the hard disk backplane 1. It should be noted that the hard disk startup circuit only initiates the hard disk power-on process after the hard disk control circuit 21 receives the startup signal. After receiving the startup signal, the hard disk control circuit 21 processes the startup signal to obtain the corresponding drive signal. The hard disk execution circuit 22, connected to the hard disk control circuit 21, receives the drive signal. This drive signal, after passing through the hard disk execution circuit 22, outputs a hard disk signal, which indicates whether the hard disk has successfully started. The hard disk backplane 1, connected to the hard disk execution circuit 22, receives the hard disk signal generated by the hard disk execution circuit 22. If the current hard disk signal indicates that the hard disk has started, the hard disk backplane 1 sends a startup signal to the hard disk control circuits 21 of the other hard disks 2. If the hard disk backplane 1 determines that the hard disk signal indicates that the hard disk has not started, then the hard disk backplane 1 needs to resend a shutdown signal to the hard disk control circuit 21 corresponding to the current hard disk 2 and send a startup signal to the hard disk control circuits 21 of the other hard disks 2.

[0129] As can be seen from the above technical solution, this application provides a hard disk boot circuit applied to a hard disk, including: a hard disk execution circuit and a hard disk control circuit; the hard disk control circuit is connected to the hard disk backplane and is used to determine the boot time based on the boot signal sent by the hard disk backplane, and to determine the drive signal based on the boot signal; the hard disk execution circuit is connected to both the hard disk control circuit and the hard disk backplane, and is used to determine the corresponding hard disk signal based on the drive signal, and send the hard disk signal to the hard disk backplane, so that when the hard disk backplane determines that the hard disk signal indicates that the hard disk is booting, it sends a boot signal to the other hard disk boot circuits. Therefore, this application uses a hard disk backplane to control the boot time of the hard disk. During the hard disk power-on boot process, it achieves its own boot based on the boot signal sent by the hard disk backplane. The timing of the hard disk backplane sending the boot signal is controllable, so when multiple hard disks are present, staggered boot times can be achieved. Compared with staggered boot circuits for controlling hard disks in related technologies, this reduces design costs.

[0130] In some embodiments, as shown in FIG5, the hard disk execution circuit 22 is a second programmable memory EFUSE2. When the hard disk execution circuit 22 is the second programmable memory EFUSE2, the circuit connection relationship is as follows: the input terminal (VIN) of the second programmable memory EFUSE2 is connected to the first terminal of the hard disk control circuit 21 and the first terminal of the hard disk backplane 1, and is used to realize the transmission of the power supply signal P12V_NVME; the status signal terminal (PG) of the second programmable memory EFUSE2 is connected to the second terminal of the hard disk backplane 1, and is used to realize the transmission of the hard disk signal P12V_NVME1 / N_PG; the enable signal terminal (EN) of the second programmable memory EFUSE2 is connected to the second terminal of the hard disk control circuit 21, and is used to realize the transmission of the drive signal P12V_NVME1 / N_EN corresponding to the hard disk execution circuit 22; in addition, the output terminal (OUT) of the second programmable memory EFUSE2 outputs the power supply signal P12V_NVME1 / N.

[0131] In addition, to ensure normal signal transmission and prevent voltage from exceeding the threshold of electronic components, the hard disk execution circuit 22 shown in Figure 5 also includes: a fourth resistor R4, a fifth resistor R5, and a third capacitor C3. Based on this, the connection relationship of the hard disk execution circuit 22 is as follows: the first terminal of the fourth resistor R4 is connected to the output terminal (OUT) of the second programmable memory EFUSE2; the second terminal of the fourth resistor R4 is connected to the status signal terminal (PG) of the second programmable memory EFUSE2, the first terminal of the fifth resistor R5, and the first terminal of the third capacitor C3; the second terminal of the fifth resistor R5 and the second terminal of the third capacitor C3 are connected and grounded.

[0132] In some embodiments, as shown in FIG5, the hard disk control circuit 21 includes: a comparator U1, an AND logic operation unit U2, a first MOSFET Q1, a Zener diode D1, and a sixth resistor R6. The circuit connections are as follows: the non-inverting input of comparator U1 is connected to the first terminal of the sixth resistor R6, and together they form the first terminal of the hard disk control circuit 21, connected to the input terminal (VIN) of the second programmable memory EFUSE2; the inverting input of comparator U1 is connected to the second terminal of the sixth resistor R6 and the negative terminal of the Zener diode D1; the pin of comparator U1 is connected to a clamping voltage source, and the output of comparator U1 is connected to the first terminal of the AND logic operation unit U2; the gate of the first MOSFET Q1 serves as the third terminal of the hard disk control circuit 21, connected to the third terminal of the hard disk backplane 1, and is used to implement the boot signal P12V_NVME. The transmission of 1 / N_EN_N is also connected to the fourth terminal of the hard disk control circuit 21 and the fourth terminal of the hard disk backplane 1, which is used to realize the transmission of disk position signal P12V_NVME1 / N_INDEF_R_N; the drain of the first MOS transistor Q1 is connected to the clamping voltage source and the second terminal of the logic operation unit U2; the third terminal of the logic operation unit U2 is connected to the enable signal terminal (EN) of the second programmable memory EFUSE2 as the second terminal of the hard disk control circuit 21, which is used to realize the transmission of drive signal P12V_NVME1 / N_EN; the source of the first MOS transistor Q1 and the positive terminal of the Zener diode D1 are grounded.

[0133] In addition, in the embodiment shown in Figure 5, the hard disk control circuit 21 also includes: a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a second MOSFET Q2, a twelfth resistor R12, a fourth capacitor C4, a thirteenth resistor R13, a fourteenth resistor R14, a fifth capacitor C5, and a fuse F1. The connection relationship of the hard disk control circuit 21 at this time is as follows: the first end of the seventh resistor R7 is connected to the first end of the sixth resistor R6; the second end of the seventh resistor R7 is connected to the first end of the eighth resistor R8 and the non-inverting input of comparator U1; the first end of the ninth resistor R9 is connected to the second end of the sixth resistor R6 and the negative terminal of Zener diode D1; the second end of the ninth resistor R9 is connected to the first end of the tenth resistor R10 and the inverting input of comparator U1; the second end of the tenth resistor R10 is connected to the first end of the eleventh resistor R11; the second end of the eleventh resistor R11 is connected to the second end of the eighth resistor R8 and grounded; the gate of the second MOSFET Q2 is connected to the output terminal of comparator U1 and the first end of logic operation unit U2; the source of the second MOSFET Q2 is connected to the second ends of the eighth resistor R8 and the eleventh resistor R11 and grounded; the drain of the second MOSFET Q2 is connected to the second end of the tenth resistor R10. The first terminal of the eleventh resistor R11 is connected to the first terminal of the eleventh resistor R12; the first terminal of the twelfth resistor R12 is connected to the output terminal of the comparator U1; the second terminal of the twelfth resistor R12 is connected to the first terminal of the fourth capacitor C4, the gate of the second MOSFET Q2, and the first terminal of the logic operation unit U2; the second terminal of the fourth capacitor C4 is grounded; the first terminal of the thirteenth resistor R13 is connected to the clamping voltage source; the second terminal of the thirteenth resistor R13 is connected to the drain of the first MOSFET Q1; the first terminal of the fourteenth resistor R14 is connected to the first terminal of the fifth capacitor C5, the gate of the first MOSFET Q1, and the first four terminals of the hard disk backplane 1; the second terminal of the fifth capacitor C5 is connected to the third terminal of the hard disk backplane 1; the second terminal of the fourteenth resistor R14 is grounded; the first terminal of the fuse F1 is connected to the input terminal (VIN) of the second programmable memory EFUSE2; the second terminal of the fuse F1 is connected to the first terminal of the sixth resistor R6 and the first terminal of the seventh resistor R7.

[0134] It should be noted that the supply voltage of its clamping voltage source is the voltage after the Zener diode D1 is clamped, which is VDD_D21.

[0135] In this embodiment, the complete hard disk control circuit 21 shown in Figure 5 operates as follows: its signal P12V_NVME passes through fuse F1 to the sixth resistor R6. When the downstream circuit is short-circuited, fuse F1 quickly blows to provide protection. The hard disk control circuit 21 can determine whether the output of P12V_NVME1 / N_EN_1 is high or low based on the magnitude of the P12V_NVME input voltage. When P12V_NVME increases to the input threshold of the hard disk control circuit 21, the output P12V_NVME1 / N_EN_1 is high. When P12V_NVME1 / N_EN_1 is high, the second MOSFET Q2 is turned on, thus giving the current hard disk control circuit 21 a hysteresis function. The hard disk control circuit 21 can determine whether the output of P12V_NVME1 / N_EN_2 is high or low based on the high / low state of FM_NVME1 / N_IFDET_R_N. When FM_NVME1 / N_IFDET_R_N is low, P12V_NVME1 / N_EN_2 outputs a high level. When both P12V_NVME1 / N_EN_1 and P12V_NVME1 / N_EN_2 are high, P12V_NVME1 / N_EN outputs a high level.

[0136] In the hard disk control circuit 21, when P12V_NVME increases to 3.3V, the Zener diode D1 turns on, and the voltage VDD_D21 is clamped at 3.3V.

[0137] At this time, the voltage at the inverting input terminal Vin- of comparator U1 is: Vin-=UR+=3.3*(R10+R11) / (R9+R10+R11);

[0138] Wherein, R10 is the resistance value of the tenth resistor R10; R11 is the resistance value of the eleventh resistor R11; and R9 is the resistance value of the ninth resistor R9.

[0139] At this time, the voltage at the non-inverting input terminal Vin+ of comparator U1 is: Vin+=P12V_NVME*R8 / (R7+R8);

[0140] Where R8 is the resistance value of the eighth resistor R8; and R7 is the resistance value of the seventh resistor R7.

[0141] Based on this, Vin+ maintains a linear relationship with P12V_NVME, and increases as P12V_NVME increases. When Vin+ = Vin- = UR+, the output P12V_NVME1 / N_EN_1 of comparator U1 is high. When P12V_NVME1 / N_EN_1 is high, it drives the second MOSFET Q2 to conduct, and the eleventh resistor R11 is short-circuited.

[0142] At this time, the voltage at the inverting input terminal Vin- of comparator U1 is: Vin-=UR-=3.3*R10 / (R9+R10);

[0143] Since UR- is less than UR+, and because comparator U1 has a hysteresis function, it prevents the output P12V_NVME1 / N_EN_1 from fluctuating between high and low levels due to fluctuations in the P12V_NVME input voltage.

[0144] It should be noted that the hard drive boot circuit in any one of the hard drives 2 has the circuit structure shown in Figure 5 above.

[0145] In addition, because the hard disk boot circuit provided in this application has a relatively complex structure, if any one of its electronic components fails, the final output signal will also fail, leading to problems in the hard disk power-on boot process. Therefore, three sets of detection circuits are added to the hard disk boot circuit provided in this application, namely the first set of detection circuits, the second set of detection circuits, and the third set of detection circuits. The first set of detection circuits is connected to the first terminal of fuse F1 and the output terminal of comparator U1 to detect P12V_NVME and P12V_NVME1 / N_EN_1; the second set of detection circuits is connected to the gate and drain of the first MOSFET Q1 to detect P12V_NVME1 / N_EN, FM_NVME1 / N_IFDET_R_N, and P12V_NVME1 / N_EN_2; the third set of detection circuits is connected to the first, second, and third terminals of logic operation unit U2 to detect P12V_NVME1 / N_EN_1, P12V_NVME1 / N_EN_2, and P12V_NVME1 / N_EN. If any signal deviates from the normal correspondence, the corresponding detection circuit generates an alarm signal for operator inspection.

[0146] Therefore, this application uses a hard drive backplane to control the hard drive's boot time. During the hard drive's power-on boot process, it boots itself based on the boot signal sent by the hard drive backplane. The timing of the hard drive backplane sending the boot signal is controllable, thus enabling staggered boot times when multiple hard drives are present. Compared to staggered boot circuits for controlling hard drives in related technologies, this reduces design costs.

[0147] On the other hand, this application also provides an electronic device, including the above-described control circuit and / or hard disk boot circuit, and having the same beneficial effects.

[0148] To enable the electronic device to achieve staggered startup of the hard drives, the electronic device includes multiple hard drives 2. That is to say, in the currently designed electronic device, the hard drive backplane 1 includes a control circuit 13 consisting of a backplane execution circuit 11 and a backplane control circuit 12, and the electronic device includes multiple hard drives 2, each of which includes a hard drive startup circuit 23 consisting of a hard drive execution circuit 22 and a hard drive control circuit 21, as shown in Figure 6.

[0149] In summary, based on the circuits shown in Figures 3, 5, and 6, the steps for achieving off-peak booting of hard disk 2 in the electronic device are as follows:

[0150] Step 1: Construct the structures shown in Figures 6, 3, and 5.

[0151] Step 2: When the backplane control circuit 12 and the backplane execution circuit 11 are running normally, P12V_NVME_EN = 1 (high level), P12V_NVME_PG = 1.

[0152] Step 3: The backplane control circuit 12 detects the signal status of FM_NVME1 / N_IFDET_R_N and P12V_NVME1 / N_PG sent by all hard drives 2.

[0153] Step 4: Filter out the drive bays (the labels of hard drive 2 itself) where FM_NVME1 / N_IFDET_R_N=0 and P12V_NVME1 / N_PG=0.

[0154] Step 5: Enable drive bay 101 (first hard drive 2), outputting P12V_NVME1_EN_N = 0 (low level). When P12V_NVME1_EN_N = 0, the first MOSFET Q1 is not turned on, and P12V_NVME1_EN_2 is high. If both P12V_NVME1_EN_1 and P12V_NVME1_EN_2 are high, then the output P12V_NVME1_EN of the AND logic unit U2 is high. At this time, the hard drive execution circuit 22 works normally, P12V_NVME1_VE0 is output normally, and P12V_NVME1_PG = 1.

[0155] Step 6: If P12V_NVME1_PG = 1 within the preset time (e.g., 1s), then enable disk bay 102 (boot the second hard drive 2) and output P12V_NVME2_EN_N = 0;

[0156] If P12V_NVME1_PG = 0 within the preset time, then disable the enable of drive bay 101 and output P12V_NVME1_EN_N = 1. Then enable the enable of drive bay 102 and output P12V_NVME2_EN_N = 0.

[0157] Step 7: If P12V_NVME2_PG = 1 within the preset time, then enable drive bay 103 and output P12V_NVME3_EN_N = 0;

[0158] If P12V_NVME2_PG = 0 within the preset time, then disable the enable of drive bay 102 and output P12V_NVME2_EN_N = 1. Then enable the enable of drive bay 103 and output P12V_NVME3_EN_N = 0.

[0159] Step 8: If P12V_NVME3_PG = 1 within the preset time, then enable drive bay 104 and output P12V_NVME4_EN_N = 0;

[0160] If P12V_NVME3_PG = 0 within the preset time, then disable the enable of drive bay 103 and output P12V_NVME3_EN_N = 1, then enable the enable of drive bay 104 and output P12V_NVME4_EN_N = 0.

[0161] Step 9: Repeat the same steps for the next workstation until all workstations are completed.

[0162] As can be seen from the above technical solution, the electronic device provided in this application includes: a control circuit and multiple hard drive boot circuits; wherein, the control circuit is disposed in the hard drive backplane, and the hard drive boot circuits are disposed in the corresponding hard drives. The hard drive backplane first sends a boot signal to any one hard drive, and after the hard drive starts, it sends a boot signal to any one of the remaining hard drives, so that the hard drives start sequentially in staggered order according to the order in which they receive the boot signals. Since the electronic device provided in this application has only one control circuit, compared with the staggered boot circuits for controlling hard drives in related technologies, the design cost is reduced and the space constraints of the hard drive backplane are alleviated. At the same time, in the structure of the control circuit and the hard drive boot circuit, the hard drive execution circuit can be controlled to start at a higher input voltage, avoiding the hard drive execution circuit from powering off due to starting at a lower input voltage. Furthermore, during the power-down process of the hard drive execution circuit, the output signal is monotonically degraded and will not become high-level in a short time due to fluctuations, thus affecting the service life of the hard drive.

[0163] On the other hand, this application also provides a peak-shaving start-up control method, applied to the above-mentioned control circuit, as shown in Figure 7. The peak-shaving start-up control method includes the following process:

[0164] S10: Send a boot signal to the corresponding hard drive based on any set of signal transmission terminals.

[0165] S11: Obtain the hard drive signal fed back by the hard drive based on the boot signal.

[0166] S12: When the hard disk signal indicates that the hard disk is starting, a start signal is sent to the corresponding hard disk through any of the remaining signal transmission terminals until all hard disks have started the startup process.

[0167] The optional implementation of step S12 is as follows:

[0168] Determine whether the hard disk signal is a high-level signal within a preset time;

[0169] If the hard disk signal is high within the preset time, the hard disk signal indicates that the hard disk is starting up, and a start signal is sent to the corresponding hard disk start control circuit through any of the remaining signal transmission terminals.

[0170] If the hard drive signal is low for a preset time, indicating that the hard drive is not started, a shutdown signal is sent to the corresponding hard drive, and a start signal is sent to the corresponding hard drive through any of the remaining signal transmission terminals.

[0171] After the hard drive signal indicates that the hard drive is not booting, it also includes:

[0172] Trigger the alarm system corresponding to the current hard drive so that the operator can determine the hard drive's boot status.

[0173] In this embodiment, the present application also provides a staggered startup control method applied to a control circuit, which includes a backplane execution circuit and a backplane control circuit. The backplane execution circuit is connected to the backplane control circuit and is used to control the power-on operation of the backplane control circuit. The backplane control circuit includes at least two sets of signal transmission terminals, each connected to a corresponding hard drive. A startup signal is sent to the corresponding hard drive through any one set of signal transmission terminals. When the hard drive signal indicates startup, a startup signal is sent to the corresponding hard drive through the remaining set of signal transmission terminals until all hard drives have started the startup process. Therefore, the present application employs a staggered startup control method, utilizing the structure of the control circuit to achieve staggered startup of multiple hard drives. Since the principle provided by the present application is that one control circuit controls multiple hard drives, compared to the staggered startup circuits for controlling hard drives in related technologies, it reduces design costs and alleviates the space constraints of the hard drive backplane layout.

[0174] Figure 8 is a structural diagram of a staggered start control device provided in an embodiment of this application. As shown in Figure 8, the staggered start control device includes: a memory 60, which is configured to store computer programs.

[0175] The processor 61 is configured to implement the steps of the off-peak startup control method as described in the above embodiment when executing a computer program.

[0176] The off-peak start control device provided in this embodiment may include, but is not limited to, smartphones, tablets, laptops, or desktop computers.

[0177] The processor 61 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 61 may be implemented using at least one hardware form selected from Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The processor 61 may also include a main processor and a coprocessor. The main processor, also known as the Central Processing Unit (CPU), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 61 may integrate a Graphics Processing Unit (GPU), which is configured to handle the rendering and drawing of content required for display on the screen. In some embodiments, the processor 61 may also include an Artificial Intelligence (AI) processor, configured to handle computational operations related to machine learning.

[0178] The memory 60 may include one or more computer-defined non-volatile readable storage media, which may be non-transitory. The memory 60 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In this embodiment, the memory 60 is at least configured to store the following computer program 601, which, after being loaded and executed by the processor 61, is capable of implementing the relevant steps of the staggered startup control method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 60 may also include an operating system 602 and data 603, etc., and the storage method may be temporary storage or permanent storage. The operating system 602 may include Windows, Unix, Linux, etc.

[0179] In some embodiments, the off-peak start control device may further include a display screen 62, an input / output interface 63, a communication interface 64, a power supply 65, and a communication bus 66.

[0180] Those skilled in the art will understand that the structure shown in Figure 8 does not constitute a limitation on the off-peak start control device and may include more or fewer components than shown.

[0181] It is understood that if the off-peak startup control method in the above embodiments is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the current technology, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods in the various embodiments of this application. The aforementioned storage medium includes: USB flash drive, mobile hard disk, read-only memory (ROM), random access memory (RAM), electrically erasable programmable ROM, register, hard disk, removable disk, CD-ROM, magnetic disk, or optical disk, and other media capable of storing program code.

[0182] Based on this, embodiments of this application also provide a computer non-volatile readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps of the above-described staggered startup control method.

[0183] Based on this, embodiments of this application also provide a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps of the above-described off-peak startup control method.

[0184] The above provides a detailed description of a peak-shaving start-up control device provided in the embodiments of this application. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple; relevant parts can be referred to the method section.

[0185] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0186] The control circuit, hard disk boot circuit, electronic device, and off-peak boot control method provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A control circuit, characterized by The application is applied to a hard disk backboard, comprising a backboard execution circuit and a backboard control circuit. The backboard execution circuit is connected with the backboard control circuit and is used for controlling the power-on operation of the backboard control circuit. The backboard control circuit comprises at least two groups of signal transmission ends, which are connected with corresponding hard disks respectively, and the start-up signal is sent to the corresponding hard disk through any one of the signal transmission ends, when the hard disk signal feedback from the corresponding hard disk indicates that the hard disk is started, the start-up signal is sent to the corresponding hard disk through any one of the remaining signal transmission ends, until the hard disks are all started.

2. The control circuit of claim 1, wherein, The hard disks corresponding to the at least two groups of signal transmission ends are started in turn according to the order of receiving the start-up signal.

3. The control circuit of claim 1, wherein, The backboard execution circuit is a first programmable memory. The output end of the first programmable memory is connected with the first end of each hard disk. The state signal end of the first programmable memory is connected with the first end of the backboard control circuit. The enable signal end of the first programmable memory is connected with the second end of the backboard control circuit. The input end of the first programmable memory is connected with a power supply.

4. The control circuit of claim 3, wherein, The backboard execution circuit further comprises a first resistor, a second resistor, a third resistor, a first capacitor and a second capacitor. The first end of the first resistor is connected with the output end of the first programmable memory, the second end of the first resistor is connected with the state signal end of the first programmable memory, the first end of the second resistor and the first end of the first capacitor. The second end of the second resistor and the first end of the first capacitor are connected and grounded. The first end of the third resistor is connected with the enable signal end of the first programmable memory and the first end of the second capacitor. The second end of the third resistor and the second end of the second capacitor are connected and grounded.

5. The control circuit of claim 3, wherein, The backboard control circuit is a complex programmable logic device. The state signal input end of the complex programmable logic device as the first end of the backboard control circuit is connected with the state signal end of the first programmable memory. The enable signal input end of the complex programmable logic device as the second end of the backboard control circuit is connected with the enable signal end of the first programmable memory. Each enable signal detection end of the complex programmable logic device is connected with the second end of the corresponding hard disk. Each in-bit signal detection end of the complex programmable logic device is connected with the third end of the corresponding hard disk. Each state signal detection end of the complex programmable logic device is connected with the fourth end of the corresponding hard disk, wherein the each enable signal detection end of the complex programmable logic device, the each in-bit signal detection end of the complex programmable logic device and the each state signal detection end of the complex programmable logic device constitute the each group of signal transmission ends of the backboard control circuit.

6. A hard disk boot-up circuit, characterized by comprising: The application is applied to a hard disk, comprising a hard disk execution circuit and a hard disk control circuit. The hard disk control circuit is connected with a hard disk backboard, used for determining a start-up time according to the start-up signal sent by the hard disk backboard and determining a driving signal based on the start-up signal. The hard disk execution circuit is connected with the hard disk control circuit and the hard disk backplane respectively, and is used for determining a corresponding hard disk signal according to the drive signal and sending the hard disk signal to the hard disk backplane, so that when the hard disk backplane determines that the hard disk signal represents hard disk starting, the starting signal is sent to the remaining hard disk starting circuits.

7. The hard disk boot circuit of claim 6, wherein, The hard disk execution circuit is a second programmable memory; The input end of the second programmable memory is connected with the first end of the hard disk control circuit and the first end of the hard disk backplane. The state signal end of the second programmable memory is connected with the second end of the hard disk backplane. The enable signal end of the second programmable memory is connected with the second end of the hard disk control circuit.

8. The hard disk boot circuit of claim 7, wherein, The hard disk execution circuit further comprises a fourth resistor, a fifth resistor and a third capacitor. The first end of the fourth resistor is connected with the output end of the second programmable memory. The second end of the fourth resistor is connected with the state signal end of the second programmable memory, the first end of the fifth resistor and the first end of the third capacitor. The second end of the fifth resistor and the second end of the third capacitor are connected and grounded.

9. The hard disk boot circuit of claim 7, wherein, The hard disk control circuit comprises a comparator, an AND logic operation unit, a first metal oxide semiconductor field effect transistor (MOS), a voltage stabilizing diode and a sixth resistor. The non-inverting input end of the comparator is connected with the first end of the sixth resistor, and the two are connected with the input end of the second programmable memory as the first end of the hard disk control circuit. The inverting input end of the comparator is connected with the second end of the sixth resistor and the negative electrode of the voltage stabilizing diode. The pin end of the comparator is connected with a clamping voltage source, and the output end of the comparator and the first end of the AND logic operation unit are connected. The gate of the first MOS is connected with the third end of the hard disk backplane as the third end of the hard disk control circuit, and is connected with the fourth end of the hard disk backplane as the fourth end of the hard disk control circuit. The drain of the first MOS is connected with the clamping voltage source and the second end of the AND logic operation unit. The third end of the AND logic operation unit is connected with the enable signal end of the second programmable memory as the second end of the hard disk control circuit. The source of the first MOS and the positive electrode of the voltage stabilizing diode are grounded.

10. The hard disk boot circuit of claim 9, wherein, The hard disk control circuit further comprises a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor and an eleventh resistor. The first end of the seventh resistor is connected with the first end of the sixth resistor, and the second end of the seventh resistor is connected with the first end of the eighth resistor and the non-inverting input end of the comparator. The first end of the ninth resistor is connected with the second end of the sixth resistor and the negative electrode of the voltage stabilizing, and the second end of the ninth resistor is connected with the first end of the tenth resistor and the inverting input end of the comparator. The second end of the tenth resistor is connected with the first end of the eleventh resistor. The second end of the eleventh resistor is connected with the second end of the eighth resistor and grounded.

11. The hard disk boot circuit of claim 10, wherein, The hard disk control circuit further comprises a second MOS. The gate of the second MOS transistor is connected with the output end of the comparator and the first end of the AND logic operation unit. The source of the second MOS transistor is connected with the second end of the eighth resistor and the second end of the eleventh resistor, and grounded. The drain of the second MOS transistor is connected with the second end of the tenth resistor and the first end of the eleventh resistor.

12. The hard disk boot circuit of claim 11, wherein, The hard disk control circuit further comprises a twelfth resistor and a fourth capacitor. The first end of the twelfth resistor is connected with the output end of the comparator. The second end of the twelfth resistor is connected with the first end of the fourth capacitor, the gate of the second MOS transistor and the first end of the AND logic operation unit. The second end of the fourth capacitor is grounded.

13. The hard disk boot circuit of claim 12, wherein, The hard disk control circuit further comprises a thirteenth resistor, a fourteenth resistor and a fifth capacitor. The first end of the thirteenth resistor is connected with the clamping voltage source. The second end of the thirteenth resistor is connected with the drain of the first MOS transistor. The first end of the fourteenth resistor is connected with the first end of the fifth capacitor, the gate of the first MOS transistor and the fourth end of the hard disk backboard. The second end of the fifth capacitor is connected with the third end of the hard disk backboard. The second end of the fourteenth resistor is grounded.

14. The hard disk boot circuit of claim 13, wherein, The hard disk control circuit further comprises a fuse. The first end of the fuse is connected with the input end of the second programmable memory. The second end of the fuse is connected with the first end of the sixth resistor and the first end of the seventh resistor.

15. The hard disk boot circuit of claim 14, wherein, The hard disk control circuit further comprises a first group of detection circuits, a second group of detection circuits and a third group of detection circuits. The first group of detection circuits is connected with the first end of the fuse and the output end of the comparator, and is used for detecting a hard disk power supply signal and a first hard disk power supply enable signal. The second group of detection circuits is connected with the gate of the first MOS transistor and the drain of the first MOS transistor, and is used for detecting a hard disk start control signal, a hard disk in-position confirmation signal and a second hard disk power supply enable signal. The third group of detection circuits is connected with the first end of the logic operation unit, the second end of the logic operation unit and the third end of the logic operation unit, and is used for detecting the first hard disk power supply enable signal, the second hard disk power supply enable signal and the hard disk start control signal.

16. An electronic device, comprising: The control circuit of any one of claims 1-5 and / or the hard disk start circuit of any one of claims 6-15.

17. A staggered start control method, characterized by, The control circuit of claim 1 comprises: sending a start signal to the corresponding hard disk based on any one group of signal transmission ends; obtaining a hard disk signal fed back by the hard disk according to the start signal; when the hard disk signal indicates that the hard disk is started, sending a start signal to the corresponding hard disk through any one group of remaining signal transmission ends until the hard disks all perform a start process.

18. The staggered start control method of claim 17, wherein, The when the hard disk signal indicates that the hard disk is started, sending a start signal to the correspondinghard disk through any one group of remaining signal transmission ends comprises: determining whether the hard disk signal is a high-level signal within a preset time; If the hard disk signal is a high level signal within the preset time, the hard disk signal represents that the hard disk is started, and a start signal is sent to the corresponding hard disk through any one of the remaining groups of signal transmission ends; If the hard disk signal is a low level signal within the preset time, the hard disk signal represents that the hard disk is not started, a shutdown signal is sent to the current corresponding hard disk, and a start signal is sent to the corresponding hard disk through any one of the remaining groups of signal transmission ends.

19. The staggered start control method of claim 18, wherein, After the hard disk signal represents that the hard disk is not started, the method further comprises: Triggering the alarm system corresponding to the current hard disk to determine the start state of the hard disk by the operator.

20. The staggered start control method of claim 18, wherein After the hard disk signal represents that the hard disk is not started, the method further comprises: Summarizing the hard disk signal through the backplane control circuit, and displaying the summary result of the hard disk signal through the display device connected with the backplane control circuit.

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