Data writing method and memory controller

Abstract

Provided in the present invention are a data writing method and a memory controller, which are applicable to a rewritable non-volatile memory module having a plurality of storage units. The method comprises the following steps: first, acquiring original data from a host system; then, executing a plurality of randomization operations on the original data, so as to acquire a plurality of pieces of write data; next, executing a first randomization verification operation on each piece of write data, so as to acquire target write data among the plurality of pieces of write data by means of the first randomization verification operation, wherein the randomization quality of the target write data is determined to be qualified; and finally, storing the target write data into a plurality of target storage units among the plurality of storage units. By means of multiple randomization operations and verification processes, the present invention effectively improves the randomness and reliability of data storage, thereby enhancing the overall performance and data security of a storage system.

Description

Data writing method and memory controller TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor storage, and in particular, to a data writing method for a rewritable non-volatile memory module and a memory controller using the method. BACKGROUND

[0002] With the rapid development of information technology, non-volatile storage devices are increasingly widely used in various electronic products. In particular, three-dimensional NAND flash memory has become the mainstream of current non-volatile storage technology due to its high storage density, low cost, and excellent performance. However, as the storage density continues to increase, the reliability of data and the interference between storage units have become increasingly prominent.

[0003] In order to improve the reliability of data storage and reduce the interference between units, data randomization technology is widely used in NAND flash memory. Traditional data randomization methods usually use a single randomization algorithm, such as a simple XOR operation or a fixed permutation table. Although this method improves the data distribution to some extent, it often does not meet expectations in the face of increasingly complex three-dimensional NAND flash memory structures.

[0004] In addition, the prior art generally lacks an effective verification mechanism for the randomization result. Without verifying the quality of randomization, directly writing data may result in uneven distribution of certain data patterns in the memory, thereby affecting storage performance and reliability. In particular, in high-density storage scenarios, improper data distribution may cause read interference, write interference, and other problems, thereby shortening the service life of the storage device. SUMMARY

[0005] The purpose of the present application is to solve the above problems, to be able to perform multiple randomization operations and effectively verify the quality of randomization, to ensure that the data written to the memory has good random distribution characteristics, thereby improving the reliability and performance of storage.

[0006] One or more embodiments of the present application provide a data writing method for a rewritable non-volatile memory module having a plurality of storage units. The method comprises: obtaining original data from a host system; performing a plurality of randomization operations on the original data to obtain a plurality of write data; performing a randomization verification operation on each write data to obtain a target write data in the plurality of write data, wherein the quality of randomization of the target write data is determined to be qualified; and storing the target write data to a plurality of target storage units among the plurality of storage units.

[0007] One or more embodiments of the present disclosure provide a memory controller suitable for a storage device configured with a rewritable non-volatile memory module, wherein the storage device is electrically connected to a host system. The memory controller comprises a memory interface control circuit electrically connected to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of storage units; and a processor electrically connected to the memory interface control circuit. The processor is configured to: obtain original data from the host system; perform a plurality of randomization operations on the original data to obtain a plurality of write data; perform a randomization verification operation on each write data to obtain a target write data of the plurality of write data, wherein a quality of randomization of the target write data is determined to be qualified; and store the target write data to a plurality of target storage units among the plurality of storage units.

[0008] Based on the above, the data writing method and the memory controller provided by the present disclosure have remarkable advantages in improving data randomization quality, optimizing storage efficiency, prolonging device life, etc. An efficient, reliable and adaptive solution is provided for data storage management of non-volatile storage devices. BRIEF DESCRIPTION OF DRAWINGS

[0009] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0010] FIG. 1 is a block diagram of a host system and a storage device according to an embodiment of the present disclosure;

[0011] FIG. 2 is a flowchart of a data writing method according to an embodiment of the present disclosure;

[0012] FIG. 3 is a schematic diagram of a randomization operation according to an embodiment of the present disclosure;

[0013] FIG. 4 is a schematic diagram of a three-dimensional circuit architecture of a plurality of storage units of a rewritable non-volatile memory module according to an embodiment of the present disclosure;

[0014] FIG. 5 is a flowchart of a randomization verification operation according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0015] Reference will now be made in detail to the exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used in the drawings and the description to refer to the same or like parts.

[0016] Figure 1 is a block diagram of a host system and a storage device according to an embodiment of the present application. Referring to Figure 1, the host system 10 is, for example, a personal computer, a notebook computer, a server. The host system 10 includes a processor 110 (also referred to as a second processor) and a host memory 120, a data transfer interface circuit 130. In this embodiment, the processor 110 is coupled to (also referred to as electrically connected to) the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, the host memory 120 and the data transfer interface circuit 130 are electrically connected to each other by a system bus. In this embodiment, the processor 110, the host memory 120 and the data transfer interface circuit 130 can be disposed on a host board of the host system 10. In this embodiment, the original data is, for example, user data transmitted by the host system 10 to the storage device 20, or data that has not been subjected to a randomization operation.

[0017] The storage device 20 includes a storage controller 210, a rewritable non-volatile memory module 220 and a connection interface circuit 230. The storage controller 210 includes a processor 211 (also referred to as a first processor), a data management circuit 212 and a memory interface control circuit 213.

[0018] In this embodiment, the host system 10 is electrically connected to the storage device 20 through the data transfer interface circuit 130 and the connection interface circuit 230 of the storage device 20 to perform a data access operation. For example, the host system 10 can store data to the storage device 20 or read data from the storage device 20 via the data transfer interface circuit 130.

[0019] In the present embodiment, the number of data transfer interface circuits 130 can be one or more. Through the data transfer interface circuits 130, the host board can be electrically connected to the storage device 20 via wired or wireless means. The storage device 20 can be, for example, a USB flash drive, a memory card, a solid state drive (SSD), or a wireless memory storage device. The wireless memory storage device can be, for example, a Near Field Communication (NFC) memory storage device, a WiFi memory storage device, a Bluetooth memory storage device, or a Bluetooth Low Energy memory storage device (e.g., iBeacon), or the like memory storage device based on various wireless communication technologies. In addition, the host board can also be electrically connected to various I / O devices such as a Global Positioning System (GPS) module, a network interface card, a wireless transmission device, a keyboard, a screen, a speaker, and the like via a system bus.

[0020] In the present embodiment, the data transfer interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In addition, data transfer between the data transfer interface circuit 130 and the connection interface circuit 230 is performed using the Non-Volatile Memory express (NVMe) communication protocol.

[0021] In another embodiment, the connection interface circuit 230 can be packaged in a chip with the memory controller 210, or the connection interface circuit 230 can be disposed outside a chip containing the memory controller 210.

[0022] In the present embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. For example, in the present embodiment, the host memory 120 can be a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), or the like. However, it must be understood that the present application is not limited thereto, and the host memory 120 can also be other suitable memories.

[0023] The memory controller 210 is used to execute a plurality of logic gates or control instructions implemented in a hardware or firmware type and perform operations such as writing, reading, and erasing data in the rewritable non-volatile memory module 220 according to instructions of the host system 10.

[0024] In more detail, the processor 211 in the memory controller 210 is a hardware with computing capability, which is used to control the overall operation of the memory controller 210. Specifically, the processor 211 is programmed with a plurality of control instructions / program codes, and when the storage device 20 is operated, the control instructions / program codes are executed to perform operations such as writing, reading and erasing data. In addition, in the present embodiment, the control instructions / program codes can also be executed to perform a data writing operation, a randomization verification operation or a randomization operation, so as to implement the data writing method provided by the present application. The control instructions / program codes corresponding to the data writing method can also be implemented as a circuit unit in hardware form, so as to implement the data writing method provided by the present application.

[0025] It is worth mentioning that, in the present embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a micro-processor, or other programmable processing units (Microprocessor), a digital signal processor (DSP), a programmable controller, an application specific integrated circuit (ASIC), a programmable logic device (PLD) or other similar circuit components, and the present application is not limited thereto.

[0026] In the present embodiment, as described above, the memory controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by the components of the memory controller 210 can also be considered as operations performed by the memory controller 210.

[0027] The data management circuit 212 is electrically connected to the processor 211, the memory interface control circuit 213, and the connection interface circuit 230. The data management circuit 212 is used to accept the indication of the processor 211 to perform data transmission. For example, data is read from the host system 10 (e.g., the host memory 120) via the connection interface circuit 230, and the read data is written into the rewritable non-volatile memory module 220 via the memory interface control circuit 213 (e.g., a write operation is performed according to a write instruction from the host system 10). For another example, data is read from one or more physical units of the rewritable non-volatile memory module 220 (the data can be read from one or more storage units of one or more physical units) via the memory interface control circuit 213, and the read data is written into the host system 10 (e.g., the host memory 120) via the connection interface circuit 230 (e.g., a read operation is performed according to a read instruction from the host system 10). In another embodiment, the data management circuit 212 can also be integrated into the processor 211.

[0028] The memory interface control circuit 213 is used to accept the indication of the processor 211 to perform a write (also referred to as programming) operation, a read operation, or an erase operation on the rewritable non-volatile memory module 220 in cooperation with the data management circuit 212.

[0029] In addition, the data to be written into the rewritable non-volatile memory module 220 is converted into a format acceptable to the rewritable non-volatile memory module 220 via the memory interface control circuit 213. Specifically, if the processor 211 wants to access the rewritable non-volatile memory module 220, the processor 211 transmits a corresponding instruction sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform a corresponding operation. For example, the instruction sequence can include a write instruction sequence to instruct writing data, a read instruction sequence to instruct reading data, an erase instruction sequence to instruct erasing data, and corresponding instruction sequences to instruct various memory operations. The instruction sequence can include one or more signals, or data on a bus. The signal or data can include an instruction code or a program code. For example, in the read instruction sequence, an identification code of reading, a memory address, a physical address, and the like are included.

[0030] In addition, the memory controller 210 establishes a logical to physical address mapping table and a physical to logical address mapping table to record the mapping relationship between the logical addresses of the logical units (e.g., logical blocks, logical pages) configured to the rewritable non-volatile memory module 220 and the physical addresses of the physical units (e.g., physical erase units / physical blocks, physical pages). In other words, the memory controller 210 can look up the physical unit mapped by a logical unit (e.g., look up the physical page mapped by a logical page; look up the physical address mapped by a logical address) through the logical to physical address mapping table (also referred to as a logical to physical mapping table), and the memory controller 210 can look up the logical unit mapped by a physical unit (e.g., look up the logical page mapped by a physical page; look up the logical address mapped by a physical address) through the physical to logical address mapping table (also referred to as a physical to logical mapping table).

[0031] In an embodiment, the memory controller 210 further includes a buffer memory 214. The buffer memory is electrically connected to the processor 211 and is used to temporarily store data and instructions from the host system 10, data from the rewritable non-volatile memory module 220, or other system data (e.g., various mapping tables, index tables, various information or data related to randomization operations and randomization verification operations) used to manage the storage device 20, so that the processor 211 can quickly access the data, instructions, or system data from the buffer memory 214. In an embodiment, the memory controller 210 can establish one or more write mapping tables in the buffer memory 214 to indicate the target physical addresses for writing valid data. It should be noted that in other embodiments, the buffer memory 214 can also be configured outside the memory controller 210. Alternatively, the memory controller 210 can be configured with the buffer memory 214 inside and outside.

[0032] The rewritable non-volatile memory module 220 is electrically connected to the memory controller 210 (the memory interface control circuit 213) and is used to store user data sent by the host system 10.

[0033] In this embodiment, each memory die (chip) of the rewritable non-volatile memory module 220 has a plurality of planes, and each plane has a plurality of physical blocks. Each physical block includes a plurality of physical program units (also referred to as physical pages). Each physical page has a plurality of memory cells (also referred to as physical bytes or bytes), each of which corresponds to a physical address. The physical address is used to record the physical location of the data stored in the memory cell. It should be noted that the present application is not limited to the size of each physical page and logical page.

[0034] FIG. 2 is a flowchart of a data writing method according to an embodiment of the present application.

[0035] Referring to FIG. 2, in step S210, the memory controller 210 (processor 211) obtains original data from the host system 10. Next, in step S220, the processor 211 performs a plurality of randomization operations on the original data to obtain a plurality of write data.

[0036] In an embodiment, the processor 211 performs a randomization operation on the original data to obtain write data, wherein the randomization operation is used to change the distribution pattern of first bit values and second bit values in the original data, so that the arrangement of the first bit values and the second bit values in the write data exhibits a random distribution characteristic, wherein the first bit values and the second bit values correspond to "0" and "1" in binary data, respectively. After performing the randomization operation, the processor 211 stores the obtained corresponding write data to the buffer memory 214.

[0037] FIG. 3 is a schematic diagram of a randomization operation according to an embodiment of the present application. For example, the randomization operation of the present application can be further illustrated by a specific example. As shown in FIG. 3, the figure shows the process of performing a randomization operation on original data. In this example, consider two groups of original data OD1 and OD2, each containing 8 bits.

[0038] OD1 consists of 8 consecutive "1"s (11111111), and OD2 consists of 8 consecutive "0"s (00000000). These two groups of data represent a non-random distribution in an extreme case, in which the distribution of the first bit value ("0") and the second bit value ("1") is highly concentrated. The original data is, for example, user data to be stored by the host system 10 to the storage device 20.

[0039] By performing the randomization operation, the corresponding write data WD1, WD2, WD3, and WD4 is obtained. Specifically:

[0040] After the (first) randomization operation A31 on OD1, WD1 (01010101) is generated.

[0041] OD1 after another (second) randomization operation A32, generates WD2 (10101010).

[0042] OD2 after a (third) randomization operation A33, generates WD3 (10101010).

[0043] OD2 after another (fourth) randomization operation A34, generates WD4 (01010101).

[0044] As can be seen from the results, regardless of whether the original data is all "1" or all "0", the write data obtained after the randomization operation presents a pattern of uniform alternation of "0" and "1". This pattern obviously changes the original distribution of the first bit value and the second bit value in the original data, so that the arrangement of "0" and "1" in the write data presents a more random distribution characteristic.

[0045] It is worth noting that although the write data in this example presents a regular alternating pattern, this is only for simplicity of explanation. In actual applications, the results of the randomization operation will usually produce a more complex and irregular bit distribution to ensure the security of data stored in the storage device.

[0046] Through this example, it can be clearly seen how the randomization operation effectively changes the distribution pattern of the bit values in the original data, thereby achieving the purpose of data randomization. This randomization not only improves the uniformity of data storage, so that the storage cells will not be affected by the non-uniform distribution of data bit values, but also enhances the security of the data.

[0047] In more detail, in an embodiment, the process of performing multiple randomization operations on the original data can use different randomization algorithms to process the original data, wherein the different randomization algorithms include at least one of the following:

[0048] (1) XOR operation: the system (e.g., processor 211) predefines multiple groups of random sequences of different lengths, stored in a lookup table. According to the size of the original data, select a random sequence of appropriate length. If the length of the original data exceeds the random sequence, use the random sequence in a loop. When performing the XOR operation, each bit of the original data is XORed with the corresponding bit of the random sequence to generate the first write data.

[0049] (2) Shift operation: the system maintains a pool of shift values, containing different cyclic shifts and logical shifts. When performing a shift operation on the original data, a value is selected from the pool and applied to the entire data block. For large data blocks, they can be segmented into fixed-size segments, each segment using a different shift value, then recombined to generate the second kind of written data.

[0050] (3) Permutation operation: the system predefines multiple permutation tables, each defining a different bit reordering pattern. A permutation table is selected and used to reorder the bits in the original data according to the defined order. For large data blocks, they can be segmented into fixed-size segments, each segment using a different permutation table, then recombined to generate the third kind of written data.

[0051] (4) Dynamic random seed operation: the system collects multiple system variables as inputs for the random seed, including but not limited to: system time (including the local time of the host system 10 or the storage device 20), data address, temperature sensor reading, power supply voltage fluctuation value, working frequency of the memory controller 210, number of recent data read / write operations, unique identifier of the storage device 20, process ID or thread ID of the host system 10, MAC address of the network interface (if available), current remaining capacity of the storage device 20, running time since the last boot, value of the internal error counter of the storage device 20, etc. The system can select one of these variables as a seed, or combine multiple variables to generate a more complex seed. For example, the system time, temperature reading, and error counter value can be combined using bit operations to generate a composite seed. Using this seed to initialize a pseudo-random number generator (such as a linear congruential generator or a Mersenne Twister algorithm), a random sequence is generated. Then, this random sequence is used to transform the original data (such as XOR operation or bitwise addition), generating the fourth kind of written data.

[0052] (5) Grouping operation: the original data is divided into multiple sub-blocks, each sub-block can be fixed size (such as 4KB) or dynamically determined (such as based on the entropy value of the data). For each sub-block, the system selects one or more of the above four operations to combine and apply. For example:

[0053] The first sub-block can first perform the XOR operation, then the shift operation.

[0054] The second sub-block can first perform the permutation operation, then use the dynamic random seed operation.

[0055] The third sub-block can only perform the dynamic random seed operation.

[0056] After processing all sub-blocks, they are recombined to form the fifth kind of written data.

[0057] Through these five different randomization operations, the system generates five different types of write data. This diverse randomization strategy increases the randomness of the data, resulting in a more uniform distribution of the bit states of the final written data.

[0058] Please return to Figure 2. Next, in step S230, the processor 211 performs a randomization verification operation on each piece of written data to obtain the target written data among the plurality of written data, wherein the quality of randomization of the target written data is determined to be qualified.

[0059] Before explaining the details of the randomization verification operation, the three-dimensional circuit architecture of the multiple memory cells of the rewritable non-volatile memory module 220 is described, wherein the multiple memory cells are considered to be configured at the intersection of M first reference lines corresponding to the X direction, P second reference lines corresponding to the Y direction, and Q third reference lines corresponding to the Z direction.

[0060] Figure 4 is a schematic diagram of the three-dimensional circuit architecture of multiple memory cells of a rewritable non-volatile memory module according to an embodiment of the present invention. This structure includes multiple key components, forming a complex three-dimensional memory array. Taking a NAND-type rewritable non-volatile memory module as an example, the specific structure is as follows:

[0061] Word Lines (WL): Marked as WL0, WL1, WL2, and WL3 in the diagram, they are arranged horizontally along the x-axis. Each plane has multiple parallel word lines used to select memory cells in a specific layer. A word line can be considered as the first baseline corresponding to the x-direction (also called the first direction).

[0062] Bit lines (BL): Marked as BL0, BL1, BL2, etc. in the diagram, they are arranged vertically along the y-axis. Word lines can be regarded as the second baseline corresponding to the Y-direction (also known as the second direction).

[0063] Cell String (CSTR): A physical structure containing a series of vertically stacked memory cells, with a top SST and a bottom GST. It represents a complete vertical NAND string in a three-dimensional memory array and is the basic building block of the memory array.

[0064] String Line (SL): denoted as SL0, SL1, SL2, etc. in the figure, arranged vertically along the z-axis direction. Each string line contains a series of vertically stacked memory cells, forming a NAND string structure. The string line can be regarded as the third reference line corresponding to the Z direction (also referred to as the third direction). The CSTR (Cell String) in the present application refers to a complete vertical structure containing a series of vertically stacked memory cells and a top SST and a bottom GST. Among them, the vertical memory cell stack part inside the CSTR can be referred to as a string line (String Line).

[0065] Source Select Line (SSL): located at the top of the NAND string, used to control the source select transistor (SST).

[0066] Ground Select Line (GSL): located at the bottom of the NAND string, used to control the ground select transistor (GST).

[0067] Common Source Line (CSL): located at the bottom, providing a common source connection for all NAND strings.

[0068] Memory Cell Transistor (MCT): denoted as MCT in the figure, is the actual data storage unit.

[0069] Source Select Transistor (SST): located at the top of each NAND string, controlled by SSL.

[0070] Ground Select Transistor (GST): located at the bottom of each NAND string, controlled by GSL.

[0071] In short, in this three-dimensional structure, the three-direction reference is:

[0072] X direction: word line (WL), first reference line;

[0073] Y direction: bit line (BL), second reference line;

[0074] Z direction: string line (SL); third reference line.

[0075] The intersection of the three reference lines is set as a memory cell (labeled as "Cell" in the figure). Each memory cell is located at the intersection of a specific WL, BL, and SL, and can independently store and access data. This three-dimensional structure significantly improves storage density, allowing more memory cells to be accommodated on the same chip area. It should be noted that the three directions are perpendicular to each other.

[0076] In an embodiment, the processor 211 obtains a plurality of bit values for each write data, each of which is one of a predetermined N-bit state. In the present application, the memory cells of the non-volatile storage device can be configured to store different amounts of bit data. The number of bits that each memory cell can store can vary depending on the specific application requirements and technical implementation, ranging from 1 bit to multiple bits. There are several types: SLC (Single-Level Cell), single-layer cell; MLC (Multi-Level Cell), multi-layer cell; TLC (Triple-Level Cell), three-layer cell; QLC (Quad-Level Cell), four-layer cell; PLC (Penta-Level Cell), five-layer cell.

[0077] Specifically, a single memory cell can be programmed to have 2 X different threshold voltage states, where X represents the number of bits that the memory cell can store. For example, when X = 1, the memory cell has two bit states and can store 1 bit of data (SLC); when X = 2, the memory cell has four bit states (MLC) and can store 2 bits of data; when X = 3, the memory cell has eight bit states and can store 3 bits of data (TLC); when X = 4, the memory cell has 16 bit states and can store 4 bits of data (QLC); when X = 5, the memory cell has 32 bit states and can store 5 bits of data (PLC). And so on. This approach allows the storage device to achieve different storage densities under the same physical structure, balancing capacity, performance, and reliability.

[0078] Taking TLC (Triple-Level Cell) flash memory as an example, each memory cell can store 3 bits of information / data, corresponding to 8 bit states (N = 8), usually denoted as S0, S1, S2, S3, S4, S5, S6, and S7. The processor 211 reads the voltage level of each memory cell and converts it to the corresponding bit state. For example, the voltage level of a certain memory cell may correspond to state S3.

[0079] The following embodiments are used to illustrate the implementation of the randomization verification operation of the present application.

[0080] Embodiment 1: Obtain the N state proportions of the N bit states of the write data.

[0081] For example, in one embodiment, assume that the storage unit is SLC, i.e., X = 1, N = 2 1 = 2.

[0082] Initially, the processor 211 obtains the multiple bit values of the write data. Assume that the obtained write data is "10110101" of eight bits.

[0083] Next, the processor 211 obtains the state proportions of the N bit states.

[0084] In this example, N = 2, indicating that there are two states, e.g., S0 = 0 and S1 = 1, and their quantities are 3 and 5, respectively.

[0085] Next, the processor 211 divides the quantity of each bit state by the total bit quantity, and can calculate:

[0086] The state proportion of bit state S0 (0): 3 / 8 = 37.5%

[0087] The state proportion of bit state S1 (1): 5 / 8 = 62.5%

[0088] Next, the processor 211 obtains the randomization quality:

[0089] In this simple embodiment, the processor 211 can preliminarily judge the randomization quality by comparing the proportions of the two states. If the proportions of the two bit states are not significantly different, it is considered that the randomization quality is good. For example, if the difference between the proportions of the two states is less than a preset threshold value, it is determined that the proportions of the two states are not significantly different, and the randomization quality is good.

[0090] Embodiment 2: Introduce a reference proportion value.

[0091] In this embodiment, the concept of a reference proportion value is introduced and used to evaluate the randomization quality.

[0092] The reference proportion value corresponding to a storage unit is 100% divided by the total quantity of the corresponding bit states. For example, taking MLC (Multi-Level Cell) as an example, X = 2, N = 2 2 = 4, the reference proportion value is 100% / 4 = 25%.

[0093] Initially, the processor 211 obtains the multiple bit values of the write data. Here, assume that the write data is "1001101110100011".

[0094] Next, the processor 211 obtains the state proportion of the N-bit states. In this example, N = 4, representing four bit states: 00, 01, 10, 11.

[0095] Next, the processor 211 divides the number of each bit state by the total number of bits, and can calculate:

[0096] Proportion of bit state S0 (00): 3 / 8 = 37.5%

[0097] Proportion of bit state S1 (01): 2 / 8 = 25%

[0098] Proportion of bit state S2 (10): 2 / 8 = 25%

[0099] Proportion of bit state S3 (11): 1 / 8 = 12.5%

[0100] Next, the processor 211 obtains the reference proportion value. Ideally, the state proportion of each of the four bit states should be equal, i.e. 100% / 4 = 25%.

[0101] Finally, the processor 211 obtains the randomization quality:

[0102] For example, the processor 211 compares the actual state proportions with the reference proportion value to evaluate the randomization quality. The randomization quality can be quantified using the average deviation or other statistical methods.

[0103] For example, the processor 211 can judge the randomization quality from the state proportions of each bit state and the reference proportion value via the following algorithm:

[0104] (1) Average deviation method

[0105] The processor 211 calculates the absolute deviation between each state proportion and the reference proportion value, and then takes the average value:

[0106] |S0 deviation| = |37.5% - 25%| = 12.5%

[0107] |S1 deviation| = |25% - 25%| = 0%

[0108] |S2 deviation| = |25% - 25%| = 0%

[0109] |S3 deviation| = |12.5% - 25%| = 12.5%

[0110] Average deviation = (12.5% + 0% + 0% + 12.5%) / 4 = 6.25%

[0111] The processor 211 can set a threshold value, e.g., 5%. If the average deviation is less than or equal to the threshold value, the randomization quality is determined to be qualified; otherwise, it is determined to be unqualified.

[0112] (2) Maximum deviation method

[0113] The processor 211 finds the maximum value among all deviations:

[0114] Maximum deviation = max(12.5%, 0%, 0%, 12.5%) = 12.5%

[0115] The processor 211 can set a corresponding threshold value (also referred to as a first preset threshold value), e.g., 10%. If the maximum deviation is not greater than the threshold value, the randomization quality is determined to be qualified; otherwise, it is determined to be unqualified.

[0116] (3) Standard deviation method

[0117] The processor 211 calculates the standard deviation of the state proportions:

[0118] Average proportion (reference proportion value) = (37.5% + 25% + 25% + 12.5%) / 4 = 25%

[0119] Standard deviation = sqrt([(37.5% - 25%) 2 + (25% - 25%) 2 + (25% - 25%) 2 + (12.5% - 25%) 2 ] / 4)

[0120] ≈ 9.01%

[0121] The processor 211 can set a corresponding threshold value, e.g., 8%. If the standard deviation is less than or equal to the threshold value, the randomization quality is determined to be

[0122] (4) Entropy method

[0123] The processor 211 calculates the entropy value of the state distribution to measure randomness:

[0124] Entropy = -∑(Pi * log2(Pi))

[0125] = - (0.375 * log2(0.375) + 0.25 * log2(0.25) + 0.25 * log2(0.25) + 0.125 * log2(0.125))

[0126] ≈ 1.91

[0127] Maximum entropy (completely random state) = log2(N) = log2(4) = 2

[0128] Relative Entropy = Actual Entropy / Maximum Entropy = 1.91 / 2 = 0.955

[0129] The processor 211 can set a corresponding threshold, for example, 0.9. If the relative entropy is greater than or equal to the threshold, the randomization quality is determined to be qualified; otherwise, it is determined to be unqualified.

[0130] Through these different statistical methods, the processor 211 can comprehensively evaluate the quality of the randomization of each write data.

[0131] When the quality of the randomization of a write data is determined to be qualified, the processor 211 can take this write data as a target write data.

[0132] In an embodiment, when the processor 211 obtains a target write data, it does not need to perform randomization verification operations on other write data any more, so as to save system resources.

[0133] However, in another embodiment, the processor 211 can perform randomization verification operations on all write data, so as to find a write data with qualified and best (e.g., the minimum maximum deviation value) randomization quality as a target write data, thereby further improving the reliability and security of data storage of the storage device 20.

[0134] Please refer back to FIG. 2. After obtaining the target write data, then in step S240, the processor 211 stores the target write data in a plurality of target storage units among the plurality of storage units of the rewritable non-volatile memory module 220. In more detail, the processor 211 corresponds the physical addresses of the plurality of target storage units to the target write data, and updates the corresponding mapping information after the target write data is programmed to the physical addresses. In addition, this process can involve the wear leveling algorithm of the flash memory controller, so as to ensure that the number of times of using the storage units is balanced, thereby prolonging the service life of the storage device.

[0135] On the other hand, the processor 211 generates and stores metadata related to the target write data, which are associated with subsequent read and recovery operations. In an embodiment, the metadata include one or more of the following:

[0136] a. Randomization algorithm identifier: used to identify the randomization algorithm used to generate the target write data, for subsequent de-randomization operations.

[0137] b. Data mapping table: records the correspondence between data blocks and physical storage unit addresses.

[0138] c. Error correction code (ECC): used to detect and correct possible bit errors.

[0139] d. Timestamp: records the time when the data is written, used for data version control and recovery.

[0140] e. Data length: records the length of the original data, used for subsequent de-randomization operation.

[0141] f. Checksum: used to verify the integrity of the data.

[0142] In an embodiment, when the storage controller 210 receives a read instruction from the host system 10, the processor 211 performs the following steps to recover the original data:

[0143] (1) Parse the read instruction: the processor 211 parses the read instruction from the host system 10, determines the logical address range of the data that needs to be read.

[0144] (2) Address translation: the processor 211 uses the mapping table of logical to physical entities to convert the logical address to the corresponding physical address.

[0145] (3) Read metadata: the processor 211 first reads the metadata related to the target data. These metadata are usually stored in predefined special pages or blocks, containing:

[0146] a. Randomization algorithm identifier

[0147] b. Data mapping table

[0148] c. Error correction code (ECC)

[0149] d. Data length

[0150] e. Checksum

[0151] (4) Read randomized data: according to the data mapping table in the metadata, the processor 211 reads the randomized target write data from the corresponding physical address.

[0152] (5) Error checking and correction: the processor 211 uses the read ECC information to perform error checking on the data. If correctable errors are found, they are corrected. If uncorrectable errors are found, the data block is marked as an error, and other recovery mechanisms are tried.

[0153] (6) Data integrity verification: in an embodiment, the processor 211 also uses the stored checksum to verify the integrity of the read data. If the verification fails, data recovery procedures may need to be initiated or an error reported to the host system.

[0154] (7) Determine the de-randomization algorithm: after obtaining the successfully decoded target write data, the processor 211 determines the de-randomization algorithm to be used according to the randomization algorithm identifier in the metadata.

[0155] (8) Perform de-randomization operation: The processor 211 performs a de-randomization operation on the read randomized data. This process is the inverse of the write-time randomization operation and can include:

[0156] a. Inverse shift operation

[0157] b. Inverse of XOR operation

[0158] c. Inverse permutation operation

[0159] d. Inverse operation using the same random seed

[0160] (9) Data length adjustment: In an embodiment, the processor 211 can also trim the de-randomized data to ensure that the recovered data length is consistent with the original data, according to the original data length recorded in the metadata.

[0161] (10) Data transmission: After obtaining the corresponding original data, the processor 211 transmits the recovered original data to the host system 10 through the connection interface circuit 230 to respond to the read instruction.

[0162] Through this detailed de-randomization process, the storage controller 210 can accurately recover the randomized target write data stored in the storage device 20 into the corresponding original data and securely transmit it to the host system 10. This process not only ensures the correct recovery of data, but also includes steps such as error detection, correction, and data integrity verification to improve the reliability and correctness of data reading. It should be noted that the randomization operation and the de-randomization operation can implement the randomization / de-randomization algorithms mentioned above via specific randomization circuitry and de-randomization circuitry. In addition, the randomization circuitry and the de-randomization circuitry can also be integrated into the same circuit unit.

[0163] FIG. 5 is a flowchart of a randomization verification operation according to an embodiment of the present application.

[0164] Referring to FIG. 5, the present embodiment describes a method for verifying the quality of write data randomization, which is suitable for a rewritable non-volatile memory module having a plurality of storage units. The method is performed by a processor of a storage controller and mainly includes the following steps:

[0165] Obtain bit values (step S510):

[0166] The processor obtains a plurality of bit values of the write data. Each bit value corresponds to one of N bit states, where N = 2 XX is the number of bits that each memory cell can store. For example, for MLC (Multi-Level Cell) flash memory, X = 2, N = 4, which means each memory cell can store 2 bits of data with 4 possible states.

[0167] Calculate state proportions (step S520):

[0168] The processor calculates N state proportions of N bits states of the written data according to the obtained multiple bit values. For example, for MLC flash memory, the possible states are 00, 01, 10, 11, and the processor calculates the proportion of each state in the written data.

[0169] Obtain reference proportion value (step S530):

[0170] The processor obtains a reference proportion value based on N bit states. Ideally, the proportion of each state should be equal, i.e. the reference proportion value is 1 / N. For example, for MLC flash memory, the reference proportion value is 25%.

[0171] Calculate deviation values (step S540):

[0172] The processor calculates N deviation values between N state proportions and reference proportion value based on multiple bit values. This step quantifies the degree of data randomization by comparing the actual state proportion with the ideal state proportion.

[0173] Determine the maximum deviation value (step S550):

[0174] The processor determines the maximum deviation value among N deviation values. This maximum deviation value represents the degree of deviation of data distribution from the ideal random state.

[0175] Judge the quality of randomization (steps S560, S570, S580):

[0176] The processor compares the maximum deviation value with a preset threshold:

[0177] a) If the maximum deviation value is not greater than the first preset threshold, it is determined that the quality of randomization of the written data is qualified (step S570).

[0178] b) If the maximum deviation value is greater than the first preset threshold, it is determined that the quality of randomization of the written data is unqualified (step S580).

[0179] In another embodiment, when the maximum deviation value is determined to be greater than the first preset threshold, the processor 211 can perform a further determination to determine the deviation degree of the overall state proportion. For example, if the maximum deviation value is greater than the first preset threshold, in addition to determining that the randomization quality is unqualified, the processor 211 can further determine whether the maximum deviation value is greater than a second preset threshold. If it is greater than the second preset threshold, one or more target deviation values (i.e., all deviation values greater than the first preset threshold are found as target deviation values) greater than the first preset threshold among the N deviation values are obtained. This step helps to identify particularly serious randomization problems.

[0180] Through this process, the processor 211 can comprehensively evaluate the randomization quality of the written data. This method not only considers the overall randomization degree, but also identifies abnormal distribution of specific bit states.

[0181] The advantages of this embodiment include:

[0182] Strong adaptability: can be applied to different types of flash memory (SLC, MLC, TLC, QLC, etc.).

[0183] Accurate evaluation: by calculating specific deviation values, a quantitative evaluation of randomization quality is provided.

[0184] Multi-level judgment: multiple thresholds are used, which can more finely classify randomization quality problems.

[0185] Problem positioning: can identify which specific state distribution has problems, which is beneficial for targeted optimization.

[0186] The following uses a complete embodiment to illustrate the randomization verification operation of the present application.

[0187] Assuming that TLC (Triple-Level Cell) flash memory is used, the preset number of bit states is 8 (N = 8), corresponding to S0 to S7. In an ideal case, the reference proportion value (P base ) of each state is 12.5%.

[0188] After reading all the memory cells, the processor 211 obtains the following actual state proportions (Px):

[0189] S0: 13.0%; S1: 11.0%; S2: 12.5%; S3: 13.2%; S4: 12.8%; S5: 11.9%; S6: 13.3%; S7: 12.3%

[0190] Next, the processor 211 calculates the deviation value (Δ) of each state, which is the absolute value of the difference between the actual proportion value (state proportion of each bit state) and the reference proportion value (i.e., Δ = |Px-Pbase |):

[0191] S0: |13.0% - 12.5%| = 0.5%

[0192] S1: |11.0% - 12.5%| = 1.5%

[0193] S2: |12.5% - 12.5%| = 0%

[0194] S3: |13.2% - 12.5%| = 0.7%

[0195] S4: |12.8% - 12.5%| = 0.3%

[0196] S5: |11.9% - 12.5%| = 0.6%

[0197] S6: |13.3% - 12.5%| = 0.8%

[0198] S7: |12.3% - 12.5%| = 0.2%

[0199] The processor 211 finds the maximum deviation value (Δmax): Δmax = 0.8% (corresponding to state S6)

[0200] Assuming the first preset threshold is 1%, then: 0.8% (Δmax) < 1% (first preset threshold).

[0201] Therefore, in this example, the processor 211 determines that the quality of the randomization of the written data is qualified via the randomization verification operation. This indicates that although there is a certain deviation between the actual distribution of each state and the ideal uniform distribution, the degree of deviation is within an acceptable range.

[0202] If the maximum deviation value exceeds the first preset threshold, the processor 211 will determine that the quality of the randomization is unqualified. For example, if the actual proportion of S1 is changed to 9%, its deviation value is 3.5%, which exceeds the first preset threshold of 1%, at which point the randomization will be determined to be unqualified (failed the randomization verification operation).

[0203] This rapid detection method can effectively identify states with abnormal distributions, providing a basis for subsequent data processing or hardware adjustment, thereby improving the reliability and performance of the flash memory.

[0204] In another embodiment, in the first randomization verification operation, the processor 211 not only determines whether the maximum deviation value exceeds the first preset threshold, but also introduces a second preset threshold for more detailed evaluation. This method can distinguish between minor randomization unqualification and serious circuit design problems. The following is a specific example to illustrate this advanced verification process:

[0205] Assume that the TLC flash memory is used, there are 1,000,000 memory cells, and 8-bit states (S0-S7). The reference percentage (P base ) is 12.5%. The first preset threshold is set to 1%, and the second preset threshold is set to 2%. After the processor 211 reads all the memory cells, the following actual state percentage (Px) is obtained: S0: 15.0%; S1: 9.0%; S2: 12.5%; S3: 10.2%; S4: 14.8%; S5: 15.9%; S6: 12.3%; S7: 10.3%.

[0206] The processor 211 calculates the deviation value (Δ) of each bit state:

[0207] S0: |15.0%-12.5%| = 2.5%

[0208] S1: |9.0%-12.5%| = 3.5%

[0209] S2: |12.5%-12.5%| = 0%

[0210] S3: |10.2%-12.5%| = 2.3%

[0211] S4: |14.8%-12.5%| = 2.3%

[0212] S5: |15.9%-12.5%| = 3.4%

[0213] S6: |12.3%-12.5%| = 0.2%

[0214] S7: |10.3%-12.5%| = 2.2%

[0215] The processor 211 determines the maximum deviation value (Δmax): Δmax = 3.5% (corresponding to state S1)

[0216] Since 3.5%>1% (the first preset threshold), the processor 211 determines that the randomization is not qualified. Then, the processor 211 continues to determine: 3.5% (Δmax)>2% (the second preset threshold).

[0217] Because the maximum deviation value exceeds the second preset threshold, the processor 211 considers that this may represent a serious problem in the circuit design of the flash memory chip. In this case, the processor 211 obtains all the states that exceed the first preset threshold (1%): S0 (2.5%), S1 (3.5%), S3 (2.3%), S4 (2.3%), S5 (3.4%), S7 (2.2%). The processor 211 marks these states as abnormal states for subsequent analysis and optimization.

[0218] In contrast, if the maximum deviation value is between the first and second preset thresholds, for example, Δmax=1.5%, the processor 211 will only obtain the state that currently exceeds the first preset threshold (S1).

[0219] This advanced verification method has the following advantages: it can quickly identify slight randomization unqualified cases; it can detect possible serious circuit design problems. When serious problems are found, more comprehensive abnormal state information is provided to facilitate in-depth analysis and targeted improvement. In addition, by distinguishing different degrees of randomization unqualified, corresponding processing strategies can be taken to improve the reliability and performance of the flash chip.

[0220] In an embodiment, when the processor 211 determines that the randomization of the write data is unqualified, further measures can be taken to assist subsequent circuit design optimization. Specifically, the processor 211 obtains the abnormal bit state corresponding to the maximum deviation value in the N-bit state; and records the abnormal bit state. In an embodiment, this record includes one or more of the following: record the type of the abnormal bit state; record the position distribution of the abnormal bit state in the write data; record the randomization operation type that leads to the abnormal bit state.

[0221] For example, assume that the write data corresponding to MLC is "11110000", the calculated state proportion is: 00:50%, 01:0%, 10:0%, 11:50%, and the maximum deviation value is 25%. Assuming that the first preset threshold is 5%, the randomization quality of the write data is determined to be unqualified.

[0222] The processor identifies that the states "00" and "11" are abnormal bit states because their deviation values (25%) are the largest.

[0223] Next, the processor records the following information:

[0224] (1) Abnormal bit state type: 00 and 11;

[0225] (2) Position distribution: 00 in the second half, 11 in the first half;

[0226] (3) Randomization operation type that leads to abnormality: for example, it may be due to a simple bit inversion operation.

[0227] It should be noted that the above examples of recording are related to the test of one threshold. However, the processor 211 can also record the corresponding abnormal bit states corresponding to the test of multiple thresholds. Specifically, after determining that the quality of the randomization of the write data is unqualified, if the maximum deviation value is not greater than the second preset threshold, the processor 211 obtains an abnormal bit state corresponding to the maximum deviation value among the N bit states, and records the abnormal bit state. On the other hand, if the maximum deviation value is greater than the second preset threshold, one or more abnormal bit states corresponding to one or more target deviation values among the N bit states are obtained, and the one or more abnormal bit states are recorded.

[0228] In addition, in some extreme examples, the quality of the randomization of all write data is unqualified. In an embodiment, the processor 211 can further adjust the plurality of randomization operations according to the abnormal bit states to regenerate a plurality of new write data; and perform the randomization verification operation on each new write data again to attempt to obtain the target write data, and then store the target write data to the plurality of target storage units. The adjustment includes: selecting or combining different randomization algorithms according to the type and distribution of abnormal bit states; adjusting the parameters of each randomization operation, such as the random sequence of the XOR operation, the shift amount of the shift operation, the permutation table of the permutation operation, etc.; increasing the complexity or strength of the randomization operation for the data part that frequently appears abnormally.

[0229] For example, after recording the information that the states "00" and "11" are abnormal bit states in the above example, the processor 211 can perform subsequent processing. For example:

[0230] (1) Adjust the randomization operation: the processor 211 can take the following adjustments:

[0231] Select a new randomization algorithm, such as introducing an adjusted random sequence of the XOR operation or block the data, and apply different randomization strategies to different blocks.

[0232] (2) Regenerate write data: the processor 211 regenerates a plurality of write data using the adjusted randomization operation.

[0233] (3) Perform randomization verification again: the processor 211 repeatedly performs the randomization verification operation on each newly generated write data until a qualified target write data is obtained.

[0234] (4) Store the target write data: the processor 211 stores the verified target write data into the plurality of target storage units

[0235] This method of dynamically adjusting randomization operations has significant technical efficacy. By analyzing abnormal bit states, the processor can selectively choose or combine different randomization algorithms, such as introducing bit shift operations or adjusting XOR sequences. Block processing of data further improves the flexibility and effectiveness of randomization. This adaptive method not only addresses specific randomization deficiencies, but also continuously optimizes data distribution, improving storage efficiency. The process of repeated verification and adjustment ensures that the data written finally has high-quality randomness, thereby prolonging the life of the storage device, improving overall performance and reliability, and reducing the risk of data hotspots and uneven wear.

[0236] The embodiment also provides a computer program product comprising computer readable code, or a non-volatile computer readable storage medium carrying computer readable code, when the computer readable code is executed in the processor of the storage device, the processor in the storage device performs the steps of the above memory test method. The computer program product can be specifically implemented by hardware, firmware, software or a combination thereof. In an optional embodiment, the computer program product is specifically embodied as a computer storage medium, and in another optional embodiment, the computer program product is specifically embodied as a software product, such as a software development kit (Software Development Kit, SDK) and the like.

[0237] The data writing method and its randomization verification operation presented by the application have significant technical efficacy. By performing multiple randomization operations on the written data and executing the corresponding verification process, this method can effectively improve the uniformity of data distribution in non-volatile memory. Specifically, this method quantifies the quality of data randomization by calculating the bit state proportion, comparing it with the reference proportion value, and determining the deviation value. A multi-level threshold judgment mechanism is introduced, which can not only identify unqualified randomization results, but also distinguish different degrees of randomization problems. Finally, the written data with qualified quality after randomization can also be obtained to store the original data. In particular, the adaptive adjustment mechanism of this method records the type, distribution position and randomization operation causing the abnormal bit state, so that the system can adjust the randomization strategy accordingly. For example, according to the abnormal state, a new randomization algorithm is selected, the XOR operation parameters are adjusted, or the data is processed in blocks. This dynamic optimization method ensures that even in the face of complex and variable data patterns, high-quality randomization results can be adaptively generated.

[0238] In addition, the iterative verification mechanism of the method further guarantees the quality of the randomized write data. By repeatedly performing the randomization operation and verification step until the target write data meeting the requirements is obtained, the method greatly improves the reliability and uniformity of the stored data. This not only optimizes the use efficiency of the storage unit, but also significantly prolongs the service life of the storage device, reduces the risk of data hotspot problems and uneven wear. In summary, the data write method and memory controller provided by the present application have significant advantages in improving data randomization quality, optimizing storage efficiency, prolonging device life, etc. It provides an efficient, reliable and adaptive solution for data storage management of non-volatile storage devices.

[0239] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A data writing method for a rewritable non-volatile memory module having multiple storage units, characterized in that, include: Retrieve raw data from the host system; Perform multiple randomization operations on the original data to obtain multiple write data; A randomization verification operation is performed on each piece of written data to obtain the target written data among the plurality of written data, wherein the quality of randomization of the target written data is determined to be qualified; The target data is written to multiple target storage units among the multiple storage units.

2. The data writing method according to claim 1, characterized in that, Each randomization operation processes the original data using a different randomization algorithm, wherein the different randomization algorithms include at least one of the following: The XOR operation performs an XOR operation between the original data and multiple predefined different random sequences; The displacement operation performs multiple different cyclic displacements or logical displacements on the original data. The permutation operation changes the order of bits in the original data according to multiple predefined permutation tables; The dynamic random seed operation generates multiple different random seeds based on system time, data address, or other system variables, and uses the multiple random seeds and the original data to generate the multiple write data. as well as The grouping operation divides the original data into multiple sub-blocks, and applies different XOR operations, shift operations, permutation operations, and dynamic random seed operations to the multiple sub-blocks.

3. The data writing method according to claim 1, characterized in that, The steps of performing the randomization verification operation on each piece of written data include: Obtain multiple bit values ​​of the written data, where each bit value corresponds to one of N bit states, and N is 2. X And X is the number of bits that can be stored in one storage unit of each storage unit; Based on the multiple bit values, obtain the percentage of N states corresponding to the N bit states of the written data; The quality of the randomization of the written data is obtained based on the proportion of the N states.

4. The data writing method according to claim 3, characterized in that, The step of performing the randomization verification operation on each piece of written data further includes: Based on the N bit states, obtain the baseline proportion value; and The quality of the randomization of the written data is obtained based on the proportions of the N states and the baseline proportion value.

5. The data writing method according to claim 4, characterized in that, The step of performing the randomization verification operation on each piece of written data further includes: Based on the multiple bit values, obtain N deviation values ​​between the N state proportions and the baseline proportion value; Determine the maximum deviation value among the N deviation values; If the maximum deviation value is not greater than the first preset threshold, the quality of the randomization of the written data is determined to be qualified; If the maximum deviation value is greater than the first preset threshold, the quality of the randomization of the written data is determined to be unqualified.

6. The data writing method according to claim 5, characterized in that, After determining that the quality of the randomization of the written data is unqualified, the method further includes: Obtain the abnormal bit state corresponding to the maximum deviation value from the N bit states; and Record the state of the abnormal bits.

7. The data writing method according to claim 6, characterized in that, If the quality of the randomization of the multiple written data is all unqualified, the method further includes: Based on the abnormal bit state, adjust the multiple randomization operations to regenerate multiple new write data; and The randomization verification operation is performed again for each new written data to attempt to obtain the target written data, and then the target written data is stored in the plurality of target storage units.

8. The data writing method according to claim 4, characterized in that, The step of performing the randomization verification operation on each piece of written data further includes: Based on the multiple bit values, obtain N deviation values ​​between the N state proportions and the baseline proportion value; Determine the maximum deviation value among the N deviation values; If the maximum deviation value is not greater than the first preset threshold, the quality of the randomization of the written data is determined to be qualified; If the maximum deviation value is greater than the first preset threshold, the randomization quality of the written data is determined to be unqualified, and it is further determined whether the maximum deviation value is greater than the second preset threshold. If the maximum deviation value is greater than the second preset threshold, one or more target deviation values ​​that are greater than the first preset threshold are obtained from the N deviation values.

9. The data writing method according to claim 8, characterized in that, After determining that the quality of the randomization of the written data is unqualified, the method further includes: If the maximum deviation value is not greater than the second preset threshold, obtain the abnormal bit state corresponding to the maximum deviation value among the N bit states, and record the abnormal bit state; and If the maximum deviation value is greater than the second preset threshold, obtain one or more abnormal bit states corresponding to the one or more target deviation values ​​from the N bit states, and record the one or more abnormal bit states.

10. A memory controller suitable for a storage device configured with a rewritable non-volatile memory module, wherein the storage device is electrically connected to a host system, characterized in that, The memory controller includes: A memory interface control circuit is provided for electrical connection to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has multiple memory cells; and The processor is electrically connected to the memory interface control circuit. The processor is configured to: Retrieve raw data from the host system; Perform multiple randomization operations on the original data to obtain multiple write data; A randomization verification operation is performed on each piece of written data to obtain the target written data among the plurality of written data, wherein the quality of randomization of the target written data is determined to be qualified; The target data is written to multiple target storage units among the multiple storage units.

11. The memory controller according to claim 10, characterized in that, Each randomization operation processes the original data using a different randomization algorithm, wherein the different randomization algorithms include at least one of the following: The XOR operation performs an XOR operation between the original data and multiple predefined different random sequences; The displacement operation performs multiple different cyclic displacements or logical displacements on the original data. The permutation operation changes the order of bits in the original data according to multiple predefined permutation tables; The dynamic random seed operation generates multiple different random seeds based on system time, data address, or other system variables, and uses the multiple random seeds and the original data to generate the multiple write data. as well as The grouping operation divides the original data into multiple sub-blocks, and applies different XOR operations, shift operations, permutation operations, and dynamic random seed operations to the multiple sub-blocks.

12. The memory controller according to claim 10, characterized in that, The steps of performing the randomization verification operation on each piece of written data include: Obtain multiple bit values ​​of the written data, where each bit value corresponds to one of N bit states, and N is 2. X And X is the number of bits that can be stored in one storage unit of each storage unit; Based on the multiple bit values, obtain the percentage of N states corresponding to the N bit states of the written data; The quality of the randomization of the written data is obtained based on the proportion of the N states.

13. The memory controller according to claim 12, characterized in that, The step of performing the randomization verification operation on each piece of written data further includes: Based on the N bit states, obtain the baseline proportion value; and The quality of the randomization of the written data is obtained based on the proportions of the N states and the baseline proportion value.

14. The memory controller according to claim 13, characterized in that, The step of performing the randomization verification operation on each piece of written data further includes: Based on the multiple bit values, obtain N deviation values ​​between the N state proportions and the baseline proportion value; Determine the maximum deviation value among the N deviation values; If the maximum deviation value is not greater than the first preset threshold, the quality of the randomization of the written data is determined to be qualified; If the maximum deviation value is greater than the first preset threshold, the quality of the randomization of the written data is determined to be unqualified.

15. The memory controller according to claim 14, characterized in that, After determining that the quality of the randomization of the written data is unacceptable, the processor is further configured to: Obtain the abnormal bit state corresponding to the maximum deviation value from the N bit states; and Record the state of the abnormal bits.

16. The memory controller according to claim 15, characterized in that, If the quality of the randomization of the plurality of written data is unsatisfactory, the processor is further configured to: Based on the abnormal bit state, adjust the multiple randomization operations to regenerate multiple new write data; and The randomization verification operation is performed again for each new written data to attempt to obtain the target written data, and then the target written data is stored in the plurality of target storage units.

17. The memory controller according to claim 13, characterized in that, The step of performing the randomization verification operation on each piece of written data further includes: Based on the multiple bit values, obtain N deviation values ​​between the N state proportions and the baseline proportion value; Determine the maximum deviation value among the N deviation values; If the maximum deviation value is not greater than the first preset threshold, the quality of the randomization of the written data is determined to be qualified; If the maximum deviation value is greater than the first preset threshold, the randomization quality of the written data is determined to be unqualified, and it is further determined whether the maximum deviation value is greater than the second preset threshold. If the maximum deviation value is greater than the second preset threshold, one or more target deviation values ​​that are greater than the first preset threshold are obtained from the N deviation values.

18. The memory controller according to claim 17, characterized in that, After determining that the quality of the randomization of the written data is unacceptable, the processor is further configured to: If the maximum deviation value is not greater than the second preset threshold, obtain the abnormal bit state corresponding to the maximum deviation value among the N bit states, and record the abnormal bit state; as well as If the maximum deviation value is greater than the second preset threshold, obtain one or more abnormal bit states corresponding to the one or more target deviation values ​​from the N bit states, and record the one or more abnormal bit states.

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