Wafer structure, packaging module and thermal test chip

Abstract

The present application relates to the technical field of thermal testing of chips. Disclosed are a wafer structure, a packaging module, and a thermal test chip. The wafer structure comprises a plurality of dies disposed at intervals and scribe lanes for connecting adjacent dies. Each die comprises a surface wiring layer, and a temperature measurement unit and a heating unit that are stacked below the surface wiring layer. Temperature measurement pins and heating pins that are independent of each other are provided on the surface wiring layer. The temperature measurement unit is electrically connected to the temperature measurement pins via temperature measurement metal vias, and the heating unit is electrically connected to the heating pins via heating metal vias. The heating pins in the plurality of dies are disposed independently of each other, and the temperature measurement pins in the plurality of dies are disposed independently of each other.

Description

Wafer structure, packaging module and thermal test chip

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Chinese Patent Application No. 202510071333.1, filed on January 16, 2025, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present application relates to the technical field of thermal testing of chips, and in particular to a wafer structure, a packaging module and a thermal test chip. BACKGROUND

[0004] With the rapid development of semiconductor technology, the integration of chips is continuously improved, and the power consumption is also increasing. In order to ensure the reliability and stability of the chip in a high-temperature working environment, thermal testing has become an indispensable part of the chip design process. Thermal test chips are widely used to simulate the working state of real chips in order to study and optimize the heat dissipation design. Thermal test chips are usually designed specifically for a certain size and type of electronic chip. For real chips of different sizes or with different thermal characteristics, independent development, wafering and packaging of corresponding thermal test chips are required, which is costly. SUMMARY

[0005] The present application provides a wafer structure, a packaging module and a thermal test chip.

[0006] The present application provides a wafer structure, a packaging module and a thermal test chip.

[0007] The present application provides a wafer structure, a packaging module and a thermal test chip.

[0008] The present application provides a wafer structure, a packaging module and a thermal test chip. BRIEF DESCRIPTION OF DRAWINGS

[0009] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0010] Figure 1 is a schematic diagram of the wafer structure embodiment of this application;

[0011] Figure 2 is a schematic cross-sectional view of a single wafer in an embodiment of the wafer structure of this application;

[0012] Figure 3 is a top view of a single wafer in an embodiment of the wafer structure of this application;

[0013] Figure 4 is a structural schematic diagram of an embodiment of the packaging module of this application;

[0014] Figure 5 is a partial structural schematic diagram of an embodiment of the packaging module of this application, wherein the die unit has been hidden;

[0015] Figure 6 is a side view of an embodiment of the packaging module of this application;

[0016] Figure 7 is a schematic diagram of a packaging state according to an embodiment of the packaging module of this application;

[0017] Figure 8 is a cross-sectional view of an embodiment of the packaging module of this application;

[0018] Figure 9 is a cross-sectional view of another embodiment of the packaging module of this application.

[0019] Explanation of reference numerals: 100, Wafer structure; 110, Chip; 111, Surface mount layer; 112, Temperature sensing unit; 113, Heating unit; 114, Temperature sensing pin; 115, Heating pin; 116, Temperature sensing metal via; 117, Heating metal via; 118, Insulating layer; 1191, Heating connection trace; 1192, Temperature sensing connection trace; 120, Substrate; 130, Cutter track; 200, Packaging module; 210, Packaging substrate; 211, Soldering unit; 212, Solder ball; 220, Die unit; 230, Transmitter board; 240, Heat sink; 250, Thermal interface material layer; 260, Underfill material layer.

[0020] The realization of the purpose, functional features and advantages of this application will be described in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the embodiments of this application.

[0022] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.

[0023] Furthermore, in the embodiments of this application, descriptions involving "first," "second," etc., are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of the embodiments of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0024] In the embodiments of this application, unless otherwise expressly specified and limited, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "fixed" can mean a fixed connection, a detachable connection, or an integral part; it can mean a mechanical connection or an electrical connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this application according to the specific circumstances.

[0025] Furthermore, the technical solutions of the various embodiments of this application can be combined with each other, but only if they are based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by the embodiments of this application.

[0026] To address the heat dissipation challenges of high-performance, high-power chips, better heat dissipation solutions are required. These typically involve using metal heating blocks, thin-film heating elements, or thermal testing chips to replace the actual chips, calibrating and verifying the feasibility of the heat dissipation approach. For actual chips of different sizes or with varying thermal characteristics, the corresponding thermal testing chips need to be independently developed, fabricated, and packaged, resulting in high development costs.

[0027] Moreover, traditional metal heating blocks or thin-film heating sheets can only generate uniform power consumption, while the internal heat generation of a real chip is uneven. Therefore, metal heating blocks and thin-film heating sheets cannot effectively characterize the junction temperature performance of a real chip when used to verify heat dissipation modules or heat dissipation solutions, especially when the internal hot spots of large-size packaged chips are prominent, which can easily lead to large deviations.

[0028] In addition, the heating unit has a low coverage area in existing thermal testing chips, resulting in uneven heating.

[0029] In view of this, the embodiments of this application provide a wafer structure, a packaging module, and a thermal testing chip. By setting multiple independent wafers on the wafer structure and utilizing dicing channels, the entire wafer structure can be cut into die units formed by arbitrary arrays of multiple wafers. This supports the packaging and processing of thermal testing chips of various sizes, reducing the development cost of thermal testing chips. Moreover, the heating unit of each wafer can be independently controlled, enabling independent adjustment of the heat output of each heating unit. Compared to the method of merging and controlling heating units, the technical solution of this application can simulate the heating of a real chip, achieving a non-uniform heating effect, thereby improving the testing effect of the thermal testing chip. In addition, the heating unit and the temperature measuring unit are stacked, eliminating the need to hollow out the heating unit, effectively increasing the heating area coverage of the heating unit, and better simulating the heating situation of a real chip.

[0030] To better understand the above technical solution, the following detailed explanation is provided in conjunction with the accompanying drawings.

[0031] As shown in Figures 1 to 3, this application embodiment proposes a wafer structure. The wafer structure 100 includes a plurality of wafers 110 spaced apart and a dicing channel 130 connecting two adjacent wafers 110. Each wafer 110 includes a surface wiring layer 111 and a temperature measuring unit 112 and a heating unit 113 stacked below the surface wiring layer 111. The surface wiring layer 111 is provided with independent temperature measuring pins 114 and heating pins 115. The temperature measuring unit 112 is electrically connected to the temperature measuring pins 114 through a temperature measuring metal via 116, and the heating unit 113 is electrically connected to the heating pins 115 through a heating metal via 117. The heating pins 115 in the plurality of wafers 110 are independently arranged, and the temperature measuring pins 114 in the plurality of wafers 110 are independently arranged.

[0032] Specifically, the wafer structure 100 includes wafers 110, and multiple wafers 110 are spaced apart. These wafers 110 can be arranged in an array, such as 2 rows and 2 columns, 8 rows and 8 columns, or 10 rows and 10 columns. Of course, the multiple wafers 110 can also be arranged irregularly. In this embodiment, the specific arrangement rules for the multiple wafers 110 are not limited.

[0033] Multiple wafers 110 are connected together via dicing channels 130. That is, two adjacent wafers 110 are connected via dicing channels 130. No devices or traces are placed in the dicing channel 130 area. Dividing the wafer structure 100 via the dicing channels 130 allows it to be cut into the required size or shape, thus meeting the needs of real chips of different specifications or forms during thermal testing. In other words, the wafer structure 100 formed by multiple spaced wafers 110 can support the packaging and processing of thermal test chips of various sizes, reducing the development cost of thermal test chips. It is understood that in this embodiment, the wafer structure 100 is designed as multiple modular wafers 110. The same wafer structure 110 can be cut into heat source modules of various sizes. After the heat source modules and substrate are packaged, a thermal test chip can be formed. That is, the design of the same wafer structure 100 can meet the processing and manufacturing of thermal test chips of various heat source module sizes, thereby effectively reducing development costs. In some embodiments, the dicing channel 130 can be a dicing groove or dicing line provided between two adjacent wafers 110, which is not limited here. In this embodiment, multiple independent wafers 110 form the entire wafer structure 100. Multiple wafers 110 are cut from the wafer structure 100 according to the required size to form a die unit 220.

[0034] Each wafer 110 includes a surface wiring layer 111. Below the surface wiring layer 111 are a temperature sensing unit 112 and a heating unit 113. The heating unit 113 generates heat to simulate the heating of a real chip; the temperature sensing unit 112 measures the temperature, which corresponds to the temperature at various locations on the real chip. In this embodiment, the heating unit 113 and the temperature sensing unit 112 are stacked below the surface wiring layer 111. They are located on different metal layers and can be electrically isolated by an insulating layer 118. This eliminates the need to hollow out the heating unit 113 to accommodate the temperature sensing unit 112, allowing the heating unit 113 to cover the entire structure, increasing the heating area coverage and improving the uniformity of heat generation, thus better simulating the heating of a real chip during operation. In some embodiments, the temperature sensing unit 112 can be located in the center, edge, or corner of the entire structure; no limitation is made here. Specifically, the heating unit 113 is located on the side of the temperature measuring unit 112 facing the surface wiring layer 111, or the temperature measuring unit 112 is located on the side of the heating unit 113 facing the surface wiring layer 111. In actual application, the choice can be made according to the specific situation, and no limitation is made here.

[0035] The surface wiring layer 111 also includes a temperature sensing pin 114 and a heating pin 115. The temperature sensing pin 114 is electrically connected to the temperature sensing unit 112 through a temperature sensing metal via 116, and the heating pin 115 is electrically connected to the heating unit 113 through a heating metal via 117, thereby providing power to the heating unit 113 and enabling signal output from the temperature sensing unit 112. In this embodiment, the heating pins 115 in the multiple chips 110 are independently configured, and the temperature sensing pins 114 in the multiple chips 110 are also independently configured. That is, the heating pin 115 in one chip 110 is independent of the heating pins 115 in other chips 110, and the temperature sensing pin 114 in one chip 110 is independent of the temperature sensing pins 114 in other chips 110. Thus, in actual use, the heat generation of each heating unit 113 can be independently controlled, and the temperature of each temperature sensing unit 112 can be acquired. By utilizing the independent control feature of each chip 110, the power consumption of any chip 110 can be controlled by adjusting the power supply output, thus simulating the non-uniform heating effect inside a real chip. Furthermore, the internal junction temperature of the chip 110 is obtained through the temperature measurement unit 112 during testing. Additionally, each chip 110 inside the heat source module (i.e., the die unit 220 mentioned below) formed after the wafer structure 100 is cut has an independent temperature measurement function, providing a large number of temperature measurement points for the heat source module. This allows for more intensive temperature monitoring within the heat source module, providing more effective temperature data for thermal testing research and improving the accuracy of thermal testing results. In some embodiments, the heating pin 115 and the temperature measurement pin 114 can be Cu pillars with SnAg alloy caps, or SnAg solder balls, respectively.

[0036] The wafer structure 100 proposed in this embodiment can be applied to both 2D and 2.5D flip chips. For 2.5D flip chips, a signal transfer medium, i.e., an adapter board, needs to be added between the substrate and the heat source, which will not be described in detail here.

[0037] In this embodiment, by setting multiple independent wafers 110 on the wafer structure 100 and utilizing the dicing channel 130, the entire wafer structure 100 can be cut into wafer 110 units arranged in any array. This supports the processing of thermal test chips of various sizes and reduces the development cost of thermal test chips. Moreover, the heating unit 113 of each wafer 110 can be controlled independently, realizing independent adjustment of the heat output of each heating unit 113. Compared with the method of merging and controlling the heating units 113, the technical solution of this application can simulate the heat generation of a real chip, achieving a non-uniform heating effect, thereby improving the testing effect of the thermal test chip. In addition, the heating unit 113 and the temperature measuring unit 112 are stacked, eliminating the need to hollow out the heating unit 113, effectively improving the heating area coverage of the heating unit 113, and better simulating the heat generation of a real chip.

[0038] In the embodiments of this application, the temperature measuring unit 112 is a temperature measuring metal trace, and the heating unit 113 is a heating metal trace, with the temperature measuring metal trace and the heating metal trace spaced apart. Designing the heating unit 113 and the temperature measuring unit 112 using metal traces can save on the processing cost of the wafer 110 structure. The heating metal trace and the temperature measuring metal trace can be made of any one of the following metals: platinum, copper, nickel, titanium, and aluminum. The heating metal trace is connected to the heating pin 115 through a heating metal via 117, and the temperature measuring metal trace is electrically connected to the temperature measuring pin 114 through a temperature measuring metal via 116.

[0039] In one embodiment, heating metal traces are uniformly arranged inside the wafer 110. In some embodiments, two heating metal traces are provided, arranged side by side, with the ends of both heating metal traces electrically connected to metal vias. Of course, one or more heating metal traces can also be provided, or they can be arranged in a circuitous manner to cover the entire wafer 110, which helps to distribute heat more evenly on the traces, reduce local hot spots, and improve the coverage of the heated area. Moreover, the size of the envelope of the heating metal traces is adapted to the size of the surface wiring layer 111, so that it can cover the entire wafer 110, resulting in more uniform heating and better heating effect.

[0040] In another embodiment, the temperature-sensing metal traces can be located in the central region of the wafer 110, or at the corners, centers of edges, etc., of the entire wafer 110, and are uniformly distributed within the temperature-sensing area. It is understood that the projection of the temperature-sensing metal traces is located at the center, corner, or center of the surface wiring layer 111, allowing for more flexible and convenient arrangement. In some embodiments, the linewidth of the temperature-sensing metal traces can be smaller to increase their resistance. Specifically, the resistance values ​​of all temperature-sensing metal traces are collected using a data acquisition device, and the junction temperature is obtained using the relationship curve between the resistance values ​​and temperature of the temperature-sensing metal traces.

[0041] In embodiments of this application, referring to FIG2, the wafer structure 100 further includes multiple insulating layers 118 stacked below the surface wiring layer 111. One insulating layer 118 has temperature-sensing metal traces, and another insulating layer 118 has heating metal traces. At least one insulating layer 118 is provided between the temperature-sensing metal traces and the heating metal traces. It is understood that the insulating layer 118 between the temperature-sensing metal traces and the heating metal traces can achieve electrical isolation between them, avoiding mutual interference. In some embodiments, the insulating layer 118 can be one layer, or two or more layers, which is not limited here. Specifically, the insulating layer 118 can be made of insulating materials such as SiO2, SiN, SiCN, and SiCOH.

[0042] In the embodiments of this application, referring to Figures 2 and 3, the surface wiring layer 111 is provided with independent heating connection traces 1191 and temperature sensing connection traces 1192. Heating pin 115, heating connection trace 1191, heating metal via 117, and heating metal trace are sequentially electrically connected. Temperature sensing pin 114, temperature sensing connection trace 1192, temperature sensing metal via 116, and temperature sensing metal trace are sequentially electrically connected. In this embodiment, the sequential electrical connection of heating pin 115, heating connection trace 1191, heating metal via 117, and heating metal trace forms a complete heating circuit for transmitting current to the heating metal trace, thereby achieving the heating function. Simultaneously, the sequential electrical connection of temperature sensing pin 114, temperature sensing connection trace 1192, temperature sensing metal via 116, and temperature sensing metal trace forms a complete temperature sensing circuit for outputting the resistance signal on the temperature sensing metal trace, thereby achieving the temperature sensing function.

[0043] In the embodiments of this application, four heating pins 115 and four temperature sensing pins 114 are provided in the same chip 110. It is understood that the two ends of the heating metal trace are respectively connected to two heating pins 115, and the two ends of the temperature sensing metal trace are respectively connected to two temperature sensing pins 114. The four heating pins 115 and the four temperature sensing pins 114 are interconnected, thus supporting the Kelvin resistance measurement method to achieve accurate resistance measurement and heating power consumption monitoring.

[0044] In the embodiments of this application, the temperature-sensing metal traces on each wafer 110 are arranged in a circuitous manner. The resistance of the temperature-sensing metal traces changes with temperature, and the temperature change can be calculated by measuring the change in resistance. Therefore, it is crucial to improve the sensitivity of the temperature-sensing metal traces to temperature changes. For this reason, in this embodiment, the temperature-sensing metal traces on each wafer 110 are arranged in a circuitous manner, which increases the total length of the temperature-sensing metal traces within a limited space. Longer traces can improve the sensitivity to temperature changes, thereby improving the accuracy of thermal test results.

[0045] In an embodiment of this application, referring to FIG2, the wafer 110 further includes a substrate 120. The wafers 110 are arranged in rows along a first direction and in columns along an orthogonal second direction on the substrate 120. The substrate 120 provides physical support for the circuits on the wafer 110. In some embodiments, the substrate 120 is a silicon wafer and does not contain other electrical components. Of course, in other embodiments, the substrate 120 may also contain active or passive components, which is not limited here. The wafers 110 are arranged in several rows along the first direction, and at the same time, the wafers 110 are arranged in several columns along the second direction perpendicular to the first direction. In this way, multiple wafers 110 are arranged on the substrate 120 in a grid-like manner to form a dense array, which can then be cut according to the required size of the heat source module. In one embodiment, the material of the substrate 120 may be Si, SiC, diamond, or other materials.

[0046] This application also proposes a packaging module 200. Referring to Figures 4 to 9, the packaging module 200 includes a packaging substrate 210 and die units 220 disposed on the packaging substrate 210. The die units 220 are cut from the wafer structure 100 described above. That is, the heat source module formed after cutting the wafer structure 100 constitutes the die unit 220. A plurality of independent bonding units 211 are spaced apart on the surface of the packaging substrate 210. The plurality of bonding units 211 are arranged in the same way as the plurality of wafers 110 and correspond one-to-one. Specifically, the specific structure of the wafer structure 100 is as described in the above embodiments. Since this packaging module 200 adopts all the technical solutions of the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be elaborated further here. It is understood that the packaging substrate 210 in this embodiment is also modularly configured, meaning that the packaging substrate 210 has multiple independent soldering units 211 arrayed on it. The arrangement of the multiple soldering units 211 is the same as the arrangement of the multiple wafers 110 on the wafer structure 100. Thus, when the wafer structure 100 is cut into heat source modules of different sizes, one packaging substrate 210 can be assembled with multiple heat source modules (i.e., die units 220) of different sizes. In other words, the modular soldering units 211 on the packaging substrate 210 can support the packaging of heat source modules of various sizes, and can electrically connect multiple heating pins 115 and multiple temperature sensing pins 114 to the corresponding soldering units 211. The same packaging design can support the processing of thermal test chips of various sizes, reducing the development cost of thermal test chips. In the embodiments of this application, each soldering unit 211 includes independently configured heating pads and temperature sensing pads. The heating pads and heating pins 115 are electrically connected, and the temperature sensing pads and temperature sensing pins 114 are electrically connected. In some embodiments, the heating pads and heating pins 115, and the temperature sensing pads and temperature sensing pins 114 are interconnected via reflow soldering. The packaging module 200 also includes solder balls 212 disposed on the bottom surface of the packaging substrate 210. Multiple solder balls 212 are provided, with some forming heating solder balls and others forming temperature sensing solder balls. The packaging substrate 210 has independent first and second traces. The heating solder balls are electrically connected to the heating pads via the first traces, and the temperature sensing solder balls are electrically connected to the temperature sensing pads via the second traces. Thus, by adjusting the power supply output, the heat output of each heating unit can be independently controlled, enabling power consumption regulation of any chip 110, and allowing independent temperature acquisition for each temperature sensing unit 112, improving the flexibility of thermal testing.

[0047] Referring to Figure 4, the size of the heat source module and the array size of all the soldering units 211 on the packaging substrate 210 are the same. The soldering units 211 on the packaging substrate 210 are all located below the heat source module, and all the solder pads are interconnected with the corresponding pins.

[0048] Referring to Figure 7, the size of the heat source module is smaller than the array size of all the soldering units 211 on the packaging substrate 210. Some of the solder pads on the packaging substrate 210 are exposed and have no corresponding pins for interconnection.

[0049] In embodiments of this application, referring to FIG9, the packaging module 200 further includes a transfer board 230, through which the die unit 220 is interconnected with the packaging substrate 210. This enables 2.5D flip-chip bonding. In some embodiments, the transfer board 230 can be any one of a silicon-based transfer board, an organic multilayer transfer layer, or a glass transfer board, with multiple independent transfer traces inside. One surface of the transfer board 230 has multiple independent transfer pads, and the other surface has transfer pins. The transfer pads and transfer pins are interconnected with their corresponding transfer traces. The heating pin 115 and the temperature sensing pin 114 are interconnected with their corresponding transfer pads, and the heating pads and temperature sensing pads are interconnected with their corresponding transfer pins, thus achieving electrical conduction between the heating circuit and the temperature sensing circuit.

[0050] In embodiments of this application, referring to Figures 8 and 9, the packaging module 200 further includes a heat sink 240, which covers the packaging substrate 210 and forms a mounting cavity with the packaging substrate 210. The die unit 220 is disposed in the mounting cavity. Thus, the heat sink 240 can effectively conduct away the heat dissipated by the entire module, thereby reducing the operating temperature and improving the reliability and stability of the device. Furthermore, the heat sink 240 also protects the die unit 220 from damage caused by the external environment. In some embodiments, the heat sink 240 and the packaging substrate 210 are bonded together.

[0051] In embodiments of this application, referring to Figures 8 and 9, the packaging module 200 further includes a thermal interface material layer 250, which fills the space between the heat sink 240 and the wafer 110. The thermal interface material layer 250 reduces the contact thermal resistance between the die unit 220 and the heat sink 240, as well as the chip junction thermal resistance. In some embodiments, the thermal interface material layer 250 can be made of an organosilicon thermal interface material, a carbon-based thermal interface material, or a metal-based thermal interface material.

[0052] In embodiments of this application, referring to Figures 8 and 9, the packaging module 200 further includes an underfill material layer 260, which fills the space between the heating pin 115 and the temperature sensing pin 114. The underfill material layer 260 fills the gap between the heating pin 115 and the temperature sensing pin 114. Furthermore, after curing, the underfill material layer 260 enhances the soldering strength of the heating pin 115 and the temperature sensing pin 114. When applied to 2.5D flip chips, the underfill material layer 260 can also be provided between the adapter pins of the transfer board 230 to improve the soldering strength of the adapter pins.

[0053] This application also proposes a thermal testing chip, which includes the packaging module 200 as described above. Specifically, the specific structure of the packaging module 200 is as described in the above embodiments. Since the thermal testing chip adopts all the technical solutions of the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0054] The above description is merely an exemplary implementation of this application and does not limit the patent scope of the embodiments of this application. Any equivalent structural transformations made based on the technical concept of the embodiments of this application and the contents of the specification and drawings of the embodiments of this application, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the embodiments of this application.

Claims

1. A wafer structure comprising a plurality of wafers spaced apart and dicing channels connecting adjacent wafers, each wafer comprising a surface wiring layer and a temperature sensing unit and a heating unit stacked below the surface wiring layer, the surface wiring layer having independent temperature sensing pins and heating pins, the temperature sensing unit being electrically connected to the temperature sensing pins via temperature sensing metal vias, and the heating unit being electrically connected to the heating pins via heating metal vias; the heating pins in the plurality of wafers being independently configured, and the temperature sensing pins in the plurality of wafers being independently configured.

2. The wafer structure as described in claim 1, wherein, The temperature measuring unit is a temperature measuring metal trace, and the heating unit is a heating metal trace, with the temperature measuring metal trace and the heating metal trace spaced apart.

3. The wafer structure as described in claim 2 further includes multiple insulating layers stacked below the surface wiring layer, wherein one insulating layer has the temperature sensing metal trace, another insulating layer has the heating metal trace, and at least one insulating layer is provided between the temperature sensing metal trace and the heating metal trace.

4. The wafer structure as described in claim 2, wherein, In the same chip, there are four heating pins and four temperature measuring pins.

5. The wafer structure as described in claim 2, wherein, The heated metal traces are evenly arranged, and the size of the envelope of the heated metal traces is adapted to the size of the surface wiring layer. And / or, the projection of the temperature-sensing metal trace is located at the center, corner, or center of the edge of the surface wiring layer.

6. The wafer structure as described in claim 1, wherein, The wafer also includes a substrate, wherein the wafers are arranged in rows in a first direction and in columns along an orthogonal second direction on the substrate.

7. A packaging module, comprising a packaging substrate and a die unit disposed on the packaging substrate, wherein the die unit is cut from a wafer structure as described in any one of claims 1 to 6, and a plurality of independent bonding units are spaced apart on the surface of the packaging substrate, wherein the plurality of bonding units are arranged in the same manner as the plurality of wafers and correspond one-to-one.

8. The packaging module as described in claim 7, wherein, Each of the welding units includes independently arranged heating pads and temperature sensing pads, with the heating pads and heating pins electrically connected to each other, and the temperature sensing pads and temperature sensing pins electrically connected to each other; the packaging module also includes independently arranged heating balls and temperature sensing balls on the bottom surface of the packaging substrate, with independently arranged first and second traces inside the packaging substrate, the heating balls being electrically connected to the heating pads through the first traces, and the temperature sensing balls being electrically connected to the temperature sensing pads through the second traces.

9. The packaging module of claim 8 further includes a relay board, wherein the die unit is interconnected with the packaging substrate through the relay board.

10. The packaging module as described in claim 8 or 9 further includes a heat sink cover, the heat sink cover being disposed on the packaging substrate and cooperating with the packaging substrate to form a mounting cavity, the die unit being disposed in the mounting cavity.

11. The packaging module of claim 10, further comprising a thermal interface material layer, the thermal interface material layer filling the space between the heat sink and the wafer.

12. The packaging module of claim 10 further includes a bottom filler layer, the bottom filler layer being filled between the heating pin and the temperature measuring pin.

13. A thermal testing chip, comprising the packaging module as described in any one of claims 7 to 12.

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