Chip structure and preparation method therefor

By designing a stacked structure and using low-temperature thin-film transistor technology, the problems of increased resistance and space constraints in chip interconnects were solved, enabling efficient interconnection of signal and power lines, expanding the selection of metal types, and avoiding alignment difficulties in traditional processes.

WO2026152873A1PCT designated stage Publication Date: 2026-07-23PEKING UNIV
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Patent Information

Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
PEKING UNIV
Filing Date
2025-11-20
Publication Date
2026-07-23

AI Technical Summary

Technical Problem

As device size shrinks, the resistance of interconnects on the front side of the chip increases, space becomes scarce, and traditional processes struggle to achieve efficient interconnection between signal and power lines. Furthermore, back-side power supply technology faces alignment difficulties and limitations in metal types.

Method used

The chip structure design includes a stacked substrate, conductive pillars, conductive rails, connection layers, and interconnect layers, avoiding wafer bonding and whole wafer thinning processes. It uses low-temperature thin-film transistors and damascus technology, increases the selection of metal conductive structure types, and realizes back-side interconnect.

Benefits of technology

It reduces chip power consumption, improves interconnect efficiency, expands the selection of metal types, avoids alignment problems, and enables high-density signal and power network cabling.

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Abstract

Embodiments of the present application provide a chip structure and a preparation method therefor. The preparation method comprises the following steps: providing a substrate, the substrate comprising a first substrate, an indicator layer, and a second substrate; forming a plurality of conductive pillars in the substrate, the conductive pillars passing through the first substrate and the indicator layer; forming a conductive rail layer on the first substrate, the conductive rail layer comprising a plurality of conductive rails, and each conductive rail being connected to at least two conductive pillars; forming a connection layer and a device layer on the conductive rail layer, wherein the connection layer comprises a dielectric portion disposed on the conductive rail layer and provided with a plurality of connection ports, and conductive portions disposed in the connection ports and connected to the conductive rails, the device layer is disposed on the connection layer and comprises a plurality of thin film transistors, and a forming temperature of the thin film transistors is not greater than a preset temperature; forming a first interconnection layer on the device layer; and forming a second interconnection layer in the second substrate, the thin film transistors being connected to the second interconnection layer via the conductive pillars, the conductive rails, the conductive portions, and the first interconnection layer.
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