Pipeline creation method and electronic device

Abstract

Embodiments of the present application relate to the field of image processing, and in particular to a pipeline creation method and an electronic device, capable of improving the efficiency of pipeline creation. The method is applied to an electronic device, the electronic device comprises a GPU, and the GPU comprises N interfaces, wherein N is a positive integer greater than or equal to 2. The method comprises: upon initiating an image processing task, dividing the image processing task into N subtasks, then respectively accessing N corresponding compilers in the GPU via the N interfaces corresponding to the N subtasks to compile the N subtasks so as to obtain N compiled subtasks, and finally merging the N compiled subtasks to obtain a pipeline corresponding to the image processing task.

Description

Piping methods and electronic equipment

[0001] This application claims priority to Chinese patent application filed on January 16, 2025, with application number 202510075803.1 and entitled "Method for Creating Pipelines and Electronic Equipment", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of image processing, and more specifically, to a method for creating pipelines and an electronic device. Background Technology

[0003] Image rendering, as a common pipeline creation method, is widely used in the image drawing process of various applications.

[0004] For example, in gaming applications, to provide users with stunning visuals, electronic devices render the graphics data provided by the game application, resulting in a rendered image, which is then displayed to the user to show the game screen. Typically, before rendering the image, the electronic device creates a pipeline and then renders the image according to the pipeline. The process of creating the pipeline involves a large amount of complex configuration and GPU compilation instructions, which usually takes a considerable amount of time. This results in a lengthy rendering process, which in turn causes the display interface to lag, negatively impacting the user experience.

[0005] Therefore, improving the efficiency of pipeline creation and enhancing user experience has become an urgent issue to be addressed. Summary of the Invention

[0006] This application provides a method and electronic device for creating pipelines, which can improve the efficiency of pipeline creation and enhance the user experience.

[0007] Firstly, a pipeline creation method is provided, applied to an electronic device including a graphics processing unit (GPU), the GPU including N interfaces, where N is a positive integer greater than or equal to 2, the method comprising:

[0008] When starting an image processing task, divide the image processing task into N sub-tasks;

[0009] By accessing the N interfaces corresponding to the N subtasks, the N compilers in the GPU are accessed respectively to compile the N subtasks and obtain N compiled subtasks;

[0010] The N compiled subtasks are merged to obtain the pipeline corresponding to the image processing task.

[0011] The pipeline creation method provided in this application is applied to an electronic device, including a GPU. The GPU includes N interfaces, where N is a positive integer greater than or equal to 2. When starting an image processing task, the method divides the image processing task into N subtasks. Then, through the N interfaces corresponding to the N subtasks, it accesses the corresponding N compilers in the GPU to compile the N subtasks, resulting in N compiled subtasks. Finally, the N compiled subtasks are merged to obtain the pipeline corresponding to the image processing task. This is equivalent to dividing the image processing task corresponding to the pipeline into N subtasks during the pipeline creation process, and then compiling them synchronously through the N compilers in the GPU, thereby improving the efficiency of compiling the image processing task and thus improving the efficiency of pipeline creation.

[0012] In conjunction with the first aspect, in some embodiments of the first aspect, the above-mentioned compilation of N subtasks to obtain N compiled subtasks includes: incremental compilation of the N subtasks to obtain N compiled subtasks.

[0013] The pipeline creation method provided in this application adopts incremental compilation when compiling subtasks, which can reduce the amount of code that needs to be compiled when compiling subtasks, thereby reducing the workload of compilation and reducing compilation time. This can effectively save the time of creating the pipeline, thereby saving the time of image processing based on the pipeline, effectively avoiding image lag, and improving user experience.

[0014] In conjunction with the first aspect, in some embodiments of the first aspect, the method further includes: storing N compiled subtasks in a preset storage area, wherein the preset storage area is a cache area of ​​the application corresponding to the image processing task.

[0015] The pipeline creation method provided in this application stores N compiled subtasks in a cache. When the same image processing task is started again, the N compiled subtasks already stored in the cache can be used directly, thereby improving the efficiency of image processing.

[0016] In some cases, after creating a pipeline, it can be stored in the cache of the first application. When the first application launches the same image processing task again, it can first check the cache to see if there is a pipeline that has already been created. If there is a pipeline that has already been created in the cache, it can directly use the pipeline that has been stored in the cache, avoiding the situation of repeatedly creating pipelines and improving the efficiency of image processing.

[0017] The first application can refer to the application corresponding to the image processing task.

[0018] In conjunction with the first aspect, in some embodiments of the first aspect, the GPU includes three interfaces: a first interface, a second interface, and a third interface. The N compilers are three compilers: a first compiler, a second compiler, and a third compiler. When starting an image processing task, the image processing task is divided into N subtasks, including: dividing the image processing task into shader subtasks, fixed-function subtasks, and dynamic-parameter subtasks; accessing the corresponding N compilers in the GPU through the N interfaces corresponding to the N subtasks to compile the N subtasks, resulting in N compiled subtasks, including: accessing the first compiler through the first interface to compile the shader subtasks; accessing the second compiler through the second interface to compile the fixed-function subtasks; and accessing the third compiler through the third interface to compile the dynamic-parameter subtasks, resulting in compiled dynamic-parameter subtasks.

[0019] In conjunction with the first aspect, in some embodiments of the first aspect, the electronic device further includes a pipeline creation module that, when initiating an image processing task, divides the image processing task into N sub-tasks, including: when the pipeline creation module detects that the image processing task has been initiated, it divides the image processing task into N sub-tasks.

[0020] In conjunction with the first aspect, in some embodiments of the first aspect, the GPU includes three interfaces: a first interface, a second interface, and a third interface. The N compilers are three compilers: a first compiler, a second compiler, and a third compiler. Through the N interfaces corresponding to the N subtasks, the corresponding N compilers in the GPU are accessed to compile the N subtasks, resulting in N compiled subtasks. This includes: a pipeline creation module accessing the first compiler through the first interface to compile shader subtasks, resulting in compiled shader subtasks; a pipeline creation module accessing the second compiler through the second interface to compile fixed-function subtasks, resulting in compiled fixed-function subtasks; and a pipeline creation module accessing the third compiler through the third interface to compile dynamic parameter subtasks, resulting in compiled dynamic parameter subtasks.

[0021] In conjunction with the first aspect, in some embodiments of the first aspect, the electronic device further includes a merger that merges N compiled subtasks to obtain a pipeline corresponding to the image processing task, including: the merger merges N compiled subtasks to obtain a pipeline corresponding to the image processing task.

[0022] In conjunction with the first aspect, in some embodiments of the first aspect, the image processing task is an image rendering task.

[0023] In a second aspect, a pipeline creation device is provided, including units for performing any of the methods in the first aspect. The device may be a terminal device or a chip within a terminal device. The device may include an input unit and a processing unit.

[0024] When the device is a terminal device, the processing unit may be a processor, and the input unit may be a communication interface; the terminal device may also include a memory for storing computer program code, which, when the processor executes the computer program code stored in the memory, causes the terminal device to perform any of the methods in the first aspect.

[0025] When the device is a chip within a terminal device, the processing unit can be an internal processing unit of the chip, and the input unit can be an output interface, pin, or circuit, etc.; the chip may also include a memory, which can be an internal memory of the chip (e.g., a register, cache, etc.) or an external memory (e.g., a read-only memory, random access memory, etc.); the memory is used to store computer program code, and when the processor executes the computer program code stored in the memory, the chip performs any of the methods in the first aspect.

[0026] In one possible implementation, the memory is used to store computer program code; the processor executes the computer program code stored in the memory, and when the computer program code stored in the memory is executed, the processor is used to execute:

[0027] Thirdly, a computer-readable storage medium is provided that stores computer program code, which, when executed by a pipeline creation device, causes the pipeline creation device to perform any of the pipeline creation methods in the first aspect.

[0028] Fourthly, a computer program product is provided, the computer program product comprising: computer program code, which, when the computer program code is run by a pipeline creation device, causes the pipeline creation device to perform any one of the pipeline creation methods in the first aspect or the second aspect.

[0029] The present application provides a method and electronic device for creating a pipeline. The method is applied to an electronic device, including a GPU, which has N interfaces, where N is a positive integer greater than or equal to 2. When starting an image processing task, the method divides the image processing task into N subtasks. Then, through the N interfaces corresponding to the N subtasks, it accesses the corresponding N compilers in the GPU to compile the N subtasks, resulting in N compiled subtasks. Finally, it merges the N compiled subtasks to obtain the pipeline corresponding to the image processing task. This is equivalent to dividing the image processing task corresponding to the pipeline into N subtasks during the pipeline creation process, and then compiling them synchronously through the N compilers in the GPU, thereby improving the efficiency of compiling the image processing task and thus improving the efficiency of pipeline creation. Attached Figure Description

[0030] Figure 1 is a schematic diagram of a hardware system applicable to the device of this application;

[0031] Figure 2 is a schematic diagram of a software system applicable to the apparatus of this application;

[0032] Figure 3 is a schematic diagram of an application scenario provided by an embodiment of this application;

[0033] Figure 4 is a schematic diagram of an application scenario provided by an embodiment of this application;

[0034] Figure 5 is a schematic diagram of a pipeline creation method provided in an embodiment of this application;

[0035] Figure 6 is a schematic diagram of another pipeline creation method provided in an embodiment of this application;

[0036] Figure 7 is a schematic diagram of another pipeline creation method provided in an embodiment of this application;

[0037] Figure 8 is a schematic diagram of a pipeline creation device provided in this application;

[0038] Figure 9 is a schematic diagram of an electronic device for creating pipelines provided in this application. Detailed Implementation

[0039] Since the embodiments of this application involve a large number of neural network applications, for ease of understanding, the relevant terms and concepts of neural networks that may be involved in the embodiments of this application will be introduced below.

[0040] (1) Pipeline.

[0041] A pipeline can be understood as a model for data processing. In a pipeline, a complex task can be broken down into multiple independent processing steps, each of which processes its input data sequentially. Each processing step can be implemented by an independent processing unit or algorithm, and they work in a specific order to form a continuous data processing flow.

[0042] For example, drawing a triangle pipeline can refer to breaking down the task of drawing a triangle into processing steps such as determining the positions of the three vertices, determining the line shape of the lines connecting the vertices, determining the color of the lines connecting the vertices, and determining the filling pattern inside the triangle.

[0043] Each processing step in a pipeline can be viewed as an independent processing unit, which can be combined or reorganized as needed to adapt to different processing requirements or tasks. This modularity and composability give pipelines good flexibility and scalability.

[0044] (2) Create pipeline.

[0045] Upon receiving an image processing instruction, the electronic device creates a pipeline to ensure that image processing proceeds sequentially according to the steps specified in the pipeline. Image processing can refer to image rendering.

[0046] It's understandable that image processing is typically handled by the GPU, while image processing instructions are usually issued by the CPU. Therefore, the pipeline creation process requires translating CPU instructions into binary code that the GPU can process. This translation usually involves the CPU accessing the GPU's compiler via an interface to convert the CPU instructions into the GPU's binary code.

[0047] (3) Image rendering.

[0048] Image rendering refers to the process of converting a 3D scene or model into an image that can be displayed on an electronic device through a series of processing steps. As a common pipeline method, image rendering is widely used in various scenarios.

[0049] For example, game applications display game visuals to users through image rendering.

[0050] For example, the three-dimensional images that virtual reality (VR) and augmented reality (AR) display to users can also be achieved through image rendering.

[0051] For example, in some films and television shows, virtual images can be generated through image rendering to be displayed to users.

[0052] For example, scientific experimental data and results can also be processed through image rendering to generate more vivid scientific experimental data and results.

[0053] For example, in the fields of urban planning and architectural design, complex 3D building models can be rendered in real time to generate simulated images of the buildings and present them to users.

[0054] For example, in the field of flight training, flight simulation applications can generate simulated flight environments through image rendering and demonstrate them to flight trainees.

[0055] For example, some educational and training applications can use image rendering to generate animated visuals of teaching content and present them to students.

[0056] For example, some applications can access cloud servers to access cloud-based graphics services. In this case, the cloud server can process the application's requests through image rendering and return the rendered image to the application.

[0057] It should be understood that before image rendering, electronic devices create a pipeline based on the specific requirements of image rendering. During pipeline creation, the CPU needs to access the compiler in the GPU through the interface between the CPU and GPU to compile CPU instructions into binary code that the GPU can process. Typically, there is only one interface between the CPU and GPU; therefore, the compilation of CPU instructions into binary code can only be done sequentially through the interface between the CPU and GPU. However, with the advent of multi-core CPUs, the CPU can execute multiple tasks simultaneously. The compilation process for CPU instructions cannot effectively leverage the advantage of multi-core CPUs executing multiple tasks concurrently, resulting in slower compilation speeds and impacting the timeliness of image rendering.

[0058] In view of this, the present application provides a method for creating a pipeline, applied in an electronic device including a GPU, which includes N interfaces, where N is a positive integer greater than or equal to 2. When starting an image processing task, the method divides the task into N subtasks. Then, through the N interfaces corresponding to the N subtasks, it accesses the corresponding N compilers in the GPU to compile the N subtasks, resulting in N compiled subtasks. Finally, the N compiled subtasks are merged to obtain the pipeline corresponding to the image processing task. This is equivalent to dividing the image processing task corresponding to the pipeline into N subtasks during pipeline creation and then simultaneously compiling them through the N compilers in the GPU, thereby improving the efficiency of compiling the image processing task and thus improving the efficiency of pipeline creation.

[0059] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0060] Figure 1 illustrates a hardware system for an electronic device applicable to this application.

[0061] Electronic device 100 can be a mobile phone, smart screen, tablet computer, wearable electronic device, in-vehicle electronic device, augmented reality (AR) device, virtual reality (VR) device, laptop computer, ultra-mobile personal computer (UMPC), netbook, personal digital assistant (PDA), projector, etc. This application embodiment does not limit the specific type of electronic device 100.

[0062] Electronic device 100 may include processor 110, external memory interface 120, internal memory 121, universal serial bus (USB) interface 130, charging management module 140, power management module 141, battery 142, antenna 1, antenna 2, mobile communication module 150, wireless communication module 160, audio module 170, speaker 170A, receiver 170B, microphone 170C, headphone jack 170D, sensor module 180, button 190, motor 191, indicator 192, camera 193, display screen 194, and subscriber identification module (SIM) card interface 195, etc. The sensor module 180 may include a pressure sensor 180A, a gyroscope sensor 180B, a barometric pressure sensor 180C, a magnetic sensor 180D, an accelerometer sensor 180E, a distance sensor 180F, a proximity sensor 180G, a fingerprint sensor 180H, a temperature sensor 180J, a touch sensor 180K, an ambient light sensor 180L, a bone conduction sensor 180M, etc.

[0063] It should be noted that the structure shown in FIG1 does not constitute a specific limitation on the electronic device 100. In other embodiments of this application, the electronic device 100 may include more or fewer components than those shown in FIG1, or the electronic device 100 may include a combination of some of the components shown in FIG1, or the electronic device 100 may include sub-components of some of the components shown in FIG1. ​​The components shown in FIG1 may be implemented in hardware, software, or a combination of software and hardware.

[0064] Processor 110 may include one or more processing units. For example, processor 110 may include at least one of the following processing units: application processor (AP), modem processor, graphics processing unit (GPU), image signal processor (ISP), controller, video codec, digital signal processor (DSP), baseband processor, and neural network processing unit (NPU). These different processing units may be independent devices or integrated devices. It should be noted that the central processing unit (CPU) mentioned below may refer to the AP in processor 110.

[0065] The controller can generate operation control signals based on the instruction opcode and timing signals to complete the control of instruction fetching and execution.

[0066] The processor 110 may also include a memory for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. This memory can store instructions or data that the processor 110 has just used or that are used repeatedly. If the processor 110 needs to use the instruction or data again, it can retrieve it directly from the memory. This avoids repeated accesses, reduces the waiting time of the processor 110, and thus improves the efficiency of the system.

[0067] Electronic device 100 can implement display functions through a GPU, a display screen 194, and an application processor. The GPU is a microprocessor for image processing, connected to the display screen 194 and the application processor. The GPU is used to perform mathematical and geometric calculations and for graphics rendering. Processor 110 may include one or more GPUs, which execute program instructions to generate or modify display information.

[0068] In some cases, the GPU can provide a compiler to the CPU, compiling CPU instructions into binary code that the GPU can understand. For example, when creating an image rendering pipeline, the CPU accesses the compiler in the GPU, compiles the corresponding CPU instructions into binary code that the GPU can understand, and then executes the binary code through the GPU to perform image rendering.

[0069] The display screen 194 can be used to display images or videos. The display screen 194 includes a display panel. The display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a mini light-emitting diode (Mini LED), a micro light-emitting diode (Micro LED), a micro OLED, or a quantum dot light-emitting diode (QLED). In some embodiments, the electronic device 100 may include one or N displays 194, where N is a positive integer greater than 1.

[0070] The hardware system of electronic device 100 has been described in detail above. The software system of electronic device 100 is described below. The software system can adopt a layered architecture, event-driven architecture, microkernel architecture, microservice architecture, or cloud architecture. This application embodiment takes a layered architecture as an example to exemplarily describe the software system of electronic device 100.

[0071] As shown in Figure 2, a layered architecture software system is divided into several layers, each with a clear role and division of labor. Layers communicate with each other through software interfaces. In some embodiments, the software system can be divided into four layers, from top to bottom: the application layer, the application framework layer, the Android Runtime and system libraries, and the kernel layer.

[0072] The application layer can include applications such as games, flight simulators, educational applications, virtual reality, augmented reality, and architectural models.

[0073] In this context, game applications can display game visuals to users and modify the visuals based on user interactions. Generating game visuals requires image rendering.

[0074] Flight simulators can receive flight parameters input by the user, and then generate a simulated flight environment based on these parameters for display to the user. The process of generating the simulated flight environment requires image rendering.

[0075] Educational applications can generate corresponding animations based on user-input teaching information and display them to students. For example, if a user inputs an incorrect answer, an animation of an incorrect answer can be generated and displayed to the student. Or, if a user inputs a correct answer, an animation of a correct answer can be generated and displayed to the student. The process of generating animations corresponding to teaching information requires image rendering.

[0076] Virtual reality and augmented reality can generate virtual 3D scenes to display to users. The process of generating virtual 3D scenes requires image rendering.

[0077] The building model can receive building parameters input by the user and generate a building model to display to the user. The user can also rotate the building model, and the model will be displayed in response to the user's rotation. The process of generating the building model requires image rendering.

[0078] The application framework layer provides application programming interfaces (APIs) and programming frameworks for applications in the application layer. The application framework layer may include some predefined functions.

[0079] For example, the application framework layer includes a window manager, content providers, a view system, a phone manager, a resource manager, and a notification manager.

[0080] For example, the application framework layer may also include modules for creating pipelines, compositors, and image rendering.

[0081] The window manager is used to manage windowed applications. It can obtain the screen size, determine if a status bar is present, lock the screen, and capture the screen.

[0082] Content providers store and retrieve data, making that data accessible to applications. This data may include videos, images, audio, made and received phone calls, browsing history and bookmarks, and phone books.

[0083] A view system includes visual controls, such as controls for displaying text and controls for displaying images. View systems can be used to build applications. A display interface can consist of one or more views; for example, a display interface including a text notification icon can include views for displaying text and views for displaying images.

[0084] The file explorer provides applications with various resources, such as localized strings, icons, images, layout files, and video files.

[0085] The pipeline module can create pipelines corresponding to image rendering tasks, so that the image rendering module can execute image rendering tasks according to the instructions of the pipeline.

[0086] The synthesizer can be used to receive compiled subtasks sent by the GPU and generate a pipeline from the compiled subtasks.

[0087] The Android Runtime consists of core libraries and a virtual machine. The Android runtime is responsible for the scheduling and management of the Android system.

[0088] The core library consists of two parts: one part is the functionalities that need to be called by the Java language, and the other part is the Android core library.

[0089] The application layer and application framework layer run in a virtual machine. The virtual machine executes the Java files of the application layer and application framework layer as binary files. The virtual machine is used to perform functions such as object lifecycle management, stack management, thread management, security and exception management, and garbage collection.

[0090] The system library can include multiple functional modules, such as: surface manager, media libraries, 3D graphics processing libraries (e.g., Open Graphics Library for Embedded Systems, OpenGL ES) and 2D graphics engines (e.g., Skia Graphics Library, SGL).

[0091] The 3D graphics processing library can be used to implement 3D graphics drawing, image rendering, compositing, and layer processing.

[0092] A 2D graphics engine is a graphics engine for 2D drawing.

[0093] The kernel layer is the layer between hardware and software. The kernel layer can include driver modules such as GPU drivers.

[0094] Creating a pipeline module allows access to the GPU's compiler via the GPU driver and GPU interfaces, enabling the compilation of CPU instructions into binary code that the GPU can recognize.

[0095] For example, a pipeline module can be created by accessing a first compiler through a GPU driver and a first interface to compile CPU instructions into binary code that the GPU can recognize. A pipeline module can also be created by accessing a second compiler through a GPU driver and a second interface to compile CPU instructions into binary code that the GPU can recognize. Furthermore, a pipeline module can be created by accessing a third compiler through a GPU driver and a third interface to compile CPU instructions into binary code that the GPU can recognize.

[0096] For ease of description, the following statements regarding creating a pipeline module to access the first compiler via a first interface can mean creating a pipeline module to access the first compiler via a GPU driver and a first interface; creating a pipeline module to access the second compiler via a second interface can mean creating a pipeline module to access the second compiler via a GPU driver and a second interface; and creating a pipeline module to access the third compiler via a third interface can mean creating a pipeline module to access the third compiler via a GPU driver and a third interface.

[0097] The application scenarios of the embodiments of this application will be briefly described below.

[0098] For example, the pipeline creation method provided in this application embodiment can be applied to the field of image processing technology. For instance, the pipeline creation method provided in this application embodiment can be used to create a pipeline corresponding to image rendering, so that the image rendering module can perform image rendering according to the tasks indicated by the pipeline and generate the rendered image.

[0099] Application Scenario 1: In response to the application's startup operation, a virtual screen is directly generated through image rendering.

[0100] The pipeline creation method provided in this application embodiment can be applied to the process of generating virtual screens when an application starts. For example, as shown in FIG3(a), in the display interface 10A, the user clicks the icon 10A1 of the "Game" application. In response to the user's click on the icon 10A1, the electronic device creates an image rendering pipeline to generate the game screen 10B as shown in FIG3(b).

[0101] In some possible cases, the pipeline creation method provided in this application embodiment can also be applied to the process of directly generating virtual images through image rendering in response to user operations, and this application embodiment does not impose any limitations on this. For example, the pipeline creation method provided in this application embodiment can also be applied to the process of directly generating virtual buildings through image rendering in response to user input of building parameters. As another example, the pipeline creation method provided in this application embodiment can also be applied to the process of directly generating a simulated flight environment through image rendering in response to user input of aircraft simulation data.

[0102] Application Scenario 2: Responding to user input, a virtual screen corresponding to the input operation is generated through image rendering.

[0103] The pipeline creation method provided in this application can be applied to respond to user input operations and generate virtual screens corresponding to the input operations through image rendering.

[0104] For example, as shown in Figure 4(a), a first option 20A1 and a second option 20A2 are displayed in the display interface 20A. If the user clicks the first option 20A1, as shown in Figure 4(b), then based on the user's click on the first option 20A1, an "Incorrect Answer" display interface 20B is generated through image rendering, as shown in Figure 4(c). If the user clicks the second option 20A2, as shown in Figure 4(d), then based on the user's click on the second option 20A2, an "Correct Answer" display interface 20C is generated through image rendering, as shown in Figure 4(e).

[0105] Unlike application scenario one, application scenario two also requires user interaction to render images.

[0106] It should be understood that the above are illustrative examples of application scenarios and do not limit the application scenarios of this application in any way.

[0107] The pipeline creation method provided in the embodiments of this application will be described in detail below with reference to Figures 5 to 7.

[0108] Figure 5 is a schematic diagram of a pipeline creation method provided in an embodiment of this application. This method is applied to an electronic device, which includes a GPU, and the GPU includes N interfaces. Here, N is a positive integer greater than or equal to 2. The method includes:

[0109] S101. When starting an image processing task, divide the image processing task into N sub-tasks.

[0110] There is a one-to-one correspondence between the N subtasks and the N interfaces.

[0111] Image processing tasks include image rendering tasks. Electronic devices can categorize image processing tasks according to their type or their difficulty; this application embodiment does not impose such limitations.

[0112] Let's take image rendering as an example to illustrate the image processing task.

[0113] Optionally, the image rendering task can be divided into a first subtask, a second subtask, and a third subtask.

[0114] The first subtask can be a shader-related subtask, the second subtask can be a fixed function-related subtask, and the third subtask can be a dynamic parameter-related subtask. When starting an image rendering task, the electronic device can divide the image rendering task into the first, second, and third subtasks.

[0115] S102. Through the N interfaces corresponding to the N subtasks, access the corresponding N compilers in the GPU to compile the N subtasks and obtain N compiled subtasks.

[0116] It is understandable that there is a one-to-one correspondence between the N subtasks and the N interfaces. Therefore, each subtask can access the corresponding compiler in the GPU through the corresponding interface to compile and obtain the compiled subtask.

[0117] The following example illustrates how a GPU has three interfaces and image processing tasks are divided into three subtasks.

[0118] For example, a GPU includes three interfaces: a first interface, a second interface, and a third interface; correspondingly, the GPU also includes three compilers: a first compiler for the first interface, a second compiler for the second interface, and a third compiler for the third interface. The image processing task is an image rendering task, which is divided into a first subtask, a second subtask, and a third subtask.

[0119] The electronic device can access the first compiler in the GPU through the first interface to compile the first subtask and obtain the compiled first subtask; the electronic device can access the second compiler in the GPU through the second interface to compile the second subtask and obtain the compiled second subtask; the electronic device can access the third compiler in the GPU through the third interface to compile the third subtask and obtain the compiled third subtask.

[0120] It is understandable that the aforementioned subtasks typically refer to a piece of program code, and compiling a subtask is equivalent to compiling the program code. In some cases, compiling a subtask can also refer to compiling and optimizing the corresponding program code.

[0121] S103. Merge the N compiled subtasks to obtain the pipeline corresponding to the image processing task.

[0122] When merging compiled subtasks, it is usually necessary to check each compiled subtask to determine if it has been compiled successfully and whether identical parameters are consistent across all subtasks. If it is confirmed that all compiled subtasks have been compiled successfully and that the same parameter has the same value across all subtasks, then the compiled subtasks can be merged to obtain the pipeline corresponding to the image processing task.

[0123] The pipeline creation method provided in this application is applied to an electronic device, including a GPU. The GPU includes N interfaces, where N is a positive integer greater than or equal to 2. When starting an image processing task, the method divides the image processing task into N subtasks. Then, through the N interfaces corresponding to the N subtasks, it accesses the corresponding N compilers in the GPU to compile the N subtasks, resulting in N compiled subtasks. Finally, the N compiled subtasks are merged to obtain the pipeline corresponding to the image processing task. This is equivalent to dividing the image processing task corresponding to the pipeline into N subtasks during the pipeline creation process, and then compiling them synchronously through the N compilers in the GPU, thereby improving the efficiency of compiling the image processing task and thus improving the efficiency of pipeline creation.

[0124] Figure 6 is a schematic diagram of a pipeline creation method provided in an embodiment of this application. This method is applied to an electronic device, which includes a GPU. The GPU includes a first interface, a second interface, a third interface, a first compiler, a second compiler, and a third compiler. The method includes:

[0125] S201. When starting an image rendering task, the image rendering task is divided into shader subtasks, fixed function subtasks, and dynamic parameter subtasks.

[0126] S202. Access the first compiler through the first interface to compile the shader subtasks and obtain the compiled shader tasks.

[0127] A shader can refer to a type of program code that runs on the GPU and performs some subtasks of the image rendering pipeline.

[0128] For example, a shader can be a vertex shader. For instance, in the process of drawing a triangle through image rendering, a vertex shader can refer to the shader that manages the three vertices. A vertex shader can be SPIR-V code that manages vertex processing. Compiling a subtask of a vertex shader can refer to compiling and optimizing the SPIR-V code for vertex processing.

[0129] For example, a shader can be a fragment shader. For instance, in the process of drawing a triangle through image rendering, a fragment shader can refer to a shader that manages the connections between the three vertices. A fragment shader can be SPIR-V code that manages fragment processing (e.g., connecting lines). Compiling a subtask of a fragment shader can refer to compiling and optimizing the SPIR-V code for fragment processing.

[0130] For example, a shader can be a geometry shader. For instance, in the process of rendering a triangle through image rendering, a geometry shader can refer to a shader that manages the patterns, designs, etc., filling the interior of the triangle. A geometry shader can be SPIR-V code that manages the filling patterns and designs. Compiling the subtasks of the geometry shader can refer to compiling and optimizing the SPIR-V code that processes the filling patterns and designs.

[0131] Alternatively, compiling the shader subtasks can refer to incremental compilation.

[0132] Incremental compilation refers to compiling only the changed code and not compiling the unchanged code. Through static and dynamic analysis of the source code, incremental compilation identifies modified code, code with changed dependencies, and affected code, thus determining which code needs recompilation and which remains unchanged. The modified code, the code with changed dependencies, and the affected code are then recompiled. Compared to regular compilation, incremental compilation reduces the amount of code compiled, the workload, and the compilation time without affecting the compilation result.

[0133] The pipeline creation method provided in this application adopts incremental compilation when compiling subtasks, which can reduce the amount of code that needs to be compiled when compiling subtasks, thereby reducing the workload of compilation and reducing compilation time. This can effectively save the time of creating the pipeline, thereby saving the time of image processing based on the pipeline, effectively avoiding image lag, and improving user experience.

[0134] S203. Access the second compiler through the second interface to compile the fixed-function subtask and obtain the compiled fixed-function subtask.

[0135] Fixed functions can refer to functions that need to be processed in an image rendering task. For example, fixed functions may include rasterization state configuration, viewport and clipping state configuration, depth and template test state configuration, blending state configuration, and multisampling state configuration.

[0136] Rasterization.

[0137] Rasterization refers to the process of converting vector graphics (graphics defined by mathematical equations or geometric primitives, such as lines, curves, polygons, etc.) into raster graphics (images composed of pixel arrays). In other words, rasterization is the process of converting graphic data into pixels. Rasterization state configuration refers to the specific parameter configuration for converting graphic data into pixels. Specifically, rasterization state configuration can include polygon mode configuration, culling mode configuration, and depth offset configuration, among others.

[0138] Viewport and Scissor State configuration.

[0139] Viewport and clipping state configuration is a crucial component of the graphics rendering pipeline, determining the area and extent of image rendering. The viewport indicates the position and size of the image within the framebuffer. Clipping state defines which pixels should be rendered into the framebuffer and which should be discarded. Viewport and clipping state are closely related. In the graphics rendering pipeline, the vertex positions output by the vertex shader are first transformed by the viewport before the clipping test. That is, different viewport parameters result in different clipping test results. Viewport and clipping state configuration can refer to the configuration of position and size parameters within the framebuffer.

[0140] Configuration of depth and template test status.

[0141] Depth and stencil test state configurations have wide applications in 3D graphics rendering. For example, they can be used to achieve special visual effects such as occlusion, shadows, masking, and outline rendering. Depth and stencil test state configurations can include depth test state configurations and stencil test state configurations. The depth test determines which pixels should be drawn to the screen during rendering. It compares the depth value of a newly generated pixel (usually stored in the Z-Buffer) with the depth value of an existing pixel at the corresponding position on the screen to determine which pixel should be displayed. The stencil test controls whether a pixel can be written to the frame buffer. It compares the value of a newly generated pixel with the value in the stencil buffer to determine whether the pixel should be written to the frame buffer. In essence, depth and stencil test state configurations refer to configuring which pixels should be drawn to the screen and which pixels can be written to the frame buffer.

[0142] Mixed state configuration and multiple sampling.

[0143] Blending state configuration controls how color values ​​output by the pixel shader are blended with color values ​​already existing in the render target during image rendering. Key parameters of blending state configuration include: BlendEnable: Whether blending is enabled. If set to FALSE, blending is not performed; RenderTargetWriteMask: Specifies which color channels (red, green, blue, alpha) can be written to the render target; SrcBlend and DestBlend: Specifies the blending factors for the source and target colors, respectively. These factors determine the weight of the source and target colors during the blending process.

[0144] Multisampling refers to reducing aliasing in the rendered result by sampling each pixel multiple times. In some cases, multisampling configuration can be set by configuring the number and quality of samples on the render target. Key parameters for multisampling configuration include the number and quality of samples. The number of samples specifies the number of times each pixel is sampled. A higher number of samples results in better anti-aliasing but also increases the computational and memory consumption of image rendering. The quality of samples specifies the distribution and weights of the sampling points. Higher quality multisampling provides better anti-aliasing but further increases computational and memory consumption.

[0145] Compiling fixed-function subtasks can refer to compiling the rasterization state configuration, viewport and clipping state configuration, depth and template test state configuration, hybrid state configuration, and multisampling state configuration mentioned above.

[0146] Optionally, compiling fixed-function subtasks refers to incremental compilation.

[0147] The specific process of incremental compilation can be found in the description in S202 above, and will not be repeated here.

[0148] S204. Access the third compiler through the third port to compile the dynamic parameter subtask and obtain the compiled dynamic parameter subtask.

[0149] The dynamic parameter subtask can include the dynamic viewport parameter update subtask, the dynamic clipping rectangle update subtask, and the dynamic linewidth and blending constant update subtask.

[0150] Dynamic viewport updates.

[0151] A dynamic viewport refers to a viewport whose images or scenes are updated in real time or on demand based on the user's movement, scaling, or rotation within the interface, reflecting the latest state or data. A dynamic viewport update subtask refers to the image rendering subtask performed during viewport movement, scaling, or rotation.

[0152] Dynamically update the clipped rectangle.

[0153] Dynamically clipping a rectangle refers to dynamically adjusting the clipping area of ​​a rectangle based on changes in the viewport or other conditions, thereby updating the displayed content. The clipping area can be a rectangular region or an irregularly shaped region; this application embodiment does not impose any limitations on this. The dynamic clipping rectangle update subtask can refer to a subtask that updates and adjusts the parameters of the clipping area.

[0154] Dynamic linewidth and blending constant updates.

[0155] During image rendering, line width can be dynamically adjusted based on certain conditions or parameters. Adjusting line width can be applied to drawing dynamic scenes or enhancing the visual effect of lines. For example, line width can be adjusted during map rendering and path drawing to indicate travel speed or emphasize certain paths.

[0156] Blending constants are parameters used in image rendering to control the degree of blending between different colors or image layers. For example, when rendering transparent objects, blending constants control the degree of blending between the object and the background. By adjusting the blending constant, different levels of transparency can be achieved. In color transitions or gradients, blending constants control the smooth transition between different colors; adjusting blending parameters can generate more natural and fluid color changes. In image compositing, blending constants control the blending method between different image layers; adjusting the blending constant can achieve different compositing effects such as overlay, multiplication, and screen blending.

[0157] Compiling the dynamic parameter subtasks yields the compiled dynamic parameter subtasks. This can refer to compiling the dynamic viewport update subtask, the dynamic clipping rectangle update subtask, and the dynamic linewidth and blend constant update subtask.

[0158] Alternatively, compiling the dynamic parameter subtask can refer to incremental compilation.

[0159] The specific process of incremental compilation can be found in the description in S202 above, and will not be repeated here.

[0160] In some possible cases, the pipeline creation method provided in this application embodiment can be applied to electronic devices including multi-core CPUs. The above-mentioned "accessing a first compiler through a first interface to compile shader subtasks and obtain compiled shader tasks", "accessing a second compiler through a second interface to compile fixed-function subtasks and obtain compiled fixed-function subtasks", and "accessing a third compiler through a third interface to compile dynamic parameter subtasks and obtain compiled dynamic parameter subtasks" can be performed by different cores in a multi-core CPU.

[0161] For example, the electronic device includes a quad-core CPU, namely core 1, core 2, core 3, and core 4. The electronic device can execute through core 1 to access a first compiler via a first interface to compile shader subtasks and obtain compiled shader tasks. Through core 2, it can execute through a second compiler via a second interface to compile fixed-function subtasks and obtain compiled fixed-function subtasks. Through core 3, it can execute through a third compiler via a third interface to compile dynamic parameter subtasks and obtain compiled dynamic parameter subtasks.

[0162] S205. Store the compiled shader subtasks, compiled fixed function subtasks, and compiled dynamic parameter subtasks in the preset storage area.

[0163] The preset storage area can refer to the cache area corresponding to the application. For example, when an electronic device responds to a game application creating a pipeline, it compiles the shader subtasks, fixed-function subtasks, and dynamic-parameter subtasks respectively, obtaining the compiled shader subtasks, compiled fixed-function subtasks, and compiled dynamic-parameter subtasks. These compiled subtasks can then be stored in the game application's cache. When the game application needs to create the pipeline again, the electronic device can first check if the pipeline exists in the game application's cache. If the game application's cache contains the already created pipeline, it can directly call that pipeline. If the game application's cache contains the pipeline, the electronic device can create the pipeline using the steps shown in S201 to S204 and the step shown in S206.

[0164] S206. Merge the compiled shader subtasks, the compiled fixed function subtasks, and the compiled dynamic parameter subtasks to obtain the pipeline corresponding to the image rendering task.

[0165] Compiled shader subtasks, compiled fixed-function subtasks, and compiled dynamic parameter subtasks can be passed to the merger via message queues or shared memory. Upon receiving these subtasks, the merger checks them to ensure that identical parameters are consistent. If the identical parameters are consistent, the merged subtasks are combined to obtain a complete pipeline, allowing the electronic device to render images according to the complete pipeline.

[0166] Optionally, after merging the compiled shader subtasks, compiled fixed-function subtasks, and compiled dynamic-parameter subtasks to obtain the pipeline corresponding to the image rendering task, the pipeline can be stored in a cache. The next time the image rendering task is executed, the cached pipeline is directly called. This saves time creating the pipeline and improves the efficiency of image rendering.

[0167] The CPU in an electronic device may include a pipeline creation module and a merger, while the GPU in the electronic device includes multiple interfaces and a compiler corresponding to each interface. When creating a pipeline for an image processing task, the pipeline creation module can divide the image processing task into subtasks. Then, the corresponding compilers are accessed through the multiple interfaces in the GPU to compile each subtask. Finally, the compiled subtasks are input into the merger for merging to obtain the pipeline corresponding to the image processing task. The following detailed description is provided using the embodiment shown in Figure 7.

[0168] Figure 7 is a flowchart illustrating another method for creating a pipeline provided in an embodiment of this application. As shown in Figure 7, the method includes:

[0169] S301. When the pipeline module detects the start of an image processing task, it divides the image processing task into N sub-tasks.

[0170] The pipeline creation module can detect whether an image processing task has started according to a preset sampling period. It's understood that image processing tasks, especially image rendering tasks, are usually performed using Vulkan. Therefore, detecting whether an image processing task has started can be done by checking if the Vulkan API has been called. If the Vulkan API has been called, the image processing task has started; if it hasn't, it hasn't.

[0171] If the Vulkan API is invoked, the image processing task is started. Creating a pipeline module can classify multiple subtasks in the image processing task, and modularize subtasks of the same type into N subtask modules.

[0172] For example, creating a pipeline module can modularize vertex shader, fragment shader, and fragment shader-related tasks as shader subtasks. Creating a pipeline module can modularize rasterization, viewport and clipping state configuration, depth and stencil test state configuration, blending state configuration, and multisampling tasks as fixed-function subtasks. Creating a pipeline module can modularize dynamic viewport updates, dynamic clipping rectangle updates, and dynamic linewidth and blending constant updates tasks as dynamic parameter subtasks.

[0173] For ease of description, we will take the image processing task as divided into three subtasks, namely the first subtask, the second subtask, and the third subtask, and the GPU as including the first interface, the second interface, the third interface, the first compiler, the second compiler, and the third compiler as an example for explanation.

[0174] S302. Create a pipeline module that accesses the first compiler in the GPU through the first interface to compile the first subtask and obtain the compiled first subtask.

[0175] Alternatively, compiling the first subtask can be done incrementally.

[0176] Optionally, before compiling the first subtask, the pipeline module can access the first application to determine if the first application's cache contains the compiled first subtask. If the first application's cache contains the compiled first subtask, it can directly obtain the compiled first subtask; if the first application's cache does not contain the compiled first subtask, it can access the first compiler in the GPU through the first interface to compile the first subtask and obtain the compiled first subtask.

[0177] The first application is the application that invokes the image processing task. For example, this image processing task is invoked by a game application to render the game's visuals. The game application is the first application mentioned above.

[0178] S303, The first compiler returns the compiled first subtask to the synthesizer.

[0179] S304. Create a pipeline module that accesses the second compiler in the GPU through the second interface to compile the second subtask and obtain the compiled second subtask.

[0180] Alternatively, compiling the second subtask can be done incrementally.

[0181] Optionally, before compiling the second subtask, the pipeline module can access the first application to determine if the first application's cache contains the compiled second subtask. If the first application's cache contains the compiled second subtask, it can directly obtain it; if the first application's cache does not contain the compiled second subtask, it can access the second compiler in the GPU through the second interface to compile the second subtask and obtain the compiled second subtask.

[0182] S305, The second compiler returns the compiled second subtask to the synthesizer.

[0183] S306. Create a pipeline module that accesses the third compiler in the GPU through a third interface to compile the third subtask and obtain the compiled third subtask.

[0184] Alternatively, compiling the third subtask can be done incrementally.

[0185] Optionally, before compiling the third subtask, the pipeline module can access the first application to determine if the first application's cache contains the compiled third subtask. If the first application's cache contains the compiled third subtask, it can directly obtain the compiled third subtask; if the first application's cache does not contain the compiled third subtask, it can access the third compiler in the GPU through the third interface to compile the third subtask and obtain the compiled third subtask.

[0186] S307, the third compiler returns the compiled third subtask to the synthesizer.

[0187] S308, the synthesizer merges the compiled first subtask, the compiled second subtask, and the compiled third subtask to obtain the pipeline.

[0188] S309, The synthesizer sends the pipeline to the image rendering module.

[0189] S310, the image rendering module performs image rendering tasks based on the pipeline.

[0190] S311, The synthesizer sends the pipeline to the first application.

[0191] S312, The first application stores the pipeline in the cache.

[0192] The first application can store the pipeline in a cache. When the first application launches the same image processing task again, it can first check the cache to see if a pipeline that has already been created exists. If the first application has a pipeline that has already been created in its cache, the first application can instruct that the pipeline be called to execute the image processing task; if the first application does not have a pipeline that has already been created in its cache, it can create the pipeline according to the steps shown in S301 to S311 above, and then execute the image processing task according to the pipeline.

[0193] Storing pipelines in a cache allows the application to directly use the cached pipelines when it restarts the same image processing task, avoiding the need to repeatedly create pipelines and improving image processing efficiency.

[0194] It should be understood that the above examples are provided to help those skilled in the art understand the embodiments of this application, and are not intended to limit the embodiments of this application to the specific values ​​or scenarios illustrated. Those skilled in the art can obviously make various equivalent modifications or changes based on the above examples, and such modifications or changes also fall within the scope of the embodiments of this application.

[0195] The pipeline creation method of this application embodiment has been described in detail above with reference to Figures 5 to 7. The device embodiment of this application will be described in detail below with reference to Figures 8 and 9. It should be understood that the pipeline creation device in the embodiments of this application can execute the various pipeline creation methods described in the foregoing embodiments of this application. That is, the specific working processes of the various products described below can be referred to the corresponding processes in the foregoing method embodiments.

[0196] Figure 8 is a schematic diagram of the pipeline creation device provided in an embodiment of this application.

[0197] It should be understood that the pipeline creation device 600 can execute the pipeline creation method shown in Figures 5 to 7; the pipeline creation device 600 includes an acquisition unit 610 and a processing unit 620. It should also be understood that network identification and network repair can be deployed within the pipeline creation device 600.

[0198] In one example, the processing unit 620 is used to divide the image processing task into N subtasks when starting the image processing task; access the corresponding N compilers in the GPU through the N interfaces corresponding to the N subtasks respectively, compile the N subtasks to obtain N compiled subtasks; and merge the N compiled subtasks to obtain the pipeline corresponding to the image processing task.

[0199] It should be noted that the aforementioned pipeline creation device 600 is embodied in the form of a functional unit. The term "unit" here can be implemented in software and / or hardware, without specific limitations.

[0200] For example, a "unit" can be a software program, a hardware circuit, or a combination of both that implements the above functions. The hardware circuit may include an application-specific integrated circuit (ASIC), electronic circuitry, a processor (e.g., a shared processor, a proprietary processor, or a group processor) and memory for executing one or more software or firmware programs, integrated logic circuitry, and / or other suitable components that support the described functions.

[0201] Therefore, the units of the various examples described in the embodiments of this application can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0202] Figure 9 shows a schematic diagram of the structure of an electronic device provided in this application. The dashed lines in Figure 9 indicate that the unit or module is optional. The electronic device 700 can be used to implement the pipeline creation method described in the above method embodiments.

[0203] Electronic device 700 includes one or more processors 701, which support the pipeline creation method in the method embodiments of electronic device 700. Processor 701 can be a general-purpose processor or a special-purpose processor. For example, processor 701 can be a central processing unit (CPU), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, such as discrete gates, transistor logic devices, or discrete hardware components.

[0204] The processor 701 can be used to control the electronic device 700, execute software programs, and process data from the software programs. The electronic device 700 may also include a communication unit 705 for inputting (receiving) and outputting (transmitting) signals.

[0205] For example, electronic device 700 may be a chip, communication unit 705 may be the input and / or output circuit of the chip, or communication unit 705 may be the communication interface of the chip, and the chip may be a component of terminal device or other electronic device.

[0206] For example, electronic device 700 can be a terminal device, communication unit 705 can be the transceiver of the terminal device, or communication unit 705 can be the transceiver circuit of the terminal device.

[0207] The electronic device 700 may include one or more memories 702, which store a program 704. The program 704 can be executed by the processor 701 to generate instructions 703, causing the processor 701 to execute the pipeline creation method described in the above method embodiments according to the instructions 703.

[0208] Optionally, the memory 702 may also store data. Optionally, the processor 701 may also read the data stored in the memory 702, which may be stored at the same memory address as the program 704, or the data may be stored at a different memory address than the program 704.

[0209] The processor 701 and memory 702 can be configured separately or integrated together; for example, integrated on the system on chip (SOC) of the terminal device.

[0210] For example, the memory 702 can be used to store the relevant program 704 of the pipeline creation method provided in the embodiments of this application, and the processor 701 can be used to call the relevant program 704 of the pipeline creation method stored in the memory 702 when performing image restoration on the terminal device, and execute the pipeline creation method of the embodiments of this application; for example, when starting an image processing task, the image processing task is divided into N sub-tasks; through the N interfaces corresponding to the N sub-tasks, the corresponding N compilers in the GPU are accessed respectively to compile the N sub-tasks to obtain N compiled sub-tasks; the N compiled sub-tasks are merged to obtain the pipeline corresponding to the image processing task.

[0211] This application also provides a computer program product that, when executed by processor 701, implements the pipeline creation method described in any of the method embodiments of this application.

[0212] The computer program product can be stored in memory 702, for example, program 704. Program 704 is finally converted into an executable object file that can be executed by processor 701 after processing such as preprocessing, compilation, assembly and linking.

[0213] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a computer, implements the pipeline creation method described in any of the method embodiments of this application. The computer program may be a high-level language program or an executable object program.

[0214] The computer-readable storage medium is, for example, memory 702. Memory 702 can be volatile memory or non-volatile memory, or memory 702 can include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0215] In this application, "at least one" means one or more, and "more than one" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or multiple items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0216] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0217] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0218] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0219] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for example, the division of units is merely a logical functional division, and other division methods may exist in actual implementation; for example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0220] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0221] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0222] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for creating pipelines, characterized in that, The method is applied to an electronic device, the electronic device including a graphics processing unit (GPU), the GPU including N interfaces, where N is a positive integer greater than or equal to 2, the method including: When starting an image processing task, the image processing task is divided into N sub-tasks; By accessing the N interfaces corresponding to the N subtasks, the N compilers in the GPU are accessed respectively to compile the N subtasks and obtain N compiled subtasks; The N compiled subtasks are merged to obtain the pipeline corresponding to the image processing task.

2. The method according to claim 1, characterized in that, The process of compiling the N subtasks to obtain N compiled subtasks includes: Incremental compilation is performed on the N subtasks to obtain the N compiled subtasks.

3. The method according to claim 1 or 2, characterized in that, The method further includes: The N compiled subtasks are stored in a preset storage area, which is the cache area of ​​the application corresponding to the image processing task.

4. The method according to any one of claims 1 to 3, characterized in that, The GPU includes three interfaces: a first interface, a second interface, and a third interface. The N compilers are three compilers: a first compiler, a second compiler, and a third compiler. When starting an image processing task, the image processing task is divided into N sub-tasks, including: When starting the image processing task, the image processing task is divided into shader subtasks, fixed function subtasks, and dynamic parameter subtasks; The process involves accessing the corresponding N compilers in the GPU through the N interfaces corresponding to the N subtasks to compile the N subtasks, resulting in N compiled subtasks, including: The first compiler is accessed through the first interface to compile the shader subtask, resulting in a compiled shader subtask. The second compiler is accessed through the second interface to compile the fixed-function subtask, resulting in the compiled fixed-function subtask. The third compiler is accessed through the third interface to compile the dynamic parameter subtask, resulting in the compiled dynamic parameter subtask.

5. The method according to any one of claims 1 to 4, characterized in that, The electronic device also includes a pipeline creation module, wherein when initiating an image processing task, the image processing task is divided into N sub-tasks, including: When the pipeline creation module detects that the image processing task has started, it divides the image processing task into N sub-tasks.

6. The method according to claim 5, characterized in that, The GPU includes three interfaces: a first interface, a second interface, and a third interface. The N compilers are three compilers: a first compiler, a second compiler, and a third compiler. The N subtasks are compiled by accessing the corresponding N compilers in the GPU through the N interfaces corresponding to the N subtasks, resulting in N compiled subtasks, including: The pipeline creation module accesses the first compiler through the first interface to compile the shader subtasks and obtain the compiled shader subtasks. The pipeline creation module accesses the second compiler through the second interface to compile the fixed-function subtasks and obtain the compiled fixed-function subtasks. The pipeline creation module accesses the third compiler through the third interface to compile the dynamic parameter subtask and obtain the compiled dynamic parameter subtask.

7. The method according to any one of claims 1 to 6, characterized in that, The electronic device further includes a merger, which performs merging processing on the N compiled subtasks to obtain the pipeline corresponding to the image processing task, including: The merger merges the N compiled subtasks to obtain the pipeline corresponding to the image processing task.

8. The method according to any one of claims 1 to 7, characterized in that, The image processing task is an image rendering task.

9. A pipeline creation device, characterized in that, The pipeline creation apparatus includes a processor and a memory, the memory for storing a computer program, and the processor for calling and running the computer program from the memory, causing the pipeline creation apparatus to perform the pipeline creation method according to any one of claims 1 to 8.

10. A chip, characterized in that, Includes a processor, which, when executing instructions, performs the pipeline creation method as described in any one of claims 1 to 8.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, causes the processor to perform the pipeline creation method according to any one of claims 1 to 8.

12. A computer program product, characterized in that, The computer program product includes: computer program code, which, when executed by a processor, causes the processor to perform the pipeline creation method according to any one of claims 1 to 8.

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