CXL module, error correction method and controller

Abstract

A CXL module, an error correction method and a medium, which relate to the technical field of data access. The CXL module comprises a controller, and a memory module connected to the controller, wherein the memory module is provided with a plurality of memory dies; and the controller is configured to: perform ECC encoding on 512-bit data to be written, so as to generate a check code of less than or equal to 32 bits, and write said 512-bit data and the check code thereof into the memory module by means of one burst; and read said 512-bit data and the check code thereof from the memory module by means of one burst, and on the basis of the check code, perform error correction processing on said 512-bit data, wherein the check code is capable of correcting errors of more than 2 bits.

Description

CXL module, error correction method and controller

[0001] This application claims priority to Chinese Patent Application No. 202510059087.8, filed on January 14, 2025, entitled "CXL Module, Error Correction Method and Medium", the contents of which are to be understood as incorporated herein by reference. Technical Field

[0002] This disclosure relates to, but is not limited to, the field of data access technology, and particularly to a CXL module, error correction method, and medium. Background Technology

[0003] In some application scenarios, such as data centers performing large-scale computing tasks, a large number of computing nodes, processors, and memory chips often need to work together. A single read / write error can cause significant losses, thus placing high demands on the reliability of memory chips in these scenarios. To improve the reliability of memory chips, these application scenarios typically incorporate ECC (Error Checking and Correcting) functionality. ECC adds additional checksums to the data through encoding, and then detects and corrects errors through decoding during data transmission or storage. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] In a first aspect, embodiments of this disclosure provide a CXL module, including a controller and a memory module connected to the controller, wherein the memory module has multiple memory chips; wherein the controller is configured to: perform ECC encoding on 512-bit data to be written, generate a check code less than or equal to 32 bits, write the 512-bit data to be written and its check code to the memory module in a single burst; and read the 512-bit data to be written and its check code from the memory module in a single burst, and perform error correction processing on the 512-bit data to be written based on the check code; wherein the check code can correct errors of more than 2 bits.

[0006] Secondly, this disclosure provides an error correction method applied to the CXL module in the above embodiments. The CXL module includes a controller and a memory module connected to the controller, the memory module having multiple memory chips. The method includes: ECC encoding of 512-bit data to be written to generate a checksum of less than or equal to 32 bits; writing the 512-bit data to be written and its checksum into the memory module in a single burst; and reading the 512-bit data to be written and its checksum from the memory module in a single burst, and performing error correction processing on the 512-bit data to be written based on the checksum; wherein the checksum can correct errors of more than 2 bits.

[0007] Thirdly, this disclosure provides a non-transient computer storage medium, which stores a computer program that, when executed by a processor, implements the error correction method described in the above embodiments.

[0008] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0009] Overview of the attached figures

[0010] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0011] Figure 1 is a schematic diagram of the structure of an embodiment of the CXL module disclosed herein;

[0012] Figure 2A is a schematic diagram of the memory module structure in one embodiment of the CXL module of this disclosure;

[0013] Figure 2B is a schematic diagram of the memory module structure in one embodiment of the CXL module of this disclosure;

[0014] Figure 3A is a schematic diagram of the memory module structure in one embodiment of the CXL module of this disclosure;

[0015] Figure 3B is a schematic diagram of the memory module structure in one embodiment of the CXL module of this disclosure;

[0016] Figure 4 is a flowchart illustrating an embodiment of the error correction method of this disclosure.

[0017] Detailed Explanation

[0018] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments and features described herein can be combined arbitrarily.

[0019] The embodiments disclosed herein are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this disclosure are not limited to the shapes or values ​​shown in the drawings.

[0020] The ordinal numbers such as "first" and "second" in this disclosure are used to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0021] This disclosure describes several embodiments, but these descriptions are exemplary and not restrictive, and many more embodiments and implementations are possible within the scope of the embodiments described herein, which will be apparent to those skilled in the art. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with or in lieu of any other feature or element in any other embodiment.

[0022] This disclosure includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this disclosure may also be combined with any conventional features or elements to form the scheme defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other disclosed schemes to form another scheme defined by the claims. Therefore, it should be understood that any feature shown and discussed in this disclosure may be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

[0023] Furthermore, in describing representative embodiments, the specification may have presented methods and processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described in this disclosure to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and process should not be limited to performing the steps in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this disclosure.

[0024] In the description of this disclosure, unless otherwise stated, "multiple" means two or more.

[0025] As shown in Figure 1, this embodiment of the present disclosure provides a CXL module, including a controller 110 and a memory module 120 connected to the controller. The memory module has multiple memory chips 121. The controller 110 is configured to: perform ECC encoding on 512-bit data to be written to generate a checksum of less than or equal to 32 bits; write the 512-bit data to be written and its checksum to the memory module in a single burst; and read the 512-bit data to be written and its checksum from the memory module in a single burst, and perform error correction processing on the 512-bit data to be written based on the checksum. The checksum can correct errors of more than 2 bits.

[0026] CXL is developed based on PCIe 5.0 and runs on top of the PCIe physical layer. Based on the characteristics of memory access, CXL is divided into three sub-protocols: 1) CXL.io, 2) CXL.mem, and 3) CXL.cache. Correspondingly, CXL devices (also called CXL modules) are divided into three types: Type 1 CXL device, Type 2 CXL device, and Type 3 CXL device. Type 2 and Type 3 devices can have multiple memory modules, which can be DDR, HBM (High Bandwidth Memory), etc. Taking Type 2 devices as an example, Type 2 devices can be accelerator cards (such as GPUs) in real-world applications. The host provides data, and the accelerator card handles the computation. The HDM model allows the host to directly manage and control the storage space on the Type 2 device, dynamically allocating and configuring device memory according to application needs, and directly performing read and write operations. CXL Type 3 devices can provide hosts with large-capacity DRAM (Dynamic Random Access Memory) and can also support persistent media (i.e., non-volatile media, such as flash memory chips).

[0027] The CXL module in this embodiment can be a second type of CXL device or a third type of CXL device. The controller 110, also known as a CXL controller, may have a CXL interface based on the CXL protocol, allowing the host CPU to interact with the controller 110 via the CXL interface. For example, based on the CXL.io protocol, the host CPU can send instructions to the controller 110; based on the CXL.mem protocol, the host CPU can read data from the memory module 120 and write external data to the memory chips 121 on the memory module 120. The control chip 110 also has a memory controller (as shown in the figure, a DDR (Double Data Rate) controller) to manage the memory chips 121. The memory chips 121 may be, for example, DRAM.

[0028] Memory module 120 can be connected to memory chip 121 via pins for writing data to or reading data from memory chip 121. The number of pins can also be referred to as the bit width of memory module 120. As an example, memory module 120 can be a DIMM (Dual Inline Memory Module) module, and the number of pins of a DIMM module is typically 80 or 72.

[0029] In this embodiment, an ECC unit can be configured in the controller 110. For example, the ECC unit can be implemented as a hardware circuit within the control chip 110 to realize the ECC function of the CXL module. The ECC unit encodes the data written to the memory module 120 to generate a data checksum. For example, the checksum can be a linear error correction code. When data needs to be read from the memory module 120, the ECC unit can use the previously generated checksum to detect whether there are any error bits in the read data and correct any error bits that appear.

[0030] According to the CXL protocol, the CXL module can write or read 512 bits of data in a single burst. The ECC unit in controller 110 can encode the 512 bits of data to be written, generate a checksum corresponding to the 512 bits of data to be written, and write the 512 bits of data to be written and the checksum to be written into memory module 120. If the checksum is less than or equal to 32 bits, the storage space occupied by the checksum in memory module 120 will not exceed 32 bits. When the CXL module reads data from memory module 120, the ECC unit in controller 110 can read the 512 bits of data to be read and the checksum to be read from memory module 120 according to the correspondence between data and checksum, and perform detection and error correction on the 512 bits of data to be read according to the checksum, which can correct errors of more than 2 bits in the 512 bits of data to be read.

[0031] As an example, the controller 110 can be encoded using the BCH (Bose–Chaudhuri–Hocquenghem codes) error correction algorithm, and the resulting check code can be 32-bit, 30-bit, 22-bit, or 20-bit.

[0032] The CXL module of this disclosure performs ECC encoding on the 512-bit data to be written, generating a checksum of less than or equal to 32 bits. The 512-bit data and its checksum can be written to the memory module in a single burst, and the same data can be read from the memory module in a single burst. Based on the checksum, errors of more than 2 bits in the 512-bit data to be written can be corrected. Data written or read in a single burst requires only one encoding or decoding, and more error bits can be corrected. It also reduces the storage resources occupied by the ECC checksum, thus enabling the CXL module to achieve more efficient error correction capabilities with a smaller capacity requirement.

[0033] In some embodiments, the memory chips on the memory module are divided into one or more groups, and each group of memory chips includes: multiple first chips for storing 512-bit data of a burst write; and one second chip for storing the checksum of the 512-bit data of a burst write.

[0034] As an example, the memory module can be DDR4 (Double Data Rate Fourth Generation Synchronous Dynamic Random Access Memory) or DDR5 (Double Data Rate Fourth Generation Synchronous Dynamic Random Access Memory), and each group of memory chips can store 512 bits of data and its checksum for a single burst write.

[0035] Figures 2A and 2B show schematic diagrams of the memory module structure in an optional embodiment of this invention. In this embodiment, when the memory module is DDR4, the structure shown in Figure 2A or Figure 2B can be used. As shown in Figure 2A, each group of memory chips may include eight × 8 first chips 210 and one × 4 second chip 220; as shown in Figure 2B, each group of memory chips may include sixteen × 4 first chips 230 and one × 4 second chip 240.

[0036] In this embodiment, ×8 indicates that the data width of the memory chip is 8 bits, and ×4 indicates that the data width of the memory chip is 4 bits. In related technologies, when a CXL module with ECC function uses DDR4 memory modules, the number of pins on the memory module is typically 72 to connect to the nine ×8 memory chips. Eight ×8 memory chips are used to store regular data, and the remaining ×8 memory chip is used to store a checksum for the regular data. Thus, at each sampling edge in a burst (i.e., the rising and falling edges of each clock cycle), the controller continuously transmits 64 bits of regular data with the eight ×8 memory chips, and simultaneously transmits an 8-bit checksum with the remaining ×8 memory chip, performing error correction on the 64 bits of regular data based on the checksum.

[0037] In this embodiment, the number of bits of the check code is no more than 32 bits. Each group of memory chips only needs to transmit a 32-bit check code in a burst to meet the ECC requirements. A second ×4 chip can be used to replace the ×8 memory chip to store the check code, thereby reducing the hardware cost of the CXL module while meeting the ECC requirements.

[0038] In an optional example of this implementation, the controller is connected to either an 8×8 first particle or a 16×4 first particle via 64 pins, and to a 1×4 second particle via 4 pins.

[0039] In this example, the memory module is a DRR4 with at least 68 pins, such as the more common 72. A burst can consist of 4 clock cycles. On the rising and falling edges of each clock cycle, the controller can transfer data with the memory chips via pins, meaning a burst can include 8 transfer processes. During each transfer, the controller can access (read or write) 64 bits of regular data in the first memory chip via the 64 pins connected to it, and simultaneously access the 4-bit checksum in the second memory chip via the 4 pins connected to it. In this way, the controller can access 512 bits of regular data and its checksum in a single burst.

[0040] Figures 3A and 3B illustrate schematic diagrams of the memory module structure in some optional embodiments of this example. In this embodiment, the memory module is a DDR5 memory module with two channels, and its structure can adopt the structure shown in Figure 3A or Figure 3B. In the embodiment shown in Figure 3A, each group of memory chips in each channel includes eight × 4 first chips 310 and one × 4 second chip 320; in the embodiment shown in Figure 3B, each group of memory chips in each channel may include eight × 4 first chips 330 and one × 2 second chip 340.

[0041] In related technologies, when a CXL module with ECC functionality uses DDR5 memory modules, the memory modules typically have 80 pins, with 40 pins per channel. Each group of memory chips in each channel consists of 10 × 4 memory chips. Eight × 4 memory chips are used to store regular data, and the remaining two × 4 memory chips are used to store a checksum. During each sampling edge of a burst, the controller can transmit 32 bits of regular data with the eight × 4 memory chips and an 8-bit checksum with the remaining two × 4 memory chips, performing error correction on the 32 bits of regular data based on the 8-bit checksum.

[0042] In this embodiment, the number of bits of the check code is no more than 32 bits. Each group of memory chips only needs to transmit 32 bits of check code in a burst to meet the ECC requirements. Each group of memory chips uses only one × 4 second chip or one × 2 second chip to store the check code. Under the premise of meeting the ECC requirements, the hardware cost of the CXL module is reduced.

[0043] In an optional example of this embodiment, eight × 4 first chips in each group of memory chips in each channel are connected to the controller via 32 pins, and one × 4 second chip or one × 2 second chip in the same group of memory chips is connected to the controller via four pins or two pins.

[0044] In this example, the memory module is DDR5, and its pin count can commonly be 80, with 40 pins per channel. Taking Figure 3A as an example, 32 pins connect eight x 4 first-stage memory chips (310) from a group of memory chips to the controller, and the other four pins connect one x 4 second-stage memory chip (320) from the same group to the controller. In this way, on each sampling edge, the controller can transmit 32 bits of regular data and a 4-bit checksum with a group of memory chips in one channel. The controller can access 512 bits of regular data and 64 bits of checksum data (the first 32 bits are the checksum, and the last 32 bits are redundant data) from a group of memory chips in one channel in a single burst.

[0045] Taking Figure 3B as an example, each channel of the memory module has 32 pins corresponding to connect eight × 4 first chips 330 from a group of memory chips to the controller, and the other two pins connect one × 2 second chip 340 from the same group of memory chips to the controller. In this way, on each sampling edge, the controller can transmit 32 bits of regular data and 2 bits of checksum with a group of memory chips in one channel. The controller can access 512 bits of regular data and 32 bits of checksum data from a group of memory chips in one channel in a single burst.

[0046] In some embodiments, when the number of bits of the checksum is no more than 30 bits, the controller is also configured to transmit 2 bits of metadata in a burst using the pin that transmits the checksum, and write the metadata and checksum into the same second particle.

[0047] In this embodiment, when the number of bits of the check code is no more than 30 bits, there are at least 2 bits of redundant data in the data obtained from a second particle in a burst. These at least 2 bits of redundant data can be replaced with metadata. In this way, the controller of the CXL module can access 512 bits of regular data from each group of first particles in a burst, and access the check code and metadata of the 512 bits of data from the second particle of the same group, thereby further improving the access performance of the CXL module and the utilization rate of storage resources.

[0048] In some embodiments, each group of memory chips also includes a ×4 third chip for storing 32-bit extended metadata corresponding to the 512-bit data to be written; the controller is also configured to write the 512-bit data to be written, its checksum, and extended metadata to the third chip in a single burst.

[0049] Taking the embodiments shown in Figures 2A and 2B as examples, when the memory module is DDR4, its pin count can be a commonly used 72 bits. To fully utilize the bit width of the memory module, a third chip of ×4 can be set in each group of memory chips (as shown by 250 in Figure 2A and 260 in Figure 2B). In this way, the controller can access 512 bits of regular data in each group of first chips, 32 bits of extended metadata in each third chip, and 32 bits of checksum data in each second chip in a single burst. The 32 bits of checksum data can include the following three cases: 32 bits of checksum; 30 bits of checksum and 2 bits of metadata; or 2 bits of metadata, a checksum less than 30 bits, and redundant data.

[0050] Taking the embodiments shown in Figures 3A and 3B as examples, when the memory module is DDR5, its pin count can be a commonly used 80 bits. To fully utilize the bit width of the memory module, a third chip of ×4 can be set in each group of memory chips (as shown by 350 in Figure 3A and 360 in Figure 3B). In this way, the controller can access 512 bits of regular data in each group of first chips, 32 bits of extended metadata in each third chip, and 32 bits of checksum data in each second chip in a single burst. The 32 bits of checksum data can include the following three cases: 32 bits of checksum; 30 bits of checksum and 2 bits of metadata; or 2 bits of metadata, a checksum less than 30 bits, and redundant data.

[0051] In this embodiment, a third chip is set in the memory module to store extended metadata, which can make full use of the pins of the memory module and improve the utilization rate of storage resources in the CXL module.

[0052] As shown in Figure 4, this embodiment of the present disclosure also provides an error correction method applied to the CXL module in the above embodiment. The CXL module includes a controller and a memory module connected to the controller, and the memory module is provided with multiple memory chips. The method may include the following steps.

[0053] Step 410: Perform ECC encoding on the 512-bit data to be written to generate a check code of less than or equal to 32 bits, and write the 512-bit data to be written and its check code into the memory module in a burst.

[0054] Step 420: Read the 512-bit data to be written and its checksum from the memory module in a burst, and perform error correction processing on the 512-bit data to be written based on the checksum.

[0055] The checksum can correct errors of two or more bits.

[0056] The error correction method in this embodiment performs ECC encoding on the 512-bit data to be written, generating a checksum of less than or equal to 32 bits. A single burst can write the 512-bit data and its checksum to the memory module, and a single burst can also read the 512-bit data and its checksum from the memory module. Based on the checksum, errors of more than 2 bits in the 512-bit data to be written can be corrected. Data written or read in a single burst requires only one encoding or decoding, and more error bits can be corrected. It also reduces the storage resources occupied by the ECC checksum, thus enabling the CXL module to achieve more efficient error correction capabilities at a lower capacity cost.

[0057] In some embodiments, the memory chips on the memory module are divided into one or more groups, and each group of memory chips includes: multiple first chips for storing 512 bits of data in a burst write; and one second chip for storing 512 bits of data in a burst write.

[0058] In some embodiments, the memory module is a DDR4 memory module, and each group of memory chips includes 8 × 8 first chips and 1 × 4 second chips, or includes 16 × 4 first chips and 1 × 4 second chips.

[0059] In some embodiments, the memory module is a DDR5 memory module with two channels, each channel having a group of memory chips including 8 × 4 first chips and 1 × 4 second chip; or including 8 × 4 first chips and 1 × 2 second chip.

[0060] In some embodiments, the controller is connected to an 8×8 first particle or a 16×4 first particle via 64 pins and to a 1×4 second particle via 4 pins.

[0061] In some embodiments, eight × 4 first chips in each group of memory chips in each channel are connected to the controller via 32 pins, and one × 4 second chip or one × 2 second chip in the same group of memory chips is connected to the controller via four pins or two pins.

[0062] In some embodiments, when the memory module is DDR4 and the number of bits of the checksum is no more than 30 bits, the error correction method may further include: transmitting 2 bits of metadata using the pin that transmits the checksum in a burst, and writing the metadata and checksum into the same second chip.

[0063] In some embodiments, the 512-bit data to be written is ECC encoded, including: the controller uses the BCH error correction algorithm to encode the 512-bit data to be written to obtain a check code; the check code has 30, 32, 22 or 20 bits.

[0064] In some embodiments, each group of memory chips also includes a ×4 third chip for storing 32-bit extended metadata corresponding to the 512-bit data to be written; the error correction method may also include: writing the 512-bit data to be written, its checksum, and extended metadata into the third chip in a single burst.

[0065] This disclosure also provides a non-transient computer storage medium, which stores a computer program that, when executed by a processor, implements the error correction method described in the above embodiments.

[0066] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

Claims

1. A CXL module, comprising a controller and a memory module connected to the controller, wherein the memory module has a plurality of memory chips; wherein, The controller is configured to: perform ECC encoding on the 512-bit data to be written, generate a checksum of less than or equal to 32 bits, and write the 512-bit data to be written and its checksum into the memory module in a single burst; and read the 512-bit data to be written and its checksum from the memory module in a single burst, and perform error correction processing on the 512-bit data to be written based on the checksum; wherein the checksum can correct errors of more than 2 bits.

2. The CXL module according to claim 1, wherein, The memory chips on the memory module are divided into one or more groups, and each group of memory chips includes: Multiple first particles are used to store 512 bits of data from a single burst write; A second particle is used to store the checksum of 512 bits of data written in a burst.

3. The CXL module according to claim 2, wherein, The memory module is a DDR4 memory module, and each group of memory chips includes 8 x 8 first chips and 1 x 4 second chip, or 16 x 4 first chips and 1 x 4 second chip.

4. The CXL module according to claim 2, wherein, The memory module is a DDR5 memory module with two channels. Each channel contains a group of memory chips consisting of 8 x 4 first chips and 1 x 4 second chip; or 8 x 4 first chips and 1 x 2 second chip.

5. The CXL module according to claim 3, wherein, The controller is connected to either an 8×8 first particle or a 16×4 first particle via 64 pins, and to a 1×4 second particle via 4 pins.

6. The CXL module according to claim 4, wherein, In each channel, the first 8 x 4 memory chips in each group are connected to the controller via 32 pins, and the second 1 x 4 memory chip or the second 1 x 2 memory chip in the same group are connected to the controller via 4 pins or 2 pins.

7. The CXL module according to claim 2, wherein, When the number of bits of the check code is no more than 30 bits, the controller is further configured to: transmit 2 bits of metadata in a burst using the pin that transmits the check code, and write the metadata and the check code into the same second particle.

8. The CXL module according to claim 1, wherein, The controller performs ECC encoding on the 512-bit data to be written, including: The controller uses the BCH error correction algorithm to encode the 512-bit data to be written to obtain the check code; The check code can be 30, 32, 22, or 20 bits.

9. The CXL module according to any one of claims 2 to 8, wherein, Each group of memory chips also includes a third chip of ×4, used to store 32-bit extended metadata corresponding to the 512-bit data to be written; The controller is also configured to write the 512-bit data to be written, its checksum, and the extended metadata to the third particle in a single burst.

10. An error correction method applied to a CXL module according to any one of claims 1 to 9, the CXL module comprising a controller and a memory module connected to the controller, the memory module having a plurality of memory chips; wherein, The method includes: The 512-bit data to be written is ECC encoded to generate a checksum of less than or equal to 32 bits. The 512-bit data and its checksum are then written to the memory module in a single burst. The 512-bit data to be written and its checksum are read from the memory module in a burst, and error correction is performed on the 512-bit data to be written based on the checksum; wherein the checksum can correct errors of more than 2 bits.

11. The method according to claim 10, characterized in that, The memory chips on the memory module are divided into one or more groups, and each group of memory chips includes: Multiple first particles are used to store 512 bits of data from a single burst write; A second particle is used to store the checksum of 512 bits of data written in a burst.

12. The method according to claim 11, characterized in that, The memory module is a DDR4 memory module, and each group of memory chips includes 8 x 8 first chips and 1 x 4 second chip, or 16 x 4 first chips and 1 x 4 second chip.

13. The method according to claim 11, characterized in that, The memory module is a DDR5 memory module with two channels. Each channel contains a group of memory chips consisting of 8 x 4 first chips and 1 x 4 second chip; or 8 x 4 first chips and 1 x 2 second chip.

14. The method according to claim 12, characterized in that, The controller is connected to either an 8×8 first particle or a 16×4 first particle via 64 pins, and to a 1×4 second particle via 4 pins.

15. The method according to claim 13, characterized in that, In each channel, the first 8 x 4 memory chips in each group are connected to the controller via 32 pins, and the second 1 x 4 memory chip or the second 1 x 2 memory chip in the same group are connected to the controller via 4 pins or 2 pins.

16. The method according to claim 11, wherein when the memory module is DDR4 and the checksum has no more than 30 bits, the method further comprises: In a burst, two bits of metadata are transmitted using the pin that transmits the checksum, and the metadata and the checksum are written into the same second particle.

17. The method according to claim 10, wherein, The step of ECC encoding the 512-bit data to be written includes: the controller using the BCH error correction algorithm to encode the 512-bit data to be written to obtain the check code; the check code has 30, 32, 22 or 20 bits.

18. The method according to any one of claims 11 to 17, wherein, Each group of memory chips also includes a third chip of ×4, used to store 32-bit extended metadata corresponding to the 512-bit data to be written; The method further includes: writing the 512-bit data to be written, its checksum, and the extended metadata into the third particle through a single burst.

19. A non-transient computer storage medium storing a computer program, wherein, When the computer program is executed by a processor, it implements the error correction method as described in any one of claims 10 to 18.

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