Data access method and related apparatus

Abstract

Embodiments of the present application provide a data access method and a related apparatus. The data access method comprises: on the basis of a first address in a first request, determining a second address and first metadata of first data from a directory cache, wherein the first request is a read request or a write request for the first data, the first address is used for indicating a logical address of the first data in a main memory connected to a chip, the second address is used for indicating a physical address of the first data in the main memory, and the first metadata is used for indicating whether the first data is in a compressed state; determining a target data bit on the basis of the second address and the first metadata, the target data bit being used for indicating a data bit of the first data in a memory row indicated by the second address; and accessing the first data on the basis of the target data bit. In the method, metadata is obtained on the basis of addresses already stored in a directory cache, and a main memory is accessed on the basis of the metadata, thereby saving storage resources for redundant storage of addresses, and saving storage resources for a chip.

Description

Data access methods and related devices

[0001] This application claims priority to Chinese Patent Application No. 202510088693.2, filed on January 20, 2025, entitled “Data Access Method and Related Apparatus”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of chip technology, and in particular to a data access method and related apparatus. Background Technology

[0003] Memory bandwidth compression is a technique used to optimize memory bandwidth. The main implementation process of memory bandwidth compression includes: after the processor (or processor core) issues a read / write request for a specific address, the on-chip directory structure determines the address corresponding to the read / write request in the stored addresses, obtains the list of sharers for that address, and performs cache coherence processing. After completing cache coherence processing, the address corresponding to the read / write request is determined in the address stored in the chip's dedicated cache, the compression-related information matching that address is obtained, and the compression-related information is used to access main memory.

[0004] In this implementation process, addresses need to be stored in the directory structure and in a dedicated cache, and redundant storage of addresses wastes the storage resources on the chip. Summary of the Invention

[0005] This application provides a data access method and related apparatus, which aim to save on-chip storage resources.

[0006] The first aspect of this application provides a data access method applied to a chip or a computer device incorporating the chip. Based on a data access request, the chip accesses data in its connected main memory to perform read or write operations on the data in the main memory. Furthermore, the chip includes a directory structure for controlling data consistency among multiple processor caches within the chip. This directory structure includes a controller for control and a directory cache for storing control information (such as a sharelist). A processor cache refers to a cache accessed by a processor; each processor has a corresponding cache for storing frequently used data from main memory, including data shared among the processors. Based on the control information, the controller ensures that shared data at the same address remains consistent across different processor caches, achieving cache consistency. Based on achieving cache consistency, the controller of this directory structure can access data in main memory.

[0007] In a first aspect of this application, the data access method includes: determining a second address and first metadata of first data from a directory cache based on a first address in a first request; wherein the first request is a read request or write request for the first data, the first address is the logical address of the first data in the main memory of the chip, the second address is the physical address of the first data in the main memory of the chip, and the first metadata is used to indicate whether the first data is in a compressed state; determining a target data bit according to the second address and the first metadata; wherein the target data bit is used to indicate the data bit of the first data in the memory row indicated by the second address; and accessing the first data according to the target data bit.

[0008] The first request can be issued by the processor on the chip, such as a read request for first data or a write request for first data. A read request for first data is used to retrieve the first data from main memory, while a write request is used to modify the first data in main memory. The first data stored in main memory is loaded into the processor cache upon the processor's first access, or pre-loaded into the processor cache when it is predicted that the processor will need it in the future, thus ensuring that the processor cache contains the first data. When the first data is loaded into the processor cache, the directory structure tracks the state of the first data and records the state of processor sharing of the first data in the directory cache. This state is then mapped to the second address of the first data and stored in the directory cache. This allows the processor to match the address to determine the state of shared first data when accessing it, maintaining cache consistency. The first address in the first request indicates the logical address of the first data in main memory, and the second address in the directory cache indicates the physical address of the first data in main memory. A mapping relationship exists between logical and physical addresses, allowing the first address to be mapped to the second address. The directory structure can determine the corresponding second address and the list of sharers corresponding to that second address based on the first request, and use the list of sharers to determine the state of processor sharing of the first data.

[0009] The storage space corresponding to the second address in the directory cache also stores the first metadata. This first metadata, located at the second address, indicates whether the first data stored in main memory is in a compressed state. A compressed state refers to the state where the data has already been compressed. A circuit module can be configured in the chip to implement data compression and decompression. This module performs compression processing on the uncompressed first data, removing redundant or duplicate information, to obtain the compressed first data. It then decompresses the compressed first data to obtain the same first data as before compression. In other words, for the first data, the uncompressed and decompressed versions carry the same information, and the compression process is lossless. If the first data lacks compressible characteristics (e.g., it lacks duplicate or redundant information), making compression impossible, the first metadata indicates that the first data is not in a compressed state. Since the first metadata is stored in the directory cache, and the directory cache synchronously stores the second address corresponding to the first metadata when the first data is loaded into the processor cache, the controller of the directory structure determines the first metadata based on the second address, saving the storage space previously used to separately store the address corresponding to the first metadata.

[0010] The compressed first data has a shorter data length and occupies fewer data bits in main memory, while the uncompressed first data has a longer data length and occupies more data bits in main memory. Data in main memory is stored in bytes as the smallest unit, and the location where this unit is stored is called a data bit. The first address determines the second address of the first data in the directory cache. Combined with the second address, the physical address of the first data in main memory is further determined. Based on this physical address and the first metadata, the specific data bits occupied by the first data are determined, i.e., the target data bits. Main memory contains memory rows, and the second address indicates the address of the memory row. By considering whether the first data is compressed or not, it is determined whether the first data is stored in a longer or shorter data row in the memory row, thus obtaining the target data bits. The first data is then accessed at the corresponding target data bits. Therefore, this chip can provide access to the compressed first data, improving memory bandwidth.

[0011] In the first aspect mentioned above, the first metadata used to indicate whether the first data is in a compressed state is stored in the directory cache, so that when the chip processes the first request to access the first data, the controller of the directory structure can match the first address of the first request with the second address in the directory cache and obtain the first metadata corresponding to the second address. This reuses the address originally used to implement cache consistency processing to determine whether the first data is compressed, omitting the storage space of repeatedly storing the address corresponding to the first metadata in the dedicated cache, thus saving the chip's storage resources.

[0012] In one possible implementation, accessing the first data based on the target data bit includes: if the first request is a write request, modifying the first data of the target data bit, and configuring the second metadata in the main memory according to whether the modified first data can be compressed; wherein the second metadata is used to indicate whether the first data is in a compressed state after being accessed; if the first request is a read request, reading the first data of the target data bit, and configuring the second metadata to indicate whether the first data is currently compressed.

[0013] In this possible implementation, main memory stores second metadata indicating whether the first data is compressed. This second metadata indicates whether the first data is in a compressed state after being accessed. If the first request is a write request, meaning it needs to modify the first data, it must first read the first data, modify it, and then compress it. If compression fails, it indicates that the modified first data cannot be compressed, and the second metadata is set to indicate that it is not in a compressed state. If compression succeeds, the second metadata is set to indicate that it is in a compressed state. If the first request is a read request, the first data is read, and the second metadata is configured to be the same as the first metadata. If the main memory already stores second metadata identical to the first metadata, the original second metadata is retained.

[0014] This implementation method enables the second metadata in the main memory to reflect the latest state of whether the first data has been compressed after it has been accessed. This allows the chip to determine the latest state of whether the first data has been compressed, maintain the accuracy of this state, and improve the reliability of accessing the first data.

[0015] In one possible implementation, the directory cache includes multiple static random access memories (SRAMs), including a first SRAM used to store first metadata. The method further includes updating the first metadata in the first SRAM based on whether the first data is in a compressed state after being accessed; wherein the updated first metadata is the same as the second metadata.

[0016] In this possible implementation, the directory cache is based on SRAM and has multiple SRAMs, each accessed independently and unaffected by access to other SRAMs. Each SRAM contains multiple transistors, providing high access speed and enabling fast access to the first metadata. The first SRAM stores the first metadata, while the other SRAMs store other information used for cache coherency processing (such as a sharer list). Independent access between the first SRAM and other SRAMs allows for a degree of parallelism in accessing the first metadata; accessing the first SRAM allows for concurrent access to other SRAMs. After accessing the first data in main memory, if the state of the accessed first data changes, the directory structure controller updates the metadata of the first data based on whether the data is now compressed. This ensures the directory structure recognizes the change and reflects the latest state of compression.

[0017] This implementation method allows for updating the first metadata in the directory cache. Therefore, upon the next access to the first data, the updated first metadata reflects the latest state of compression, accurately determining which data bits the first data is currently in, thus maintaining the accuracy of data access. Furthermore, the first metadata is stored in the first SRAM across multiple SRAMs, enabling parallel access independently of the other SRAMs. This parallel access allows for access to more data simultaneously, thereby improving the access bandwidth to the directory cache.

[0018] In one possible implementation, the chip further includes a processor connected to the controller, and the directory cache is also used to store a first sharer list, which indicates the status of processors sharing the first data. The method further includes: updating the first sharer list; if the updated first sharer list indicates that at least one processor is sharing the first data, then retrieving the configured second metadata from main memory; if the updated first sharer list indicates that no processor is sharing the first data, then not updating the first metadata.

[0019] In this possible implementation, the processor is connected to the controller of the directory structure, enabling the controller to manage the first data stored in the processor cache through a first sharer list stored in the directory cache. The first sharer list indicates the status of processors sharing the first data. The first sharer list includes the processor's identifier, the consistency status of the first data, etc. The identifier identifies the processor, and the consistency status includes whether the first data is shared by multiple processor caches, whether the first data has been modified, and whether the first data in the processor cache is consistent with the first data in main memory. The directory cache contains multiple SRAMs, including a second SRAM, which stores the first sharer list. The first and second SRAMs are independently accessible. After the controller maps a second address based on a first request, it updates the first sharer list corresponding to the second address based on the first request, such as adding or removing sharers, so that the updated first sharer list reflects the latest sharing status. If the first sharer list indicates that at least one processor is sharing the first data, the second address and corresponding first metadata are still retained in the directory cache, thereby retrieving the second metadata configured in main memory and updating the first metadata. If the first sharer list indicates that no processor shares the first data, the second address and the corresponding first metadata are cleared, and no update operation is performed on the first metadata. Specifically, if the first request is a read request for the first data, since it only involves obtaining a copy of the first data and not modifying the first data, the processors still share the first data after reading it. In this case, the updated first sharer list still indicates that a processor shares the first data, and the first metadata can be updated. If the first request is a write request for the first data, after modifying the first data, since the first data has changed, the modified first data may still be shared by a processor or may not be shared by a processor. Therefore, it is necessary to determine whether a processor still shares the first data based on the updated first sharer list, and whether to use the second metadata to update the first metadata. The first metadata is updated if a processor still shares the first data; otherwise, it is not updated. If the controller cannot obtain the first metadata because the first request does not map the second address, it needs to access the second metadata in main memory, update the second metadata in main memory and the corresponding second address to the directory cache, so that the first metadata at the second address in the directory cache can be accessed next time.

[0020] With this implementation, the controller of the directory structure can update the first metadata when necessary to maintain its accuracy, taking into account whether there are still processors sharing the first metadata, and omit the update operation when no update is needed, thus saving the chip's computing resources.

[0021] In one possible implementation, the first metadata is stored in a first cache line, which is contained in multiple cache lines of a first storage partition bank. The first bank is contained in multiple banks of a first SRAM, and each bank is a partition for independent access. The first metadata in the first SRAM is updated based on whether the first data is in a compressed state after being accessed, including: reading the first cache line; wherein the first cache line includes multiple metadata; updating the first metadata in the multiple metadata based on whether the first data is in a compressed state after being accessed; and writing the updated multiple metadata into the first cache line.

[0022] In this possible implementation, the first SRAM is divided into multiple banks, each bank including multiple cache lines. Each bank has corresponding control logic and access ports for independently handling access requests. The multiple banks contain a first bank storing first metadata, and the first bank includes multiple cache lines, each containing a first cache line storing first metadata. The first cache line contains multiple metadata, and these multiple metadata contain the first metadata. The first metadata indicates whether the first data is in a compressed state; that is, it actually has two states, represented by 0 or 1. 0 or 1 only occupies 1 bit when stored, while the first cache line can store multiple bits of metadata. Therefore, multiple metadata can be concatenated and stored in the first cache line, making full use of the storage resources of the first cache line. When accessing SRAM, the cache line is the smallest access unit. To update the first metadata, the data in the first cache line needs to be read, the first metadata in the first cache line needs to be updated, and the updated data in the first cache line needs to be written back to the first cache line, completing the update of the first metadata. While updating the first metadata in the first bank, other banks in multiple banks can be accessed in parallel, such as reading other metadata in other banks in parallel. Multiple metadata can be accessed at the same time, thereby improving the access bandwidth of the first SRAM.

[0023] Using this implementation, the first bank in the first SRAM can be accessed independently, thus updating the first metadata in the first bank in parallel without interference from accesses by other banks in the first SRAM. Furthermore, the first metadata occupies only a small amount of storage space, and the first cache line contains multiple metadata entries, fully utilizing the storage resources of the first SRAM.

[0024] In one possible implementation, the multiple SRAMs also include a second SRAM, which can be accessed independently of the first SRAM. The method further includes: determining a second sharer list from the second SRAM based on a second request; wherein the second request is a read request or write request for second data, and the second sharer list is used to record the state in which the second data is shared by the chip's processor; parsing the second request and the second sharer list to obtain a parsing result; and updating the second sharer list if the parsing result indicates that the state in which the second data is shared by the processor has changed.

[0025] In this possible implementation, the second SRAM used to store the sharer list and the first SRAM used to store metadata in the multiple SRAMs of the directory cache are accessed independently. This allows for simultaneous read and write operations on the metadata in the first SRAM and the sharer list in the second SRAM. For example, the sharer list and metadata can be updated in parallel without interference. During the process of accessing the first data based on the first request, the directory structure controller also simultaneously receives a second request from other processors, indicating access to the second data. This requires the directory structure controller to maintain the state of processors sharing the second data and to update the second sharer list corresponding to the second data. While updating the second sharer list, since the second sharer list is stored in the independently accessible second SRAM, the metadata in the first SRAM is also updated synchronously, thereby improving the access bandwidth of the directory cache.

[0026] In one possible implementation, the directory cache has multiple groups, including a first group, each group including multiple cache lines, the first group including a target cache line that matches a first address, and determining the first metadata of a second address and first data from the directory cache based on the first address in the first request, including: determining the first group among the multiple groups of the directory cache based on the group index of the first address; and determining the second address and the first metadata within the first group.

[0027] In this possible implementation, the directory cache is divided into multiple groups, each group containing multiple cache lines. If the directory cache includes multiple SRAMs, then each group includes multiple cache lines from different SRAMs. The second address and the first metadata are stored in target cache lines, and the target cache lines contain different cache lines; for example, the second address may exist in a cache line of one SRAM, and the first metadata may exist in a cache line of another SRAM. The first address includes a group index, a tag, and an offset. The group index is used to determine the first group where the first data resides, the tag is used to determine the corresponding target cache line, and the offset is used to locate the specific byte of the data to find the second address and the first metadata. This allows for quick location of the group containing the second address and the first metadata, and further precise determination of the second address and the first metadata.

[0028] In one possible implementation, determining the target data bit based on the second address and the first metadata includes: if the first metadata indicates that the first data is in a compressed state, then the target data bit is a data bit of a first length in the memory row indicated by the second address; if the first metadata indicates that the first data is not in a compressed state, then the target data bit is a data bit of a second length in the memory row indicated by the second address; wherein the first length is less than the second length.

[0029] In this possible implementation, the length of the target data bits differs depending on whether the first data is compressed. When the first data is compressed, the length is the first length; when the first data is not compressed, the length is the second length. The smaller first length results in the smaller storage space occupied by the first data, and the saved storage space can be used to store other data, such as the second data. When accessing data in main memory at the same time, although the read and write speed of main memory remains unchanged, the smaller length of the compressed data allows for the simultaneous access of more data, such as the simultaneous access of the first and second data, thereby improving memory bandwidth.

[0030] A second aspect of this application provides a chip, comprising: a processor configured to issue a first request; wherein the first request is a read request or a write request for first data; a directory structure including a directory cache and a controller connected to the directory cache, the controller being connected to the processor; wherein: the directory cache is configured to store a second address and first metadata of the first data, the first metadata being configured to indicate whether the first data is in a compressed state; the controller is configured to determine the second address and the first metadata from the directory cache based on the first address in the first request, determine a target data bit based on the second address and the first metadata, and access the first data based on the target data bit, wherein the first address is the logical address of the first data in the main memory of the chip, and the second address is the physical address of the first data in the main memory of the chip.

[0031] When the processor needs to access the first data in main memory, it issues a first request. This first request is received by the directory structure controller. The controller first parses the state of the shared first data in the processor cache based on the first address in the first request to maintain cache consistency. During this process, the controller looks up the second address and the first metadata from the directory cache of the directory structure based on the first address, and then accesses the first data. The directory cache stores the second address and the first metadata; the second address is used to correspond with the first metadata, indicating that the first metadata corresponds to the first data.

[0032] In the second aspect mentioned above, when the chip processes the first request to access the first data, it determines whether the first data is in a compressed state based on the first metadata by determining the second address already stored in the directory cache and the first metadata, and then accesses the main memory. This allows the chip to reuse the address originally used to implement cache consistency processing to determine whether the first data is compressed, thus eliminating the need to repeatedly store the address corresponding to the first metadata in the dedicated cache and saving the chip's storage resources.

[0033] In one possible implementation, when the controller accesses the first data based on the target data bit, it specifically performs the following: if the first request is a write request, it modifies the first data of the target data bit and configures the second metadata in the main memory according to whether the modified first data can be compressed; wherein, the second metadata is used to indicate whether the first data is in a compressed state after being accessed; if the first request is a read request, it reads the first data of the target data bit and configures the second metadata to indicate whether the first data is currently compressed.

[0034] In one possible implementation, the directory caches multiple SRAMs, including a first SRAM used to store first metadata; the controller is also used to: update the first metadata in the first SRAM based on whether the first data is in a compressed state after being accessed; wherein the updated first metadata is the same as the second metadata.

[0035] In one possible implementation, the directory cache is further used to store a first sharer list, which indicates the status of processors sharing the first data. When the controller retrieves the second metadata configured from main memory, it specifically updates the first sharer list. If the updated first sharer list indicates that at least one processor is sharing the first data, the controller updates the first metadata in the first SRAM based on whether the first data is in a compressed state after being accessed. The controller is also used to: if the updated first sharer list indicates that no processor is sharing the first data, the controller does not update the first metadata.

[0036] In one possible implementation, the first SRAM includes multiple banks, each bank being a partition for independent access. The multiple banks include the first bank, the first bank includes multiple cache lines, and the multiple cache lines include the first cache line, which is used to store first metadata. When the controller updates the first metadata in the first SRAM based on the second metadata, it specifically reads the first cache line, which includes multiple metadata. Based on whether the first data is in a compressed state after being accessed, it updates the first metadata among the multiple metadata and writes the updated multiple metadata into the first cache line.

[0037] In one possible implementation, the multiple SRAMs also include a second SRAM, which can be accessed independently of the first SRAM; the controller is further configured to: determine a second sharer list from the second SRAM based on a second request, wherein the second request is a read request or a write request for the second data, the second sharer list is used to record the state in which the second data is shared by the processor, parse the second request and the second sharer list to obtain a parsing result, and update the second sharer list if the parsing result indicates that the state in which the second data is shared by the processor has changed.

[0038] In one possible implementation, the directory cache has multiple groups, including a first group, each group including multiple cache lines, the first group including a target cache line that matches a first address; the controller, when used to determine the first metadata of the second address and the first data from the directory cache based on the first address in the first request, specifically uses: a group index based on the first address to determine the first group among the multiple groups of the directory cache, and within the first group to determine the second address and the first metadata.

[0039] In one possible implementation, the controller, when determining the target data bit based on the second address and the first metadata, specifically performs the following: if the first metadata indicates that the first data is in a compressed state, then the target data bit is a data bit of a first length in the memory row indicated by the second address; if the first metadata indicates that the first data is not in a compressed state, then the target data bit is a data bit of a second length in the memory row indicated by the second address; wherein the first length is less than the second length.

[0040] A third aspect of this application provides a data access device, including a chip as described in the second aspect or any possible implementation of the second aspect, wherein the chip implements the method of the first aspect or any possible implementation of the first aspect when it is running.

[0041] The technical effects of the second aspect, any implementation of the second aspect, or the third aspect of this application can be described with reference to the description of the corresponding technical effects in the first aspect or any possible implementation of the first aspect. Attached Figure Description

[0042] Figure 1 is a schematic diagram of the chip structure provided in an embodiment of this application;

[0043] Figure 2 is a schematic diagram of the structure of the data access device provided in an embodiment of this application;

[0044] Figure 3 is a flowchart illustrating the data access method provided in an embodiment of this application;

[0045] Figure 4 is an exemplary schematic diagram of the data storage method in the directory cache provided in the embodiments of this application;

[0046] Figure 5 is an exemplary schematic diagram of the main memory storage method provided in the embodiments of this application;

[0047] Figure 6 is a schematic diagram of the interaction between various units in the chip provided in the embodiment of this application;

[0048] Figure 7 is a schematic diagram of the interaction between units in the chip when using a multi-request parallel processor as provided in the embodiments of this application;

[0049] Figure 8 is another structural schematic diagram of the chip provided in the embodiment of this application;

[0050] Figure 9 is another structural schematic diagram of the chip provided in the embodiment of this application;

[0051] Figure 10 is a schematic diagram illustrating the effect of the compression unit provided in the embodiment of this application;

[0052] Figure 11 is another structural schematic diagram of the chip provided in the embodiment of this application;

[0053] Figure 12 is an exemplary schematic diagram of simultaneous access to multiple SRAMs provided in an embodiment of this application;

[0054] Figure 13 is another structural schematic diagram of the chip provided in the embodiment of this application;

[0055] Figure 14 is an exemplary schematic diagram of simultaneous access to multiple banks provided in an embodiment of this application;

[0056] Figure 15 is another structural schematic diagram of the data access device provided in the embodiments of this application. Detailed Implementation

[0057] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such terms are used interchangeably where appropriate so that the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0058] It should be understood that, in addition, the character " / " in this document generally indicates that the preceding and following objects are in an "or" relationship. "At least one of the following" or similar expressions in this document are used to indicate any combination of the listed items; for example, at least one of A, B, and / or C represents the following six situations: A exists alone, B exists alone, C exists alone, A and B exist simultaneously, B and C exist simultaneously, A and C exist simultaneously, and A, B, and C exist simultaneously, where A, B, and C can be single or multiple. In the embodiments of this application, "instruction" means control, that is, one object controls another object to perform an action, and the controlled object must perform the action. Furthermore, "instruction" also means notification, that is, one object informs another object to perform an action, and the object informed to perform the action chooses to perform the action or not to perform the action. In addition, "instruction" can be a direct instruction, such as one object directly issuing the instruction to another object; it can also be an indirect instruction, that is, one object issuing the instruction to another object through one or more intermediate objects. Furthermore, the meaning of "instruction" is also based on the meaning expressed in the embodiments of this application, and is not limited here. In the embodiments of this application, "one or more" is understood as one or more, and vice versa. "One or more" also means "at least one".

[0059] The data access method described in this application can be applied to the chip 100 shown in FIG. 1. The chip 100 includes a processor 101, a directory structure 102, and a processor cache 103 connected to the processor 101. The processor 101 includes multiple cores 1011. Furthermore, those skilled in the art will understand that the terms "processor" and "core" can correspond to each other. For example, in the following embodiments of this application, "multiple processors" can refer to "multiple cores," and "processor 1, processor 2" can also refer to "core 1, core 2." The directory structure 102 includes a controller 1021 and a directory cache 1022. The controller 1021 is connected to the cores 1011, the processor cache 103, and the directory cache 1022. The directory structure can also refer to a home agent (HA). The HA is used to achieve cache consistency. For example, when a core 1011 modifies or accesses shared data in the processor cache 103, the HA ensures that other cores 1011 perceive the shared data as consistent. The processor cache 103 may include multiple cache structures corresponding to each core 1011.

[0060] Chip 100 is a miniature device that integrates electronic components onto semiconductor material. The electronic components primarily consist of transistors, which are connected to form circuit modules with different functions on chip 100. For example, by connecting multiple transistors to form an arithmetic logic unit (ALU) and control logic, a processor 101 is obtained. The processor 101 executes instructions and can access data in the processor cache 103. A processor 101 contains one or more cores 1011, each of which processes data independently. By connecting multiple transistors to form control logic, a controller 1021 is obtained, which manages the data flow between different circuit modules on chip 100. Connecting multiple transistors also forms memory, such as a processor cache 103 built on SRAM. The processor cache 103 includes multiple memory cells, each containing six transistors, and each memory cell can store one bit of data. SRAM offers fast access speeds, but each memory cell requires a large number of transistors, resulting in a large footprint when placed on chip 100. Since chip 100 is a miniature structure, its area needs to be controlled, leading to a smaller memory size and a smaller data storage capacity. To store more data, main memory can be configured externally on chip 100 using dynamic random access memory (DRAM) or other methods. A single DRAM cell includes one transistor and one capacitor; its access speed is slow, but it is suitable for storing more data. Data in main memory can be processed by processor 101. For frequently used or recently accessed data, controller 1021 can copy these data from main memory to processor cache 103. Processor 101 accesses this data copy in processor cache 103 at a higher speed than accessing it from main memory.

[0061] The data stored in processor cache 103 corresponds to the data stored in main memory. Specifically, this correspondence can be based on the storage address of the data in main memory. For example, if data 1 is stored at address 1 in main memory, then the corresponding data 1 at address 1 is stored in processor cache 103. When processor 101 accesses data 1 at address 1, it looks up the data 1 in processor cache 103 or directly accesses the data 1 in main memory. If multiple cores 1011 each store data 1 at address 1 in processor cache 103 (specifically, in different sub-cache units included in processor cache 103) and access data 1 at address 1 respectively, each core 1011 will have a different value for data 1 at address 1. For example, processor cache 103 includes cache A and cache B, where cache A is accessed by core A and cache B is accessed by core B. Cache A stores data A, which is identical to the data at the corresponding address 1 in main memory; that is, data A has not been modified since being loaded from main memory. Cache B stores data B, which is also a copy of the data at address 1. However, at some point, kernel B modifies data B, so that although data B is still a copy of the data at address 1, its specific value changes. If kernel A still accesses the data according to the original data A, the processor will not be accessing the latest data at address 1, which may lead to an exception. For example, address 1 stores business data for a specific service. This business data changes over time, and the processor should process it according to the latest data. However, kernel A and kernel B process this business data at different times. After kernel B modifies the business data, kernel A should be informed of the modification so that kernel A can process business data consistent with kernel B. To achieve this, chip 100 has a directory structure 102.

[0062] The main principle of directory structure 102 is to track the access status of each core 1011 to data in processor cache 103 through the circuit structure (controller 1021) on chip 100, and record the corresponding status in directory cache 1022. Whenever core 1011 accesses data at a certain address, the access to that data is uniformly controlled through the status of that data in directory cache 1022, thereby maintaining the consistency of data at the same address stored in processor cache 103 by different cores 1011. A directory represents a structure for recording information. A directory includes information from multiple records, and the information from each record corresponds to data at the same address. For chip 100 with directory structure 102, when processor 101 accesses data, controller 1021 of directory structure 102 will first maintain cache consistency. If processor 101 modifies data at a certain address in processor cache 103, controller 1021 needs to make the same modification to the data at the same address in main memory to maintain the accuracy of the data at that address in main memory. At this time, main memory needs to be accessed. Furthermore, if the processor 101 merely reads data from the processor cache 103 without modifying it, it can avoid accessing main memory. However, in some cases, even if the processor cache 103 contains data at a certain address that the processor 101 can read, the controller 1021 can still access the data at the same address in main memory and provide it to the processor 101. Therefore, regardless of whether the processor 101 is reading or writing data, the controller 1021 can access the corresponding data in main memory.

[0063] To improve memory bandwidth, compressed data can be stored in main memory. Compressed data is shorter, occupies less space in main memory, and can store more data. Accessing multiple addresses simultaneously in main memory further increases bandwidth. However, if the data is not compressible, accessing main memory still requires accessing the data at its original length. Therefore, depending on whether the data in main memory is compressed, different lengths of data need to be accessed. Before accessing, it's necessary to determine if the data in main memory is compressed. This requires obtaining metadata indicating whether the data in main memory is compressed. To determine which address this information indicates, the metadata needs to be stored along with the address. Compared to directly storing the address and metadata in a dedicated cache, this embodiment stores the metadata in a directory cache 1022 and corresponds it to the address in the directory cache 1022. This allows reuse of addresses in the directory cache 1022 originally used for maintaining cache consistency for metadata confirmation, saving storage resources on the chip 100.

[0064] The data access method described in this application embodiment can also be applied to the data access device shown in FIG2. In the data access device 200 shown in FIG2, chip 201 is the same as chip 100 in FIG1. ​​Chip 201 is connected to main memory 202 and can access main memory 202. Main memory 202 and chip 201 can be connected via a bus and can be mounted on a motherboard, which can serve as a data access device. Alternatively, a computer device containing the motherboard can also serve as a data access device.

[0065] The aforementioned chip or data access device containing the chip can implement a data processing method, which can be executed by a controller of the directory structure within the chip, as shown in Figure 3. This data processing method includes steps 301-303. Each step is described in detail below.

[0066] Step 301. Based on the first address in the first request, determine the second address and the first metadata of the first data from the directory cache.

[0067] The first request is a request to access data. The first address included in the first request indicates the location of the accessed data in memory. The data stored at the first address is the first data. The first request indicates that the object issuing the request needs to access the first data. Access includes reading or writing. Writing data can modify existing data stored at the first address. The object issuing the first request is, for example, a processor. The object issuing the first request is connected to the controller of the on-chip directory structure, enabling the controller to receive the first request. The specific information carried by the first address is specified by the object issuing the first request; for example, the processor specifies the first address based on the location of the data it needs to access during instruction execution. The first address corresponds to the address of the first data stored in main memory. Specifically, the first address indicates the logical address of the first data in main memory. This logical address may be different from the actual address where the first data is stored in main memory, such as a logical address obtained by mapping from a physical address through a virtual memory mechanism. However, they can also be the same, and this application embodiment does not limit this. The directory cache is a cache in the directory structure used to store the second address, the directory entry corresponding to the second address (such as a list of sharers), and the first metadata corresponding to the second address. The second address corresponds to the first data and is used to indicate the physical address of the first data in main memory. It can be the same as, or different from, the address of the first data in main memory and have a corresponding relationship; no limitation is made here. The first metadata corresponds to the first data and is used to indicate whether the first data is in a compressed state or not.

[0068] After receiving the first request, the directory structure controller needs to synchronously maintain cache consistency and obtain the first metadata. During this process, the second address stored in the directory cache can be used to maintain cache consistency and obtain the corresponding first metadata, making full use of the existing second address.

[0069] To achieve cache consistency, the directory cache includes not only a second address and first metadata, but also multiple lists of sharers. These sharer lists include the first sharer list corresponding to the first data, which contains first status information, first node information, etc. The first status information indicates the status of the first data on each processor, such as modified, exclusive, shared, invalid, etc. The first node information marks which cache nodes hold the first data, for example, the processor (kernel) identifier. When a processor accesses the first data in main memory, and the first data is not in the processor cache, the directory structure controller accesses main memory to configure the second address in the directory cache based on the address information of the first data in main memory, and then loads the first data from main memory into the processor cache.

[0070] Upon receiving the first request, the directory structure controller can obtain the first metadata and the first sharer list as follows: The controller parses the first address from the first request message, matches the first address with multiple addresses in the directory cache to obtain the second address corresponding to the first address, and obtains the metadata corresponding to the second address as the first metadata of the first data. After obtaining the second address corresponding to the first address, the controller also synchronously obtains the first sharer list corresponding to the second address, maintaining cache consistency based on the first sharer. The second address, the first metadata, and the first sharer list are stored in cache lines of the directory cache. Furthermore, the second address, the first metadata, and the first sharer list can be stored in different cache lines or in the same cache line; this is not limited here. When stored in different cache lines, the controller is configured to record the correspondence between the second address, the first metadata, and the first sharer list to find the first metadata and the first sharer list corresponding to the second address based on this correspondence. When stored in the same cache line, after determining the second address, the controller directly obtains the first metadata and the first sharer list from the cache line containing the second address.

[0071] After obtaining the first list of sharers, the controller parses the list to determine if the first data already exists in the processor cache. If the first request is a read request and the first data already exists in the processor cache, the controller directly accesses the processor cache to provide the first data to the object that issued the first request, without accessing main memory. If the first request is a write request and the first data already exists in the processor cache, the first data in the processor cache needs to be modified. Since the modified first data invalidates the original first data, the controller can mark the data state of the processor cache that still contains the original first data as invalid. If the first data in the processor cache cannot be accessed, for example, because it cannot be modified due to being exclusively used by another processor, the controller does not access the first data in the processor cache but accesses the first data in main memory instead. Furthermore, in other implementations, if the controller determines that the first request is a read request, it directly accesses the first data in main memory even if the first data exists in the processor cache, without accessing the first data in the processor cache; this is not a limitation here.

[0072] Before accessing the first data in main memory, the controller updates the first sharer list in the directory cache. Specifically, if the first request is a read request, after reading the first data in the processor cache, without modifying or deleting the first data, the processor cache still contains the original first data, the processor's shared state of the first data remains unchanged, and the first sharer list containing this state also remains unchanged. Therefore, the updated first sharer list still exists and includes the previous processor's shared state of the first data. If the first request is a write request, the existence of the first sharer list depends on whether, after modifying the first data, there are still processors sharing a portion of the first data. If there are still processors sharing a portion of the first data, the updated first sharer list still exists and includes the processor's shared state of that portion of the first data. If, after the first data is modified, no processor shares the first data, the updated first sharer list does not exist. When the first sharer list exists, after accessing the first data in main memory, the controller updates the first metadata corresponding to the second address in the directory cache to reflect whether the first data in main memory is in a compressed state after the update.

[0073] Data in the directory cache is stored in a specific organized manner, and the controller is configured to access this data according to this organization. For example, if a directory entry (which may include a second address, first metadata, and a list of first sharers) is specified to be stored only in a specific location in the directory cache, the controller will directly search for the corresponding directory entry at that specified location during a query. Alternatively, if a directory entry is specified to be stored in any location, the controller will need to search the entire directory cache to determine where the directory entry is stored. Or, a directory entry may be specified to be stored in a group, and can be stored anywhere within that group; in this case, the controller can first locate the group where the directory entry is stored, and then search for the directory entry within each location within that group.

[0074] As shown in Figure 4, the directory cache is organized into multiple sets, including set 1, set 2, ... set N. Each set contains multiple cache lines. The cache lines in set 1 include a target cache line, which stores a second address, a list of first sharers, and first metadata. The second address matches the first address. The first address contains a set index, which indicates the set corresponding to the second address. Based on the first address in the first request, the second address and the first metadata of the first data are determined from the directory cache. Specifically, this involves: determining set 1 among the multiple sets in the directory cache based on the set index of the first address; and determining the second address and the first metadata within set 1. The first address may include a set index and a tag. The controller searches for the corresponding set 1 according to the set index, matches the tag with multiple addresses within the set, obtains the second address corresponding to that tag, and thus obtains the first metadata corresponding to the second address. This method quickly determines which set the second address is in and finds the second address and first metadata within that set. Furthermore, the first metadata can be flexibly stored in any cache line within the set, enhancing storage flexibility.

[0075] Furthermore, the aforementioned target cache line can be replaced with multiple cache lines. That is, the second address, the first sharer list, and the first metadata can be stored in caches of different SRAMs. For example, the directory cache includes a first SRAM, a second SRAM, and a third SRAM. Thus, the first metadata can be stored in cache line 1 of the first SRAM, the first sharer list in cache line 2 of the second SRAM, and the second address in cache line 3 of the third SRAM. In this case, the controller maps cache lines 1, 2, and 3. Therefore, after determining the second address in cache line 3, it can look up the corresponding cache lines 1 and 2 for cache line 3 and retrieve the first metadata and the first sharer list. Alternatively, both the first sharer list and the second address can be stored in cache line 2, or other methods can be used to store directory entries, as long as the controller determines the correspondence between the information within the same directory entry. No limitation is imposed here.

[0076] Step 302. Determine the target data bits based on the second address and the first metadata.

[0077] The target data bit is used to indicate the data bits of the first data in the memory row indicated by the second address. Based on the second address, the location (memory row) of the first data in main memory can be determined, and based on the first metadata, the specific data length corresponding to that location can be determined. Specifically, if the first metadata indicates that the first data is in a compressed state, the target data bit is the first length of data bits in the memory row indicated by the second address; if the first metadata indicates that the first data is not in a compressed state, the target data bit is the second length of data bits in the memory row indicated by the second address; wherein the first length is less than the second length. The controller is pre-configured to determine the specific data bits stored in the second address in main memory according to the length of the compressed first data when it is determined that the first data is in a compressed state. When it is determined that the first data is not in a compressed state, the specific data bits stored in the second address in main memory are determined according to the original length of the first data before compression. The specific values ​​of the first length and the second length depend on the configuration of the compression unit in the chip and are not limited here.

[0078] In the chip, the compression unit is specifically implemented as a circuit structure. This circuit structure is configured based on a certain compression algorithm. Without changing the circuit structure, the length of the same data after compression at different times is the same. Therefore, the first length can be determined based on the length of the first data in a compressed state obtained after data compression by the compression unit. If the first data is uncompressed, its original length is used as the second length. Furthermore, the aforementioned first or second length can be configured as a fixed value. For example, if the first data is in a compressed state, data bits of length x are accessed; if the first data is not in a compressed state, data bits of length y are accessed, where x is less than y. Additionally, the length information of the first data in a compressed state can also be stored separately, without limitation.

[0079] As shown in Figure 5, uncompressed and compressed data occupy different numbers of bits in main memory. In the uncompressed data storage method shown in Figure 5, each memory row contains error correction bits, metadata bits, high bits, and low bits. The error correction bits are used to correct errors in the data stored in the high and low bits. The metadata bits indicate whether the data stored in the high and low bits is in a compressed state. The high bit represents the higher data bits in the row, and the low bit represents the lower data bits in the row. The specific lengths of the high and low bits are not limited. When uncompressed data is stored in a memory row, it occupies both the high and low bits due to its larger length, while compressed data, due to its smaller length, occupies only the low bits. Memory rows can correspond to main memory addresses; the address of the memory row storing the first data corresponds to both the first address and the second address.

[0080] Step 303. Access the first data based on the target data bit.

[0081] When accessing the first data according to the target data bit, the corresponding access operation can be performed based on whether the first request is a read request or a write request. If the first request is a write request, the first data of the target data bit is modified, and the second metadata in the main memory is configured according to whether the modified first data can be compressed; wherein, the second metadata is used to indicate whether the first data is in a compressed state after being accessed; if the first request is a read request, the first data of the target data bit is read, and the second metadata is configured to indicate whether the first data is currently compressed.

[0082] If the first request indicates reading the first data, and the first metadata indicates that the first data is in a compressed state, then the low-order data is read. If the first metadata indicates that the first data is not in a compressed state, then both the high-order and low-order data are read. If the first request indicates writing the first data, the first data needs to be modified. During the modification process, if the first metadata indicates that the first data is in a compressed state, then the low-order data is read, decompressed, and the decompressed first data is modified. The modified first data is then re-attempted for compression. If compression is successful, the compressed data is stored in the low-order data; otherwise, it is stored in the corresponding data bits according to its original size. If the first metadata indicates that the first data is not in a compressed state, then the first data is directly read from the high-order and low-order data, modified, and then re-attempted for compression. The data is then stored in the corresponding data bits based on whether compression is successful. After reading the first data, the state of whether the first data is compressed remains unchanged and is maintained. After writing the first data, the state of whether the first data is compressed is updated based on whether it is actually in a compressed state.

[0083] The directory cache contains multiple directory entries. Each directory entry contains information such as address, metadata, and a list of sharers. Different directory entries contain different information. When a chip has multiple cores, these cores can issue requests in parallel as they execute instructions. The controller of the directory structure receives multiple requests simultaneously, and since these requests access data at different addresses, the corresponding directory entries are also different. To ensure that the metadata and sharer lists in the directory entries are up-to-date, access to different directory entries may occur simultaneously. For example, the controller receives a request from kernel 1, retrieves directory entry 1 for that request, and further performs cache consistency maintenance (updating the sharer list in directory entry 1) based on this entry. This determines the data bit in main memory that kernel 1 needs to access. Subsequently, the controller accesses the corresponding data bit. Because the accessed data changes from a compressed to an uncompressed state, the metadata in directory entry 1 needs to be updated. During the same time period of updating the metadata of directory entry 1, the controller also determines that the sharer list in directory entry 2 needs to be updated based on a request from kernel 2, and is currently updating the sharer list in directory entry 2. This necessitates updating the metadata in directory entry 1 and the sharer list in directory entry 2 within time period 2 (actually a very short period). To enable parallel updates, the directory cache can include multiple SRAMs, each accessed independently relative to the others, meaning the data stored within can be read and written independently. Metadata can be stored in the same SRAM, while the sharer list can be stored in another SRAM. In this case, the controller can access both directory entry 1 and directory entry 2 simultaneously, allowing for access to a larger number of directory entries and a larger data volume, thus resulting in higher access bandwidth.

[0084] Therefore, multiple SRAMs, including a first SRAM and a second SRAM, are independently accessible. The first SRAM stores multiple metadata, including the first metadata itself. Other SRAMs are also included to store other data, such as a first sharer list and a second address. The directory cache also stores the first sharer list, which indicates the status of processors sharing the first data. Parsing the first sharer list yields a resolution result. For example, the resolution result might indicate that at least one processor is sharing the first data, or that no processor is sharing the first data. Based on the resolution result, if at least one processor is sharing the first data, the configured second metadata is retrieved from main memory; otherwise, the first metadata is not updated. This ensures that the first metadata is updated promptly to reflect the latest status when it may change, and that the necessary resources for updating are omitted when it will not change.

[0085] After accessing the first data, the controller updates the first metadata in the first SRAM based on whether the accessed first data is in a compressed state, setting the first metadata in the first SRAM to the same value as the second metadata. The controller then determines the storage location of the first metadata in the first SRAM based on the second address and updates the first metadata at that location. This ensures that the first metadata in the directory cache reflects the latest state of whether the first data is in a compressed state.

[0086] While accessing the first SRAM, the controller can access the second SRAM in parallel. Therefore, if the controller receives another request, namely the second request, which requires accessing data at a different address, the controller can query the second sharer list from the second SRAM based on the second request. Here, the second request is a read request or write request for the second data, and the second sharer list is used to record the state in which the second data is shared by the chip's processor. The controller parses the second request and the second sharer list to obtain the parsing result. If the parsing result indicates that the state in which the second data is shared by the processor has changed, the second sharer list is updated.

[0087] SRAM consists of a two-dimensional array with interleaved rows and columns, and each intersection can store one bit. When accessing SRAM at a specific address, the entire row corresponding to that address is accessed, and this row contains multiple bits. Since metadata is used to indicate whether data is compressed, it can be represented by 0 or 1, requiring only one bit. Therefore, multiple metadata entries can be concatenated and stored in a single row. When accessing specific metadata, the entire row is accessed first, followed by the specific metadata within that row. If updating metadata in a cached row is required, the entire row must be read, updated, and then rewritten to the cached row. Therefore, updating the same metadata involves multiple accesses to the first SRAM. In contrast, updating the sharer list in the second SRAM simply involves writing the updated sharer list into the second SRAM. Overall, when the controller processes multiple requests within a given period, because the same metadata involves multiple accesses, the number of different sharer lists accessible by the second SRAM may be higher than the number of different metadata entries accessible by the first SRAM. This creates a bottleneck in metadata updates and in the complete processing of requests. To enable the first SRAM to access different metadata simultaneously as much as possible (i.e., parallel access to different metadata), the first SRAM can be designed as a bank (storage partition), dividing it into multiple banks that can be accessed in parallel. Each bank includes multiple cache lines, and different banks contain different cache lines. Each bank is a partition for independent access. The first metadata is stored in the first cache line, the first cache line is contained in the first bank, and the first bank is contained in the first SRAM. The cache lines in each bank are used to store the concatenated metadata. When updating the first metadata, multiple metadata from the first cache line can be read; based on whether the first data is in a compressed state after being accessed, the first metadata of the multiple metadata is updated, specifically by replacing the first metadata in the multiple metadata with the same value as the second metadata; the updated multiple metadata is then written to the first cache line.

[0088] As shown in Figure 6, this application embodiment provides a data access method, including:

[0089] Step 601. The processor sends a write request to the controller, and the controller receives the write request accordingly.

[0090] During operation, a processor may need to modify the value of some data, at which point it issues a write request. A write request may include a write address, write data, write request type, processor identifier, or other information. The write address indicates the location of the data to be written in main memory; the write data contains the actual data to be written; the write request type indicates that the access operation is for writing data; the processor identifier indicates which processor or core issued the request; and other information includes read / write permissions, priority, etc. Write requests issued by the processor can be transmitted to the controller via the bus. The controller can maintain a request queue to receive multiple write requests.

[0091] Step 602. The controller obtains the first address from the write request and matches it with the second address.

[0092] The second address can be stored in a second SRAM, that is, in the same SRAM as the sharer list, and an address in the second SRAM and its corresponding sharer list can be stored in a cache line. In the second SRAM, the cache line containing the second address stores the first sharer list. The second address corresponding to the first address is obtained by matching the first address with multiple addresses in the second SRAM. Alternatively, the address in the directory cache can also be stored in other SRAMs, such as a third SRAM. Regardless of which SRAM the address is stored in, the controller is configured to determine the correspondence between the address and the metadata and sharer list.

[0093] Step 603. The controller obtains the first metadata corresponding to the second address.

[0094] The first metadata is stored in the first SRAM, which is primarily used to store metadata. The cache line containing the first metadata contains multiple metadata items. After determining the second address, the controller determines the cache line corresponding to the second address in the first SRAM and retrieves the first metadata from that cache line. The corresponding cache line includes multiple metadata items, not just the first metadata. To determine the first metadata from the multiple metadata items in the cache line, the offset bits contained in the second address can be extracted, and the specific location of the first metadata in that cache line can be calculated based on the offset bits. Furthermore, the second SRAM may contain an index pointing to the cache line in the first SRAM. Based on this, after determining the second address from the second SRAM, the index of the row containing the second address points to the cache line in the first SRAM, thus determining which cache line the first metadata is stored in.

[0095] Step 604. The controller obtains the list of first sharers corresponding to the second address.

[0096] Steps 604 and 603 can be executed sequentially or simultaneously. The controller can obtain the first sharer list and the first metadata sequentially or simultaneously. If the second address is stored in the second SRAM, it is stored in the cache line containing the first sharer list, and the first sharer list can be obtained directly from the cache line containing the second address. If the second address is stored in another SRAM (the third SRAM), the second address in the third SRAM can be mapped to the first sharer list in the second SRAM to obtain the first sharer list based on this mapping.

[0097] Step 605. The controller parses the first list of sharers.

[0098] Parsing the first sharer list mainly involves using the information contained in the first sharer list and combining it with the write request to determine how to perform subsequent operations. For example, suppose kernel 1 issues a write request, and the first sharer list includes: kernel 2 (shared), kernel 3 (shared), and kernel 4 (holds write permissions). Kernel 1 is not in the first sharer list and needs to obtain write permissions; kernel 4 needs to release its state and write it back to main memory; kernels 2 and 3 need to invalidate the corresponding cache lines. After that, the first sharer list can be updated. Updating the first sharer list maintains cache consistency. Maintaining cache consistency takes time. During this time, because the metadata is stored in the directory cache, the controller can synchronously obtain the first metadata, which has lower latency compared to waiting for cache consistency processing to complete and then querying the first metadata in other storage units.

[0099] Step 606. The controller updates the first sharer list of the second SRAM.

[0100] After parsing the first sharer list, the controller can determine which processors (cores) are sharing the data and update the first sharer list as needed. When a new processor (core) requests access to the data, it needs to be added to the list. When a processor (core) releases data or the data is written back to main memory, that processor (core) needs to be removed. For example, in the above example, the first sharer list can be updated to: Core 1 (holds write permissions). In the example above, Cores 2 and 3 receive invalidation notifications and clear the data stored in the corresponding cache lines. After Core 4 writes back the data, the main memory is updated. Core 1 completes the write operation after obtaining exclusive permissions.

[0101] Step 607. The controller modifies the first data and the second metadata according to the first metadata.

[0102] Based on the second address, the physical location of the first data in main memory, such as the starting position, can be determined. The first metadata determines whether the first data is in a compressed state, and further, it determines how many data bits to offset from the starting position, thus determining from which data bits the first data will be obtained. For example, based on the starting address 0x1000 and the length of the compressed data (e.g., 64 bytes), the actual storage location of the data in main memory can be calculated. Accessing physical address 0x1000 yields 64 bytes of the first data. After obtaining the 64 bytes of the first data, it is decompressed. The decompressed first data is modified according to the write data indicated in the write request. After modification, compression is performed again. At this point, it may be found that the modified first data is no longer compressible, requiring an update to the state of the metadata corresponding to the first data. This state is stored in main memory, specifically in the memory row corresponding to the second address. By updating the metadata bits in the memory row corresponding to the second address from a compressed state (e.g., 1) to a non-compressed state (e.g., 0), the metadata in main memory can be updated, yielding the second metadata. If the modified data can still be compressed, the metadata bits in the memory row corresponding to the second address will be in a compressed state before and after the update (e.g., 1). In this case, the second metadata is actually the same as the first metadata.

[0103] Step 608. The controller updates the first metadata of the first SRAM.

[0104] After the controller modifies the first data, it checks whether the modified first data can compress and update the first metadata in the first SRAM. Since the first metadata is stored in a cache line in the first SRAM after being concatenated with other metadata, and the first SRAM is accessed in cache lines as the smallest access unit, it is necessary to obtain the entire cache line containing the first metadata, locate the first metadata within that line, update the first metadata, and then rewrite the entire cache line containing the updated first metadata back into the cache line, completing the first metadata update. For example, if the second metadata is 0 and the first metadata is 1, then the first metadata is updated to 0. After the first metadata is updated, the next time the first data is accessed, it can be determined whether the first data is currently in a compressed state, allowing access to the precise data bits and improving memory bandwidth.

[0105] By matching the addresses stored in the directory cache, it is possible to maintain cache consistency for each address while determining whether the data at that address is in a compressed state. This address can be used for multiple purposes simultaneously, saving storage space compared to storing addresses for different purposes separately. Furthermore, through updates, the primary metadata in the directory cache reflects the latest compression status of the data in main memory in real time, enabling accurate access to the corresponding data bits in main memory.

[0106] As shown in Figure 7, this application embodiment provides a data access method, including:

[0107] Step 701. Processor 1 sends a request 1 to the controller to access data 1, and the controller receives the request 1 accordingly.

[0108] Processor 1, as the computing core of the chip, accesses main memory data to perform computational operations via Request 1. The controller receives requests from Processor 1 and coordinates hardware modules such as the directory cache and main memory to complete subsequent processing. Request 1 can be a read request or a write request, used to retrieve or modify data, respectively. Request 1 contains information such as a logical address and request type, which the controller needs to parse. The logical address is mapped to a physical address; the logical address can be viewed as an address from a software perspective, while the physical address is the address actually stored in the hardware. The controller reads Request 1 from the bus, parses its content, and extracts the logical address for subsequent address matching. The request type is used to determine the subsequent operation flow (e.g., different processing flows correspond to read or write operations).

[0109] The controller can also perform request verification to ensure logical addresses are valid and prevent unauthorized access. Furthermore, the controller can check processor permissions to prevent unauthorized access to sensitive data. When multiple processors send requests simultaneously, the controller can store request 1 in a request queue, queuing them by priority or time order. After receiving a request, the controller can schedule it according to priority or fairness policies. For example, high-priority requests from real-time applications (such as audio / video decoding) are processed first, while low-priority requests from non-critical tasks (such as background data migration) are deferred. The controller can also predict the address range accessed by processors by analyzing historical requests and preload data into the processor cache. If multiple requests read the same data block, the requests can be merged.

[0110] Step 702. The controller uses address 1 in request 1 to determine group 1 that matches address 1 among multiple groups.

[0111] After the controller extracts the logical address (address 1) from request 1, it needs to search for the data record matching address 1 in the directory cache. The directory cache is divided into sets, meaning it contains multiple sets, each corresponding to SRAM1 and SRAM2 respectively. Each set contains multiple entries. The data stored in each set includes addresses, metadata, a list of sharers, or other information. Set 1 is selected using a portion of the address (such as the low-order bits). Address 1 (the logical address) in request 1 generates an index value using a mapping function (such as modulo, hash, or directly extracting the low-order bits) to locate set 1. Assuming address 1 is 0x1234ABCD, and the directory cache has 64 sets (set index range 0-63), the low 6 bits of the address are taken, converted to decimal 53, and used as the set index, indicating that set 1 is the set with index 53.

[0112] Step 703. The controller retrieves metadata 1 from group 1 in SRAM1.

[0113] After determining group 1, the controller matches the addresses contained in group 1, which are stored in SRAM2. Therefore, multiple addresses in group 1 in SRAM2 are matched with address 1 to obtain address 2. Further, address 2 is mapped to SRAM1, and metadata 1 is obtained from SRAM1.

[0114] Step 704. The controller obtains the list of sharers in group 1 from SRAM2.

[0115] After determining address 2 within group 1, the sharer list 1 is obtained based on the cache line containing address 2. The cache line containing address 2 is located in SRAM2. SRAM1 and SRAM2 can be accessed independently.

[0116] Step 705. The controller updates the sharer list 1.

[0117] The controller updates the sharer list 1 based on request 1, including obtaining the sharing status related to address 1 from the sharer list, and based on the operation of request 1 and the sharing status in the sharer list, determining whether to perform an invalidation operation or add a new sharer, and respectively removing the invalidated sharer record or adding a new sharer.

[0118] Step 706. The controller writes the updated sharer list 1 to SRAM 2.

[0119] After updating sharer list 1, the updated sharer list 1 is written according to the cache line corresponding to address 2. At this point, maintaining cache consistency is complete, and data in main memory can be accessed subsequently.

[0120] Step 707. Determine the target data bits of data 1 based on metadata 1.

[0121] Metadata 1 indicates the compression status of data 1 in main memory. Metadata 1 contains a flag indicating whether the data is compressed. A flag of 1 indicates that the data has been compressed. A flag of 0 indicates that the data has not been compressed. If Metadata 1 indicates that data 1 is not compressed, the controller accesses the target data bit according to the structure of uncompressed data. When accessing uncompressed data, the target data bit directly points to the original data block in main memory without decompression. If Metadata 1 indicates that the data has been compressed, the target data bit is accessed according to the structure of compressed data, and the target data bit points to the compressed data block. Address 1 is a logical address in main memory, and the memory row where the data block is located can be determined based on address 1. The controller calculates the target data bit based on the memory row and the size of the data block. A memory row is a storage unit in main memory, which can be 64 bytes, 128 bytes, or larger.

[0122] Step 708. The controller accesses main memory based on request 1 and the target data bits.

[0123] If request 1 is a read request, the target data bits are read. If data 1 is compressed, it needs to be decompressed. If request 1 is a write request, the target data bits are read first. If data 1 is compressed, it is decompressed, modified, and then compressed again. If compression is successful, the compressed data is rewritten to the lower data bits of main memory. If compression fails, the original data size is written to the corresponding data bits in main memory. After accessing main memory, the metadata 2 corresponding to data 1 in main memory may change, for example, from compressed to uncompressed. In this case, metadata 2 is updated to the latest compression / uncompressed state.

[0124] Step 709. Processor 2 sends a request 2 to the controller to access data 2, and the controller receives the request 2 accordingly.

[0125] While the controller is processing request 1 from processor 1, processor 2 may issue request 2 at any time to access data 2 in main memory. In this case, the controller will process them in parallel. In the example shown in Figure 7, processor 2 issues request 2 before the controller updates metadata 2. At this time, the controller receives request 2 and begins processing request 2.

[0126] Step 710. Using address 3 in request 2, determine the list 2 of sharers that match address 3.

[0127] The controller can search for a matching address 4 in multiple addresses of SRAM2 based on address 3, and use the list of sharers corresponding to address 4 as sharer list 2.

[0128] Step 711. Update the list of sharers 2.

[0129] The process of updating the sharer list 2 mainly includes updating the status of the sharers corresponding to address 3, such as adding new sharers or removing existing sharers.

[0130] Step 712. Update metadata 1.

[0131] Replace metadata 1 at address 2 with metadata 2 to complete the update of metadata 1.

[0132] Step 713. Write the updated list of sharers 2 to SRAM2.

[0133] Since steps 712 and 713 access SRAM1 and SRAM2 respectively, the access between different SRAMs does not interfere with each other, so they can be executed simultaneously. For the entire directory cache, multiple different pieces of information can be accessed at the same time, which improves the access bandwidth of the directory cache.

[0134] By using the above method, multiple requests can be processed and accessed in parallel, thereby improving the chip's data access bandwidth.

[0135] As shown in Figure 8, this embodiment of the application provides a chip 800, which includes a processor 801 and a directory structure 802. The directory structure 802 includes a controller 8021 connected to the processor 801 and a directory cache 8022 connected to the controller 8021. The processor 801 is used to issue a first request, which is a read request or a write request for first data. The directory cache 8022 is used to store a second address and first metadata of the first data, the first metadata indicating whether the first data is in a compressed state. The controller 8021 is used to determine the second address and the first metadata from the directory cache 8022 based on the first address in the first request, determine the target data bit according to the second address and the first metadata, and access the first data according to the target data bit. The first address indicates the logical address of the first data in the main memory of the chip 800, and the second address indicates the physical address of the first data in the main memory of the chip 800.

[0136] Processor 801 is a component used for executing instructions and performing operations. Processor 801 can issue read or write requests to access data in main memory (which can be located externally to the chip and connected to controller 8021). Read requests are used to retrieve data from main memory, while write requests are used to update data in main memory. Processor 801 sends requests to controller 8021 via a bus. Processor 801 can be a multi-core processor, which includes multiple cores and corresponding caches, called processor caches. Processor caches can include multiple levels of cache, such as Level 1, Level 2, and Level 3 caches. The access speed of Level 1, Level 2, and Level 3 caches decreases sequentially, while their storage capacity increases sequentially. Multiple Level 1 caches can be configured, each connected to one core and accessed independently by that core. Level 2 caches can be exclusively used by each core or shared by all cores, while Level 3 caches are shared by all cores. Each core can store the same data in its dedicated cache. Here, "same data" refers to data corresponding to the same main memory address. The data stored in the processor cache is actually a copy of the data in main memory, corresponding to the address of the data in main memory. When multiple cores store data at the same address in their respective caches, different cores may perform different operations on the data at the same address, potentially writing different values ​​and causing inconsistency. To maintain the consistency of data at the same address in the processor cache, the processor 801 can access the data in the processor cache under the management of the directory structure 802, thus maintaining cache consistency.

[0137] The directory structure 802 maintains the cache coherency of the processor 801 through the controller 8021 and the directory cache 8022. There can be one or more controllers 8021. If the processor 801 has a large number of cores, multiple controllers 8021 can be configured to communicate with the cores.

[0138] The controller 8021 can control the processor 801's access to the processor cache based on requests from the processor 801, and maintain the state information in the directory cache 8022 used to achieve cache coherency. The controller 8021 can also parse requests from the processor 801 and access data in main memory. The directory cache 8022 is a cache used to store directory entries. Directory entries can be updated under the control of the controller 8021. Directory entries contain addresses, a list of sharers, and metadata. The address indicates which location in main memory the directory entry corresponds to; the sharer list indicates the sharing status of the data at that address by the processor 801; and the metadata indicates whether the main memory data corresponding to that address is in a compressed state. The address of the directory entry includes a second address, which indicates the physical storage location in the first data main memory and maps to the logical address (first address). This allows the controller 8021 of the directory structure 802 to obtain the first metadata corresponding to the second address while maintaining cache consistency using the second address, and access the main memory based on the first metadata. This eliminates the need for separate storage space for the address corresponding to the first metadata, and enables the maintenance of cache consistency and the acquisition of the first metadata to be processed synchronously. This results in high parallelism, high processing efficiency of the chip 800, and low processing latency.

[0139] As shown in Figure 9, chip 900 includes a processor 901, a controller 902, a directory cache 903, and a compression unit 904. Controller 902 is connected to processor 901, directory cache 903, and compression unit 904. Compression unit 904 is used for compression and decompression. When chip 900 writes data to its connected main memory, compression unit 904 can compress the data and write the compressed data to main memory. When retrieving the compressed data from main memory, compression unit 904 can decompress the compressed data. Thus, the data processed by processor 901 is uncompressed data, and it can process data according to the uncompressed data. After setting up compression unit 904, although the read / write speed of main memory is not improved, processor 901 can access more data at the same time, and the bandwidth of processor 901 accessing main memory is improved, thereby improving the bandwidth of chip 900 accessing main memory.

[0140] Since the data length is reduced after compression by the compression unit 904, while the data length before compression is relatively large, whether the data is compressed or not affects the data bits accessed in main memory. Therefore, when accessing data in main memory, the controller 902 needs to determine the target data bit in main memory based on the first metadata obtained from the directory cache 903 and the first request issued by the processor 901, and access the main memory at the target data bit. Specifically, if the first metadata indicates that the first data is in a compressed state, the target data bit is a data bit of the first length in the memory row indicated by the second address; if the first metadata indicates that the first data is not in a compressed state, the target data bit is a data bit of the second length in the memory row indicated by the second address; wherein, the first length is less than the second length. After determining the target data bit, the first data is accessed in conjunction with the first request and the target data bit. Specifically, if the first request is a write request, the first data of the target data bit is modified, and the second metadata in the main memory is configured according to whether the modified first data can be compressed. The second metadata is used to indicate whether the first data is in a compressed state after being accessed. If the first request is a read request, the first data of the target data bit is read, and the second metadata is configured to indicate whether the first data is currently compressed.

[0141] Directory cache 903 is also used to store a first sharer list, which indicates the status of processors 901 sharing the first data. Controller 902 is also used to update the first sharer list. If the updated first sharer list indicates that at least one processor 901 is sharing the first data, then the first metadata in directory cache 903 is updated based on whether the first data is in a compressed state after being accessed; if the updated first sharer list indicates that no processor 901 is sharing the first data, then the first metadata in directory cache 903 is not updated. Directory cache 903 has multiple groups, including a first group. Each group includes multiple cache lines. The first group includes a target cache line that matches a first address. Based on the first address in the first request, a second address and the first metadata of the first data are determined from directory cache 903, including: determining the first group among the multiple groups of directory cache 903 based on the group index of the first address; and determining the second address and the first metadata within the first group.

[0142] As shown in Figure 10, assuming that without a compression unit, the main memory can provide access to at most n data at the same time, after setting up a compression unit, the compression unit can compress the data size to half of the original data, i.e., 0.5n. Then, when the processor accesses 2n data in the main memory, the compression unit can compress the 2n data into two 0.5n data. At this time, the main memory still provides access to n data, but the processor actually accesses 2n data at the same time. For the processor, the access bandwidth of the main memory is increased, thereby increasing the main memory access bandwidth.

[0143] As shown in Figure 11, chip 1100 includes a processor 1101, a controller 1102, a directory cache 1103, and a compression unit 1104. The controller 1102 is connected to the processor 1101, the directory cache 1103, and the compression unit 1104. The directory cache 1103 includes a first SRAM (11031) and a second SRAM (11032). A basic storage cell of the SRAM includes six or more transistors. Taking six transistors as an example, four transistors can form two cross-coupled inverters for storing data (0 or 1), and the other two transistors are used to access data. A basic cell can store 0 or 1. The first SRAM and the second SRAM can each have independent address lines and independent data lines. The address lines are used to receive independent access addresses, and the data lines are used to transmit data.

[0144] The first SRAM (11031) is used to store multiple metadata, including the first metadata. The second SRAM (11032) is used to store multiple addresses and multiple lists of sharers, with each address corresponding to one list of sharers. The multiple addresses include the second address, and the multiple lists of sharers include the first list of sharers. The first SRAM (11031) and the second SRAM (11032) can be accessed independently. After accessing main memory based on the first request and the first metadata, the controller 1102 updates the first metadata in the first SRAM (11031) based on whether the accessed first data is in a compressed state. The controller 1102 may receive multiple requests within a period of time, including the first request and the second request. While accessing the first data based on the first request, the controller 1102 can also be used to access the second data based on the second request. Maintaining cache consistency is also involved in accessing the second data based on the second request. This requires updating the second sharer list corresponding to the second data. This process includes: determining the second sharer list from the second SRAM (11032) based on the second request; where the second request is either a read request or a write request for the second data, and the second sharer list records the state of the second data being shared by the chip's processor 1101; parsing the second request and the second sharer list to obtain a parsing result; and updating the second sharer list if the parsing result indicates a change in the state of the second data being shared by the processor 1101. In this way, the first SRAM (11031) and the second SRAM (11032) can be accessed in parallel, simultaneously reading and writing data in both the first and second SRAMs, such as updating metadata and the sharer list respectively, thereby improving the overall access bandwidth of the directory cache 1103.

[0145] As shown in Figure 12, the first SRAM of the directory cache includes multiple cache lines, each storing multiple metadata. The second SRAM of the directory cache also contains multiple cache lines, each including an address and a list of sharers. Since the first and second SRAMs can be accessed independently, updating the first metadata in the first SRAM and updating the second sharer list in the second SRAM do not result in access conflicts, thus improving the access bandwidth of the directory cache.

[0146] As shown in Figure 13, chip 1300 includes processor 1301, controller 1302, directory cache 1303, and compression unit 1304. Controller 1302 is connected to processor 1301, directory cache 1303, and compression unit 1304. Directory cache 1303 includes a first SRAM (13031) and a second SRAM (13032). The first SRAM (13031) includes a first bank and a second bank. The first SRAM (13031) includes multiple banks, each bank being a partition for independent access. The first bank includes multiple cache lines, and the multiple cache lines include the first cache line, which is used to store first metadata. When dividing the banks, the storage array of the first SRAM can be divided into multiple independent regions, each region being a bank. Each bank can be configured with independent address decoding logic and read / write circuits, and each bank can be configured with independent data lines and control signals. Controller 1302 is also used to: read the first cache line, which includes multiple metadata, replace the first metadata in the multiple metadata with the second metadata, and write the replaced metadata into the first cache line.

[0147] As shown in Figure 14, the first bank and second bank of the first SRAM each contain multiple different cache lines, and each cache line stores multiple metadata. Since each bank can be accessed independently, while updating the first metadata in the first bank, the third metadata in the second bank can also be read. The third metadata indicates whether the second data is in a compressed state. Before accessing the second data, the controller needs to read the third metadata to determine if the second data is compressed, and then access the corresponding data bits. In this way, multiple metadata can be accessed simultaneously, improving the access bandwidth of the first SRAM.

[0148] As shown in Figure 15, this application embodiment provides a data access device 1500, including a chip 1501 and main memory 1502 connected to the chip 1501. The chip 1501 can be the chip involved in the above embodiments, such as the chip shown in Figures 1, 8, 9, 11, or 12. The chip 1501 is used to implement the data access method involved in the above embodiments. This data processing device can be a circuit board containing the chip 1501 and main memory 1502, or any other computer device, such as a server, terminal device, etc.

[0149] When a server's processor accesses a large amount of data in main memory, the chip can utilize metadata stored in the directory cache to determine if the data to be accessed is compressed. If compressed, fewer data bits need to be accessed, allowing access to more data within a given main memory access speed, thus increasing bandwidth. Furthermore, metadata is retrieved using existing addresses in the directory cache, eliminating the need for additional address storage. This saves storage resources that can be used to store other important data, such as encrypted information. Additionally, omitting duplicate addresses reduces chip size and contributes to miniaturization. Simultaneously, the server chip retrieves metadata while maintaining cache consistency. Since the directory structure controller can synchronously retrieve metadata, latency caused by waiting for cache consistency maintenance is reduced, improving server data processing efficiency and making it suitable for large-scale data processing scenarios.

[0150] The processor mentioned above is a general-purpose central processing unit, a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits used to access main memory data.

[0151] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. However, these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

A data access method, characterized in that, The method is applied to a controller of a directory structure, the directory structure further including a directory cache, the directory structure being integrated into a chip, and the method comprising: Based on the first address in the first request, a second address and first metadata of the first data are determined from the directory cache; wherein, the first request is a read request or a write request for the first data, the first address is used to indicate the logical address of the first data in the main memory connected to the chip, the second address is used to indicate the physical address of the first data in the main memory, and the first metadata is used to indicate whether the first data is in a compressed state. The target data bit is determined based on the second address and the first metadata; wherein the target data bit is used to indicate the data bit of the first data in the memory row indicated by the second address; Access the first data based on the target data bits. The method according to claim 1, characterized in that, Accessing the first data based on the target data bit includes: If the first request is a write request, then the first data of the target data bit is modified, and the second metadata in the main memory is configured according to whether the modified first data can be compressed; wherein, the second metadata is used to indicate whether the first data is in a compressed state after being accessed; If the first request is a read request, then the first data of the target data bit is read, and the second metadata is configured to indicate whether the first data is currently compressed. The method according to claim 2, characterized in that, The directory cache includes multiple static random access memories (SRAMs), the multiple SRAMs including a first SRAM used to store the first metadata, and the method further includes: Based on whether the first data is in a compressed state after being accessed, the first metadata in the first SRAM is updated; wherein the updated first metadata is the same as the second metadata. The method according to claim 3, characterized in that, The chip further includes a processor connected to the controller, and the directory cache is further used to store a first sharer list, the first sharer list being used to indicate the state of the processor sharing the first data. The method further includes: Update the first list of sharers; If the updated first sharer list indicates that at least one processor is sharing the first data, then the first metadata in the first SRAM is updated based on whether the first data is in a compressed state after being accessed; If the updated list of first sharers indicates that no processor is sharing the first data, then the first metadata is not updated. The method according to any one of claims 3 or 4, characterized in that, The first metadata is stored in a first cache line, which is contained in multiple cache lines of a first storage partition bank. The first bank is contained in multiple banks of the first SRAM, and each bank is a partition for independent access. The step of updating the first metadata in the first SRAM based on whether the first data is in a compressed state after being accessed includes: Read the first cache line; wherein the first cache line includes multiple metadata; Based on whether the first data is in a compressed state after being accessed, update the first metadata among the plurality of metadata; Write the updated metadata to the first cache line. The method according to any one of claims 3-5, characterized in that, The plurality of SRAMs further includes a second SRAM, which can be accessed independently of the first SRAM, and the method further includes: Based on the second request, a second sharer list is determined from the second SRAM; wherein the second request is a read request or a write request for the second data, and the second sharer list is used to record the status of the second data being shared by the processor of the chip; Parse the second request and the second list of sharers to obtain the parsing result; If the parsing result indicates a change in the state of the second data being shared by the processor, then the second sharer list is updated. The method according to any one of claims 1-6, characterized in that, The directory cache has multiple groups, including a first group. Each group includes multiple cache lines. The first group includes a target cache line that matches the first address. Determining the first metadata of the second address and the first data from the directory cache based on the first address in the first request includes: Based on the group index of the first address, the first group is determined among the multiple groups in the directory cache; Within the first group, the second address and the first metadata are determined. The method according to any one of claims 1-7, characterized in that, Determining the target data bits based on the second address and the first metadata includes: If the first metadata indicates that the first data is in a compressed state, then the target data bit is the first length of data bits in the memory row indicated by the second address; If the first metadata indicates that the first data is not in a compressed state, then the target data bit is the second length of data bits in the memory row indicated by the second address; Wherein, the first length is less than the second length. A chip characterized in that, include: A processor, the processor being configured to issue a first request; wherein the first request is a read request or a write request for first data; A directory structure, comprising a directory cache and a controller connected to the directory cache, the controller being connected to the processor; wherein: The directory cache is used to store the second address and the first metadata of the first data, and the first metadata is used to indicate whether the first data is in a compressed state. The controller is configured to determine the second address and the first metadata from the directory cache based on the first address in the first request, determine the target data bit according to the second address and the first metadata, and access the first data according to the target data bit. The first address is used to indicate the logical address of the first data in the main memory of the chip, and the second address is used to indicate the physical address of the first data in the main memory of the chip. The chip according to claim 9 is characterized in that, The directory caches multiple SRAMs, including a first SRAM used to store the first metadata. The controller is further configured to: update the first metadata in the first SRAM based on whether the first data is in a compressed state after being accessed. The chip according to claim 10 is characterized in that, The first SRAM includes multiple banks, each bank being a partition for independent access. The multiple banks include a first bank, and the first bank includes multiple cache lines, the multiple cache lines including a first cache line, which is used to store the first metadata. The controller is further configured to: read the first cache line, the first cache line including multiple metadata, update the multiple metadata based on whether the first data is in a compressed state after being accessed, and write the updated multiple metadata into the first cache line. The chip according to claim 10 or 11 is characterized in that, The plurality of SRAMs also includes a second SRAM, which can be accessed independently of the first SRAM; The controller is further configured to: determine a second sharer list from the second SRAM based on a second request, wherein the second request is a read request or a write request for the second data, the second sharer list is used to record the state in which the second data is shared by the processor, parse the second request and the second sharer list to obtain a parsing result, and update the second sharer list if the parsing result indicates that the state in which the second data is shared by the processor has changed. The chip according to any one of claims 9-12 is characterized in that, The directory cache has multiple groups, including a first group, each group including multiple cache lines, the first group including a target cache line, the target cache line matching the first address; The controller is further configured to: determine the first group among multiple groups in the directory cache based on the group index of the first address, and within the first group, determine the second address and the first metadata. A data access device, characterized in that, The chip includes any one of claims 9-13, wherein the chip, when in operation, implements the method of any one of claims 1-8.

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