Method and apparatus for determining page scheduling strategy, and device
By comparing the row address of the DRAM memory bank with the historical access row address, a suitable page scheduling strategy is selected, which solves the problem of high DRAM memory access latency, realizes the collaborative work of the processor and memory, and improves system performance.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- BEIJING VCORE TECH CO LTD
- Filing Date
- 2025-12-29
- Publication Date
- 2026-07-23
AI Technical Summary
In the existing technology, how to select a suitable DRAM page scheduling strategy to reduce memory access latency is an urgent problem to be solved.
By comparing the address of the memory cell to be accessed with the address of the historical accessed cell, the DRAM page scheduling strategy, including the page open strategy and the page close strategy, is determined and selected according to the processor's request, so as to realize the coordinated work of the processor and memory.
It enables accurate determination of page scheduling strategies in different scenarios, reduces memory access latency, and improves the overall performance of the processor.
Smart Images
Figure CN2025146867_23072026_PF_FP_ABST
Abstract
Description
Methods, apparatus and equipment for determining page scheduling strategies Cross-references to related applications
[0001] This application is based on and claims priority to Chinese Patent Application No. 202510059849.4, filed on January 15, 2025, the entire contents of which are incorporated herein by reference. Technical Field
[0002] This disclosure relates to the field of computer technology, and in particular to a method, apparatus, and device for determining a page scheduling strategy. Background Technology
[0003] DRAM (Dynamic Random Access Memory) plays a crucial role in computer systems, primarily used to store temporary data and programs, supporting rapid data processing and operation of the system.
[0004] In related technologies, DRAM supports page scheduling strategies including open-page mode and closed-page mode. How to select a suitable page scheduling strategy to reduce memory access latency during data access is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention
[0005] This disclosure provides a method, apparatus, and device for determining a page scheduling strategy. The method selects a memory page scheduling strategy based on the request to be issued by the processor, enabling the processor and memory to work together. Compared with existing methods of randomly selecting page scheduling strategies or using fixed page scheduling strategies, this method achieves accurate determination of page scheduling strategies in different scenarios.
[0006] This disclosure provides a method for determining a page scheduling strategy, including the following steps.
[0007] The row address of the memory cell to be accessed in the target queue is compared with the historical access row address of the memory cell to obtain the comparison result; the historical access row address is the row address corresponding to the most recent access of the memory cell before the current time.
[0008] Based on the comparison results, the memory page scheduling strategy corresponding to the storage body is determined.
[0009] According to the method for determining a page scheduling strategy provided in this disclosure, the step of determining the memory page scheduling strategy corresponding to the memory bank based on the comparison result includes:
[0010] If the row address of the storage entity to be accessed is the same as the historical access row address of the storage entity, the memory page scheduling policy corresponding to the storage entity is determined to be the page open policy.
[0011] If the row address of the storage entity to be accessed is different from the historical access row address of the storage entity, the memory page scheduling policy corresponding to the storage entity is determined to be the page closing policy.
[0012] According to the method for determining a page scheduling strategy provided in this disclosure, before comparing the row address of the memory cell to be accessed in the target queue with the historical access row address of the memory cell, the method further includes:
[0013] When the row address of the memory to be accessed is included in multiple queues, the target queue is determined from the multiple queues according to their priorities; the target queue is the queue with the highest priority among the multiple queues.
[0014] According to the page scheduling strategy determination method provided in this disclosure, when the plurality of queues include a deterministic request queue and a predictive request queue, the priority of the deterministic request queue is higher than the priority of the predictive request queue; when the plurality of queues include a read request queue and a write request queue, the priority of the read request queue is higher than the priority of the write request queue.
[0015] According to the page scheduling strategy determination method provided in this disclosure, when the plurality of queues include at least two of a memory access failure queue, a prefetch queue, and a write-back queue, the priority of the memory access failure queue is higher than the priority of the write-back queue; the priority of the write-back queue is higher than the priority of the prefetch queue.
[0016] According to the method for determining a page scheduling policy provided in this disclosure, after determining the memory page scheduling policy corresponding to the memory bank, the method further includes:
[0017] The row addresses of the multiple storage banks to be accessed and the memory page scheduling policies corresponding to the multiple storage banks are sent to the memory controller; the memory controller is used to determine whether to send the row addresses of the multiple storage banks to be accessed to the memory device first, based on the memory page scheduling policies corresponding to each storage bank.
[0018] According to the method for determining a page scheduling strategy provided in this disclosure, an access history table is maintained for each storage bank in the memory device; the access history table is used to record the row address corresponding to the most recent access of each storage bank before the current time.
[0019] According to the method for determining a page scheduling strategy provided in this disclosure, when it is determined that there are no unprocessed requests in the target memory, the memory page scheduling strategy corresponding to the target memory is dynamically adjusted; the target memory is any memory device.
[0020] This disclosure also provides a device for determining a page scheduling strategy, comprising the following modules:
[0021] The processing module is used to compare the row address of the storage body to be accessed in the target queue with the historical access row address of the storage body, and obtain the comparison result; the historical access row address is the row address corresponding to the most recent access of the storage body before the current time.
[0022] The determination module is used to determine the memory page scheduling strategy corresponding to the storage bank based on the comparison result.
[0023] This disclosure also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement a method for determining a page scheduling strategy as described above.
[0024] This disclosure also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method for determining the page scheduling strategy as described above.
[0025] This disclosure also provides a computer program product, including a computer program that, when executed by a processor, implements a method for determining a page scheduling strategy as described above.
[0026] The method, apparatus, and device for determining the page scheduling policy disclosed herein determine the memory page scheduling policy corresponding to the memory bank based on the comparison result between the row address of the memory bank to be accessed and the historical access row address of the memory bank; that is, the memory page scheduling policy is selected according to the request to be issued by the processor, realizing the collaborative work of the processor and memory. Compared with the existing random selection of page scheduling policy or fixed page scheduling policy, it realizes the accurate determination of page scheduling policy under different scenarios. Attached Figure Description
[0027] To more clearly illustrate the technical solutions in this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0028] Figure 1 is a schematic diagram of the memory access process provided in this disclosure.
[0029] Figure 2 is a schematic diagram of the page closing mode provided in this disclosure.
[0030] Figure 3 is a schematic diagram of the page opening mode provided in this disclosure.
[0031] Figure 4 is one of the flowcharts illustrating the method for determining the page scheduling strategy provided in this disclosure.
[0032] Figure 5 is a second flowchart illustrating the method for determining the page scheduling strategy provided in this disclosure.
[0033] Figure 6 is a flowchart of the method for determining the page scheduling strategy provided in this disclosure.
[0034] Figure 7 is a schematic diagram of the device for determining the page scheduling strategy provided in this disclosure.
[0035] Figure 8 is a schematic diagram of the structure of the electronic device provided in this disclosure. Detailed Implementation
[0036] To make the objectives, technical solutions, and advantages of this disclosure clearer, the technical solutions of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.
[0037] The method, apparatus, and equipment for determining the page scheduling strategy of this disclosure are described below with reference to Figures 1-8.
[0038] To facilitate a clearer understanding of the technical solutions of the various embodiments of this application, some technical content related to the various embodiments of this application will be introduced first.
[0039] Rapid advancements in processor architecture technology and continuous improvements in manufacturing processes have led to sustained increases in processor and memory performance. However, these improvements are not proportional; processor performance gains significantly outpace memory performance, greatly exacerbating the conflict between computation and memory access within the processor. The crucial role of improved storage system speed in overall processor system performance enhancement is becoming increasingly prominent. Industry-wide optimization of memory access has been a major driving force behind processor architecture optimization.
[0040] As shown in Figure 1, a DRAM memory cell typically consists of a three-dimensional address space, including bank address, row address, and column address. DRAM access is divided into three phases: Row Access, Column Access (also known as Command Access), and Precharge. DRAM consists of multiple banks, each with a row buffer. The data in the row buffer constitutes a page. When a bank in an idle state receives a row address, it enters the Row Access phase, performs an Activate Row operation (ACT), latches the row address, and reads the row into the Row Buffer. When a bank receives a column address and a command, it enters the Column Access phase, performing a corresponding Read (RD) or Write (WT) operation based on the received command. After the operation is complete, the DRAM enters the Precharge phase, performs a Precharge operation (PRE), and writes the data in the Row Buffer back to the DRAM memory cell. Modern DRAM memory supports page scheduling strategies, including open page mode and closed page mode. In Open Page mode, after the column selection cycle is completed, the page remains in the row active state, meaning the data in the row buffer is not written back to the DRAM memory cell. If subsequent accesses target the same row of the memory bank, row selection cycles for subsequent accesses can be saved. Correspondingly, after the operation is completed, the DRAM is precharged, and the data in the row buffer is written back to the DRAM memory cell; this mode is called Close Page mode.
[0041] As shown in Figure 2, the operation state switching process in Close Page mode is as follows: The memory bank in the idle state first performs a row activation operation (ACT), then a read operation (RD) or a write operation (WT). Taking a read operation as an example, finally, a precharge operation (PRE) is performed, returning to the idle state. Operation latency refers to the clock cycles from the issuance of the row activation command to the return of data, including row selection time (tRCD) and column selection time (CL). CL (CAS*Latency) represents the number of clock cycles from the column selection signal becoming valid to the sampling of the first read request data; CL is typically 2 or 3. tRCD (RAS*to CAS*) represents the number of clock cycles from row selection to column selection; tRCD is typically 2 or 3. tRP (RAS*Precharge) represents the number of clock cycles from precharge to the occurrence of the next row selection transaction; tRP is typically 2 or 3. The specific clock cycle settings for CL, tRCD, and tRP are determined based on the comparison between the system bus clock frequency and the DRAM frequency. In this embodiment, CL, tRCD, and tRP are set to 2, 3, and 2, respectively. The Latency of the Close Page strategy = tRCD + CL = 3 + 2 = 5.
[0042] As shown in Figure 3, in Open Page mode, the page remains in the row active state after the column select cycle is completed. The DRAM access latency differs between Page Hit and Page Miss scenarios (Non-Uniform DRAM Access Latency). The read operation state transition process in Open Page mode is as follows: When accessing a memory bank in the row active state, if the accessed row is the same as an open row in the accessed memory bank (i.e., Page Hit), only a read operation (RD, Read) or a write operation needs to be performed. If the accessed row is different from an open row in the accessed memory bank (i.e., Page Miss), a precharge operation (PRE, Precharge) is performed first, followed by a row activation operation (ACT, Activate Row), and finally a read operation (RD, Read) or a write operation. In the case of a Page Hit, the read operation latency only includes the column select time (CL), i.e., Latency = CL = 2. In the event of a page collision (Miss), the read operation latency consists of three parts: precharge time (tRP), row select time (tRCD), and column select time (CL), i.e., Latency = tRP + tRCD + CL = 2 + 3 + 2 = 7. Therefore, in order to improve memory device performance and reduce system memory access latency, only by adopting a flexible memory page scheduling strategy can the technical advantages provided by memory devices be fully utilized.
[0043] Figure 4 is one of the flowcharts illustrating the method for determining the page scheduling strategy provided in this disclosure. As shown in Figure 4, the method includes the following:
[0044] Step 401: Compare the row address of the memory to be accessed in the target queue with the historical access row address of the memory, and obtain the comparison result; the historical access row address is the row address corresponding to the most recent access of the memory before the current time.
[0045] Specifically, DRAM supports two page scheduling strategies: open page mode and closed page mode. How to select a suitable page scheduling strategy to reduce memory access latency during data access is a technical problem that urgently needs to be solved by those skilled in the art.
[0046] To address the aforementioned issues, this embodiment first compares the row address of the memory bank to be accessed in the target queue with the historical access row address of the memory bank to obtain a comparison result. The historical access row address is the row address corresponding to the most recent access of each memory bank before the current time. For example, this embodiment compares the addresses of all queue entries in the processor cache invalidation queue, prefetch queue, and write-back queue with the row address of the processor's last access to each memory bank in memory to obtain a comparison result. Optionally, the comparison result includes both identical and dissimilar results.
[0047] Step 402: Based on the comparison results, determine the memory page scheduling strategy corresponding to the storage bank.
[0048] Specifically, in this embodiment, after comparing the row address of the memory bank to be accessed in the target queue with the historical access row address of the memory bank and obtaining the comparison result, the memory page scheduling strategy corresponding to the memory bank can be determined based on the comparison result. Optionally, a correspondence between the comparison result and the memory page scheduling strategy can be established in advance. If the comparison result is the same, one page scheduling strategy is adopted; if the comparison result is different, another page scheduling strategy is adopted. That is, in this embodiment, the memory page scheduling strategy corresponding to the memory bank is determined by the actual future memory access requests that the processor will issue and the row address of the most recently accessed memory bank, generating guidance information for the memory page scheduling strategy. In other words, the memory page scheduling strategy is selected according to the request to be issued by the processor, realizing the collaborative work of the processor and memory, reducing the latency of memory access. Compared with the existing random selection of page scheduling strategy or fixed page scheduling strategy, it realizes the accurate determination of page scheduling strategy in different scenarios.
[0049] The method in the above embodiments determines the memory page scheduling strategy corresponding to the memory bank based on the comparison result between the row address of the memory bank to be accessed and the historical access row address of the memory bank; that is, the memory page scheduling strategy is selected according to the request to be issued by the processor, realizing the collaborative work of the processor and memory. Compared with the existing random selection of page scheduling strategy or fixed page scheduling strategy, it realizes the accurate determination of page scheduling strategy in different scenarios.
[0050] In one embodiment, the row address of the memory bank to be accessed in the target queue is compared with the historical access row address of the memory bank to obtain a comparison result; the historical access row address is the row address corresponding to the most recent access of the memory bank before the current time; based on the comparison result, the memory page scheduling policy corresponding to the memory bank is determined, including:
[0051] If the row address of the storage entity to be accessed is the same as the historical access row address of the storage entity, the memory page scheduling policy corresponding to the storage entity is determined to be the page open policy;
[0052] If the row address of the storage entity to be accessed is different from the historical access row address of the storage entity, the memory page scheduling policy corresponding to the storage entity is determined to be the page closing policy.
[0053] Specifically, when the row address of the memory bank to be accessed is the same as the row address of the memory bank's historical accesses, the memory page scheduling policy corresponding to the memory bank is determined to be the page open policy. That is, when the row address of the memory bank to be accessed is the same as the row address of the memory bank's historical accesses, the row corresponding to the current memory access operation has already been activated. Using the page open policy can effectively save the row activation latency (tRCD) and improve memory access performance.
[0054] When the row address of the memory bank to be accessed is different from the historical row address of the memory bank, the memory page scheduling policy corresponding to the memory bank is determined to be the page closing policy. That is, when the row address of the memory bank to be accessed is different from the historical row address of the memory bank, using the page open policy will produce additional latency (tRP) introduced by precharging, which will have a negative impact on memory access performance. Therefore, the page closing policy needs to be selected.
[0055] For example, the addresses of operations to be sent to the memory controller in the processor include: the address of the miss request to be sent to the memory controller for Last Level Cache (LLC) access miss, the prefetch address to be sent to the memory controller, and the address of the processor write-back request to be sent to the memory controller. The address of the miss request to be sent to the memory controller comes from the memory miss queue; the prefetch address to be sent to the memory controller comes from the prefetch queue; and the address of the processor write-back request to be sent to the memory controller comes from the write-back queue. This application compares the addresses of the requests to be sent for all queue entries in the processor's Last Level Cache miss queue, prefetch queue, and write-back queue with the address of the last memory access sent by the processor to each memory bank. For each memory bank, it determines whether there is a page hit. If there is a page hit for a memory bank and a page conflict exists, it instructs the memory bank with such a page conflict to adopt the Close Page mode and provides a page scheduling policy for each memory bank to adopt the Close Page mode.
[0056] In other words, based on the characteristics of DRAM access, for applications with good locality of memory access operations, the Open Page strategy is adopted. If the row corresponding to the current memory access operation is already activated, the memory access latency is only the latency from read command to data transfer. Compared to the Close Page strategy, it saves the latency caused by row activation, which can greatly reduce memory access latency. That is, for applications with good locality of memory access operations, the Open Page strategy makes good use of the locality of accessing the same row, and its memory access efficiency is better than the Close Page strategy. In addition, the Close Page strategy requires a precharge operation after a memory access operation. If the memory controller has unprocessed requests, precharging will affect the processing of subsequent read requests. Therefore, for processors that support multiple access requests issued simultaneously and applications with intensive memory access, the Open Page strategy is superior to the Close Page strategy. However, for applications with poor locality of memory access operations, the Close Page strategy performs a precharge operation after each memory access operation, so the memory access latency consists of row activation and read command latency. For the Open Page strategy, due to page conflicts at the beginning of each memory access operation, the memory access latency consists of precharging, row activation, and read command latency. In other words, for applications with a high probability of page conflicts, using the Close Page mode can actually reduce the precharge latency added to memory access caused by row address conflicts. Therefore, for applications with poor locality of memory access operations, the Close Page strategy is more efficient than the Open Page strategy.
[0057] The method in the above embodiments determines the memory page scheduling policy corresponding to the memory bank as a page open policy when the row address of the memory bank to be accessed is the same as the historical access row address of the memory bank, which can effectively save row activation latency (tRCD); when the row address of the memory bank to be accessed is different from the historical access row address of the memory bank, it determines the memory page scheduling policy corresponding to the memory bank as a page close policy, which can avoid introducing additional latency (tRP). In other words, the memory page scheduling policy is selected according to the request to be issued by the processor, so that the processor and memory work together to achieve accurate determination of the page scheduling policy in different scenarios.
[0058] In one embodiment, before comparing the row address of the memory to be accessed in the target queue with the historical access row address of the memory, the method further includes:
[0059] When multiple queues contain the row address of the memory to be accessed, the target queue is determined from the multiple queues based on their priorities; the target queue is the queue with the highest priority among the multiple queues.
[0060] Specifically, when there are access requests in multiple queues, this embodiment of the application determines the queue with the highest priority as the target queue, so that the access requests in the target queue can be sent to the memory controller for processing first, thus realizing the batch processing of access requests in multiple queues.
[0061] In one embodiment, when multiple queues include at least two of a memory access invalidation queue, a prefetch queue, and a write-back queue, the priority of the multiple queues includes:
[0062] The memory access invalidation queue has a higher priority than the write-back queue;
[0063] The priority of writing back to the queue is higher than that of the prefetch queue.
[0064] Specifically, in this embodiment, when multiple queues include a memory access invalidation queue, a prefetch queue, and a write-back queue, since the memory access invalidation queue and the write-back queue contain requests that are determined to be issued, while the prefetch queue contains requests that are guessed to be issued, this embodiment prioritizes sending access requests from the memory access invalidation queue and the write-back queue to the memory controller for processing. Optionally, if the request in the memory access invalidation queue is a read request, the processor's instructions need to wait for the result of the read request before execution, while the request in the write-back queue is a write request, which only needs to be written back to memory, this embodiment prioritizes sending access requests from the memory access invalidation queue to the memory controller for processing, and then sends access requests from the write-back queue to the memory controller for processing.
[0065] The method described in the above embodiments, by setting the priorities of deterministic requests and predictive requests, as well as read requests and write requests, enables the combination of processor requests and memory page scheduling strategies to function better, reducing memory access latency and improving the overall performance of the processor.
[0066] In one embodiment, after determining the memory page scheduling policy corresponding to the storage bank, the method further includes:
[0067] The row addresses of multiple storage banks to be accessed and the memory page scheduling policies corresponding to the multiple storage banks are sent to the memory controller; the memory controller is used to determine whether to send the row addresses of each storage bank to be accessed to the memory device first, based on the memory page scheduling policies corresponding to each storage bank.
[0068] Specifically, in this embodiment, after sending the row addresses of multiple memory banks to be accessed and the corresponding memory page scheduling policies to the memory controller, the memory controller can control each memory bank to process access requests based on the received memory page scheduling policies. Optionally, if the page scheduling policy of a memory bank is determined to be a page open policy, the corresponding access request is sent first for processing.
[0069] For example, in this embodiment, each queue of the processor no longer selects an access to memory according to a random strategy, but instead prioritizes the entry with the same address as the last access line of the corresponding memory bank in the memory bank access history table and issues an access request. Multiple access requests in the memory controller are also selected according to the page hit priority principle and sent to the DRAM memory device. When sending a request to the memory controller, the processor schedules the request based on the page information that has already been requested.
[0070] In the method of the above embodiments, the processor sends the row addresses of multiple memory banks to be accessed and the memory page scheduling policies corresponding to the multiple memory banks to the memory controller. Then, the memory controller can control each memory bank to process the access request based on the memory page scheduling policy guidance information received for each memory bank, thereby achieving efficient processing of access requests.
[0071] In one embodiment, the method for determining the page scheduling strategy further includes:
[0072] Maintain an access history table for each storage bank in the memory device; the access history table records the row address corresponding to the most recent access to each storage bank before the current time.
[0073] Specifically, in this embodiment, the processor can maintain an access history table for each memory bank, recording the row address of the last memory access for each memory bank. This allows the processor to compare the row address of the memory bank to be accessed in the target queue with the last memory access row address of the memory bank in the access history table, obtain the comparison result, and determine the memory page scheduling strategy corresponding to the memory bank, thus achieving accurate determination of the page scheduling strategy.
[0074] For example, as shown in Figure 5, the processor maintains an access history table for each memory bank, recording the row address of the last memory access for each bank. The processor compares the addresses of the memory entries to be accessed in the memory access miss queue, prefetch queue, and write-back queue with the memory bank addresses and row addresses in the memory bank access history table. If there is no page hit for the corresponding memory bank and a page conflict exists, the processor instructs the corresponding page-conflicting memory bank to adopt a page-closed mode. The processor guides the memory page scheduling strategy based on actual future access requests. Optionally, when sending a request to the memory controller, the processor prioritizes queue entries with the same row address as the last memory access for the corresponding memory bank, including selection from the memory miss queue, prefetch queue, and write-back queue. When the addresses of all entries in the processor's last-level cache miss queue, prefetch queue, and write-back queue are available, the priority is memory miss queue > write-back queue > prefetch queue. Optionally, the number of memory bank access history tables is equal to the number of memory banks in the memory chip. In the DDR SDRAM device used in the embodiments of this disclosure, the number of logical memory banks of each chip is set to n, then there are n memory bank access history tables from 0 to n-1, where n is a positive integer.
[0075] In the method of the above embodiments, the processor can maintain an access history table for each memory bank, record the row address of the last memory access for each memory bank, and thus determine the memory page scheduling policy corresponding to the memory bank based on the last memory access row address of the memory bank in the access history table, thereby achieving accurate determination of the page scheduling policy.
[0076] For example, as shown in Figure 6, the memory controller page scheduling strategy on the memory side is as follows:
[0077] When the memory controller determines that there are unprocessed requests for a corresponding memory bank, it adopts Open Page mode to continue processing subsequent read requests. When the memory controller sends a request to the memory device, it schedules the request based on the memory device's Page status information, prioritizing requests with Page hits. If the memory controller determines that there are no unprocessed requests for a corresponding memory bank, it dynamically adjusts the Page mode. If the processor provides a Close Page mode policy for a memory bank without unprocessed requests, then that memory bank adopts the Close Page policy and undergoes precharging. After each memory bank operation command is completed, the specific operations of memory page scheduling are as follows: After a read or write operation command is completed, it is determined whether the memory controller has determined that the currently accessed memory bank will adopt Close Page mode. If the currently accessed memory bank is determined to adopt Close Page mode, precharging is performed; otherwise, the currently accessed memory bank adopts Open Page mode to continue processing subsequent read requests.
[0078] The memory page scheduling strategy dynamically adjusts the page mode based on processor guidance, combining the advantages of Open Page and Close Page strategies. The memory controller only switches page modes when there are no unprocessed requests, avoiding the impact of precharging on subsequent read request processing. Compared to existing technologies, the method combining processor requests and memory page scheduling strategies has the following advantages: it integrates the advantages of Open Page and Close Page strategies, compares the addresses of memory items to be accessed in the processor's memory access invalidation queue, prefetch queue, and write-back queue with the row addresses in the access history tables of each memory bank, generates guidance information for the memory page scheduling strategy, and schedules requests in each queue based on already issued memory access requests, setting priorities based on deterministic and predictive requests, as well as read and write requests. This allows the method combining processor requests and memory page scheduling strategies to function better, reducing memory access latency and improving overall processor performance.
[0079] The following describes the apparatus for determining the page scheduling strategy provided in this disclosure. The apparatus described below corresponds to the method described above for determining the page scheduling strategy. The apparatus for determining the page scheduling strategy according to an embodiment of this application is shown in Figure 7, and includes:
[0080] The processing module 710 is used to compare the row address of the memory to be accessed in the target queue with the historical access row address of the memory and obtain the comparison result; the historical access row address is the row address corresponding to the most recent access of the memory before the current time.
[0081] The determination module 720 is used to determine the memory page scheduling strategy corresponding to the storage bank based on the comparison results.
[0082] Optionally, the determining module 720 is specifically used for:
[0083] If the row address of the storage entity to be accessed is the same as the historical access row address of the storage entity, the memory page scheduling policy corresponding to the storage entity is determined to be the page open policy;
[0084] If the row address of the storage entity to be accessed is different from the historical access row address of the storage entity, the memory page scheduling policy corresponding to the storage entity is determined to be the page closing policy.
[0085] Optionally, the processing module 710 is further configured to:
[0086] When multiple queues contain the row address of the memory to be accessed, the target queue is determined from the multiple queues based on their priorities; the target queue is the queue with the highest priority among the multiple queues.
[0087] Optionally, the memory access invalidation queue has a higher priority than the write-back queue;
[0088] The priority of writing back to the queue is higher than that of the prefetch queue.
[0089] Optionally, the determining module 720 is further configured to:
[0090] The row addresses of multiple storage banks to be accessed and the memory page scheduling policies corresponding to the multiple storage banks are sent to the memory controller; the memory controller is used to determine whether to send the row addresses of each storage bank to be accessed to the memory device first, based on the memory page scheduling policies corresponding to each storage bank.
[0091] Optionally, the processing module 710 is further configured to:
[0092] Maintain an access history table for each storage bank in the memory device; the access history table records the row address corresponding to the most recent access to each storage bank before the current time.
[0093] Figure 8 illustrates a schematic diagram of the physical structure of an electronic device, which may include: a processor 810, a communication interface 820, a memory 830, and a communication bus 840. The processor 810, communication interface 820, and memory 830 communicate with each other via the communication bus 840. The processor 810 can invoke logical instructions in the memory 830 to execute a method for determining a page scheduling policy. This method includes: comparing the row address of the memory bank to be accessed in the target queue with the historical access row address of the memory bank, and obtaining a comparison result; the historical access row address is the row address corresponding to the most recent access of the memory bank before the current time; and determining the memory page scheduling policy corresponding to the memory bank based on the comparison result.
[0094] Furthermore, the logical instructions in the aforementioned memory 830 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this disclosure, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0095] On the other hand, this disclosure also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the page scheduling strategy determination method provided by the above methods. The method includes: comparing the row address of the memory bank to be accessed in the target queue with the historical access row address of the memory bank, and obtaining a comparison result; the historical access row address is the row address corresponding to the most recent access of the memory bank before the current time; and determining the memory page scheduling strategy corresponding to the memory bank based on the comparison result.
[0096] In another aspect, this disclosure also provides a non-transitory computer-readable storage medium having a computer program stored thereon. When executed by a processor, the computer program implements a method for determining the page scheduling strategy provided by the above methods. The method includes: comparing the row address of a memory bank to be accessed in a target queue with the historical access row address of the memory bank, and obtaining a comparison result; the historical access row address is the row address corresponding to the most recent access of the memory bank before the current time; and determining the memory page scheduling strategy corresponding to the memory bank based on the comparison result.
[0097] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.
[0098] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.
[0099] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure.
Claims
1. A method of determining a page scheduling policy, wherein, The method comprises the following steps: comparing a row address of a memory bank to be accessed in a target queue with a historical access row address of the memory bank, and obtaining a comparison result; the historical access row address is a row address corresponding to a time when the memory bank was last accessed before a current time; determining a memory page scheduling strategy corresponding to the memory bank according to the comparison result.
2. The method of claim 1, wherein, The method further comprises the following steps: in a case where the row address of the memory bank to be accessed and the historical access row address of the memory bank are the same, determining that the memory page scheduling strategy corresponding to the memory bank is a page opening strategy; in a case where the row address of the memory bank to be accessed and the historical access row address of the memory bank are different, determining that the memory page scheduling strategy corresponding to the memory bank is a page closing strategy.
3. The method of claim 1 or 2, wherein, Before the comparison between the row address of the memory bank to be accessed in the target queue and the historical access row address of the memory bank, the method further comprises the following steps: in a case where the row address of the memory bank to be accessed is included in a plurality of queues, determining a target queue from the plurality of queues according to priorities of the plurality of queues; the target queue is a queue with the highest priority among the plurality of queues.
4. The method of claim 3, wherein, in a case where the plurality of queues comprise a deterministic request queue and a predictive request queue, the priority of the deterministic request queue is higher than the priority of the predictive request queue; in a case where the plurality of queues comprise a read request queue and a write request queue, the priority of the read request queue is higher than the priority of the write request queue.
5. The method of claim 3, wherein, in a case where the plurality of queues comprise at least two of a memory access invalidation queue, a prefetch queue and a writeback queue, the priority of the memory access invalidation queue is higher than the priority of the writeback queue; the priority of the writeback queue is higher than the priority of the prefetch queue.
6. The method of claim 5, wherein, After the determination of the memory page scheduling strategy corresponding to the memory bank, the method further comprises the following steps: sending a plurality of row addresses of the memory banks to be accessed and a plurality of memory page scheduling strategies corresponding to the memory banks to a memory controller; the memory controller is configured to determine whether to preferentially send the row addresses of the memory banks to be accessed to a memory device based on the memory page scheduling strategies corresponding to the memory banks.
7. The method of claim 6, wherein, The method further comprises the following steps: maintaining an access history table corresponding to each memory bank in a memory device; the access history table is configured to record a row address corresponding to a time when each memory bank was last accessed before a current time.
8. The method of claim 6, wherein, The method further comprises the following steps: when it is determined that there is no unprocessed request in a target memory bank, dynamically adjusting a memory page scheduling strategy corresponding to the target memory bank; the target memory bank is any memory bank in a memory device.
9. An apparatus for determining a page scheduling policy, wherein, The device comprises: a processing module configured to compare a row address of a memory bank to be accessed in a target queue with a historical access row address of the memory bank, and obtain a comparison result; the historical access row address is a row address corresponding to a time when the memory bank was last accessed before a current time; a determination module configured to determine a memory page scheduling strategy corresponding to the memory bank according to the comparison result.
10. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein, The processor implements the determination method of the page scheduling strategy as claimed in any one of claims 1 to 8 when executing the program.
11. A non-transitory computer readable storage medium having stored thereon a computer program, wherein, The computer program implements the determination method of the page scheduling strategy as claimed in any one of claims 1 to 8 when executed by the processor.