Display substrate and display apparatus

Abstract

Provided are a display substrate and a display apparatus. The display substrate comprises: a base substrate, wherein the base substrate comprises a display area and a non-display area, and the non-display area is located at at least one side of the display area; and a driving circuit layer, which is located on one side of the base substrate, wherein the driving circuit layer comprises a shift register located in the non-display area, the shift register comprises a plurality of cascaded shift register units, and each shift register unit comprises: a first sub-circuit, which is configured to provide a light-emission control signal, and a second sub-circuit, which is configured to provide a second reset control signal; and the driving circuit layer further comprises a first power line, the first power line is configured to provide low-level signals to the shift register units and comprises a first-power first sub-line and a first-power second sub-line, the first sub-circuit is electrically connected to the first-power first sub-line, the second sub-circuit is electrically connected to the first-power second sub-line, and the first-power first sub-line and the first-power second sub-line are arranged independently of each other.

Description

Display substrate and display device Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) have shown great application potential in the display and lighting fields as a novel type of light-emitting device, thus attracting widespread attention from the industry. With the increase in refresh rates of OLED products, shift registers are required to provide higher frequency drive signals, which may cause abnormal level fluctuations in the drive signal during high-low level transitions, affecting the dimming effect.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] In one aspect of this disclosure, a display substrate is provided, comprising:

[0005] A substrate, the substrate including a display area and a non-display area, the non-display area being located on at least one side of the display area; and

[0006] A driving circuit layer, located on one side of the substrate, includes a shift register located in the non-display area. The shift register includes multiple cascaded shift register units, each comprising: a first sub-circuit configured to provide a light emission control signal; and a second sub-circuit configured to provide a second reset control signal.

[0007] The driving circuit layer further includes a first power line configured to provide a low-level signal to the shift register unit.

[0008] The first power line includes a first power first sub-line and a first power second sub-line. The first sub-circuit is electrically connected to the first power first sub-line, and the second sub-circuit is electrically connected to the first power second sub-line. The first power first sub-line and the first power second sub-line are independently configured.

[0009] According to an exemplary embodiment of this disclosure, the non-display area includes a first area and a second area, wherein the first area is located on one side of the display area, and both the first sub-circuit and the second sub-circuit are located in the first area; the second area is located on the side of the first area away from the display area.

[0010] The driving circuit layer further includes: a first conductive layer and a third power line located on the first conductive layer, the third power line comprising a first portion located in the first region and a second portion located in the second region.

[0011] Wherein, in a first direction, the first portion and the second portion are spaced apart, and the first direction is parallel to the direction from the second region to the first region; and

[0012] In the first direction, the orthographic projection of the first power supply first sub-line on the substrate falls into the gap region between the orthographic projections of the first portion and the second portion on the substrate.

[0013] According to an exemplary embodiment of the present disclosure, at least a portion of the first power supply first sub-line is located in the first conductive layer.

[0014] According to an exemplary embodiment of this disclosure, the driving circuit layer further includes a second power line configured to provide a high-level signal to the shift register unit.

[0015] The second power line includes a second power first sub-line and a second power second sub-line. The first sub-circuit is electrically connected to the second power first sub-line, and the second sub-circuit is electrically connected to the second power second sub-line. The second power first sub-line and the second power second sub-line are independently configured.

[0016] According to an exemplary embodiment of this disclosure, both the first power supply first sub-line and the second power supply first sub-line extend along a second direction, which is parallel to the cascading direction of the plurality of shift register units, and intersects the first direction.

[0017] In the first direction, the orthographic projection of the second power supply first sub-line on the substrate falls into the gap region between the orthographic projections of the first portion and the second portion on the substrate.

[0018] According to an exemplary embodiment of the present disclosure, in the first direction, the orthographic projection of the second power supply first sub-line on the substrate falls into the gap region between the orthographic projections of the first power supply first sub-line and the second portion on the substrate.

[0019] According to an exemplary embodiment of the present disclosure, the shift register unit further includes a fourth sub-circuit configured to provide a first scan control signal, the fourth sub-circuit being located in the first region;

[0020] The first power line also includes a first power third sub-line and a first power fourth sub-line, both of which are electrically connected to the fourth sub-circuit.

[0021] The first power supply first sub-line, the first power supply second sub-line, the first power supply third sub-line, and the first power supply fourth sub-line are all independently configured.

[0022] According to an exemplary embodiment of this disclosure, the shift register unit further includes a third sub-circuit configured to provide a first reset control signal, the third sub-circuit being electrically connected to a second sub-line of the first power supply; and / or,

[0023] The shift register unit further includes a fifth sub-circuit configured to provide a second scan control signal, and the fifth sub-circuit is electrically connected to the second sub-line of the first power supply.

[0024] According to an exemplary embodiment of this disclosure, the driving circuit layer further includes a second conductive layer, the second conductive layer being located on the side of the first conductive layer closer to the substrate.

[0025] At least a portion of the first power supply second sub-line, the first power supply third sub-line, and the first power supply fourth sub-line are located in the second conductive layer.

[0026] According to an exemplary embodiment of the present disclosure, the first power line further includes a first power fifth sub-line and a first power sixth sub-line;

[0027] The shift register unit further includes a third sub-circuit, which is configured to provide a first reset control signal and is electrically connected to the fifth sub-line of the first power supply.

[0028] The shift register unit further includes a fifth sub-circuit configured to provide a second scan control signal, and the fifth sub-circuit is electrically connected to the sixth sub-line of the first power supply.

[0029] The first power supply first sub-line, the first power supply second sub-line, the first power supply third sub-line, the first power supply fourth sub-line, the first power supply fifth sub-line, and the first power supply sixth sub-line are all independently configured.

[0030] According to an exemplary embodiment of this disclosure, the first power supply first sub-line includes a third portion located in the first conductive layer and a fourth portion located in the second conductive layer, the third portion and the fourth portion being electrically connected; and / or,

[0031] The first power supply second sub-line includes a fifth portion located in the first conductive layer and a sixth portion located in the second conductive layer, the fifth portion and the sixth portion being electrically connected; and / or,

[0032] The first power supply third sub-line includes a seventh portion located in the first conductive layer and an eighth portion located in the second conductive layer, the seventh portion and the eighth portion being electrically connected; and / or,

[0033] The first power supply fourth sub-line includes a ninth portion located in the first conductive layer and a tenth portion located in the second conductive layer, and the ninth portion and the tenth portion are electrically connected.

[0034] According to an exemplary embodiment of the present disclosure, the first portion includes a plurality of first gaps located in the first region, wherein the orthographic projections of the first power second sub-line, the first power third sub-line, and the first power fourth sub-line on the substrate fall within the orthographic projections of the plurality of first gaps on the substrate.

[0035] According to an exemplary embodiment of the present disclosure, in the first direction, the first sub-circuit is located between the second portion and the display area, the second sub-circuit is located between the first sub-circuit and the display area, the third sub-circuit is located between the second sub-circuit and the display area, the fourth sub-circuit is located between the third sub-circuit and the display area, and the fifth sub-circuit is located between the fourth sub-circuit and the display area;

[0036] The first part includes a first sub-conductive portion, a second sub-conductive portion, a third sub-conductive portion, and a fourth sub-conductive portion that are sequentially moved away from the second part in the first direction;

[0037] The plurality of first gaps includes: a first sub-gap located between the first sub-conductive portion and the second sub-conductive portion; a second sub-gap located between the second sub-conductive portion and the third sub-conductive portion; and a third sub-gap located between the third sub-conductive portion and the fourth sub-conductive portion.

[0038] Wherein, the orthographic projection of the first power supply second sub-line on the substrate falls within the orthographic projection of the first sub-gap on the substrate; the orthographic projection of the first power supply third sub-line on the substrate falls within the orthographic projection of the second sub-gap on the substrate; and the orthographic projection of the first power supply fourth sub-line on the substrate falls within the orthographic projection of the third sub-gap on the substrate.

[0039] According to an exemplary embodiment of the present disclosure, the second power supply second sub-line is located on the side of the first power supply second sub-line away from the display area, and the orthographic projection of the second power supply second sub-line on the substrate falls within the orthographic projection of the first sub-gap on the substrate.

[0040] The second power line also includes a second power third sub-line and a second power fourth sub-line, both of which are electrically connected to the fourth sub-circuit.

[0041] Wherein, the second power supply third sub-line is located on the side of the first power supply third sub-line away from the display area, and the orthographic projection of the second power supply third sub-line on the substrate falls within the orthographic projection of the second sub-gap on the substrate; and

[0042] The second power supply fourth sub-line is located on the side of the first power supply fourth sub-line away from the display area, and the orthographic projection of the second power supply fourth sub-line on the substrate falls within the orthographic projection of the third sub-gap on the substrate.

[0043] According to an exemplary embodiment of the present disclosure, the non-display area further includes a third region located at a corner of the non-display area and on the same side as the first region and the second region. The third power line further includes a connecting portion located in the third region, and the first portion and the second portion are electrically connected through the connecting portion.

[0044] According to an exemplary embodiment of the present disclosure, the connecting portion includes a plurality of protrusions facing the first portion and the second portion, the plurality of protrusions being electrically connected to the second portion, the first sub-conductive portion, the second sub-conductive portion, the third sub-conductive portion and the fourth sub-conductive portion, respectively.

[0045] According to an exemplary embodiment of this disclosure, in the first direction, the distance between the second portion and the second power supply first sub-line is greater than or equal to 4 micrometers; and / or,

[0046] In the first direction, the distance between the first power supply first sub-line and the second power supply first sub-line is greater than or equal to 4 micrometers.

[0047] According to an exemplary embodiment of this disclosure, the voltage of the low-level signal provided by the first power line is in the range of -14V to -7V; and / or,

[0048] The voltage of the signal provided by the third power line is in the range of -4V to -2V.

[0049] In another aspect of this disclosure, a display device is provided, comprising a display substrate as described in any of the preceding claims. Attached Figure Description

[0050] The foregoing contents, as well as other objects, features, and advantages of this disclosure, will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0051] Figure 1 is a plan view of a display substrate according to an embodiment of the present disclosure;

[0052] Figure 2 is an equivalent circuit diagram of the pixel circuit of a single light-emitting element in a display substrate according to an embodiment of the present disclosure;

[0053] Figure 3 is a schematic diagram of the structure of a single shift register unit according to an embodiment of the present disclosure;

[0054] Figure 4 is an equivalent circuit diagram of a first sub-circuit according to an embodiment of the present disclosure;

[0055] Figure 5 is a partial planar schematic diagram of the non-display area of ​​a display substrate according to some exemplary embodiments;

[0056] Figure 6 is a partial planar schematic diagram of the first conductive layer in Figure 5;

[0057] Figure 7 is a partial planar schematic diagram of the combination of the second and third conductive layers in Figure 5;

[0058] Figure 8 is a schematic diagram of the cross section taken along line AA' in Figure 5;

[0059] Figures 9A and 9B are schematic diagrams of the structure of a shift register in the related technology. Figure 9A shows the connection relationship between different sub-circuits and the first power supply line in the shift register, and Figure 9B shows the connection relationship between different sub-circuits and the second power supply line in the shift register.

[0060] Figure 10 is a waveform diagram of the signal in the second sub-line of the first power supply according to some embodiments;

[0061] Figures 11A and 11B are schematic diagrams of the structure of a shift register according to some embodiments of the present disclosure, wherein Figure 11A shows the connection relationship between different sub-circuits and the first power supply line in the shift register, and Figure 11B shows the connection relationship between different sub-circuits and the second power supply line in the shift register.

[0062] Figure 12 is a partial plan view of a combination of multiple film layers in the non-display area of ​​a display substrate according to some embodiments of the present disclosure;

[0063] Figure 13 is a partial planar schematic diagram of the first conductive layer in Figure 12;

[0064] Figures 14A and 14B are schematic diagrams of the structure of a shift register according to some embodiments of the present disclosure, wherein Figure 14A shows the connection relationship between different sub-circuits and the first power supply line in the shift register, and Figure 14B shows the connection relationship between different sub-circuits and the second power supply line in the shift register.

[0065] Figure 15A is a partial plan view of a first power supply first sub-line according to an embodiment of the present disclosure; Figure 15B is a partial plan view of a first power supply second sub-line according to an embodiment of the present disclosure; Figure 15C is a partial plan view of a first power supply third sub-line according to an embodiment of the present disclosure; Figure 15D is a partial plan view of a first power supply fourth sub-line according to an embodiment of the present disclosure.

[0066] Figure 16A is a plan view of a combination of multiple film layers in the corner region of a display substrate according to some embodiments; Figure 16B is a plan view of the first conductive layer in Figure 16A; and

[0067] Figure 17A is a plan view of a combination of multiple film layers in the corner region of a display substrate according to some other embodiments, and Figure 17B is a plan view of the first conductive layer in Figure 17A.

[0068] It should be noted that, for clarity, the dimensions of layers, structures, or regions in the accompanying drawings used to describe embodiments of the present invention may be enlarged or reduced; that is, these drawings are not drawn to actual scale. Detailed Implementation

[0069] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0070] It should be noted that, for clarity and / or descriptive purposes, the dimensions and relative dimensions of components may be enlarged in the accompanying drawings. Therefore, the dimensions and relative dimensions of the individual components are not necessarily limited to those shown in the drawings. In the specification and accompanying drawings, the same or similar reference numerals indicate the same or similar parts.

[0071] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

[0072] In this document, unless otherwise specified, directional terms such as "up," "down," "left," "right," "inner," and "outer" are used to indicate orientation or positional relationships based on the accompanying drawings, and are used only for the convenience of describing this disclosure, and are not intended to indicate or imply that the device, element, or component referred to must have a specific orientation, or be constructed or operated in a specific orientation. It should be understood that when the absolute position of the described object changes, the relative positional relationships they represent may also change accordingly. Therefore, these directional terms should not be construed as limitations on this disclosure.

[0073] In this document, the directional terms "first direction" and "second direction" are used to describe different orientations of the display substrate, such as the row direction and column direction of the display substrate. It should be understood that such representations are merely exemplary descriptions and not limitations of this disclosure.

[0074] In this document, unless otherwise stated, the term "electrical connection" can mean that two components or elements are directly electrically connected, for example, component or element A is in direct contact with component or element B, and an electrical signal can be transmitted between them; it can also mean that two components or elements are electrically connected through a conductive medium, such as a conductive wire, for example, component or element A is electrically connected to component or element B through a conductive wire to transmit an electrical signal between the two components or elements; it can also mean that two components or elements are electrically connected through at least one electronic component, for example, component or element A is electrically connected to component or element B through at least one thin-film transistor to transmit an electrical signal between the two components or elements.

[0075] In this document, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this document, the channel region refers to the region through which current primarily flows. A capacitor is a device that includes at least two terminals: a first plate and a second plate. The first plate of a capacitor can also be referred to as the first terminal of the capacitor, and the second plate can also be referred to as the second terminal of the capacitor.

[0076] In this paper, the control electrode can be the gate electrode, the first electrode can be the drain electrode, and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this paper, the "source electrode" and "drain electrode" can be interchanged.

[0077] In this article, "parallel" refers to the state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore also includes the state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" refers to the state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore also includes the state where the angle is greater than 85° and less than 95°.

[0078] In this article, "film" and "layer" can be interchanged. For example, "conductive layer" can sometimes be replaced with "conductive film". Similarly, "insulating film" can sometimes be replaced with "insulating layer".

[0079] In this paper, "same-layer arrangement" or "located in the same layer" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple structures in a same-layer arrangement may be made of the same material, while the final materials may be the same or different.

[0080] The technical terms used in this disclosure are briefly described below to help those interested in the subject matter better understand this solution.

[0081] DC dimming: Changes screen brightness by directly adjusting voltage or current. It has advantages such as smooth brightness adjustment, accurate color reproduction, and no flicker, making it suitable for users who view screens for extended periods. However, DC dimming may lose color accuracy at high brightness levels and may cause color unevenness at low brightness levels.

[0082] PWM dimming: This method adjusts brightness by rapidly switching the backlight on and off, offering advantages such as significant energy savings and a wide brightness adjustment range. However, PWM dimming may cause flickering at low brightness levels, potentially leading to eye fatigue or discomfort for some users.

[0083] Figure 1 is a plan view of a display substrate according to an embodiment of the present disclosure.

[0084] Exemplary, in an embodiment of this disclosure, a display substrate 1000 is provided. Referring to FIG1, the display substrate 1000 includes a substrate 1, which includes a display area AA and a non-display area NA.

[0085] For example, the non-display area NA is located on at least one side of the display area AA. For instance, the non-display area NA surrounds the display area AA.

[0086] For example, the display substrate 1000 further includes: a plurality of pixels PX, a plurality of drive signal lines DRL, and a shift register GOA. The plurality of pixels PX are located in the display area AA of the display substrate 1000, and the shift register GOA is located in the non-display area NA of the display substrate 1000. The plurality of pixels PX are arranged in an array in the first direction X and the second direction Y to form a multi-row, multi-column pixel array.

[0087] It should be noted that, in this article, the scan driving circuit may include, but is not limited to, gate driving circuit, light emission control scan driving circuit, etc., and the scan driving circuit may include a shift register, which may include multiple cascaded shift register units.

[0088] For example, multiple drive signal lines DRL extend along a first direction X and are spaced apart in a second direction Y. The multiple drive signal lines DRL are electrically connected to multiple pixels PX and a shift register GOA, respectively. The shift register can provide one or more drive signals to the pixels PX through the drive signal lines DRL, thereby driving the pixels to emit light.

[0089] For example, the multiple drive signal lines DRL may include multiple light emission control signal lines, multiple initialization signal lines, and multiple scan control signal lines. For instance, the light emission control signal lines can provide light emission control signals to control the light emission element L to emit light. The initialization signal lines can provide initialization signals to initialize the source or drain voltages of at least a portion of the transistors in the pixel circuit 20. The scan control signal lines can provide scan control signals to control the on / off state of at least a portion of the transistors in the pixel circuit 20.

[0090] For example, the shift register GOA may include multiple cascaded shift register units GOAs. For instance, the multiple shift register units GOAs may include a first-level shift register unit GOA1, a second-level shift register unit GOA2, ..., an Nth-level shift register unit GOAN, where N is the total number of shift register units.

[0091] For example, at least one drive signal line DRL is connected to a plurality of pixels PX in a pixel row, and at least one drive signal line DRL connected to the pixel row is connected to at least one level of shift register unit in shift register GOA, so that a drive signal can be provided to the pixels in the row through the shift register unit, thereby driving the pixels in the row to emit light and display.

[0092] In some embodiments, the shift register GOA can be located in the non-display areas NA on either side of the display area AA. The shift registers GOA on both sides can provide the same gate drive signal, realizing bilateral driving of the pixels. The bilateral driving GOA design can reduce the impact of voltage drop in the gate lines, thereby improving the uniformity of pixel display and enhancing the display effect.

[0093] In some embodiments, the shift register GOA can be located in the non-display area NA on one side of the display area AA, enabling single-sided pixel driving. This single-sided driving GOA design reduces the wiring space occupied by the GOA, which is beneficial for achieving narrower bezels on the display substrate.

[0094] For example, at least one pixel PX may include pixel circuitry 20 and a light-emitting element L. Shift register GOA provides drive signals (e.g., the drive signals may include one or more of a light-emitting control signal, a reset control signal, and a scan control signal) to the transistors in pixel circuitry 20 so that pixel circuitry 20 can drive the light-emitting element L to emit light.

[0095] For example, pixel circuit 20 may include multiple transistors (such as thin-film transistors, TFTs) and at least one capacitor Cst. For instance, pixel circuit 20 may be an "8T1C" circuit, a "7T1C" circuit, a "7T2C" circuit, a "3T1C" circuit, or a "5T1C" circuit, etc., where "T" refers to a thin-film transistor, and the number before "T" indicates the number of thin-film transistors; "C" refers to a capacitor, and the number before "C" indicates the number of capacitors.

[0096] It is understood that the embodiments of this disclosure do not specifically limit the circuit structure of the pixel circuit 20. In the following embodiments of this disclosure, only the pixel circuit is an "8T1C" circuit as an example to illustrate this application.

[0097] Figure 2 is an equivalent circuit diagram of the pixel circuit of a single light-emitting element in a display substrate according to an embodiment of the present disclosure.

[0098] For example, when the pixel circuit 20 is an "8T1C" circuit, referring to FIG2, the pixel circuit 20 may include a first initialization transistor M1, a compensation transistor M2, a driving transistor M3, a data writing transistor M4, a first light-emitting control transistor M5, a second light-emitting control transistor M6, a second initialization transistor M7, a third initialization transistor M8, and a storage capacitor C01.

[0099] The control terminal of the first initialization transistor M1 is electrically connected to the first reset control signal terminal ReP, the first terminal of the first initialization transistor M1 is electrically connected to the initialization signal terminal Vi, and the second terminal of the first initialization transistor M1 is electrically connected to node O1.

[0100] The control electrode of the compensation transistor M2 is electrically connected to the scan control signal terminal Ga, the first electrode of the compensation transistor M2 is electrically connected to node O1, and the second electrode of the compensation transistor M2 is electrically connected to node O3.

[0101] The control electrode of the driving transistor M3 is electrically connected to node O1, the first electrode of the driving transistor M3 is electrically connected to node O2, and the second electrode of the driving transistor M3 is electrically connected to node O3.

[0102] The control electrode of the data writing transistor M4 is electrically connected to the scan control signal terminal Ga, the first electrode of the data writing transistor M4 is electrically connected to node O2, and the second electrode of the data writing transistor M4 is electrically connected to the data signal terminal Vdata.

[0103] The control electrode of the first light-emitting control transistor M5 is electrically connected to the light-emitting control signal terminal EM, the first electrode of the first light-emitting control transistor M5 is electrically connected to the fourth power supply line VDD, and the second electrode of the first light-emitting control transistor M5 is electrically connected to node O2.

[0104] The control electrode of the second light-emitting control transistor M6 is electrically connected to the light-emitting control signal terminal EM, the first electrode of the second light-emitting control transistor M6 is electrically connected to node O3, and the second electrode of the second light-emitting control transistor M6 is electrically connected to node O4.

[0105] The control terminal of the second initialization transistor M7 is electrically connected to the second reset control signal terminal ReH, the first terminal of the second initialization transistor M7 is electrically connected to node O4, and the second terminal of the second initialization transistor M7 is electrically connected to the initialization signal terminal Vi.

[0106] The control terminal of the third initialization transistor M8 is electrically connected to the second reset control signal terminal ReH, the first terminal of the third initialization transistor M8 is electrically connected to node O2, and the second terminal of the third initialization transistor M8 is electrically connected to the initialization signal terminal Vi.

[0107] The first terminal of the storage capacitor C01 is electrically connected to the fourth power line VDD, and the second terminal of the storage capacitor C01 is electrically connected to node O1.

[0108] The first electrode of the light-emitting element L is electrically connected to node O4, and the second electrode of the light-emitting element L is electrically connected to the third power line VSS.

[0109] The scan control signal terminal Ga receives the scan control signal from the shift register GOA, and the light emission control signal terminal EM receives the light emission control signal from the shift register GOA, thereby controlling the on / off state of multiple transistors in the pixel circuit 20. The first reset control signal terminal ReP and the second reset control signal terminal ReH receive the reset control signal from the shift register GOA, thereby controlling the on / off state of at least some transistors (e.g., the first initialization transistor M1, the second initialization transistor M7, and the third initialization transistor M8) in the pixel circuit 20. By controlling the scan control signal, the light emission control signal, and the reset control signal from the shift register GOA, data can be written to the pixel circuit, thereby driving the light-emitting element L to emit light.

[0110] For example, the scan control signal terminal Ga can receive one or more scan control signals to drive the switching on and off of multiple transistors in the pixel circuit 20, respectively. For instance, the scanning control signals can be used to control the switching on and off of the second transistor M2 and the fourth transistor M4, respectively.

[0111] For example, the light emission control signal terminal EM can receive one or more light emission control signals to control the on / off state of multiple transistors in the pixel circuit 20, respectively. For instance, the on / off state of the fifth transistor M5 and the sixth transistor M6 can be controlled by the light emission control signals, respectively.

[0112] For example, the first reset control signal terminal ReP can receive a first reset signal to control the on / off state of the first initialization transistor M1, thereby writing the initialization signal provided by the initialization signal terminal Vi into node O1. For example, the second reset control signal terminal ReH can receive a second reset signal to control the on / off state of the second initialization transistor M7 and the third initialization transistor M8, thereby writing the initialization signal provided by the initialization signal terminal Vi into nodes O2 and O4.

[0113] Figure 3 is a schematic diagram of the structure of a single shift register unit according to an exemplary embodiment of the present disclosure, and Figure 4 is an equivalent circuit diagram of a first sub-circuit according to an embodiment of the present disclosure.

[0114] For example, in an embodiment of this disclosure, referring to Figures 2-4, a shift register unit GOAs may include a first sub-circuit 100, a second sub-circuit 200, a third sub-circuit 300, a fourth sub-circuit 400, and a fifth sub-circuit 500.

[0115] For example, at least one of the first sub-circuit 100, the second sub-circuit 200, the third sub-circuit 300, the fourth sub-circuit 400 and the fifth sub-circuit 500 may include a plurality of transistors (such as thin-film transistors TFTs) and at least one capacitor Cst.

[0116] For example, the circuit structures of the first sub-circuit 100, the second sub-circuit 200, the third sub-circuit 300, the fourth sub-circuit 400, and the fifth sub-circuit 500 may be the same or different.

[0117] For example, the first sub-circuit 100 is configured to provide a light emission control signal em. For instance, the first sub-circuit 100 may be connected to a first power line VGL, a second power line VGH, and a light emission control signal output terminal EM. out Electrical connection. LED control signal output terminal EM out It can be electrically connected to one or more light emission control signal terminals EM in the pixel circuit 20, thereby transmitting the light emission control signal em in the shift register GOA to the pixel circuit 20.

[0118] For example, the first power line VGL is configured to provide a low-level signal to the shift register unit GOAs, and the second power line VGH is configured to provide a high-level signal to the shift register unit GOAs. By adjusting the voltage amplitude and frequency of the signals transmitted in the first power line VGL and the second power line VGH, the output terminal EM of the light emission control signal can be adjusted. out The voltage amplitude and frequency of the output signal.

[0119] In the following embodiments of this disclosure, the first sub-circuit 100 is only taken as an example of a "13T3C" circuit to illustrate this application.

[0120] For example, referring to FIG4, the first sub-circuit 100 may include transistors Z1, Z2, ..., Z13 and capacitors C001, C002, and C003. The first sub-circuit 100 also includes a light emission control signal output terminal EM. out EM light control signal output terminal out It is configured to provide a light emission control signal.

[0121] For example, the first sub-circuit 100 may be electrically connected to the signal input line STV, the first clock signal line Eck, the second clock signal line Ecb, the third clock signal line Ecx, the first power supply line VGL, and the second power supply line VGH.

[0122] The control electrode of transistor Z1 is electrically connected to the first clock signal line Eck, the first electrode of transistor Z1 is electrically connected to the signal input line STV, and the second electrode of transistor Z1 is electrically connected to node N1.

[0123] The control electrode of transistor Z2 is electrically connected to node N1, the first electrode of transistor Z2 is electrically connected to node N2, and the second electrode of transistor Z2 is electrically connected to the first clock signal line Eck.

[0124] The control electrode of transistor Z3 is electrically connected to the first clock signal line Eck, the first electrode of transistor Z3 is electrically connected to the first power supply line VGL, and the second electrode of transistor Z3 is electrically connected to node N2.

[0125] The control electrode of transistor Z4 is electrically connected to node N5, the first electrode of transistor Z4 is electrically connected to node N6, and the second electrode of transistor Z4 is electrically connected to the second clock signal line Ecb.

[0126] The control electrode of transistor Z5 is electrically connected to node N2, the first electrode of transistor Z5 is electrically connected to the second power line VGH, and the second electrode of transistor Z5 is electrically connected to node N6.

[0127] The control electrode of transistor Z6 is electrically connected to node N3, the first electrode of transistor Z6 is electrically connected to the second clock signal line Ecb, and the second electrode of transistor Z6 is electrically connected to node N4.

[0128] The control electrode of transistor Z7 is electrically connected to the second clock signal line Ecb, the first electrode of transistor Z7 is electrically connected to node N4, and the second electrode of transistor Z7 is electrically connected to node N7.

[0129] The control electrode of transistor Z8 is electrically connected to node N1, the first electrode of transistor Z8 is electrically connected to node N7, and the second electrode of transistor Z8 is electrically connected to the second power supply line VGH.

[0130] The control electrode of transistor Z9 is electrically connected to node N7, the first electrode of transistor Z9 is electrically connected to the second power supply line VGH, and the second electrode of transistor Z9 is connected to the light emission control signal output terminal EM. out Electrical connection.

[0131] In some embodiments, by controlling the conduction of transistor Z9, the signal in the second power line VGH can be transmitted to the light emission control signal output terminal EM. out In other words, the output terminal EM of the light emission control signal. out The output light control signal can be adjusted by the signal in the second power line VGH.

[0132] The control electrode of transistor Z10 is electrically connected to node N5, and the first electrode of transistor Z10 is connected to the light emission control signal output terminal EM. out Electrical connection: The second terminal of transistor Z10 is electrically connected to the first power supply line VGL.

[0133] In some embodiments, by controlling the conduction of transistor Z10, the signal in the first power line VGL can be transmitted to the light emission control signal output terminal EM. out In other words, the output terminal EM of the light emission control signal. out The output light control signal can also be adjusted via the signal in the first power line VGL.

[0134] In some embodiments, one of transistors Z9 and Z10 can be selectively turned on while the other is turned off, thereby controlling the output terminal EM of the light emission control signal. out Output a high-level signal or a low-level signal.

[0135] The control electrode of transistor Z11 is electrically connected to the first power line VGL, the first electrode of transistor Z11 is electrically connected to node N2, and the second electrode of transistor Z11 is electrically connected to node N3.

[0136] The control electrode of transistor Z12 is electrically connected to the first power supply line VGL, the first electrode of transistor Z12 is electrically connected to node N1, and the second electrode of transistor Z12 is electrically connected to node N5.

[0137] The control electrode of transistor Z13 is electrically connected to the third clock signal line Ecx, the first electrode of transistor Z13 is electrically connected to the second power supply line VGH, and the second electrode of transistor Z13 is electrically connected to node N1.

[0138] The first plate of capacitor C001 is electrically connected to node N3, and the second plate of capacitor C001 is electrically connected to node N4.

[0139] The first plate of capacitor C002 is electrically connected to node N7, and the second plate of capacitor C001 is electrically connected to the second power line VGH.

[0140] The first plate of capacitor C003 is electrically connected to node N6, and the second plate of capacitor C001 is electrically connected to node N5.

[0141] By controlling multiple signals in the signal input line STV, the first clock signal line Eck, the second clock signal line Ecb, the third clock signal line Ecx, the first power supply line VGL, and the second power supply line VGH, a low-level signal in the first power supply line VGL or a high-level signal in the second power supply line VGH can be written to the light emission control signal output terminal EM. out This allows for the adjustment of the light-emitting control signals in the pixel circuit. The quality of the signals in the first power line VGL and the second power line VGH affects the driving performance of the pixel circuit, and consequently, the display effect of the display substrate.

[0142] Exemplary, referring to Figures 2 and 3, the second sub-circuit 200 is configured to provide a second reset control signal reh. For example, the second sub-circuit 200 may be connected to the first power line VGL, the second power line VGH, and the second reset control signal output terminal ReH. out Electrical connection. Second reset control signal output terminal ReH outIt can be electrically connected to the second reset control signal terminal ReH in the pixel circuit 20, thereby transmitting the second reset control signal reh in the shift register GOA to the pixel circuit 20. The voltage amplitude and frequency of the second reset control signal reh can be adjusted by adjusting the voltage amplitude and frequency of the signals transmitted in the first power line VGL and the second power line VGH.

[0143] For example, the third sub-circuit 300 is configured to provide a first reset control signal rep. For instance, the third sub-circuit 300 may be connected to a first power supply line VGL, a second power supply line VGH, and the first reset control signal output terminal ReP. out Electrical connection. First reset control signal output terminal ReP out It can be electrically connected to the first reset control signal terminal ReP in the pixel circuit 20, thereby transmitting the first reset control signal rep in the shift register GOA to the pixel circuit 20. The voltage amplitude and frequency of the first reset control signal rep can be adjusted by adjusting the voltage amplitude and frequency of the signals transmitted in the first power line VGL and the second power line VGH.

[0144] In some embodiments, the first reset control signal rep and the second reset control signal reh may be the same or different.

[0145] In some embodiments, the pixel circuit 20 is connected to the first reset control signal output terminal ReP out The number of the first reset control signal terminals ReP for electrical connection can be one or more.

[0146] In some embodiments, the pixel circuit 20 is connected to the second reset control signal output terminal ReH out The number of the second reset control signal terminals ReH in the electrical connection can be one or more.

[0147] For example, continuing to refer to Figures 2 and 3, the fourth sub-circuit 400 is configured to provide a first scan control signal ga1. For instance, the fourth sub-circuit 400 may be connected to a first power supply line VGL, a second power supply line VGH, and the first scan control signal output terminal Ga1. out Electrical connection. First scan control signal output terminal Ga1 out It can be electrically connected to one or more scan control signal terminals Ga in the pixel circuit 20, thereby transmitting the first scan control signal ga1 in the shift register GOA to the pixel circuit 20. The voltage amplitude and frequency of the first scan control signal ga1 can be adjusted by adjusting the voltage amplitude and frequency of the signals transmitted in the first power line VGL and the second power line VGH.

[0148] For example, the fifth sub-circuit 500 is configured to provide a second scan control signal ga2. For instance, the fifth sub-circuit 500 may be connected to a first power line VGL, a second power line VGH, and a second scan control signal output terminal Ga2. out Electrical connection. Second scan control signal output terminal Ga2 out It can be electrically connected to one or more scan control signal terminals Ga in the pixel circuit 20, thereby transmitting the second scan control signal ga2 in the shift register GOA to the pixel circuit 20. The voltage amplitude and frequency of the second scan control signal ga2 can be adjusted by adjusting the voltage amplitude and frequency of the signals transmitted in the first power line VGL and the second power line VGH.

[0149] In some embodiments, the first scan control signal ga1 and the second scan control signal ga2 may be the same or different.

[0150] In some embodiments, the pixel circuit 20 is connected to the first scan control signal output terminal Ga1 out The number of scan control signal terminals Ga in the electrical connection can be one or more.

[0151] In some embodiments, the pixel circuit 20 is connected to the second scan control signal output terminal Ga2 out The number of scan control signal terminals Ga in the electrical connection can be one or more.

[0152] For example, a shift register unit GOAs may include a first sub-circuit 100, a second sub-circuit 200, a third sub-circuit 300, a fourth sub-circuit 400, and two fifth sub-circuits 500.

[0153] For example, a shift register unit GOAs can drive two rows of pixels.

[0154] In some embodiments, the first power line VGL may include multiple first power sub-lines for providing low-level signals to one or more of the following sub-circuits: a first sub-circuit 100, a second sub-circuit 200, a third sub-circuit 300, a fourth sub-circuit 400, and a fifth sub-circuit 500.

[0155] In some embodiments, the second power line VGH may include multiple second power sub-lines for providing high-level signals to one or more of the following sub-circuits: a first sub-circuit 100, a second sub-circuit 200, a third sub-circuit 300, a fourth sub-circuit 400, and a fifth sub-circuit 500.

[0156] Figure 5 is a partial plan view of the non-display area of ​​a display substrate according to some exemplary embodiments; Figure 6 is a partial plan view of the first conductive layer in Figure 5; Figure 7 is a partial plan view of the combination of the second and third conductive layers in Figure 5; and Figure 8 is a cross-sectional view taken along line AA' in Figure 5.

[0157] Exemplary, in some embodiments, referring to FIG5, the display substrate includes a non-display area NA located on at least one side of the display area AA. The non-display area NA includes a first region S1 and a second region S2. The first region S1 may be adjacent to the display area AA, and the second region S2 is located on the side of the first region S1 away from the display area AA.

[0158] For example, at least a portion of the shift register GOA is located in the first region S1. For instance, at least a portion of the shift register unit, including the first sub-circuit 100, the second sub-circuit 200, the third sub-circuit 300, the fourth sub-circuit 400, and the fifth sub-circuit 500, may all be located in the first region S1.

[0159] It should be noted that in Figures 5 and 12, the area where the first sub-circuit 100 is located is labeled "ECK" and "ECB", the area where the second sub-circuit 200 is located is labeled "HCK" and "HCB", the area where the third sub-circuit 300 is located is labeled "PCK" and "PCB", the area where the fourth sub-circuit 400 is located is labeled "NCK" and "NCB", and the area where the fifth sub-circuit 500 is located is labeled "GCK" and "GCB".

[0160] For example, the second region S2 can be an edge region close to the border of the display substrate.

[0161] By way of example, referring to Figures 5 and 8, the display substrate may include a substrate 1 and a driving circuit layer 10 located on one side of the substrate 1. The pixel circuit 20 and the shift register GOA may both be located in the driving circuit layer 10.

[0162] For example, the driving circuit layer 10 may include a first semiconductor layer 107, a sixth conductive layer 106, a fifth conductive layer 105, a fourth conductive layer 104, a third conductive layer 103, a second conductive layer 102, and a first conductive layer 101 disposed sequentially away from the substrate 1. The display substrate may also include a plurality of insulating layers located between the plurality of conductive layers.

[0163] For example, the channel layer of the shift register GOA and the multiple transistors in the pixel circuit 20 can be located on the first semiconductor layer 107, the control electrode G of the multiple transistors and the first electrode ED1 of the capacitor can be located on the sixth conductive layer 106, the second electrode ED2 of the capacitor can be located on the fifth conductive layer 105, the source and drain of the transistors can be located on the fourth conductive layer 104, and at least a portion of the source and drain of the transistors can be electrically connected to the conductive transition portion located on the third conductive layer 103.

[0164] For example, the pixel circuit 20 and multiple transistors in the shift register GOA can be formed in the same process step.

[0165] In some embodiments, referring to Figures 2 and 8, a fourth power line VDD may be located in the second conductive layer 102. The fourth power line VDD can be used to provide a high-level signal to the pixel circuit 20. A third power line VSS may be located in the first conductive layer 101. The third power line VSS can be used to provide a low-level signal to the pixel circuit 20.

[0166] For example, referring to FIG7, the first power line VGL may include a plurality of first power sub-lines VGLi located in the third conductive layer 103. The second power line VGH may include a plurality of second power sub-lines VGHi located in the second conductive layer 102.

[0167] For example, referring to FIG6, the third power line VSS may be located in the first conductive layer 101. The third power line VSS may include a first portion VSS1 located in the first region S1 and a second portion VSS2 located in the second region S2.

[0168] In some embodiments, the first part VSS1 and the second part VSS2 can be connected as a whole, which is beneficial to improve the conductivity of the third power line VSS, reduce the voltage drop in the third power line VSS, and improve the voltage uniformity in the third power line VSS.

[0169] For example, the third power line VSS may also include a portion located in the display area AA for electrical connection with the pixel circuitry, thereby providing a low-level signal to multiple light-emitting elements. For example, the portion of the third power line VSS located in the display area AA may employ a grid-like design to further improve the voltage uniformity in the third power line VSS across different regions, thereby enhancing the light emission uniformity of the display substrate.

[0170] For example, the voltage of the signal provided by the third power line VSS is in the range of -4V to -2V.

[0171] For example, referring to FIG6, the first part VSS1 may include multiple openings VH. The multiple openings VH can be used to release the gas generated in the part of the film layer below the first conductive layer 101, avoiding defects such as bubbling or cracking in the large-area conductive layer (e.g., the third power line VSS), which is beneficial to improving the film quality of the first conductive layer 101.

[0172] The second part, VSS2, can be designed as a single surface. Since the second part, VSS2, is located at the edge of the display substrate, this design can improve the flatness of the edge film layer, which is beneficial to enhancing the reliability of the encapsulation layer formed in subsequent processes.

[0173] With the development of display technology, the requirements for display effects of display products are becoming increasingly higher, which in turn places higher demands on the driving signals. For example, when OLED display products use DC dimming or PWM dimming, the frequency of the light emission control signal output by the first sub-circuit 100 increases from 12Hz to 36Hz. This places increasingly higher demands on the speed of level change and voltage stability in the first power line VGL and / or the second power line VGH.

[0174] Figures 9A and 9B are schematic diagrams of the structure of a shift register in the related art. Figure 9A shows the connection relationship between different sub-circuits and the first power supply line in the shift register, and Figure 9B shows the connection relationship between different sub-circuits and the second power supply line in the shift register. Figure 10 is a signal waveform diagram in the second sub-line of the first power supply according to some embodiments.

[0175] In related technologies, the first sub-circuit 100, the second sub-circuit 200, the third sub-circuit 300, and the fifth sub-circuit 500 share the same set of first power supply sub-lines and second power supply sub-lines. For example, referring to Figure 9A, the first sub-circuit 100, the second sub-circuit 200, the third sub-circuit 300, and the fifth sub-circuit 500 are all electrically connected to the first power supply second sub-line VGL2. As another example, referring to Figure 9B, the first sub-circuit 100, the second sub-circuit 200, the third sub-circuit 300, and the fifth sub-circuit 500 are all electrically connected to the second power supply second sub-line VGH2.

[0176] The inventors discovered through research that as the signal frequency in the first and second power supply sub-lines increases, the charging and discharging time of the first and second power supply sub-lines during high-low level switching is shortened. When the first sub-circuit 100, the second sub-circuit 200, the third sub-circuit 300, and the fifth sub-circuit 500 share the same first power supply second sub-line VGL2, the charging and discharging processes of the first power supply second sub-line VGL2 connected to different sub-circuits will interfere with each other, causing low-level fluctuations in the first power supply second sub-line VGL2 during high-low level transitions. For example, in Figure 10, when the signal vg12 in the first power supply second sub-line VGL2 changes from a high level (e.g., v2) to a low level (e.g., v1), the low-level signal exhibits sawtooth fluctuations, resulting in unstable light emission control signals output by the shift register and affecting the dimming effect of the display substrate.

[0177] When the first sub-circuit 100, the second sub-circuit 200, the third sub-circuit 300 and the fifth sub-circuit 500 share the same second power supply second sub-line VGH2, the charging and discharging processes of the second power supply second sub-line VGLH2 connected to different sub-circuits will also interfere with each other, affecting the stability of the shift register output signal, and thus affecting the dimming effect of the display substrate.

[0178] In order to improve the stability of the light emission control signal output by the shift register, some embodiments of this disclosure add a set of independent first power supply first sub-line and second power supply first sub-line electrically connected to the first sub-circuit. This can reduce or even eliminate the interference of the first power supply first sub-line and second power supply first sub-line in other sub-circuits to the first power supply first sub-line and second power supply first sub-line in the first sub-circuit, which is beneficial to improving the stability of the light emission control signal output by the first sub-circuit and thus improving the display effect of the display substrate.

[0179] Figures 11A and 11B are schematic diagrams of the structure of shift registers according to some embodiments of the present disclosure. Figure 11A shows the connection relationship between different sub-circuits and the first power line in the shift register, and Figure 11B shows the connection relationship between different sub-circuits and the second power line in the shift register. Figure 12 is a partial planar schematic diagram of the combination of multiple film layers in the non-display area of ​​a display substrate according to some embodiments of the present disclosure. Figure 13 is a partial planar schematic diagram of the first conductive layer in Figure 12.

[0180] Exemplary, in an embodiment of this disclosure, referring to FIG3 and FIG11A, the shift register unit GOAs includes: a first sub-circuit 100 configured to provide a light emission control signal; and a second sub-circuit 200 configured to provide a second reset control signal.

[0181] The display substrate includes a first power line VGL located on the driving circuit layer. The first power line VGL is configured to provide a low-level signal to the shift register unit. The first power line VGL may include multiple first power sub-lines. The multiple first power sub-lines can provide low-level signals to multiple sub-circuits in the shift register unit GOAs, respectively.

[0182] For example, the voltage of the low-level signal provided by the first power line VGL is in the range of -14V to -7V.

[0183] For example, the first power line VGL may include a first power first sub-line VGL1 and a first power second sub-line VGL2. A first sub-circuit 100 is electrically connected to the first power first sub-line VGL1, and a second sub-circuit 200 is electrically connected to the first power second sub-line VGL2. The first power first sub-line VGL1 and the first power second sub-line VGL2 are independently configured.

[0184] It should be noted that, in the embodiments of this disclosure, the independent configuration of the two power lines means that the signals transmitted in the two power lines come from two different signal sources, and the signals transmitted in the two power lines are independent of each other. For example, "the first sub-line VGL1 and the second sub-line VGL2 of the first power supply are independently configured" means that the signals transmitted by the first sub-line VGL1 and the first sub-line VGL2 of the first power supply come from two different signal sources, and the voltage amplitude and frequency of the signals transmitted by the first sub-line VGL1 and the first sub-line VGL2 of the first power supply can be the same or different.

[0185] This design reduces the likelihood of signals in the first power supply sub-line VGL1 being interfered with by signals in other first power supply sub-lines (such as the second power supply sub-line VGL2), thereby improving the stability of signals in the first power supply sub-line VGL1 and the stability of the light emission control signal output by the shift register, which is beneficial to improving the display effect of the display substrate.

[0186] For example, the display substrate may further include a second power line VGH located in the driving circuit layer. The second power line VGH is configured to provide a high-level signal to the shift register unit. The second power line VGH may include multiple second power sub-lines. The multiple second power sub-lines can provide high-level signals to multiple sub-circuits in the shift register unit GOAs, respectively.

[0187] For example, referring to FIG11B, the second power line VGH includes a second power first sub-line VGH1 and a second power second sub-line VGH2. The first sub-circuit 100 is electrically connected to the second power first sub-line VGH1, and the second sub-circuit 200 is electrically connected to the second power second sub-line VGH2. The second power first sub-line VGH1 and the second power second sub-line VGH2 are independently configured.

[0188] This design reduces the likelihood of signals in the first sub-line VGH1 of the second power supply being interfered with by signals in other second power supply sub-lines (such as the second sub-line VGH2 of the second power supply), thereby improving the stability of signals in the first sub-line VGH1 of the second power supply. This is beneficial for further improving the stability of the light emission control signal output by the shift register and improving the display effect of the display substrate.

[0189] Exemplarily, referring to Figures 11A and 12, the shift register unit further includes a fourth sub-circuit 400, which is configured to provide a first scan control signal. The fourth sub-circuit 400 is located in the first region S1. The first power line VGL also includes a first power third sub-circuit VGL3 and a first power fourth sub-circuit VGL4. Both the first power third sub-circuit VGL3 and the first power fourth sub-circuit VGL4 are electrically connected to the fourth sub-circuit 400.

[0190] In some embodiments, by adjusting the output signals of the third sub-line VGL3 and the fourth sub-line VGL4 of the first power supply, the output signals of the third sub-line VGL3 and the fourth sub-line VGL4 of the first power supply can be superimposed to reduce or even eliminate the step in the output signal and improve the reliability of the output signal.

[0191] For example, the first power supply first sub-line VGL1, the first power supply second sub-line VGL2, the first power supply third sub-line VGL3, and the first power supply fourth sub-line VGL4 are all independently configured. That is, the first power supply first sub-line VGL1, the first power supply second sub-line VGL2, the first power supply third sub-line VGL3, and the first power supply fourth sub-line VGL4 can be connected to four different signal sources respectively.

[0192] This design reduces the likelihood of signal interference among the four power supply sub-lines VGL1, VGL2, VGL3, and VGL4, thereby improving signal stability.

[0193] Since the first scan control signal output by the fourth sub-circuit 400 is related to the signals in the third sub-line VGL3 and the fourth sub-line VGL4 of the first power supply, improving the stability of the signals in the third sub-line VGL3 and the fourth sub-line VGL4 of the first power supply is beneficial to improving the stability of the first scan control signal output by the fourth sub-circuit 400, thereby improving the display effect of the display substrate.

[0194] For example, referring to FIG11B, the second power supply line VGH further includes a second power supply third sub-line VGH3 and a second power supply fourth sub-line VGH4. Both the second power supply third sub-line VGH3 and the second power supply fourth sub-line VGH4 are electrically connected to the fourth sub-circuit 400. In some embodiments, by adjusting the output signals of the second power supply third sub-line VGH3 and the second power supply fourth sub-line VGH4, the output signals of the two power supply third sub-line VGH3 and the second power supply fourth sub-line VGH4 can be superimposed to reduce or even eliminate the step in the output signal, thereby improving the reliability of the output signal.

[0195] For example, the first sub-line VGH1, the second sub-line VGH2, the third sub-line VGH3, and the fourth sub-line VGH4 of the second power supply are all independently configured. That is, the first sub-line VGH1, the second sub-line VGH2, the third sub-line VGH3, and the fourth sub-line VGH4 of the second power supply can be connected to four different signal sources respectively.

[0196] This design reduces the likelihood of signal interference between the first sub-line VGH1, the second sub-line VGH2, the third sub-line VGH3, and the fourth sub-line VGH4 of the second power supply, further improving the stability of the first scan signal output by the fourth sub-circuit 400 and thus enhancing the display effect of the display substrate.

[0197] By way of example, referring to Figures 11A and 11B, the shift register unit may further include a third sub-circuit 300, which is configured to provide a first reset control signal. The third sub-circuit 300 is electrically connected to the first power supply second sub-line VGL2; and / or, the third sub-circuit 300 is electrically connected to the second power supply second sub-line VGH2.

[0198] For example, the shift register unit further includes a fifth sub-circuit 500, which is configured to provide a second scan control signal. The fifth sub-circuit 500 is electrically connected to the first power supply second sub-line VGL2; and / or, the fifth sub-circuit 500 is electrically connected to the second power supply second sub-line VGH2.

[0199] With this design, the second sub-circuit 200, the third sub-circuit 300 and the fifth sub-circuit 500 can share the first power supply second sub-line VGL2 and the second power supply second sub-line VGH2, which can reduce the number of first power supply sub-lines in the first power supply line and save wiring space.

[0200] For example, referring to Figures 12 and 13, the non-display area NA includes a first area S1 and a second area S2. The first area S1 is located on one side of the display area AA (e.g., the first area S1 is located on the left side of the display area AA), and the second area S2 is located on the side of the first area S1 away from the display area AA.

[0201] In some embodiments, the first sub-circuit 100, the second sub-circuit 200, the third sub-circuit 300, the fourth sub-circuit 400, and the fifth sub-circuit 500 may all be located in the first region S1.

[0202] For example, in the first direction X, the second sub-circuit 200 is located between the first sub-circuit 100 and the display area AA, the third sub-circuit 300 is located between the second sub-circuit 200 and the display area AA, the fourth sub-circuit 400 is located between the third sub-circuit 300 and the display area AA, and the fifth sub-circuit 500 is located between the fourth sub-circuit 400 and the display area AA, wherein the first direction X is parallel to the direction from the second region S2 to the first region S1. That is, the first sub-circuit 100, the second sub-circuit 200, the third sub-circuit 300, the fourth sub-circuit 400, and the fifth sub-circuit 500 are arranged sequentially along the direction closest to the display area.

[0203] In some embodiments, at least a portion of the first power line VGL and the second power line VGH may be located on the same layer as the third power line VSS.

[0204] For example, the first power supply first sub-line VGL1, the second power supply first sub-line VGH1, and the third power supply line VSS can all be located in the first conductive layer 101. For instance, the third power supply line VSS includes a first portion VSS1 located in the first region S1 and a second portion VSS2 located in the second region S2. In the first direction X, the first portion VSS1 and the second portion VSS2 are spaced apart.

[0205] For example, in the first direction X, the first sub-circuit 100 is located between the second portion VSS2 and the display area AA. For instance, the first sub-circuit 100 is located between the second portion VSS2 and the second sub-circuit 200.

[0206] For example, in the first direction X, the orthographic projection of the first power supply first sub-line VGL1 on the substrate falls into the gap region F0 between the orthographic projections of the first portion VSS1 and the second portion VSS2 on the substrate.

[0207] With this design, the first power supply first sub-line VGL1 can be placed in the area of ​​the first conductive layer 101 close to the first sub-circuit 100, which facilitates the electrical connection between the first power supply first sub-line VGL1 and the conductive components in the first sub-circuit 100, and helps to reduce the difficulty of wiring.

[0208] For example, both the first power supply first sub-line VGL1 and the second power supply first sub-line VGH1 extend along the second direction Y, which is parallel to the cascading direction of the plurality of shift register units, and intersects the first direction X. In the first direction X, the orthographic projection of the second power supply first sub-line VGH1 onto the substrate falls into the gap region F0 between the orthographic projections of the first portion VSS1 and the second portion VSS2 onto the substrate.

[0209] The first power supply first sub-line VGL1 and the second power supply first sub-line VGH1 can be located in the same gap region F0. This design reduces the distance between the first power supply first sub-line VGL1 and the second power supply first sub-line VGH1 and the area where the first sub-circuit 100 is located, facilitating the electrical connection between the first power supply first sub-line VGL1 and the second power supply first sub-line VGH1 and the first sub-circuit 100, and reducing the difficulty of wiring.

[0210] For example, in the first direction X, the orthographic projection of the first sub-line VGH1 of the second power supply on the substrate falls into the gap region between the orthographic projections of the first sub-line VGL1 of the first power supply and the second part VSS2 on the substrate.

[0211] For example, in the first direction X, the distance d1 between the second part VSS2 and the second power supply first sub-line VGH1 is greater than or equal to 4 micrometers; and / or, in the first direction X, the distance d2 between the first power supply first sub-line VGL1 and the second power supply first sub-line VGH1 is greater than or equal to 4 micrometers.

[0212] This design avoids short circuits between adjacent second parts VSS2, second power supply first sub-line VGH1, and first power supply first sub-line VGL1, which helps improve the yield of the display substrate.

[0213] In some embodiments, the first power supply second sub-line VGL2, the first power supply third sub-line VGL3, and the first power supply fourth sub-line VGL4 may all be located in the first conductive layer 101; and / or, the second power supply second sub-line VGH2, the second power supply third sub-line VGH3, and the second power supply fourth sub-line VGH4 may all be located in the first conductive layer 101.

[0214] For example, continuing to refer to FIG13, the first portion VSS1 may include a plurality of first gaps F1 located in the first region S1. The orthographic projections of the first power supply second sub-line VGL2, the first power supply third sub-line VGL3, and the first power supply fourth sub-line VGL4 on the substrate fall within the orthographic projections of the plurality of first gaps F1 on the substrate.

[0215] For example, the first part VSS1 includes a first sub-conductive part VSS11, a second sub-conductive part VSS12, a third sub-conductive part VSS13 and a fourth sub-conductive part VSS14 that are sequentially located away from the second part VSS2 in the first direction X.

[0216] The plurality of first gaps F1 include: a first sub-gap F11 located between a first sub-conductive portion VSS11 and a second sub-conductive portion VSS12; a second sub-gap F12 located between a second sub-conductive portion VSS12 and a third sub-conductive portion VSS13; and a third sub-gap F13 located between a third sub-conductive portion VSS13 and a fourth sub-conductive portion VSS14.

[0217] For example, the orthographic projection of the second sub-line VGL2 of the first power supply onto the substrate falls within the orthographic projection of the first sub-gap F11 onto the substrate. The orthographic projection of the third sub-line VGL3 of the first power supply onto the substrate falls within the orthographic projection of the second sub-gap F12 onto the substrate. The orthographic projection of the fourth sub-line VGL4 of the first power supply onto the substrate falls within the orthographic projection of the third sub-gap F14 onto the substrate.

[0218] For example, the second power supply second sub-line VGH2 is located on the side of the first power supply second sub-line VGL2 away from the display area AA, and the orthographic projection of the second power supply second sub-line VGH2 on the substrate falls within the orthographic projection of the first sub-gap F11 on the substrate.

[0219] For example, the second power supply third sub-line VGH3 is located on the side of the first power supply third sub-line VGL3 away from the display area AA, and the orthographic projection of the second power supply third sub-line VGH3 on the substrate falls within the orthographic projection of the second sub-gap F12 on the substrate.

[0220] For example, the second power supply fourth sub-line VGH4 is located on the side of the first power supply fourth sub-line VGL4 away from the display area AA, and the orthographic projection of the second power supply fourth sub-line VGH4 on the substrate falls within the orthographic projection of the third sub-gap F13 on the substrate.

[0221] With this design, multiple first power lines VGL and multiple second power lines VGH can be sequentially set in multiple gap areas in the third power line, so that the distance between multiple sub-circuits in the shift register unit and the corresponding electrically connected first power lines VGL and second power lines VGH is relatively close, which facilitates wiring design, reduces process difficulty, and reduces costs.

[0222] In some embodiments, the first sub-circuit 100, the second sub-circuit 200, the third sub-circuit 300, the fourth sub-circuit 400, and the fifth sub-circuit 500 in the shift register unit can be connected to an independent first power supply line VGL and an independent second power supply line VGH, thereby improving the stability of the output signals of the multiple sub-circuits such as the first sub-circuit 100, the second sub-circuit 200, the third sub-circuit 300, the fourth sub-circuit 400, and the fifth sub-circuit 500.

[0223] Figures 14A and 14B are schematic diagrams of the structure of shift registers according to some embodiments of the present disclosure. Figure 14A shows the connection relationship between different sub-circuits and the first power supply line in the shift register, and Figure 14B shows the connection relationship between different sub-circuits and the second power supply line in the shift register.

[0224] For example, referring to FIG14A, the first power line VGL may include a first power first sub-line VGL1, a first power second sub-line VGL2, a first power third sub-line VGL3, a first power fourth sub-line VGL4, a first power fifth sub-line VGL5, and a first power sixth sub-line VGL6.

[0225] The first sub-circuit 100 is electrically connected to the first sub-line VGL1 of the first power supply. The second sub-circuit 200 is electrically connected to the second sub-line VGL2 of the first power supply. The third sub-circuit 300 is electrically connected to the fifth sub-line VGL5 of the first power supply. Both the third sub-line VGL3 and the fourth sub-line VGL4 of the first power supply are electrically connected to the fourth sub-circuit 400. The fifth sub-circuit 500 is electrically connected to the sixth sub-line VGL6 of the first power supply.

[0226] For example, the first power supply first sub-line VGL1, the first power supply second sub-line VGL2, the first power supply third sub-line VGL3, the first power supply fourth sub-line VGL4, the first power supply fifth sub-line VGL5, and the first power supply sixth sub-line VGL6 are all independently configured.

[0227] This design reduces mutual interference between the first power supply sub-line VGL1, the second power supply sub-line VGL2, the third power supply sub-line VGL3, the fourth power supply sub-line VGL4, the fifth power supply sub-line VGL5, and the sixth power supply sub-line VGL6, thereby improving the stability of the output signals of multiple sub-circuits in the shift register unit and enhancing the display effect of the display substrate.

[0228] For example, referring to FIG14B, the second power line VGH may include a second power first sub-line VGH1, a second power second sub-line VGH2, a second power third sub-line VGH3, a second power fourth sub-line VGH4, a second power fifth sub-line VGH5, and a second power sixth sub-line VGH6.

[0229] The first sub-circuit 100 is electrically connected to the first sub-line VGH1 of the second power supply. The second sub-circuit 200 is electrically connected to the second sub-line VGH2 of the second power supply. The third sub-circuit 300 is electrically connected to the fifth sub-line VGH5 of the second power supply. Both the third sub-line VGH3 and the fourth sub-line VGH4 of the second power supply are electrically connected to the fourth sub-circuit 400. The fifth sub-circuit 500 is connected to the sixth sub-line VGH6 of the second power supply.

[0230] For example, the first sub-line VGH1, the second sub-line VGH2, the third sub-line VGH3, the fourth sub-line VGH4, the fifth sub-line VGH5, and the sixth sub-line VGH6 of the second power supply are all independently configured.

[0231] This design reduces mutual interference between the first sub-line VGH1, the second sub-line VGH2, the third sub-line VGH3, the fourth sub-line VGH4, the fifth sub-line VGH5, and the sixth sub-line VGH6 of the second power supply, thereby further improving the stability of the output signals of multiple sub-circuits in the shift register unit and improving the display effect of the display substrate.

[0232] In some embodiments, multiple first power lines VGL and multiple second power lines VGH may be located in multiple conductive film layers. For example, at least a portion of the first power line VGL1 is located in the first conductive layer 101. At least a portion of the first power line VGL2, the first power line VGL3, and the first power line VGL4 is located in the second conductive layer 102.

[0233] By placing multiple first power lines VGL and multiple second power lines VGH in multiple conductive film layers, on the one hand, more wiring space can be provided for the wiring of multiple first power lines VGL and multiple second power lines VGH, which facilitates wiring design; on the other hand, the barrier effect of the spacer film between different conductive layers can be used to reduce the mutual influence between the radiated magnetic fields generated by the AC signals in multiple first power lines VGL and / or multiple second power lines VGH, which can further improve the signal stability in multiple first power lines VGL and multiple second power lines VGH.

[0234] In some embodiments, at least a portion of the first power line VGL may employ a stacked design.

[0235] Figure 15A is a partial plan view of a first power supply first sub-line according to an embodiment of the present disclosure; Figure 15B is a partial plan view of a first power supply second sub-line according to an embodiment of the present disclosure; Figure 15C is a partial plan view of a first power supply third sub-line according to an embodiment of the present disclosure; Figure 15D is a partial plan view of a first power supply fourth sub-line according to an embodiment of the present disclosure.

[0236] For example, referring to FIG15A, the first power supply first sub-line VGL1 may include a third portion VGL11 located in the first conductive layer 101 and a fourth portion VGL12 located in the second conductive layer 102, wherein the third portion VGL11 and the fourth portion VGL12 are electrically connected. This design reduces the resistance of the first power supply first sub-line VGL1 and the voltage drop in the first power supply first sub-line VGL1, which is beneficial for improving the driving effect of the shift register unit.

[0237] For example, referring to FIG15B, the first power supply second sub-line VGL2 may include a fifth portion VGL21 located in the first conductive layer 101 and a sixth portion VGL22 located in the second conductive layer 102, wherein the fifth portion VGL21 and the sixth portion VGL22 are electrically connected. This design reduces the resistance of the first power supply second sub-line VGL2 and the voltage drop in it, which is beneficial for improving the driving effect of the shift register unit.

[0238] For example, referring to FIG15C, the first power supply third sub-line VGL3 may include a seventh portion VGL31 located in the first conductive layer 101 and an eighth portion VGL32 located in the second conductive layer 102. The seventh portion VGL31 and the eighth portion VGL32 are electrically connected. With this design, the resistance of the first power supply third sub-line VGL3 can be reduced, the voltage drop in the first power supply third sub-line VGL3 can be reduced, which is beneficial to improving the driving effect of the shift register unit.

[0239] For example, referring to FIG15D, the first power supply fourth sub-line VGL4 includes a ninth portion VGL41 located in the first conductive layer 101 and a tenth portion VGL42 located in the second conductive layer 102. The ninth portion VGL41 and the tenth portion VGL42 are electrically connected. With this design, the resistance of the first power supply fourth sub-line VGL4 can be reduced, the voltage drop in the first power supply fourth sub-line VGL4 can be reduced, which is beneficial to improving the driving effect of the shift register unit.

[0240] In some embodiments, at least a portion of the plurality of first power lines VGL can be formed by utilizing at least a portion of the conductive components in the second conductive layer 102 and the third conductive layer 103 to form a stacked first power line VGL, thereby reducing the resistance of the first power line VGL.

[0241] In some embodiments, at least a portion of the second power line VGH may employ a stacked design. For example, at least a portion of the second power line VGH may be formed by stacked conductive components located in the first conductive layer 101 and the second conductive layer 102. Alternatively, at least a portion of the second power line VGH may be formed by stacked conductive components located in the second conductive layer 102 and the third conductive layer 103. This design reduces the resistance of at least a portion of the second power line VGH.

[0242] In some embodiments of this disclosure, the first portion VSS1 and the second portion VSS2 of the third power line VSS can be electrically connected in the corner area of ​​the display substrate.

[0243] Figure 16A is a plan view of a combination of multiple film layers in the corner area of ​​a display substrate according to some embodiments, and Figure 16B is a plan view of the first conductive layer in Figure 16A; Figure 17A is a plan view of a combination of multiple film layers in the corner area of ​​a display substrate according to other embodiments, and Figure 17B is a plan view of the first conductive layer in Figure 17A.

[0244] For example, referring to Figures 16A and 16B, the third power line VSS can form a continuous conductive layer in the non-display area NA. For example, the non-display area NA includes a first region S1, a second region S2, and a third region S3. For example, the first region S1 and the second region S2 can be located on one side (e.g., the left side) of the display area AA, and the third region S3 is located in the corner area of ​​the non-display area, and the third region S3 is on the same side as the first region S1 and the second region S2.

[0245] In some embodiments, the first portion VSS1 located in the first region S1, the second portion VSS2 located in the second region S2, and the portion VSS3 located in the third region S3 of the third power line VSS are designed as a single surface. The portion VSS4 located in the display area AA of the third power line is designed as a grid. This design reduces the voltage drop in the third power line VSS, which helps to improve the light emission uniformity of the display substrate.

[0246] However, in some embodiments, referring to FIG17B, in order to leave wiring space for the first power line VGL and the second power line VGH, the first part VSS1 located in the first region S1 and the second part VSS2 located in the second region S2 of the third power line VSS cannot be directly connected.

[0247] In order to reduce the resistance of the third power line VSS, in some embodiments of this disclosure, the third power line VSS further includes a connecting portion VSS3 located in the third region S3, and the first portion VSS1 and the second portion VSS2 are electrically connected through the connecting portion VSS3.

[0248] For example, the connecting portion VSS3 includes a plurality of protrusions VSS30 facing the first portion VSS1 and the second portion VSS2. The plurality of protrusions VSS30 are electrically connected to the second portion VSS2, the first sub-conductive portion VSS11, the second sub-conductive portion VSS12, the third sub-conductive portion VSS13 and the fourth sub-conductive portion VSS14, respectively.

[0249] This design allows for sufficient wiring space for multiple first power lines VGL and second power lines VGH while ensuring a low overall resistance for the third power line VSS. This facilitates electrical connection between multiple first power lines VGL and second power lines VGH and multiple sub-circuits in the shift register unit, while also reducing the voltage drop in the third power line VSS and improving the uniformity of light emission from the display substrate.

[0250] Optionally, embodiments of this disclosure also provide a display device, which may include the aforementioned display substrate 1000. The display device may include, but is not limited to, any product or component with display functionality, such as electronic paper, mobile phones, tablet computers, monitors, laptops, digital photo frames, and navigators. It should be understood that this display device has the same beneficial effects as the display substrate provided in the foregoing embodiments.

[0251] While some embodiments of the general concept of this disclosure have been shown and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the general concept of this disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. A display substrate, characterized in that, include: A substrate, the substrate including a display area and a non-display area, the non-display area being located on at least one side of the display area; and A driving circuit layer, located on one side of the substrate, includes a shift register located in the non-display area. The shift register includes multiple cascaded shift register units, each comprising: a first sub-circuit configured to provide a light emission control signal; and a second sub-circuit configured to provide a second reset control signal. The driving circuit layer further includes a first power line configured to provide a low-level signal to the shift register unit. The first power line includes a first power first sub-line and a first power second sub-line. The first sub-circuit is electrically connected to the first power first sub-line, and the second sub-circuit is electrically connected to the first power second sub-line. The first power first sub-line and the first power second sub-line are independently configured.

2. The display substrate according to claim 1, wherein, The non-display area includes a first area and a second area, the first area being located on one side of the display area, and both the first sub-circuit and the second sub-circuit being located in the first area; The second region is located on the side of the first region that is furthest from the display area; The driving circuit layer further includes: a first conductive layer and a third power line located on the first conductive layer, the third power line comprising a first portion located in the first region and a second portion located in the second region. Wherein, in a first direction, the first portion and the second portion are spaced apart, and the first direction is parallel to the direction from the second region to the first region; and In the first direction, the orthographic projection of the first power supply first sub-line on the substrate falls into the gap region between the orthographic projections of the first portion and the second portion on the substrate.

3. The display substrate according to claim 2, wherein, At least a portion of the first power supply first sub-line is located in the first conductive layer.

4. The display substrate according to claim 2 or 3, wherein, The driving circuit layer also includes a second power line configured to provide a high-level signal to the shift register unit. The second power line includes a second power first sub-line and a second power second sub-line. The first sub-circuit is electrically connected to the second power first sub-line, and the second sub-circuit is electrically connected to the second power second sub-line. The second power first sub-line and the second power second sub-line are independently configured.

5. The display substrate according to claim 4, wherein, Both the first power supply first sub-line and the second power supply first sub-line extend along a second direction, which is parallel to the cascading direction of the plurality of shift register units and intersects with the first direction. In the first direction, the orthographic projection of the second power supply first sub-line on the substrate falls into the gap region between the orthographic projections of the first portion and the second portion on the substrate.

6. The display substrate according to claim 5, wherein, In the first direction, the orthographic projection of the second power supply first sub-line on the substrate falls into the gap region between the orthographic projections of the first power supply first sub-line and the second portion on the substrate.

7. The display substrate according to any one of claims 2-6, wherein, The shift register unit further includes a fourth sub-circuit configured to provide a first scan control signal, the fourth sub-circuit being located in the first region; The first power line also includes a first power third sub-line and a first power fourth sub-line, both of which are electrically connected to the fourth sub-circuit. The first power supply first sub-line, the first power supply second sub-line, the first power supply third sub-line, and the first power supply fourth sub-line are all independently configured.

8. The display substrate according to claim 7, wherein, The shift register unit further includes a third sub-circuit configured to provide a first reset control signal, the third sub-circuit being electrically connected to a second sub-line of the first power supply; and / or The shift register unit further includes a fifth sub-circuit configured to provide a second scan control signal, and the fifth sub-circuit is electrically connected to the second sub-line of the first power supply.

9. The display substrate according to claim 7, wherein, The driving circuit layer further includes a second conductive layer, which is located on the side of the first conductive layer closer to the substrate. At least a portion of the first power supply second sub-line, the first power supply third sub-line, and the first power supply fourth sub-line are located in the second conductive layer.

10. The display substrate according to claim 7, wherein, The first power line also includes a first power fifth sub-line and a first power sixth sub-line; The shift register unit further includes a third sub-circuit, which is configured to provide a first reset control signal and is electrically connected to the fifth sub-line of the first power supply. The shift register unit further includes a fifth sub-circuit configured to provide a second scan control signal, and the fifth sub-circuit is electrically connected to the sixth sub-line of the first power supply. The first power supply first sub-line, the first power supply second sub-line, the first power supply third sub-line, the first power supply fourth sub-line, the first power supply fifth sub-line, and the first power supply sixth sub-line are all independently configured.

11. The display substrate according to claim 9, wherein, The first power supply first sub-line includes a third portion located in the first conductive layer and a fourth portion located in the second conductive layer, the third portion and the fourth portion being electrically connected; and / or, The first power supply second sub-line includes a fifth portion located in the first conductive layer and a sixth portion located in the second conductive layer, the fifth portion and the sixth portion being electrically connected; and / or, The first power supply third sub-line includes a seventh portion located in the first conductive layer and an eighth portion located in the second conductive layer, the seventh portion and the eighth portion being electrically connected; and / or, The first power supply fourth sub-line includes a ninth portion located in the first conductive layer and a tenth portion located in the second conductive layer, and the ninth portion and the tenth portion are electrically connected.

12. The display substrate according to claim 8 or 10, wherein, The first part includes a plurality of first gaps located in the first region, and the orthographic projections of the first power second sub-line, the first power third sub-line, and the first power fourth sub-line on the substrate fall within the orthographic projections of the plurality of first gaps on the substrate.

13. The display substrate according to claim 12, wherein, In the first direction, the first sub-circuit is located between the second portion and the display area, the second sub-circuit is located between the first sub-circuit and the display area, the third sub-circuit is located between the second sub-circuit and the display area, the fourth sub-circuit is located between the third sub-circuit and the display area, and the fifth sub-circuit is located between the fourth sub-circuit and the display area; The first part includes a first sub-conductive portion, a second sub-conductive portion, a third sub-conductive portion, and a fourth sub-conductive portion that are sequentially moved away from the second part in the first direction; The plurality of first gaps includes: a first sub-gap located between the first sub-conductive portion and the second sub-conductive portion; a second sub-gap located between the second sub-conductive portion and the third sub-conductive portion; and a third sub-gap located between the third sub-conductive portion and the fourth sub-conductive portion. Wherein, the orthographic projection of the first power supply second sub-line on the substrate falls within the orthographic projection of the first sub-gap on the substrate; the orthographic projection of the first power supply third sub-line on the substrate falls within the orthographic projection of the second sub-gap on the substrate; and the orthographic projection of the first power supply fourth sub-line on the substrate falls within the orthographic projection of the third sub-gap on the substrate.

14. The display substrate according to claim 13, wherein, The second power supply second sub-line is located on the side of the first power supply second sub-line away from the display area, and the orthographic projection of the second power supply second sub-line on the substrate falls within the orthographic projection of the first sub-gap on the substrate; The second power line also includes a second power third sub-line and a second power fourth sub-line, both of which are electrically connected to the fourth sub-circuit. Wherein, the second power supply third sub-line is located on the side of the first power supply third sub-line away from the display area, and the orthographic projection of the second power supply third sub-line on the substrate falls within the orthographic projection of the second sub-gap on the substrate; and The second power supply fourth sub-line is located on the side of the first power supply fourth sub-line away from the display area, and the orthographic projection of the second power supply fourth sub-line on the substrate falls within the orthographic projection of the third sub-gap on the substrate.

15. The display substrate according to any one of claims 2-14, wherein, The non-display area further includes a third area, which is located at the corner of the non-display area and on the same side as the first area and the second area. The third power line also includes a connecting portion located in the third area, and the first portion and the second portion are electrically connected through the connecting portion.

16. The display substrate according to claim 15, wherein, The connecting portion includes a plurality of protrusions facing the first portion and the second portion, the plurality of protrusions being electrically connected to the second portion, the first sub-conductive portion, the second sub-conductive portion, the third sub-conductive portion and the fourth sub-conductive portion, respectively.

17. The display substrate according to any one of claims 4-6, wherein, In the first direction, the distance between the second portion and the first sub-line of the second power supply is greater than or equal to 4 micrometers; and / or, In the first direction, the distance between the first power supply first sub-line and the second power supply first sub-line is greater than or equal to 4 micrometers.

18. The display substrate according to any one of claims 2-17, wherein, The voltage of the low-level signal provided by the first power line is in the range of -14V to -7V; and / or, The voltage of the signal provided by the third power line is in the range of -4V to -2V.

19. A display device comprising a display substrate as claimed in any one of claims 1-18.

Images