Shift register, driving circuit, driving method, and display device

Abstract

The present disclosure relates to the technical field of display, and provides a shift register, a driving circuit, a driving method, and a display device. The shift register comprises: a first control circuit, configured to provide a first power supply voltage to a first node under the control of a first clock signal; a gating circuit, configured to provide the first clock signal to the first node under the control of a plurality of gating signals; an input circuit, configured to provide the first power supply voltage to a second node under the control of the potential of the first node and a second clock signal, and use a control signal to control the potential of the second node; a second control circuit, configured to provide a third power supply voltage or a fourth power supply voltage to a third node under the control of the potential of the second node and a second power supply voltage of a second power supply; and an output circuit, configured to provide a third clock signal or the second power supply voltage to an output end as an outputted scan signal under the control of the potentials of the second node and the third node.

Description

Shift registers, driving circuits, driving methods, and display devices

[0001] This application claims priority to Chinese patent application 202510066560.5, filed on January 15, 2025, the contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of display technology, and in particular to a shift register, a driving circuit, a driving method, and a display device. Background Technology

[0003] To achieve a good balance between power consumption and high refresh rates, displays typically employ local high refresh rate (DRPR) technology. This technology requires the driver circuitry to have flexible activation capabilities. Common shift register driver circuits offer limited driving capabilities for displays and cannot adjust in real time according to the image, thus failing to meet the more flexible high refresh rate requirements of displays. Summary of the Invention

[0004] This disclosure provides a shift register, a driving circuit, a driving method, and a display device.

[0005] According to a first aspect, this disclosure provides a shift register, comprising: a first control circuit configured to provide a first power supply voltage of a first power source to a first node under the control of a first clock signal from a first clock terminal; a gating circuit configured to provide a first clock signal to the first node under the control of a plurality of gating signals from a plurality of gating terminals; an input circuit configured to provide a first power supply voltage to a second node under the control of the potential of the first node and a second clock signal from a second clock terminal, and to control the potential of the second node using a control signal from a control terminal; a second control circuit configured to provide a third power supply voltage of a third power source or a fourth power supply voltage of a fourth power source to a third node under the control of the potential of the second node and the second power supply voltage of the second power source; and an output circuit configured to provide a third clock signal from a third clock terminal or a second power supply voltage to an output terminal as an output scan signal under the control of the potentials of the second node and the third node.

[0006] According to a second aspect, this disclosure provides a driving circuit including M shift registers as provided in any embodiment of this disclosure; wherein the m-th shift register is electrically connected to a first gating line, the (m+x)-th shift register is electrically connected to a second gating line, the gating signal output from the first gating line and the gating signal output from the second gating line are not simultaneously active, 1≤m≤Mx, 1≤x<M, M is a positive integer greater than 1, and m and x are positive integers.

[0007] According to a third aspect, this disclosure provides a display device, including a display panel; and a driving circuit as provided in the embodiments of this disclosure; wherein the display panel includes a plurality of sub-pixel units arranged in an array, and the driving circuit is used to drive the sub-pixel units.

[0008] According to a fourth aspect, this disclosure provides a driving method applied to a shift register provided in an embodiment of this disclosure, comprising: during the duration of a first level of a q-th clock sub-signal, a (q+1)-th clock sub-signal jumps from a second level to a first level, 1 ≤ q ≤ Q-1, where q is an integer; during the duration of the first level of a Q-th clock sub-signal, a control signal jumps from a second level to a first level; wherein, a third clock signal includes Q clock sub-signals whose effective levels are sequentially shifted, where Q is a positive integer; and a first clock signal and a control signal are not simultaneously at an effective level. Attached Figure Description

[0009] Figure 1 is a schematic diagram of the structure of a shift register according to an embodiment of the present disclosure;

[0010] Figure 2 is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure;

[0011] Figure 3 is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure;

[0012] Figure 4A is a signal timing diagram of a shift register according to an embodiment of the present disclosure;

[0013] Figure 4B is a signal timing diagram of a shift register according to another embodiment of the present disclosure;

[0014] Figure 5 is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure;

[0015] Figure 6 is a signal timing diagram of a shift register according to another embodiment of the present disclosure;

[0016] Figure 7A is a schematic diagram of the drive circuit according to an embodiment of the present disclosure;

[0017] Figures 7B and 7C are schematic diagrams of the signal timing of a shift register according to another embodiment of the present disclosure;

[0018] Figure 8 is a schematic diagram of the structure of a drive circuit according to another embodiment of the present disclosure;

[0019] Figure 9 is a schematic diagram of the structure of a display device according to an embodiment of the present disclosure;

[0020] Figure 10 is a flowchart of a driving method according to an embodiment of the present disclosure. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure. It should be noted that throughout the accompanying drawings, the same elements are represented by the same or similar reference numerals. In the following description, some specific embodiments are used for descriptive purposes only and should not be construed as limiting this disclosure in any way, but are merely examples of embodiments of this disclosure. Conventional structures or configurations will be omitted where they may cause confusion in understanding this disclosure. It should be noted that the shapes and dimensions of the components in the figures do not reflect actual size and proportion, but are only schematic representations of the embodiments of this disclosure.

[0022] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure shall have the ordinary meaning as understood by those skilled in the art. The terms "first," "second," and similar words used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components.

[0023] Furthermore, in the description of the embodiments disclosed herein, the terms "connected" or "connected to" can refer to two components being directly connected, or to two components being connected via one or more other components. Additionally, these two components can be connected or coupled via wired or wireless means.

[0024] The source and drain of the switching transistor used in this embodiment are symmetrical, so their source and drain can be interchanged. In this embodiment, according to its function, the control electrode can be called the control electrode, one of the source and drain is called the first electrode, and the other of the source and drain is called the second electrode.

[0025] It should be noted that in the description of the embodiments of this disclosure, the symbol SCOUT can represent either a scan signal or the output terminal of the scan signal. Similarly, the symbol GVDD can represent either a power supply or the voltage provided by the power supply, the symbol VGL can represent either a power supply or the voltage provided by the power supply, and the symbol VGH can represent either a power supply or the voltage provided by the power supply. For example, power supplies VGL and LVGL can provide low voltages, while power supplies VGH and GVDD can provide high levels. The following embodiments are the same, and similar parts will not be described again.

[0026] Figure 1 is a schematic diagram of the structure of a shift register according to an embodiment of the present disclosure.

[0027] As shown in Figure 1, the shift register 100 includes a first control circuit 110, a gating circuit 120, an input circuit 130, a second control circuit 140, and an output circuit 150.

[0028] In this embodiment of the disclosure, the first control circuit 110 is electrically connected to the first clock terminal CLK1, the first power supply VGH, and the first node P. Under the control of the first clock signal CLK1 from the first clock terminal CLK1, the first control circuit 110 provides the first power supply voltage VGH of the first power supply VGH to the first node P.

[0029] For example, the first clock signal CLK1 can control the switching between a connected or disconnected state between the first power supply VGH and the first node P. For example, when the first clock signal CLK1 controls the first power supply VGH to be in a connected state with the first node P, the first control circuit 110 writes the first power supply voltage VGH into the first node P.

[0030] In this embodiment, the gating circuit 120 is electrically connected to a plurality of gating terminals D0 to Dn, a first clock terminal CLK1, and a first node P. Under the control of a plurality of gating signals from the plurality of gating terminals, the gating circuit 120 provides the first clock signal CLK1 to the first node P.

[0031] For example, multiple strobe signals D0 to Dn can control whether the first clock terminal CLK1 and the first node P are in a connected or disconnected state. When multiple strobe signals D0, ..., Dn control the first clock terminal CLK1 and the first node P to be in a conducting state, the strobe circuit 120 can write the first clock signal CLK1 to the first node P.

[0032] In this embodiment, when all the multiple gating signals D0 to Dn are low and the first clock signal CLK1 is low, the first node P is at a high potential, and the circuit is in the gating stage. When at least one of the multiple gating signals D0 to Dn is high and the first clock signal CLK1 is low, the low level of the first clock signal CLK1 is provided to the first node P, and the potential of the first node P is pulled low. At this time, the shift register 100 is in the non-gating stage.

[0033] In this embodiment, the input circuit 130 is electrically connected to the second clock terminal CLK2, the control terminal CS, the first power supply VGH, the first node P, and the second node QN. Under the control of the potential of the first node P and the second clock signal CLK2 from the second clock terminal CLK2, the input circuit 130 provides the first power supply voltage VGH to the second node QN and controls the potential of the second node QN using the control signal CS from the control terminal CS.

[0034] For example, the second clock signal CLK2 and the first node P can jointly control the switching between the first power supply VGH and the second node QN in an on or off state. For example, when the second clock signal CLK2 and the first node P control the first power supply VGH and the second node QN to be in an on state, the input circuit 130 writes the first power supply voltage VGH into the second node QN to pull up the potential of the second node QN.

[0035] The control signal CS is used to stabilize the potential of the second node QN, preventing the potential of the second node QN from being pulled down. Under the control of the control signal CS, the input circuit 130 can also pull the potential of the second node QN high to stabilize the high potential of the second node QN.

[0036] In this embodiment, the second control circuit 140 is electrically connected to the second node QN, the third power supply GVDD, the fourth power supply LVGL, the second power supply VGL, and the third node QB. Under the control of the potential of the second node QB and the second power supply voltage VGL of the second power supply VGL, the second control circuit 140 provides the third power supply voltage GVDD of the third power supply GVDD or the fourth power supply voltage LVGL of the fourth power supply LVGL to the third node QB.

[0037] For example, the third power supply voltage GVDD and the potential of the second node QN can jointly control the switching between the fourth power supply LVGL and the third node QB in a connected or disconnected state. For example, when the third power supply voltage GVDD and the potential of the second node QN control the fourth power supply LVGL to be in a connected state with the third node QB, the second control circuit 140 writes the fourth power supply voltage LVGL into the third node QB to pull down the potential of the third node QB.

[0038] In this embodiment, the output circuit 150 is electrically connected to the second node QN, the third node QB, the third clock terminal CLKE, and the output terminal SCOUT. Under the control of the potentials of the second node QN and the third node QB, the output circuit 150 provides the third clock signal CLKE or the second power supply voltage VGL from the third clock terminal to the output terminal SCOUT as the output scan signal.

[0039] For example, the potential of the third node QB can control whether the second power supply VGL and the output terminal SCOUT are in a connected or disconnected state. When the potential of the third node QB controls the second power supply VGL to be in a connected state with the output terminal SCOUT, the output circuit 140 provides the second power supply voltage VGL to the output terminal SCOUT, and the output terminal SCOUT outputs a low-level signal.

[0040] For example, the potential of the second node QN can control whether the third clock terminal CLKE and the output terminal SCOUT are in a connected or disconnected state. When the potential of the second node QN controls the third clock terminal CLKE and the output terminal SCOUT to be in a connected state, the output circuit 140 provides the third clock signal CLKE to the output terminal SCOUT, and the output terminal SCOUT outputs the third clock signal CLKE.

[0041] When shift register 100 is in the non-gated stage, the second control circuit 140 controls the second node QB to be low and the third node QB to be high, enabling shift register 100 to output a low voltage during the non-gated stage. When the shift register is in the gated stage, the second control circuit 140 controls the second node to be low and the third node QB to be low, enabling the shift register output circuit 150 to output normally, achieving the reverse potential action of the second node QN and the third node QB.

[0042] In this embodiment, when multiple gating signals are all low, the first node P remains high, causing the second node QN to be high, thereby ensuring that the output terminal SCOUT of the output circuit 150 outputs normally, and the shift register 100 remains in the gating stage. When one of the multiple gating signals is high, the potential of the first node P is pulled low, causing the second node QN to be low, the output terminal SCOUT of the output circuit 150 outputs a low-level signal, and the shift register 100 is in the non-gating stage.

[0043] The scan signal output from the SCOUT terminal can be used to drive the N-type transistors in the pixel circuit. For example, when the scan signal level is high, the N-type transistor is turned on, and data signals can be written, thus refreshing the screen. When the scan signal level is low, the N-type transistor is turned off, and data signals cannot be written, thus preventing the screen from refreshing and keeping it unchanged.

[0044] For example, the levels of the strobe signals D0 to Dn can indicate whether the transistors in the pixel circuit, which are electrically connected to the shift register 100, are turned on. For instance, when the strobe signals D0 to Dn are low, the first power supply voltage VGH is written to the first node P, the potential of the first node P is pulled high, and the output terminal SCOUT outputs the third clock signal CLKE as a scan signal. At this time, the N-type transistors in the pixel circuit can switch to the on state, and the corresponding display screen is refreshed.

[0045] When any of the strobe signals D0 to Dn is high, the potential of the first node P is pulled low by the low level of the first clock signal CLK1, the second node QN is at a low potential, and the level of the scan signal output by the output terminal SCOUT remains low. At this time, the N-type transistors in the pixel circuit remain in the off state based on the low-level scan signal, and the corresponding display screen does not refresh.

[0046] According to embodiments of this disclosure, by controlling the potentials of the first node P and the second node QN based on a gating signal, it can be determined whether the shift register 100 is in the gating stage, thereby controlling whether a pixel row electrically connected to the shift register 100 is refreshed. In a driving circuit including multiple shift registers, any shift register can be selected for gating by a gating signal, thereby enabling each pixel row in the pixel circuit to have the ability to be flexibly turned on, realizing control over whether a single pixel row is refreshed.

[0047] In this embodiment, the second node QN is used to control the output of the third clock signal CLKE to the output terminal SCOUT. With the second node QN at a high potential, the third clock terminal CLKE and the output terminal SCOUT are connected. The output circuit 140 provides the third clock signal CLKE to the output terminal SCOUT, and the output terminal SCOUT outputs the third clock signal CLKE. By using the control signal CS to control the second node QN to remain stably high, the output terminal SCOUT can be stably controlled to output the scan signal, reducing noise.

[0048] Figure 2 is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure.

[0049] As shown in Figure 2, the shift register 200 includes a first control circuit 210, a gating circuit 220, an input circuit 230, a second control circuit 240, an output circuit 250, a pull-down circuit 260, and a reset circuit 270.

[0050] In the embodiments of this disclosure, the first control circuit 210, the gating circuit 220, the input circuit 230, the second control circuit 240 and the output circuit 250 refer to the first control circuit 110, the gating circuit 120, the input circuit 130, the second control circuit 140 and the output circuit 150 described above, respectively, and will not be repeated for the sake of brevity.

[0051] In embodiments of this disclosure, pull-down circuit 260 is electrically connected to a first node P, a second node QN, a third node QB, a second clock terminal CLK2, and a fourth power supply LVGL. Under the control of the potential of the first node P and the second clock signal CLK2, pull-down circuit 260 provides the fourth power supply voltage LVGL to the potential of the third node QB. Under the control of the third node QB, pull-down circuit 260 provides the fourth power supply voltage LVGL to the second node QN.

[0052] For example, the potential of the first node P and the second clock signal CLK2 can control whether the fourth power supply LVGL and the third node QB are in a connected or disconnected state. When the potential of the first node P and the second clock signal CLK2 control the fourth power supply LVGL to be in a connected state with the third node QB, the pull-down circuit 260 provides the fourth power supply voltage LVGL to the third node QB to pull down the potential of the third node QB.

[0053] With the third node QB at a low potential, the fourth power supply LVGL is connected to the second node QN. At this time, the pull-down circuit 260 provides the fourth power supply voltage LVGL to the second node QN to pull down the potential of the second node QN.

[0054] When the output circuit 250 outputs the third clock signal CLKE to the output terminal SCOUT, the pull-down circuit 260 controls the potential of the second node QB to be low, thereby preventing the second node QB from coupling to a high potential and causing noise in the scanning signal.

[0055] In the embodiments of this disclosure, the reset circuit 270 is electrically connected to the first clock terminal CLK1, the fourth node Q, and the fourth power supply LVGL. Under the control of the first clock signal CLK1, the reset circuit 270 provides the fourth power supply voltage LVGL to the fourth node Q to pull down the potential of the fourth node Q. At this time, the first node P is at a high level. Under the control of the high level of the first node P, the reset circuit 270 provides the potential of the fourth node Q to the second node QN to pull down the potential of the second node QN, thereby resetting the potentials of the second node QN and the fourth node Q. When the shift register 100 is in the strobe stage, the reset circuit 270 can continuously reset the fourth node Q.

[0056] In embodiments of this disclosure, input circuit 230 is electrically connected to a first power supply VGH, a second clock terminal CLK2, a control terminal CS, a first node P, a second node QN, and a fourth node Q. Under the control of the second clock signal CLK2, input circuit 230 provides the first power supply voltage VGH to the fourth node Q. Under the control of the potential of the first node P, input circuit 230 provides the potential of the fourth node Q to the second node QN. Under the control of the control signal CS, input circuit 230 couples the control signal CS to the second node QN.

[0057] For example, the second clock signal CLK2 can control whether the first power supply VGH and the fourth node Q are in a connected or disconnected state. When the second clock signal CLK2 controls the first power supply VGH to be in a connected state with the fourth node Q, the input circuit 230 provides the first power supply voltage VGH to the fourth node Q to pull up the potential of the fourth node Q.

[0058] The potential of the first node P can control whether the second node QN and the fourth node Q are in a connected or disconnected state. When the potential of the first node P controls the second node QN and the fourth node Q to be in a connected state, the input circuit 230 provides the high potential of the fourth node Q to the second node QN to pull up the potential of the second node QN.

[0059] The high potential of the second node QN can control the output circuit 250 to provide the third clock signal CLKE to the output terminal SCOUT in order to output the scan signal.

[0060] When the level of the control signal CS changes, the input circuit 230 can couple the level change of the control signal CS to the second node QN. For example, when the potential of the control signal CS is pulled high, the high level of the control signal CS can be coupled to the second node QN, thereby pulling the potential of the second node QN high again.

[0061] Under the control of the high level of the second node QN, the output circuit 250 can stably output the third clock signal CLKE, reducing the noise of the scan signal.

[0062] In this embodiment, the output circuit 250 may include multiple sub-output terminals, which are configured to output multiple scan signals to drive multiple rows of sub-pixel units. It should be noted that this disclosure does not limit the number of output terminals.

[0063] For example, the third clock terminal CKLE may include the first sub-clock terminal and the second sub-clock terminal, and the output terminal SCOUT may include the first sub-output terminal and the second sub-output terminal.

[0064] Under the control of the potential of the second node QN, the output circuit 250 outputs the first clock sub-signal from the first sub-clock terminal to the first sub-output terminal. When the first sub-output terminal outputs the first clock sub-signal, the output circuit 250 couples the first clock sub-signal to the second node QN, thereby pulling up the potential of the second node QN. Under the control of the second node QN with its potential pulled up, the output circuit 250 outputs the second clock sub-signal from the second sub-clock terminal to the second sub-output terminal. Since the potential of the second node QN is pulled up by the first clock sub-signal, the second node QN can be stably maintained at a high potential, and at this time, the connection between the second sub-clock terminal and the second sub-output terminal can be stably controlled.

[0065] During the duration of the first level of the second clock sub-signal, the first clock sub-signal jumps from the first level to the second level, and the control signal jumps from the second level to the first level.

[0066] For example, the first level is high, and the second level is low. During the duration of the first level of the second clock sub-signal, if the first clock sub-signal is high, the high level of the first clock signal is coupled to the second node QN, and the potential of the second node QN is further pulled high. When the first clock sub-signal transitions from high to low, the potential of the second node QN decreases accordingly due to the change in the potential of the first clock sub-signal. In this case, the control signal CS transitions from low to high. The input circuit 230 couples the high level of the control signal CS to the second node QN, at which point the potential of the second node QN can also be pulled high. The potential of the second node QN can be maintained at the potential before the first clock sub-signal transitions from high to low, thereby ensuring that the second sub-output terminal stably outputs the second clock sub-signal and reducing the noise of the scan signal output by the second sub-output terminal.

[0067] Figure 3 is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure.

[0068] As shown in Figure 3, the shift register 300 includes a first control circuit 310, a gating circuit 320, an input circuit 330, a second control circuit 340, an output circuit 350, a pull-down circuit 360, and a reset circuit 370.

[0069] In this embodiment, the first control circuit 310 includes transistors T1, T11, and T13, capacitor C1, and capacitor C2. The gating circuit 320 includes transistors T2 to T9, transistor T10, and transistor T12 connected in parallel, wherein transistors T2 to T9 can be gating transistors. The input circuit 330 includes transistors T14 and T22. The second control circuit 340 includes transistors T15, T16, T17, T18, and T19. The output circuit 350 includes transistors T28 to T35 and capacitors C3 to C6. The pull-down circuit 360 includes transistors T20, T21, T23, T24, and T25. The reset circuit 370 includes transistors T26 and T27. Transistors T1 to T35 are all N-type transistors.

[0070] In this embodiment, the second node is a second node Q1 separated from the third node Q. The output terminals include output terminals SCout(i), SCout(i+1), SCout(i+2), and SCout(i+3). The third clock terminal includes clock terminals CLKE1, CLKE2, CLKE3, and CLKE4. Clock terminal CLKD is a control terminal.

[0071] The control electrode of transistor T1 is electrically connected to the first clock terminal CLK1, the first electrode of transistor T1 is electrically connected to the first power supply VGH, and the second electrode of the first transistor T1 is electrically connected to the control electrode of transistor T11.

[0072] The control electrode of transistor T11 is electrically connected to the first terminal of capacitor C1. The first terminal of transistor T11 is electrically connected to power supply VGH. The second terminal of transistor T11 is electrically connected to the first node P. The second terminal of capacitor C1 is electrically connected to the first node P.

[0073] The control electrode of transistor T13 is electrically connected to the first node P, the first electrode of transistor T13 is electrically connected to the first power supply VGH, and the second electrode of transistor T13 is electrically connected to the second electrode of transistor T12.

[0074] The first terminal of capacitor C2 is electrically connected to the first power supply VGH, and the second terminal of capacitor C2 is electrically connected to the first node P.

[0075] The control terminals of transistors T2 to T9 are electrically connected to the selection terminals D0 to D7, respectively. The second terminals of transistors T2 to T9 are electrically connected to the first clock terminal CLK1. The first terminals of transistors T2 to T9 are electrically connected to the second terminals of transistors T10 and T12.

[0076] The control terminals of transistors T10 and T12 are electrically connected to the third node QB. The first terminal of transistor T10 is electrically connected to the first terminal of capacitor C1, and the first terminal of transistor T12 is electrically connected to the first node P.

[0077] The control electrode of the fourteenth transistor T14 is connected to the second clock terminal CLK2, the first electrode of the fourteenth transistor T14 is connected to the first power supply VGH, and the second electrode of the fourteenth transistor T14 is connected to the fourth node Q.

[0078] The control electrode of transistor T22 is electrically connected to the first node P, the first electrode of transistor T22 is electrically connected to the fourth node Q, and the second electrode of transistor T22 is electrically connected to the second node Q1.

[0079] The control electrode and first electrode of transistor T15 are electrically connected to the third power supply GVDD, and the second electrode of transistor T15 is electrically connected to the first electrode of transistor T16.

[0080] The control electrode of transistor T16 is electrically connected to the third power supply GVDD, and the second electrode of transistor T16 is electrically connected to the control electrode of transistor T18.

[0081] The control electrode of transistor T17 is electrically connected to the second node Q1, the first electrode of transistor T17 is electrically connected to the control electrode of transistor T18, and the second electrode of transistor T17 is electrically connected to the second power supply VGL.

[0082] The first terminal of transistor T18 is electrically connected to the third power supply GVDD, and the second terminal of transistor T18 is electrically connected to the third node QB.

[0083] The control electrode of transistor T19 is connected to the second node Q1, the first electrode of transistor T19 is connected to the third node QB, and the second electrode of transistor T19 is connected to the fourth power supply LVGL.

[0084] The control electrode of transistor T20 is electrically connected to the first node P, the first electrode of transistor T20 is electrically connected to the third node QB, and the second electrode of transistor T20 is electrically connected to the first electrode of transistor T21.

[0085] The control electrode of transistor T21 is electrically connected to the first clock terminal CLK1, and the second electrode of transistor T21 is electrically connected to the fourth power supply LVGL.

[0086] The control terminals of transistors T23 and T24 are electrically connected to the third node QB. Transistors T23 and T24 are connected in series. The first terminal of transistor T23 is electrically connected to the second node Q1, and the second terminal of transistor T24 is electrically connected to the fourth power supply LVGL.

[0087] The control electrode of transistor T25 is electrically connected to the second node Q1, the first electrode of transistor T25 is electrically connected to the second electrode of transistor T23, and the second electrode of transistor T25 is electrically connected to the first power supply VGH.

[0088] Transistor T26 and the thirtieth transistor T27 are connected in series. The control electrodes of transistors T26 and T27 are electrically connected to the first clock terminal CLK1. The first electrode of transistor T26 is electrically connected to the fourth node Q. The second electrode of the thirtieth transistor T27 is electrically connected to the fourth power supply LVGL.

[0089] In this embodiment of the disclosure, the control terminals of transistors T28, T30, T32, and T34 are all electrically connected to the second node Q1, and the control terminals of transistors T29, T31, T33, and T35 are all electrically connected to the third node QB.

[0090] The first terminal of transistor T28 is electrically connected to the clock terminal CLKE1, and the second terminal of transistor T28 is electrically connected to the output terminal SCout(i).

[0091] The control electrode of transistor T29 is electrically connected to the third node QB, the first electrode of transistor T29 is connected to the second power supply VGL, and the second electrode of transistor T29 is electrically connected to the output terminal SCout(i).

[0092] The first end of capacitor C3 is connected to the second node Q1, and the second end of capacitor C3 is connected to the output terminal SCout(i).

[0093] The control electrode of transistor T30 is connected to the second node Q1, the first electrode of transistor T30 is connected to the clock terminal CLKE2, and the second electrode of transistor T30 is connected to the output terminal SCout(i+1).

[0094] The control electrode of transistor T31 is connected to the third node QB, the first electrode of transistor T31 is connected to the second power supply VGL, and the second electrode of transistor T31 is connected to the output terminal SCout(i+1).

[0095] The first terminal of capacitor C4 is electrically connected to the second node Q1, and the second terminal of capacitor C4 is electrically connected to the output terminal SCout(i+1).

[0096] The first terminal of transistor T32 is electrically connected to the clock terminal CLKE3, and the second terminal of transistor T32 is electrically connected to the output terminal SCout(i+2).

[0097] The control electrode of transistor T33 is electrically connected to the third node QB, the first electrode of transistor T33 is connected to the second power supply VGL, and the second electrode of transistor T33 is electrically connected to the output terminal SCout(i+2).

[0098] The first end of capacitor C5 is connected to the second node Q1, and the second end of capacitor C5 is connected to the output terminal SCout(i+2).

[0099] The control electrode of transistor T34 is connected to the second node Q1, the first electrode of transistor T34 is connected to the clock terminal CLKE4, and the second electrode of transistor T34 is connected to the output terminal SCout(i+3).

[0100] The control electrode of transistor T35 is connected to the third node QB, the first electrode of transistor T35 is connected to the second power supply VGL, and the second electrode of transistor T35 is connected to the output terminal SCout(i+3).

[0101] The first terminal of capacitor C6 is electrically connected to the second node Q1, and the second terminal of capacitor C6 is electrically connected to the output terminal SCout(i+3).

[0102] It should be noted that this disclosure does not limit the number of output terminals.

[0103] Figures 4A and 4B are the signal timing diagrams of the shift register in Figure 3. Figure 4A shows the timing waveforms of each signal in each stage during the forward scan process.

[0104] The following description uses the shift register structure shown in Figure 3 as an example, combined with the signal timing diagrams shown in Figures 4A and 4B, to illustrate the operation of the shift register provided in this embodiment. The forward scan operation of the shift register includes five stages.

[0105] For example, Figure 4A shows the signal timing of shift register 300 during the five stages S1-S5 of the forward scan process. Figure 4A also shows the signal timing provided to the first-stage shift register in a cascaded set of multiple shift registers.

[0106] In the first stage S1, the first clock signal CLK1 outputs a high level, turning on transistor T1. The first power supply voltage VGH is supplied to the control electrode of transistor T11 through transistor T1, turning on transistor T11. The first power supply voltage VGH is then supplied to the first node P through transistor T11, pulling the potential of the first node P high. Transistors T26 and T27 turn on. The fourth power supply voltage LVGL is supplied to the fourth node Q through transistors T25 and T26, pulling the potential of the fourth node Q low. The high potential of the first node P controls transistor T22 to turn on, and the low potential of the fourth node Q is supplied to the second node Q1, pulling the potential of the second node Q1 low, thereby resetting the fourth node Q and the second node Q1.

[0107] During forward scanning, when the first clock signal CLK1 is high, the above nodes can also be reset.

[0108] The first clock signal CLK1 changes from high level to low level, the strobe signals D0 to D7 are low level, the second clock signal CLK2 is low level, and the clock signals CLKE1 to CLKE4 are low level.

[0109] The fourth power supply voltage LVGL is lower than the second power supply voltage VGL. Since the threshold voltage Vth of transistors T29, T31, T33 and T35 is prone to negative drift, which can lead to leakage, when the fourth power supply voltage LVGL is lower than the second power supply voltage VGL, it can make Vgs(LVGL-VGL) of the transistor in the off state negative.

[0110] When the first clock signal CLK1 is high, transistor T1 is turned on under the control of the first clock signal CLK1. Since the first power supply voltage VGH is supplied to the first terminal of capacitor C1 through transistor T1, capacitor C1 is charged. Capacitor C1 stores a high level, making the potential of the first node P high.

[0111] Under the control of the third power supply voltage GVDD, transistors T15, T16 and T18 are turned on, making the third node QB high.

[0112] Under the control of the high level of the third node QB, transistors T23 and T24 are turned on. The fourth power supply voltage LVGL is supplied to the second node Q1 through transistors T24 and T23, causing the potential of the second node Q1 to be pulled low.

[0113] Under the control of the high level of the first node P, transistor T22 is turned on, and the low level of the second node Q1 is provided to the fourth node Q through transistor T22, so that the potential of the fourth node Q is kept low.

[0114] Under the control of strobe signals D0 to D7, transistors T2 to T9 are turned off, and the potential of the first node P will not be reduced due to the influence of transistors T2 to T9, and the potential of the first node P remains at a high level.

[0115] When the first clock signal CLK1 changes from high level to low level, transistor T1 is turned off under the control of the first clock signal CLK1. Since capacitor C1 remains at a high potential, transistor T11 remains on, so that the first power supply voltage VGH is supplied to the first node P, and the first node P remains at a high level.

[0116] In the second stage S2, the first clock signal CLK1 is at a low level and the second clock signal CLK2 is at a high level.

[0117] Under the control of the second clock signal CLK2, transistor T14 is turned on, and the first power supply voltage VGH is provided to the fourth node Q through transistor T14, making the potential of the fourth node Q high. Under the control of the high level of the first node P, transistor T22 is turned on. The high level of the fourth node Q is provided to the second node Q1 through transistor T22.

[0118] Under the control of the high level of the second node Q1, transistors T17 and T19 are turned on. The second power supply voltage VGL is supplied to transistor T18 through transistor T17, and transistor T18 is turned off under the control of the second power supply voltage VGL.

[0119] Under the control of the second clock signal CLK2, transistor T21 is turned on. Under the control of the high level of the first node P, transistor T20 is turned on. At this time, the fourth power supply voltage LVGL is provided to the third node QB through transistors T20 and T21, causing the potential of the third node QB to be pulled low.

[0120] In this embodiment, when the strobe signals D0 to D7 are all low and the first clock signal CLK1 is low, the first and second terminals of transistors T2-T9 are both low. However, since the threshold voltage Vth is usually negative, without transistors T10 and T12, transistors T2-T9 may not be completely turned off, resulting in Vgs being less than 0. This would cause the potential of the first node P to become low under the influence of the first clock signal CLK1. The transistors T10 and T12 in the shift register of this disclosure are turned off under the control of the low potential of the third node QB, thus preventing leakage caused by the first node P being connected to a low potential through transistors T2 to T9.

[0121] Furthermore, when the second node Q1 is high, transistors T17 and T19 are turned on. Since transistors T15, T16, and T18 are relatively small, when transistor T17 is on, the control electrode of transistor T18 drops to a negative voltage, operating in the saturation region. When transistor T19 is on, it operates in the linear region. Therefore, controlling the third node QB to low, the second control circuit 340 achieves the effect of potential inversion.

[0122] In the third stage S3, the first clock signal CLK1 and the second clock signal CLK2 remain at a low level.

[0123] Under the control of the second clock signal CLK2, the potentials of the fourth node Q and the second node Q1 remain high, while the potential of the third node QB is low. Under the control of the high level of the second node Q1, transistors T28, T30, T32, and T34 are turned on.

[0124] Clock signal CLKE1 is provided to output terminal SCout(i) through transistor T28, therefore the scan signal output by output terminal SCout(i) is the same as clock signal CLKE1. Clock signal CLKE2 is provided to output terminal SCout(i+1) through transistor T30, therefore the scan signal output by output terminal SCout(i+1) is the same as clock signal CLKE2. Clock signal CLKE3 is provided to output terminal SCout(i+2) through transistor T32, therefore the scan signal output by output terminal SCout(i+2) is the same as clock signal CLKE3. Clock signal CLKE4 is provided to output terminal SCout(i+3) through transistor T34, therefore the scan signal output by output terminal SCout(i+3) is the same as clock signal CLKE4.

[0125] Due to the bootstrap effect of capacitors C3, C4, C5, and C6, after transistor T28 is turned on, capacitor C3 couples the high level of output terminal SCout(i) to the second node Q1. After transistor T30 is turned on, capacitor C4 couples the high level of output terminal SCout(i+1) to the second node Q1. After transistor T32 is turned on, capacitor C5 couples the high level of output terminal SCout(i+2) to the second node Q1. After transistor T30 is turned on, capacitor C6 couples the high level of output terminal SCout(i+3) to the second node Q1.

[0126] Since transistors T28, T30, T32, and T34 are all controlled by the second node Q1, the high potential of the second node Q1 is gradually dissipated as the potential of the second node Q1 is sequentially supplied to the control terminals of transistors T28, T30, T32, and T34. Therefore, the control capability of transistors T28, T30, T32, and T34 may gradually weaken.

[0127] Through the bootstrap effect of capacitors C3, C4, C5, and C6, the potential of the second node Q2 can be further increased, thereby achieving stable control of the control electrodes of transistors T28, T30, T32, and T34.

[0128] When the clock signal CLKE1 is output at the output terminal SCout(i), capacitor C3 pulls the potential of the second node Q1 high. When the clock signal CLKE2 is output at the output terminal SCout(i+1), capacitor C4 pulls the potential of the second node Q1 high. At this time, during the process of the clock signal CLKE1 being output at the output terminal SCout(i), the stable high level of the second node Q1 controls the output, and then the bootstrap effect of capacitors C3 and C4 raises the high potential of the second node Q1, thereby controlling the output terminal SCout(i) to stably output the scan signal and reduce noise.

[0129] The process of outputting the scan signal at the output terminals SCout(i+1) and SCout(i+2) is similar, and will not be elaborated further for the sake of simplicity.

[0130] When the clock signal CLKE4 is output at the output terminal SCout(i+2), capacitors C5 and 6 pull the potential of the second node Q1 high. However, when the clock signal CLKE2 output at the output terminal SCout(i+1) transitions from high to low, the bootstrap effect of capacitor C5 on the second node Q1 disappears, and the potential of the second node Q1 drops. At this time, the clock signal CLKD is high, and capacitor C7, through its bootstrap effect, can couple the high level of the clock signal CLKD to the second node Q1, thereby ensuring that the second node Q1 can control transistor T35 to be in a stable conducting state, reducing the noise of the clock signal CLKE4 output at the output terminal SCout(i+2).

[0131] At the end of the third stage S3, as capacitor C1 finishes discharging, the potential of the first node P becomes low under the control of the low level of the first clock signal CLK1. The gating stage of the shift register ends, and the output terminals SCout(i), SCout(i+1), SCout(i+2), and SCout(i+3) maintain a low-level output signal.

[0132] In the fourth stage S4, the first clock signal CLK1 is at a high level.

[0133] Under the control of the first clock signal CLK1, transistors T26 and T27 are turned on. The fourth power supply voltage LVGL is supplied to the fourth node Q through transistors T27 and T26, causing the potential of the fourth node Q to be pulled low.

[0134] Under the control of the first clock signal CLK1, transistor T1 is turned on, and the first power supply voltage VGH is provided to the first node P through transistor T11, making the potential of the first node P high, and simultaneously recharging the capacitor C1 that was discharged in the third stage S3. At this time, transistor T22 is turned on, and the potential of the second node Q1 drops to low.

[0135] Under the control of the low level of the second node Q1, transistors T17 and T19 are turned off, and transistor T18 is turned on. The third power supply voltage GVDD is supplied to the third node QB through transistor T18, making the potential of the third node QB high.

[0136] In the fifth stage S5, the strobe signal D0 of the strobe terminal D0 is at a high level, and the first clock signal CLK1 is at a low level.

[0137] Under the control of the strobe signal D0, transistor T2 is turned on. Under the control of the high level of the third node QB, transistors T10 and T12 are turned on, and the first clock signal CLK1 is provided to the control electrode of transistor T11 through transistors T2 and T10, while transistor T11 is turned off. The first clock signal CLK1 is provided to the first node P through transistors T2 and T12, causing the potential of the first node P to go low.

[0138] Under the control of the low level of the first node P, transistor T22 is turned off, which causes the potential of the second node Q1 to drop to a low level, and transistors T28, T30, T32 and T34 are turned off.

[0139] Under the control of the high level of the third node QB, transistors T29, T31, T33 and T35 are turned on, and the second power supply voltage VGL is provided to the output terminals SCout(i), SCout(i+1), SCout(i+2) and SCout(i+3).

[0140] Under the control of the first clock signal CLK1 and the strobe signal D0, the shift register is in the non-strobe stage at this time.

[0141] In this embodiment, the shift register is selected using 14 signals: strobe signals D0-D7, clock signals CLK1 and CLK2, and clock signals CLKE1 to CLKE4, resulting in a simplified architecture. Each shift register, under the control of the second node Q1, can provide four scan signals. The potential of the second node Q1 is stabilized by capacitor C7, eliminating the need for multiple second nodes to control multiple outputs, thus simplifying the shift register structure. Reducing the number of second nodes Q1 also simplifies the number of pull-down transistors in the pull-down circuit 360, further simplifying the circuit structure.

[0142] Multiple strobe signals can support the selection and display of multiple pixel rows. For example, if the number of strobe signals is 2^n, the decoding bit depth implemented by the strobe signals is n, and the maximum number of rows supported is 2^n. For example, the decoding bit depth implemented by strobe signals D0~D7 and D0'~D7' is 8.

[0143] The drive circuit GOA is composed of shift registers 300, with every two shift registers 300 forming a drive unit. The two shift registers in the same drive unit receive the same strobe signal.

[0144] For example, strobe signals D0 to D7 are inverted signals of strobe signals D0' to D7', respectively. Specifically, strobe signals D0 and D0' are not simultaneously active; strobe signals D1 and D1' are not simultaneously active; strobe signals D2 and D2' are not simultaneously active; strobe signals D3 and D3' are not simultaneously active; strobe signals D4 and D4' are not simultaneously active; strobe signals D5 and D5' are not simultaneously active; strobe signals D6 and D6' are not simultaneously active; and strobe signals D7 and D7' are not simultaneously active.

[0145] In the shift register GOA provided in this embodiment, the 8 strobe signals can support 2048 (28*8) rows of strobes. If the number of rows needs to be increased, each additional strobe signal can support twice the number of rows of strobes.

[0146] During the reverse scan, the clock signal inversely proportional to the first clock signal CLK1 can be provided to the first clock input of the last-stage shift register in the driver circuit, and the clock signal inversely proportional to the second clock signal CLK2 can be provided to the second clock input of the last-stage shift register in the driver circuit. During the reverse scan, the timing sequence of each signal in the five stages S1-S5 of the last-stage shift register is similar to that described in Figure 4A, and will not be repeated for simplicity.

[0147] Figure 4B is a schematic diagram of the signal timing of a shift register according to another embodiment of the present disclosure.

[0148] Figure 4B shows the signal timing provided to the last stage shift register in a cascaded series of shift registers.

[0149] The timing changes of the first clock signal CLK1, the second clock signal CLK2, the strobe signals D0 to D7, the clock signals CLK1 to CLKE4, and the potential changes of the first node P, the third node QB, and the fourth node Q shown in Figure 4B can be referenced from Figure 4A. For the sake of simplicity, similar parts will not be described again.

[0150] As shown in Figure 4B, the clock signal CLKD is high in the second stage S2 and the third stage S3. In this case, when the potential of the second node Q1 is pulled high in the second stage S2, the high potential of the clock signal CLKD is coupled to the second node Q1. Therefore, compared to the potential of the second node Q1 shown in Figure 4A, the potential of the second node Q1 shown in Figure 4B is pulled high twice.

[0151] In this case, the potential of the second node Q1 can be stabilized at a higher potential in advance, thereby controlling the output terminals SCout(i), SCout(i+1), SCout(i+2), and SCout(i+3) to stably output the scan signal and reduce noise.

[0152] Figure 5 is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure.

[0153] As shown in Figure 5, the shift register 500 includes a first control circuit 510, a gating circuit 520, an input circuit 530, a second control circuit 540, an output circuit 550, a pull-down circuit 560, and a reset circuit 570.

[0154] In the embodiments disclosed herein, the first control circuit 510, the gating circuit 520, the second control circuit 540, the pull-down circuit 560, and the reset circuit 570 can be referred to in terms of their structures as described above, and will not be repeated for the sake of brevity.

[0155] In this embodiment of the disclosure, the first terminal of capacitor C7 of input circuit 530 is electrically connected to clock signal CLKE1, and the second terminal of capacitor C7 is electrically connected to second node Q1.

[0156] For example, in a driver circuit consisting of multiple shift registers 500, the first-stage shift register can be electrically connected to clock terminals CLKE1, CLKE2, CLKE3, and CLKE4, outputting clock signals CLKE1, CLKE2, CLKE3, and CLKE4 to the four output terminals respectively. The second-stage shift register can be electrically connected to clock terminals CLKE5, CLKE6, CLKE7, and CLKE8, outputting clock signals CLKE5, CLKE6, CLKE7, and CLKE8 to the four output terminals respectively.

[0157] The previous stage shift register can be electrically connected to the first clock input CLK1 and the second clock input CLK2. The next stage shift register can be electrically connected to clock inputs CLK3 and CLK4.

[0158] The timing of clock signals CLKE1 to CLKE8 and the timing of clock signals CLK1 to CLK4 are shown in Figure 6.

[0159] The previous stage shift register can use the clock signal CLKE5 as the control signal, and the next stage shift register can use the clock signal CLKE1 as the control signal.

[0160] The high levels of clock signals CLKE1 to CLKE8 are sequentially shifted and output, and the high levels of clock signals CLK1 to CLK4 are sequentially shifted and output. Clock signals CLKE1 and CLKE5 are inverted clock signals, and they are not simultaneously active.

[0161] In this embodiment of the disclosure, using clock signals CLKE1 and CLKE5 as control signals can reduce signal traces in the drive circuit, simplify the circuit structure, and reduce the circuit area.

[0162] The potential changes of the first node P, the second node Q1, the third node QB and the fourth node Q shown in Figure 6 can be referenced in Figure 4A. For the sake of simplicity, similar parts will not be described again.

[0163] Figure 7A is a schematic diagram of the structure of a drive circuit according to an embodiment of the present disclosure.

[0164] As shown in Figure 7A, the drive circuit 700 includes M shift registers. For example, the shift registers can be any one of the shift registers 100, 200, 300 and 500 described above.

[0165] In this embodiment of the disclosure, the m-th shift register is electrically connected to the first gating line, and the (m+x)-th shift register is electrically connected to the second gating line. The gating signal output by the first gating line and the gating signal output by the second gating line are not simultaneously active. 1≤m≤Mx, 1≤x<M, where M is a positive integer greater than 1, and m and x are positive integers.

[0166] For example, the strobe input D0 of the first shift register is electrically connected to the strobe signal line d0, and the strobe input D0 of the third shift register is electrically connected to the strobe signal line d0'. The strobe signals provided by the strobe signal lines d0' and d0 are not simultaneously active.

[0167] For example, when the strobe signal d0' is high, the strobe signal d0 is low. When the strobe signal d0 is high, the strobe signal d0' is low.

[0168] In this embodiment of the disclosure, the driving circuit 700 further includes clock lines clke1 to clke8, a first control line clkd1, and a second control line clkd3.

[0169] The control terminal CS of the m-th shift register is electrically connected to the first control line clkd1, and the third clock terminals CLKE1 to CLKE4 of the m-th shift register are electrically connected to the clock lines clke1 to clke4, respectively.

[0170] The control terminal CS of the (m+y)th shift register is electrically connected to the second control line clkd3, and the third clock terminals CLKE1~CLKE4 of the (m+y)th shift register are electrically connected to the clock lines clke5~clke8, where 1≤m≤My, 1≤y<M, and y is a positive integer.

[0171] For example, the control terminal CS of the first shift register GOA1 is electrically connected to the first control line clkd1, and the third clock terminals CLKE1 to CLKE4 of the first shift register GOA1 are electrically connected to clock lines clke1 to clke4, respectively. The control terminal CS of the second shift register GOA2 is electrically connected to the second control line clkd3, and the third clock terminals CLKE1 to CLKE4 of the second shift register GOA2 are electrically connected to clock lines clke5 to clke8.

[0172] In this embodiment of the present disclosure, the control signal CLKD1 output by the first control line clkd1 and the control signal CLKD3 output by the second control line clkd3 are not simultaneously active. The control signal CLKD1 output by the first control line clkd1 can be consistent with the level change of the clock signal CLKE5 output by the clock line clke5, and the control signal CLKD3 output by the second control line clkd3 can be consistent with the level change of the clock signal CLKE1 output by the clock line clke1.

[0173] In some embodiments, the shift registers GOA1 to GOAM of the driving circuit 700 can be referenced to the shift register 300 shown in FIG3. For example, the operation of the shift register GOA1 can be referenced to FIG3 and FIG4A. In this case, the timing of each signal received by the driving circuit 700 can be as shown in FIG7A.

[0174] According to an embodiment of the present disclosure, FIG7A shows the signal changes of clock signals CLK1 to CLK4, clock signals CLKE1 to CLKE8, strobe signals D0 to D7, first node P, second node Q1, second sub-node Q2, third node QB, fourth node Q, and scan signals SCout(1) to SCout(4).

[0175] The timing changes of the first node P, the second node Q1, the second sub-node Q2, the third node QB and the fourth node Q of the scan signals SCout(1) to SCout(4) shown in Figure 7B are similar to the timing changes of the signals described above, and will not be repeated for the sake of brevity.

[0176] In some embodiments, the shift registers GOA1 to GOAM of the driving circuit 700 can be referenced to the shift register 300 shown in FIG3. For example, the operation of the shift register GOA1 can be referenced to FIG3 and FIG4B. In this case, the timing of each signal received by the driving circuit 700 can be as shown in FIG7C.

[0177] The timing changes of the first node P, the second node Q1, the second sub-node Q2, the third node QB and the fourth node Q of the scan signals SCout(1) to SCout(4) shown in Figure 7C are similar to the timing changes of the signals described above, and will not be repeated for the sake of brevity.

[0178] In this embodiment of the present disclosure, the clock signal output by clock line clk3 connected to shift register GOA2 described above has a similar function to the clock signal output by clock line clk1 connected to shift register GOA1 described above. The clock signal output by clock line clk4 connected to shift register GOA2 described above has a similar function to the clock signal output by clock line clk2 connected to shift register GOA1 described above. The clock signals output by clock lines clk5 to clk8 connected to shift register GOA2 described above have a similar function to the clock signals output by clock lines clk1 to clk4 connected to shift register GOA1 described above. The clock signal output by clock line clkd3 connected to shift register GOA2 described above has a similar function to the clock signal output by clock line clkd1 connected to shift register GOA1 described above. For the sake of simplicity, these will not be described in detail again.

[0179] In this embodiment of the disclosure, the driving circuit 700 may include P driving unit groups, and each driving unit group may include multiple shift registers as described in this embodiment of the disclosure. The multiple shift registers included in the driving unit group are connected in the same way as the multiple gate lines.

[0180] For example, drive unit group 710 includes shift register GOA1 and shift register GOA2. Shift register GOA1 and shift register GOA2 are connected in the same way as multiple strobe lines. It should be noted that Figure 7A only schematically shows the structure of each drive unit group in drive circuit 700 including two shift registers.

[0181] In this embodiment of the disclosure, the multiple gate lines may include multiple gate lines d0 to d7 of the first gate group and multiple gate lines d0' to d7' of the second gate group. For example, the shift registers in the p-th drive unit group are all electrically connected to the first gate group, and the shift registers in the (p+1)-th drive unit group are all electrically connected to the second gate group. The gate signal output by the first gate group is opposite to the gate signal output by the second gate group, 1 ≤ p < P, where P is a positive integer greater than 1.

[0182] In the embodiments of this disclosure, the M shift registers do not need to be cascaded, and the output signal is not controlled by other shift registers. When applied to the drive circuit 700, it can realize the output of random frame shift signals.

[0183] In embodiments of this disclosure, the number of gate lines in the first gate group is the same as the number of gate lines in the second gate group, and the number of gate lines in each gate group is the same as the number of gate transistors in the shift register. For example, the first gate group includes 8 gate lines d0 to d7, and the second gate group includes 8 gate lines d0' to d7'.

[0184] Each gate line in the gate group outputs a gate signal that controls a gate transistor. This disclosure does not limit the number of gate lines and gate transistors; the number can be set according to actual needs.

[0185] In the embodiments of this disclosure, the multiple shift registers included in the p-th drive unit group are connected in the same way as the multiple gate lines included in the first gate group, and the multiple shift registers included in the p+1-th drive unit group are connected in the same way as the multiple second gate lines included in the second gate group.

[0186] For example, a driver unit group may include two shift registers, and the shift registers within the group are connected to the strobe terminals in the same way. For two adjacent driver unit groups, the connection methods between the shift registers and the strobe terminals of the different driver unit groups are different.

[0187] For example, strobe signals D0 and D0' cannot be active at the same time; strobe signals D1 and D1' cannot be active at the same time; strobe signals D2 and D2' cannot be active at the same time; strobe signals D3 and D3' cannot be active at the same time; strobe signals D4 and D4' cannot be active at the same time; strobe signals D5 and D5' cannot be active at the same time; strobe signals D6 and D6' cannot be active at the same time; and strobe signals D7 and D7' cannot be active at the same time.

[0188] Figure 8 is a schematic diagram of the structure of a drive circuit according to another embodiment of the present disclosure.

[0189] As shown in Figure 8, the driving circuit 800 includes M shift registers. For example, the shift registers can be any one of the shift registers 100, 200, 300 and 500 described above.

[0190] In the embodiments disclosed herein, the connection relationships between the select terminals D0 to D7 of the shift register and the select lines, the connection relationships between the clock terminals CLK1 and CLK2 and the clock lines clk1 to clk4, and the connection relationships between the clock terminals CLKE1 to CLKE4 and the clock lines clk1 to clk8 can be referred to Figure 7A, and will not be elaborated further for the sake of brevity.

[0191] In this embodiment of the disclosure, the control terminal CS of the m-th shift register is electrically connected to the clock line clke5, and the control terminal CS of the (m+y)-th shift register is electrically connected to the clock line clke1, where 1≤m≤My, 1≤y<M, and y is a positive integer;

[0192] For example, the control terminal CS of the first shift register GOA1 is electrically connected to the clock line clke5, and the control terminal CS of the second shift register GOA2 is electrically connected to the clock line clke1.

[0193] In this embodiment of the disclosure, the clock signal CLKE5 of clock line clke5 and the clock signal CLKE1 output by clock line clke1 are not both at an active level.

[0194] In some embodiments, the shift registers GOA1 to GOAM of the driving circuit 800 can be referenced to the shift register 500 shown in FIG. 5. For example, the operation of the shift register GOA1 can be referenced to FIG. 5 and FIG. 6. In this case, the timing of each signal received by the driving circuit 800 can be as shown in FIG. 6.

[0195] In this embodiment of the present disclosure, the clock signal output by clock line clk3 connected to shift register GOA2 described above has a similar function to the clock signal output by clock line clk1 connected to shift register GOA1 described above. The clock signal output by clock line clk4 connected to shift register GOA2 described above has a similar function to the clock signal output by clock line clk2 connected to shift register GOA1 described above. The clock signals output by clock lines clk5 to clk8 connected to shift register GOA2 described above have a similar function to the clock signals output by clock lines clk1 to clk4 connected to shift register GOA1 described above. The clock signal output by clock line clk1 connected to shift register GOA2 described above has a similar function to the clock signal output by clock line clk5 connected to shift register GOA1 described above. For the sake of brevity, these details will not be repeated.

[0196] In this embodiment of the disclosure, the driving circuit 800 may also include P driving unit groups, each driving unit group may include multiple shift registers as described in this embodiment of the disclosure. The multiple shift registers included in the driving unit group are connected in the same way as the multiple gate lines.

[0197] For example, the drive unit group 810 can refer to the drive unit group 710 described above, and will not be repeated for the sake of brevity.

[0198] Figure 9 is a schematic diagram of the structure of a display device according to an embodiment of the present disclosure.

[0199] As shown in Figure 9, the display device 900 includes a display panel 910 and a driving circuit 920.

[0200] In this embodiment of the disclosure, the display panel 910 includes a plurality of sub-pixel units arranged in an array, and a driving circuit is used to drive the sub-pixel units. Each row of pixel units Piexl in the display panel 910 forms a pixel row 911.

[0201] In this embodiment, the driving circuit 920 can be the driving circuit 700 and driving circuit 800 described above, and will not be repeated here. A shift register 921 in the driving circuit 920 can drive a pixel row 911, thereby controlling whether a single pixel row is selected.

[0202] It should be noted that the number of subpixel units included in the display panel 910 is for illustrative purposes only, and this disclosure does not limit the number of subpixel units.

[0203] The driver circuit 920 includes multiple shift registers that support gating, each shift register being connected to sub-pixel units in a different row. When it is necessary to refresh the sub-pixel units in a certain row, the driver circuit can select the corresponding shift register to refresh the specified row of sub-pixel units.

[0204] Figure 10 is a flowchart of a driving method according to an embodiment of the present disclosure.

[0205] As shown in Figure 10, the driving method may include operations S1010-S1020.

[0206] In the embodiments of this disclosure, the driving method can be applied to the shift register 100, shift register 200, shift register 300 and shift register 500 described above.

[0207] During operation S1010, during the duration of the first level of the q-th clock sub-signal, the (q+1)-th clock sub-signal transitions from the second level to the first level. 1 ≤ q ≤ Q-1, where q is an integer.

[0208] During operation S1020, during the duration of the first level of the Q-th clock sub-signal, the control signal jumps from the second level to the first level.

[0209] In this embodiment of the disclosure, operations S1010-S1020 are similar to those performed by shift registers 300 and 500 as described above, and will not be repeated here.

[0210] In this embodiment of the disclosure, the third clock signal includes Q clock sub-signals whose effective levels are sequentially shifted, where Q is a positive integer. The first clock signal and the control signal are not simultaneously active. For example, the third clock signal includes clock signals CLKE1 to CLKE4. The first clock signal can be clock signal CLKE1.

[0211] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0212] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0213] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A shift register, comprising: The first control circuit is configured to provide a first power supply voltage of the first power supply to the first node under the control of a first clock signal from a first clock terminal; The gating circuit is configured to provide the first clock signal to the first node under the control of multiple gating signals from multiple gating terminals; The input circuit is configured to provide the first power supply voltage to the second node under the control of the potential of the first node and a second clock signal from the second clock terminal, and to control the potential of the second node using a control signal from the control terminal; The second control circuit is configured to provide the third power supply voltage of the third power supply or the fourth power supply voltage of the fourth power supply to the third node under the control of the potential of the second node and the second power supply voltage of the second power supply. The output circuit is configured to provide a third clock signal from the third clock terminal or the second power supply voltage to the output terminal as an output scan signal, under the control of the potentials of the second node and the third node.

2. The shift register according to claim 1, wherein, The input circuit is electrically connected to the first power supply, the second clock terminal, the control terminal, the first node, the second node, and the fourth node; The input circuit is configured as follows: Under the control of the second clock signal, the first power supply voltage is provided to the fourth node; Under the control of the potential of the first node, the potential of the fourth node is provided to the second node; as well as Under the control of the control signal, the control signal is coupled to the second node.

3. The shift register according to claim 1, wherein, The third clock terminal includes a first sub-clock terminal and a second sub-clock terminal, and the output terminal includes a first sub-output terminal and a second sub-output terminal; the output circuit is configured as follows: Under the control of the potential of the second node, the first clock sub-signal from the first sub-clock terminal is output to the first sub-output terminal; as well as Under the control of the potential of the second node, the second clock sub-signal from the second sub-clock terminal is output to the second sub-output terminal; During the duration of the first level of the second clock sub-signal, the first clock sub-signal changes from the first level to the second level, and the control signal changes from the second level to the first level.

4. The shift register according to claim 1, further comprising: The pull-down circuit is electrically connected to the first node, the second node, the third node, the second clock terminal, and the fourth power supply. The pull-down circuit is configured as follows: Under the control of the potential of the first node and the second clock signal, the fourth power supply voltage is provided to the potential of the third node; as well as Under the control of the third node, the fourth power supply voltage is provided to the second node.

5. The shift register according to claim 1, further comprising: The reset circuit is electrically connected to the first clock terminal, the fourth node, and the fourth power supply. The reset circuit is configured to provide the fourth power supply voltage to the fourth node under the control of the first clock signal.

6. The shift register according to claim 1, wherein, The gating circuit is electrically connected to the plurality of gating terminals and the first node, and the gating circuit is configured to: Under the control of the first level of any one of the plurality of strobe signals, the first clock signal is provided to the first node.

7. The shift register according to claim 6, wherein, The gating circuit is also electrically connected to the third node, and the gating circuit is further configured to; Under the control of the first level of the third node and the first level of any one of the plurality of strobe signals, the first clock signal is provided to the potential of the first node.

8. The shift register according to claim 1, wherein, The input circuit includes a first transistor, a second transistor, and a first capacitor; Wherein, the control electrode of the first transistor is electrically connected to the second clock terminal, the first electrode of the first transistor is electrically connected to the first power supply, and the second electrode of the first transistor is electrically connected to the fourth node. The control electrode of the second transistor is electrically connected to the first node, the first electrode of the second transistor is electrically connected to the fourth node, and the second electrode of the second transistor is electrically connected to the second node; and The first terminal of the first capacitor is the control terminal, and the second terminal of the first capacitor is electrically connected to the second node.

9. The shift register according to claim 1, wherein, The gating circuit includes a third transistor, a fourth transistor, and multiple gating transistors; The control electrode of the third transistor is electrically connected to the third node, the first electrode of the third transistor is electrically connected to the first control circuit, and the second electrode of the third transistor is electrically connected to the first electrode of the plurality of gate transistors. The control electrode of the fourth transistor is electrically connected to the third node, the first electrode of the fourth transistor is electrically connected to the first node, and the second electrode of the fourth transistor is electrically connected to the first electrode of the plurality of gating transistors; the control electrodes of the plurality of gating transistors are respectively electrically connected to the plurality of gating terminals, and the second electrodes of the plurality of gating transistors are electrically connected to the first clock terminal.

10. The shift register according to claim 4, wherein, The pull-down circuit includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor; Wherein, the control electrode of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the third node, and the second electrode of the fifth transistor is electrically connected to the first electrode of the sixth transistor; The control electrode of the sixth transistor is electrically connected to the first clock terminal, and the second electrode of the sixth transistor is electrically connected to the fourth power supply. The control electrode of the seventh transistor and the control electrode of the eighth transistor are electrically connected to the third node; The seventh transistor is connected in series with the eighth transistor, the first terminal of the seventh transistor is electrically connected to the second node, and the second terminal of the eighth transistor is electrically connected to the fourth power supply; The control electrode of the ninth transistor is electrically connected to the second node, the first electrode of the ninth transistor is electrically connected to the second electrode of the seventh transistor, and the second electrode of the ninth transistor is electrically connected to the first power supply.

11. The shift register according to claim 1, wherein, The first control circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor, a second capacitor, and a third capacitor; The control electrode of the tenth transistor is electrically connected to the first clock terminal, the first electrode of the tenth transistor is electrically connected to the first power supply, and the second electrode of the tenth transistor is electrically connected to the control electrode of the eleventh transistor. The first electrode of the eleventh transistor is electrically connected to the first power supply, and the second electrode of the eleventh transistor is electrically connected to the first node; The control electrode of the twelfth transistor is electrically connected to the first node, the first electrode of the twelfth transistor is electrically connected to the first power supply, and the second electrode of the twelfth transistor is electrically connected to the gating circuit; The first terminal of the second capacitor is electrically connected to the control electrode of the eleventh transistor, and the second terminal of the second capacitor is electrically connected to the first node; and The first terminal of the third capacitor is electrically connected to the first power source, and the second terminal of the third capacitor is electrically connected to the first node.

12. The shift register according to claim 1, wherein, The second control circuit includes a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor; The control electrode and the first electrode of the thirteenth transistor are electrically connected to the third power supply, and the second electrode of the thirteenth transistor is electrically connected to the first electrode of the fourteenth transistor. The control electrode of the fourteenth transistor is electrically connected to the third power supply, and the second electrode of the fourteenth transistor is electrically connected to the control electrode of the sixteenth transistor; The control electrode of the fifteenth transistor is electrically connected to the second node, the first electrode of the fifteenth transistor is electrically connected to the control electrode of the sixteenth transistor, and the second electrode of the fifteenth transistor is electrically connected to the second power supply. The first electrode of the sixteenth transistor is electrically connected to the third power supply, and the second electrode of the sixteenth transistor is electrically connected to the third node; The control electrode of the seventeenth transistor is electrically connected to the second node, the first electrode of the seventeenth transistor is electrically connected to the third node, and the second electrode of the seventeenth transistor is electrically connected to the fourth power supply.

13. The shift register according to claim 5, wherein, The output circuit includes an eighteenth transistor and a nineteenth transistor; The eighteenth and nineteenth transistors are connected in series, their control electrodes are electrically connected to the first clock terminal, the first electrode of the eighteenth transistor is electrically connected to the fourth node, and the second electrode of the nineteenth transistor is electrically connected to the fourth power supply.

14. A driving circuit, comprising: M shift registers as described in any one of claims 1-13; The m-th shift register is electrically connected to the first gating line, and the (m+x)-th shift register is electrically connected to the second gating line. The gating signals output by the first gating line and the gating signals output by the second gating line are not simultaneously active. 1 ≤ m ≤ Mx, 1 ≤ x < M, where M is a positive integer greater than 1, and m and x are positive integers.

15. The driving circuit according to claim 14 further includes a first clock line, a second clock line, a first control line, and a second control line; in, The control terminal of the m-th shift register is electrically connected to the first control line, and the third clock terminal of the m-th shift register is electrically connected to the first clock line. The control terminal of the (m+y)th shift register is electrically connected to the second control line, and the third clock terminal of the (m+y)th shift register is electrically connected to the second clock line. 1≤m≤My, 1≤y<M, and y is a positive integer. Specifically, the control signal output from the first control line and the control signal output from the second control line are not simultaneously active; the level change of the control signal output from the first control line is consistent with the level change of the clock signal output from the second clock line; and the level change of the control signal output from the second control line is consistent with the level change of the clock signal output from the first clock line.

16. The driving circuit according to claim 14 further includes a first clock line and a second clock line; in, The third clock terminal of the m-th shift register is electrically connected to the first clock line, and the control terminal of the m-th shift register is electrically connected to the second clock line. The third clock terminal of the (m+y)th shift register is electrically connected to the second clock line, and the control terminal of the (m+y)th shift register is electrically connected to the first clock line, where 1≤m≤My, 1≤y<M, and y is a positive integer; The clock signal output from the first clock line and the clock signal output from the second clock line are not both at an active level.

17. The driving circuit according to claim 14, wherein, It includes P groups of drive units, where P is a positive integer, and each group of drive units includes a plurality of shift registers as described in any one of claims 1-13; The drive unit group includes multiple shift registers and multiple strobe lines connected in the same way.

18. A display device, comprising: Display panel; as well as The driving circuit as described in any one of claims 14-17; The display panel includes multiple sub-pixel units arranged in an array, and the driving circuit is used to drive the sub-pixel units.

19. A driving method applied to a shift register as described in any one of claims 1-13, comprising: During the duration of the first level of the qth clock sub-signal, the (q+1)th clock sub-signal jumps from the second level to the first level, 1≤q≤Q-1, where q is an integer; During the duration of the first level of the Q-th clock sub-signal, the control signal jumps from the second level to the first level; The third clock signal includes Q clock sub-signals whose effective levels are shifted sequentially, where Q is a positive integer; the first clock signal and the control signal are not simultaneously at the effective level.

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