Array substrate, manufacturing method, and display device
By simplifying the patterning and etching processes of the array substrate, reducing the number of film layers and the thickness of the insulating layer, the problems of complex and thick array substrate fabrication are solved, achieving efficient production and thinning.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- BOE TECHNOLOGY GROUP CO LTD
- Filing Date
- 2026-01-04
- Publication Date
- 2026-07-23
AI Technical Summary
The existing array substrate manufacturing process is complex and cumbersome, and the large number of film layers results in a thicker substrate, which is not conducive to thinning and is also more costly and less efficient.
By employing a 9-layer patterning process and a 2-layer etching process, and by setting the transition part and the gate of the driving transistor in the same layer, the number of patterning processes is reduced, the process cost is lowered, the number of film layers is reduced, and the thickness of the third insulating layer is reduced.
It simplifies the manufacturing process of array substrates, improves production efficiency, reduces production costs, and enables array substrates to be made thinner and lighter.
Smart Images
Figure CN2026070168_23072026_PF_FP_ABST
Abstract
Description
Array substrate, manufacturing method and display device
[0001] Cross-references to related applications
[0002] This application claims priority to Chinese Patent Application No. 202510062915.3, filed on January 15, 2025, with the State Intellectual Property Office of the People's Republic of China, entitled "Array Substrate, Manufacturing Method and Display Device", the entire contents of which are incorporated herein by reference. Technical Field
[0003] This invention relates to the field of display technology, and in particular to array substrates, manufacturing methods, and display devices. Background Technology
[0004] Organic light-emitting diodes (OLEDs), quantum dot light-emitting diodes (QLEDs), micro light-emitting diodes (Micro LEDs), and mini light-emitting diodes (Mini LEDs) are among the light-emitting devices that possess advantages such as self-illumination and low energy consumption, making them a hot topic in current display device application research. Generally, pixel circuits are used in display devices to drive the light-emitting devices to emit light. Summary of the Invention
[0005] The array substrate provided in this embodiment includes: a substrate including a plurality of pixel circuits;
[0006] The pixel circuit includes: a driving transistor and a first capacitor; the gate of the driving transistor is electrically connected to the first plate of the first capacitor through a first adapter, the first electrode of the driving transistor is electrically connected to a first node, and the second electrode of the driving transistor is electrically connected to the second plate of the first capacitor through a second adapter.
[0007] The first transition portion, the gate of the driving transistor, and the second transition portion are disposed on the same layer.
[0008] In some possible implementations, the first adapter, the first electrode of the first capacitor, and the second electrode of the first capacitor overlap each other in their orthogonal projections onto the substrate.
[0009] In some possible implementations, the second adapter, the first electrode of the first capacitor, and the second electrode of the first capacitor overlap each other in their orthogonal projections onto the substrate.
[0010] In some possible implementations, the orthographic projection of the second adapter onto the substrate does not overlap with the orthographic projections of the first adapter and the gate of the driving transistor onto the substrate.
[0011] In some possible implementations, the pixel circuit further includes: a second capacitor;
[0012] The first plate of the second capacitor is electrically connected to the first power signal line, and the second plate of the second capacitor is electrically connected to the second plate of the first capacitor through the second adapter.
[0013] The second adapter is located on the same layer as the first adapter.
[0014] In some possible implementations, the first plate of the second capacitor, the first plate of the first capacitor, and the first power signal line are located on the same layer.
[0015] The second plate of the second capacitor is located on the same layer as the second plate of the first capacitor.
[0016] In some possible implementations, the orthographic projection of the second adapter onto the substrate overlaps with the orthographic projections of the first electrode of the second capacitor and the second electrode of the second capacitor onto the substrate.
[0017] In some possible implementations, the first plate of the second capacitor, the second plate of the second capacitor, and the gate of the driving transistor overlap each other in their orthogonal projections onto the substrate.
[0018] In some possible implementations, the pixel circuit further includes: a first transistor;
[0019] The gate of the first transistor is electrically connected to the first reset signal line, the first terminal of the first transistor is electrically connected to the first initialization signal line through the third adapter, and the second terminal of the first transistor is electrically connected to the gate of the driving transistor through the first adapter.
[0020] The third adapter, the first reset signal line, and the first adapter are located on the same layer.
[0021] In some possible implementations, the orthographic projection of the third adapter onto the substrate overlaps with the orthographic projection of the first initialization signal line onto the substrate.
[0022] In some possible implementations, the first initialization signal line and the first power signal line are located on the same layer.
[0023] In some possible implementations, the first capacitor further includes a third plate; the second electrode of the first transistor is multiplexed as the third plate of the first capacitor, and the third plate is electrically connected to the first plate of the first capacitor through the first adapter.
[0024] In some possible implementations, the pixel circuit further includes: a second transistor;
[0025] The gate of the second transistor is electrically connected to the first scan signal line, the first terminal of the second transistor is electrically connected to the gate of the driving transistor through the first adapter, and the second terminal of the second transistor is electrically connected to the data signal line.
[0026] The first scan signal line and the first adapter are located on the same layer, while the first scan signal line and the data signal line are located on different layers.
[0027] In some possible implementations, the pixel circuit further includes a third transistor;
[0028] The gate of the third transistor is electrically connected to the first light-emitting control signal line, the first electrode of the third transistor is electrically connected to the first power signal line through the fourth adapter, and the second electrode of the third transistor is electrically connected to the first node.
[0029] The first adapter, the fourth adapter, and the first light emission control signal line are located on the same layer.
[0030] In some possible implementations, the orthographic projection of the fourth adapter onto the substrate overlaps with the orthographic projection of the first power signal line onto the substrate.
[0031] In some possible implementations, the pixel circuit further includes a fourth transistor;
[0032] The gate of the fourth transistor is electrically connected to the second light-emitting control signal line, the first electrode of the fourth transistor is electrically connected to the second plate of the first capacitor through the fifth adapter, and the second electrode of the fourth transistor is electrically connected to the second node.
[0033] The first adapter, the fifth adapter, and the second light emission control signal line are located on the same layer.
[0034] In some possible implementations, the fifth adapter is positioned between the first reset signal line and the first initialization signal line in the orthographic projection of the substrate.
[0035] In some possible implementations, the pixel circuit further includes: a fifth transistor;
[0036] The gate of the fifth transistor is electrically connected to the second reset signal line, the first terminal of the fifth transistor is electrically connected to the second node, and the second terminal of the fifth transistor is electrically connected to the second initialization signal line through the sixth adapter.
[0037] The fifth adapter, the sixth adapter, and the second reset signal line are located on the same layer.
[0038] In some possible implementations, the orthographic projection of the sixth adapter onto the substrate overlaps with the orthographic projection of the second initialization signal line onto the substrate.
[0039] In some possible implementations, the second initialization signal line is located on the same layer as the second plate of the first capacitor.
[0040] In some possible implementations, the first power signal line, the first light emission control signal line, the first scan signal line, the first reset signal line, the first initialization signal line, the second light emission control signal line, the second reset signal line, and the second initialization signal line all extend along a first direction;
[0041] The first power signal line, the first light emission control signal line, the first scan signal line, the first reset signal line, the first initialization signal line, the second light emission control signal line, the second reset signal line, and the second initialization signal line are arranged at intervals along the second direction.
[0042] The first direction and the second direction are intersected.
[0043] The display device provided in this disclosure includes the array substrate described above.
[0044] The method for fabricating the array substrate described above, as provided in this embodiment, includes:
[0045] A first conductive layer, a second conductive layer, a semiconductor layer, and a third conductive layer are sequentially formed on the substrate to form a pixel circuit located on the substrate.
[0046] Wherein, the first conductive layer includes the first electrode of the first capacitor; the second conductive layer includes the second electrode of the first capacitor; the semiconductor layer includes the active layer of the driving transistor; and the third conductive layer includes the gate of the driving transistor, the first transition portion, and the second transition portion. Attached Figure Description
[0047] Figure 1 shows some structural schematic diagrams of array substrates in related technologies;
[0048] Figure 2 shows some other structural schematic diagrams of array substrates in related technologies;
[0049] Figure 3 is a schematic diagram of some structures of the array substrate provided in the embodiments of this disclosure;
[0050] Figure 4 is a schematic diagram of some other structures of the array substrate provided in the embodiments of this disclosure;
[0051] Figure 5 is a schematic diagram of some structures of the pixel circuit provided in the embodiments of this disclosure;
[0052] Figure 6 is a schematic diagram of some layout structures of pixel circuits provided in the embodiments of this disclosure;
[0053] Figure 7 is a schematic diagram of some other layout structures of the pixel circuit provided in the embodiments of this disclosure;
[0054] Figure 8 is a schematic diagram of some further layout structures of the pixel circuit provided in the embodiments of this disclosure;
[0055] Figure 9 is a schematic diagram of some further layout structures of the pixel circuit provided in the embodiments of this disclosure;
[0056] Figure 10 is a schematic diagram of some further layout structures of the pixel circuit provided in the embodiments of this disclosure;
[0057] Figure 11 is a schematic diagram of some further layout structures of the pixel circuit provided in the embodiments of this disclosure;
[0058] Figure 12 is a schematic diagram of some layout structures of the pixel circuit provided in the embodiments of this disclosure;
[0059] Figure 13 is a schematic diagram of some layout structures of the pixel circuit provided in the embodiments of this disclosure;
[0060] Figure 14 is a schematic diagram of some further layout structures of the pixel circuit provided in the embodiments of this disclosure;
[0061] Figure 15 is a schematic diagram of some other structures of the pixel circuit provided in the embodiments of this disclosure. Detailed Implementation
[0062] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Furthermore, the embodiments and features in the embodiments of the present invention can be combined with each other without conflict. Based on the described embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0063] Unless otherwise defined, the technical or scientific terms used in this invention shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.
[0064] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of the invention. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.
[0065] In related technologies, the specific process flow for patterning and etching processes required on the array substrate is shown in Table 1 below.
[0066] Table 1
[0067] In related technologies, as shown in Figure 1 and Table 1, the fabrication method of an array substrate generally includes: forming a first insulating layer 101 on a substrate 100; forming a first conductive layer 102 (e.g., Gate 1 in Table 1) on the side of the first insulating layer 101 facing away from the substrate 100; forming a second insulating layer 103 on the side of the first conductive layer 102 (e.g., Gate 1 in Table 1) facing away from the substrate 100; forming a second conductive layer 104 (e.g., Gate 2 in Table 1) on the side of the second insulating layer 103 facing away from the substrate 100; forming a third insulating layer 105 on the side of the second conductive layer 104 (e.g., Gate 2 in Table 1) facing away from the substrate 100; and forming a third insulating layer 105 on the side of the third insulating layer 105 facing away from the substrate 100. A semiconductor layer 106 (e.g., IGZO in Table 1) is formed. A fourth insulating layer 107 is formed on the side of the semiconductor layer 106 (e.g., IGZO in Table 1) facing away from the substrate 100. A third conductive layer 108 (e.g., Gate 3 in Table 1) is formed on the side of the fourth insulating layer 107 facing away from the substrate 100. A fifth insulating layer 109 is formed on the side of the third conductive layer 108 (e.g., Gate 3 in Table 1) facing away from the substrate 100. After forming the fifth insulating layer 109, a first via layer (e.g., ILD-L in Table 1) and a second via layer (e.g., ILD-O in Table 1) are formed sequentially according to design requirements. Then, the third conductive layer 108 can connect to the first via layer (e.g., ILD-L in Table 1) and the first... The conductive layer 102 or the second conductive layer 104 are electrically connected. The third conductive layer 108 can be electrically connected to the semiconductor layer 106 through a second via layer (e.g., ILD-O in Table 1). A fourth conductive layer 110 (e.g., SD1 in Table 1) is formed on the side of the fifth insulating layer 109 facing away from the substrate 100. A sixth insulating layer 111 is formed on the side of the fourth conductive layer 110 (e.g., SD1 in Table 1) facing away from the substrate 100. In a subsequent fabrication method, exemplaryly, it further includes: forming a passivation layer (e.g., PVX in Table 1) on the side of the sixth insulating layer 111 facing away from the substrate 100, and forming a first planarization layer (e.g., PLN1 in Table 1) on the side of the passivation layer (e.g., PVX in Table 1) facing away from the substrate 100. A fifth conductive layer (e.g., SD2 in Table 1) is formed on the side of the first planarization layer (e.g., PLN1 in Table 1) facing away from the substrate 100. A second planarization layer (e.g., PLN2 in Table 1) is formed on the side of the fifth conductive layer (e.g., SD2 in Table 1) facing away from the substrate 100. A mask layer (e.g., T-Mask in Table 1) is formed on the side of the second planarization layer (e.g., PLN2 in Table 1) facing away from the substrate 100. An anode layer (e.g., Anode in Table 1) is formed on the side of the mask layer (e.g., T-Mask in Table 1) facing away from the substrate 100. A pixel definition layer (e.g., HPDL in Table 1) is formed on the side of the anode layer (e.g., Anode in Table 1) facing away from the substrate 100.
[0068] It should be noted that, as shown in Figure 1 and Table 1, the following layers can be formed using patterning processes: a first conductive layer 102 (e.g., Gate 1 in Table 1), a second conductive layer 104 (e.g., Gate 2 in Table 1), a semiconductor layer 106 (e.g., IGZO in Table 1), a third conductive layer 108 (e.g., Gate 3 in Table 1), a fourth conductive layer 110 (e.g., SD1 in Table 1), a passivation layer (e.g., PVX in Table 1), a first planarization layer (e.g., PLN1 in Table 1), a fifth conductive layer (e.g., SD2 in Table 1), a second planarization layer (e.g., PLN2 in Table 1), a mask layer (e.g., T-Mask in Table 1), an anode layer (e.g., Anode in Table 1), and a pixel definition layer (e.g., HPDL in Table 1); and a first via layer (e.g., ILD-L in Table 1) and a second via layer (e.g., ILD-O in Table 1). For example, the patterning process may include only photolithography, or it may include both photolithography and etching steps, and may also include other processes such as printing and inkjet printing to form a predetermined pattern; photolithography refers to a process that uses photoresist, photomasks, exposure machines, etc., to form patterns, including processes such as film formation, exposure, and development. In specific implementations, the appropriate patterning process can be selected according to the structure formed in this invention.
[0069] For example, array substrates in related technologies generally require 12-layer patterning and 2-layer etching processes. It can be seen that the manufacturing process of array substrates is relatively complex and cumbersome, which is not conducive to production efficiency and production cost.
[0070] Furthermore, the array substrate in the related technology has a large number of film layers, resulting in a relatively thick array substrate, which is not conducive to achieving thinner and lighter designs. Therefore, the related technology reduces the thickness of the array substrate by reducing the thickness of the third insulating layer 105, as shown in Figures 1 and 2. The thickness of the third insulating layer 105 in Figure 1 is about 4000 Å, and the thickness of the third insulating layer 105 in Figure 2 is about 2500 Å. However, even if the thickness of the third insulating layer 105 is reduced, the overall thinning effect of the array substrate is not very obvious, that is, the thinning effect is small.
[0071] Based on the above problems, this disclosure provides a method for fabricating an array substrate. The specific process flow for patterning and etching processes required on the array substrate is shown in Table 2 or Table 3 below.
[0072] For example, the fabrication method of the array substrate provided in the embodiments of this disclosure can be flexibly changed and adjusted according to the design requirements of the pixel circuit.
[0073] Table 2
[0074] Table 3
[0075] As shown in Figure 3 and Table 2, the method for fabricating the array substrate in this embodiment includes: forming a first insulating layer 101 on a substrate 100; forming a first conductive layer 102 (e.g., Gate 1 in Table 2) on the side of the first insulating layer 101 facing away from the substrate 100; forming a second insulating layer 103 on the side of the first conductive layer 102 (e.g., Gate 1 in Table 2) facing away from the substrate 100; forming a second conductive layer 104 (e.g., Gate 2 in Table 2) on the side of the second insulating layer 103 facing away from the substrate 100; and forming a third insulating layer 105 on the side of the second conductive layer 104 (e.g., Gate 2 in Table 2) facing away from the substrate 100. A semiconductor layer 106 (e.g., IGZO in Table 2) is formed on the side of the third insulating layer 105 facing away from the substrate 100. A fourth insulating layer 107 is formed on the side of the semiconductor layer 106 (e.g., IGZO in Table 2) facing away from the substrate 100. After forming the fourth insulating layer 107, a first via layer (e.g., ILD-1 in Table 2) is formed according to design requirements. A third conductive layer 108 (e.g., Gate 3 in Table 2) is formed on the side of the fourth insulating layer 107 facing away from the substrate 100. The third conductive layer 108 (e.g., Gate 3 in Table 2) can then connect with the first conductive layer 102 and the second conductive layer 108 through the first via layer (e.g., ILD-1 in Table 2). Layer 104 or semiconductor layer 106 are electrically connected. A fifth insulating layer 109 is formed on the side of the third conductive layer 108 (e.g., Gate 3 in Table 2) facing away from the substrate 100. After forming the fifth insulating layer 109, a second via layer (e.g., ILD2 in Table 2) is formed according to design requirements. A fourth conductive layer 110 (e.g., SD1 in Table 2) is formed on the side of the fifth insulating layer 109 facing away from the substrate 100. The fourth conductive layer 110 (e.g., SD1 in Table 2) can then be electrically connected to the third conductive layer 108 (e.g., Gate 3 in Table 2) through the second via layer (e.g., ILD2 in Table 2). A sixth insulating layer 111 is formed on the side facing away from the substrate 100. In the subsequent fabrication method, exemplaryly, it further includes: forming a first planarization layer (e.g., PLN1 in Table 2) on the side of the sixth insulating layer 111 facing away from the substrate 100; forming an anode layer (e.g., Anode in Table 2) on the side of the first planarization layer (e.g., PLN1 in Table 2) facing away from the substrate 100; forming a barrier layer (e.g., A-PDL in Table 2) on the side of the anode layer (e.g., A-PDL in Table 2) facing away from the substrate 100; and forming a pixel definition layer (e.g., HPDL in Table 2) on the side of the barrier layer (e.g., A-PDL in Table 2) facing away from the substrate 100.
[0076] It should be noted that, as shown in Figure 3 and Table 2, a patterning process can be used to form the first conductive layer 102 (e.g., Gate 1 in Table 2), the second conductive layer 104 (e.g., Gate 2 in Table 2), the semiconductor layer 106 (e.g., IGZO in Table 2), the third conductive layer 108 (e.g., Gate 3 in Table 2), the fourth conductive layer 110 (e.g., SD1 in Table 2), the first planarization layer (e.g., PLN1 in Table 2), the anode layer (e.g., Anode in Table 2), the barrier layer (e.g., A-PDL in Table 2), and the pixel definition layer (e.g., HPDL in Table 2); and an etching process can be used to form the first via layer (e.g., ILD-1 in Table 2) and the second via layer (e.g., ILD-2 in Table 2). For example, the patterning process may only include photolithography, or it may include photolithography and etching steps, and may also include other processes such as printing and inkjet printing for forming a predetermined pattern; the photolithography process refers to a process that uses photoresist, photomasks, exposure machines, etc., to form patterns, including film deposition, exposure, and development processes. In specific implementation, the appropriate patterning process can be selected according to the structure formed in this invention.
[0077] As shown in Figure 4 and Table 3, the method for fabricating the array substrate in this embodiment may include: forming a second insulating layer 103 on a substrate 100; forming a second conductive layer 104 (e.g., Gate 2 in Table 2) on the side of the second insulating layer 103 facing away from the substrate 100; forming a third insulating layer 105 on the side of the second conductive layer 104 (e.g., Gate 2 in Table 2) facing away from the substrate 100; forming a semiconductor layer 106 (e.g., IGZO in Table 2) on the side of the third insulating layer 105 facing away from the substrate 100; and forming a semiconductor layer 106 (e.g., IGZO in Table 2) on the side of the third insulating layer 105 facing away from the substrate 100. A fourth insulating layer 107 is formed on one side of the substrate 100. After the fourth insulating layer 107 is formed, a first via layer (e.g., ILD-1 in Table 2) is formed according to design requirements. A third conductive layer 108 (e.g., Gate 3 in Table 2) is formed on the side of the fourth insulating layer 107 facing away from the substrate 100. The third conductive layer 108 (e.g., Gate 3 in Table 2) can be electrically connected to the first conductive layer 102, the second conductive layer 104, or the semiconductor layer 106 through the first via layer (e.g., ILD-1 in Table 2). The third conductive layer 108 (e.g., Gate 3 in Table 2) faces away from the substrate. A fifth insulating layer 109 is formed on one side of substrate 100. After forming the fifth insulating layer 109, a second via layer (e.g., ILD2 in Table 2) is formed according to design requirements. A fourth conductive layer 110 (e.g., SD1 in Table 2) is formed on the side of the fifth insulating layer 109 facing away from substrate 100. The fourth conductive layer 110 (e.g., SD1 in Table 2) can be electrically connected to the third conductive layer 108 (e.g., Gate 3 in Table 2) through the second via layer (e.g., ILD2 in Table 2). A sixth insulating layer 111 is formed on the side of the fourth conductive layer 110 (e.g., SD1 in Table 2) facing away from substrate 100. The subsequent fabrication method, exemplaryly, further includes: forming a first planarization layer (e.g., PLN1 in Table 2) on the side of the sixth insulating layer 111 facing away from the substrate 100; forming an anode layer (e.g., Anode in Table 2) on the side of the first planarization layer (e.g., PLN1 in Table 2) facing away from the substrate 100; forming a barrier layer (e.g., A-PDL in Table 2) on the side of the anode layer (e.g., Anode in Table 2) facing away from the substrate 100; and forming a pixel definition layer (e.g., HPDL in Table 2) on the side of the barrier layer (e.g., A-PDL in Table 2) facing away from the substrate 100.
[0078] It should be noted that, as shown in Figure 4 and Table 3, a patterning process can be used to form the second conductive layer 104 (e.g., Gate 2 in Table 2), the semiconductor layer 106 (e.g., IGZO in Table 2), the third conductive layer 108 (e.g., Gate 3 in Table 2), the fourth conductive layer 110 (e.g., SD1 in Table 2), the first planarization layer (e.g., PLN1 in Table 2), the anode layer (e.g., Anode in Table 2), the barrier layer (e.g., A-PDL in Table 2), and the pixel definition layer (e.g., HPDL in Table 2); and an etching process can be used to form the first via layer (e.g., ILD-1 in Table 2) and the second via layer (e.g., ILD-2 in Table 2). For example, the patterning process may only include photolithography, or it may include photolithography and etching steps, and may also include other processes for forming a predetermined pattern, such as printing and inkjet printing; photolithography refers to a process that uses photoresist, photomasks, exposure machines, etc., including film deposition, exposure, and development processes. In specific implementations, the appropriate patterning process can be selected according to the structure formed in this invention.
[0079] For example, the thickness of the third insulating layer 105 in the practical example of this disclosure is about 1000 Å.
[0080] For example, in the practical embodiment of this disclosure, the resistance of the conductive material used in the third conductive layer is less than the resistance of the conductive material used in the second conductive layer.
[0081] For example, the material of the semiconductor layer includes metal oxide semiconductor materials, such as IGZO (Indium Gallium Zinc Oxide), and of course, other metal oxide semiconductor materials can also be used, which are not limited here. It should be noted that the semiconductor layer includes a source region, a drain region, and a channel region located between the source region and the drain region; wherein, the source region and the drain region can be conductive regions formed by doping with n-type impurities or p-type impurities.
[0082] For example, the material of the conductive layer can be a conductive material. For example, the conductive material may include metal materials or alloy materials such as aluminum, molybdenum, and titanium, or it may include metal oxides, such as indium tin oxide (ITO). The embodiments of this disclosure do not limit the material of each film layer.
[0083] For example, the above-mentioned insulating layer, planarization layer, barrier layer and pixel definition layer are all formed of insulating materials. As needed, organic insulating materials, such as polyimide, resin materials, etc., can be selected, or inorganic insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, etc. The embodiments of this disclosure do not specifically limit the materials of each film layer.
[0084] In summary, the fabrication method of the array substrate in this embodiment employs only a 9-layer patterning process and a 2-layer etching process, or an 8-layer patterning process and a 2-layer etching process. This demonstrates a relatively simple fabrication process, significantly improving production efficiency and reducing production costs. Furthermore, the reduction in the number of film layers on the array substrate and the further reduction in the thickness of the third insulating layer greatly achieves a thinner array substrate, thereby further realizing a lighter and thinner design.
[0085] Based on the above-described method for fabricating an array substrate, the array substrate provided in this embodiment of the present disclosure, as shown in Figures 5 and 6, includes: a substrate 100, which includes a plurality of pixel circuits 200.
[0086] The pixel circuit 200 includes: a driving transistor T0 and a first capacitor C1; the gate of the driving transistor T0 is electrically connected to the first plate of the first capacitor C1 (e.g., C1-1 in FIG6) through a first junction (e.g., Z1 in FIG6), the first electrode of the driving transistor T0 is electrically connected to the first node N1, and the second electrode of the driving transistor T0 is electrically connected to the second plate of the first capacitor C1 (e.g., C1-2 in FIG6) through a second junction (e.g., Z2 in FIG6).
[0087] The first transition section (e.g., Z1 in FIG. 6), the gate of the driving transistor T0, and the second transition section (e.g., Z2 in FIG. 6) are disposed on the same layer.
[0088] By setting the first transition portion, the gate of the driving transistor, and the second transition portion on the same layer, the utilization rate of the layer can be greatly improved, thereby reducing the number of patterning processes, reducing process costs, and improving production efficiency.
[0089] In some embodiments of this disclosure, as shown in FIG6, the orthographic projections of the first adapter Z1, the first electrode C1-1 of the first capacitor, and the second electrode C1-2 of the first capacitor on the substrate 100 overlap each other.
[0090] In some embodiments of this disclosure, as shown in FIG6, the orthographic projections of the second adapter Z2, the first electrode C1-1 of the first capacitor, and the second electrode C1-2 of the first capacitor C1 on the substrate 100 overlap each other.
[0091] In some embodiments of this disclosure, as shown in FIG6, the orthographic projection of the second transition portion Z2 on the substrate 100 does not overlap with the orthographic projection of the first transition portion Z1 and the gate of the driving transistor T0 on the substrate 100.
[0092] In some embodiments of this disclosure, as shown in FIG5 and FIG6, the pixel circuit 200 further includes: a second capacitor C2;
[0093] The first plate of the second capacitor C2 (e.g., C2-1 in Figure 6) is electrically connected to the first power signal line VDD, and the second plate of the second capacitor C2 (e.g., C2-2 in Figure 6) is electrically connected to the second plate of the first capacitor C1 (e.g., C1-2 in Figure 6) through the second adapter (e.g., Z2 in Figure 6).
[0094] The second transition section (e.g., Z2 in Figure 6) is located on the same layer as the first transition section (e.g., Z1 in Figure 6).
[0095] In some embodiments of this disclosure, as shown in FIG6, the first plate C2-1 of the second capacitor, the first plate C1-1 of the first capacitor, and the first power signal line VDD are located on the same layer.
[0096] The second plate C2-2 of the second capacitor is located on the same layer as the second plate C1-2 of the first capacitor.
[0097] In some embodiments of this disclosure, as shown in FIG6, the orthographic projection of the second adapter Z2 on the substrate 100 overlaps with the orthographic projections of the first electrode C2-1 and the second electrode C2-2 of the second capacitor on the substrate 100.
[0098] In some embodiments of this disclosure, as shown in FIG6, the first plate C2-1 of the second capacitor, the second plate C2-2 of the second capacitor, and the gate of the driving transistor T0 overlap each other on the substrate 100.
[0099] In some embodiments of this disclosure, as shown in FIG5 and FIG6, the pixel circuit 200 further includes: a first transistor T1;
[0100] The gate of the first transistor T1 is electrically connected to the first reset signal line Reset1. The first terminal of the first transistor T1 is electrically connected to the first initialization signal line Vinit1 through the third adapter (e.g., Z3 in Figure 6). The second terminal of the first transistor T1 is electrically connected to the gate of the driving transistor T0 through the first adapter (e.g., Z1 in Figure 6).
[0101] The third adapter (e.g., Z3 in Figure 6), the first reset signal line Reset1, and the first adapter (e.g., Z1 in Figure 6) are located on the same layer.
[0102] In some embodiments of this disclosure, as shown in FIG6, the orthographic projection of the third adapter Z3 on the substrate 100 overlaps with the orthographic projection of the first initialization signal line Vinit1 on the substrate 100.
[0103] In some embodiments of this disclosure, as shown in FIG6, the first initialization signal line Vinit1 and the first power signal line VDD are located on the same layer.
[0104] In some embodiments of this disclosure, as shown in Figures 5 and 6, the first capacitor C1 further includes a third plate (e.g., C1-3 in Figure 6); the second electrode of the first transistor T1 is multiplexed as the third plate of the first capacitor C1 (e.g., C1-3 in Figure 6), and the third plate (e.g., C1-3 in Figure 6) is electrically connected to the first plate of the first capacitor C1 (e.g., C1-1 in Figure 6) through a first adapter (e.g., Z1 in Figure 6).
[0105] In the practical example of this disclosure, the second electrode of the first transistor is reused as the third electrode of the first capacitor. This arrangement can increase the capacitance of the first capacitor while saving the space occupied by the first capacitor, thereby improving space utilization.
[0106] In some embodiments of this disclosure, as shown in FIG5 and FIG6, the pixel circuit 200 further includes: a second transistor T2;
[0107] The gate of the second transistor T2 is electrically connected to the first scan signal line Gate1. The first terminal of the second transistor T2 is electrically connected to the gate of the driving transistor T0 through the first adapter (e.g., Z1 in Figure 6). The second terminal of the second transistor T2 is electrically connected to the data signal line DA.
[0108] The first scan signal line Gate1 and the first adapter (e.g., Z1 in Figure 6) are located on the same layer, while the first scan signal line Gate1 and the data signal line DA are located on different layers.
[0109] In some embodiments of this disclosure, as shown in Figures 5 and 6, the pixel circuit 200 further includes a third transistor T3;
[0110] The gate of the third transistor T3 is electrically connected to the first light-emitting control signal line EM1, the first terminal of the third transistor T3 is electrically connected to the first power supply signal line VDD through the fourth adapter (e.g., Z4 in Figure 6), and the second terminal of the third transistor T3 is electrically connected to the first node N1.
[0111] The first adapter (e.g., Z1 in Figure 6), the fourth adapter (e.g., Z4 in Figure 6), and the first light-emitting control signal line EM1 are located on the same layer.
[0112] In some embodiments of this disclosure, as shown in FIG6, the orthographic projection of the fourth adapter Z4 on the substrate 100 overlaps with the orthographic projection of the first power signal line VDD on the substrate 100.
[0113] In some embodiments of this disclosure, as shown in FIG5 and FIG6, the pixel circuit 200 further includes: a fourth transistor T4;
[0114] The gate of the fourth transistor T4 is electrically connected to the second light-emitting control signal line EM2. The first electrode of the fourth transistor T4 is electrically connected to the second electrode plate (e.g., C1-2 in Figure 6) of the first capacitor C1 through the fifth adapter (e.g., Z5 in Figure 6). The second electrode of the fourth transistor T4 is electrically connected to the second node N2.
[0115] The first adapter (e.g., Z1 in Figure 6), the fifth adapter (e.g., Z5 in Figure 6), and the second light-emitting control signal line EM2 are located on the same layer.
[0116] In some embodiments of this disclosure, as shown in FIG6, the orthographic projection of the fifth adapter Z5 on the substrate 100 is located between the orthographic projections of the first reset signal line Reset1 and the first initialization signal line Vinit1 on the substrate 100.
[0117] In some embodiments of this disclosure, as shown in FIG5 and FIG6, the pixel circuit 200 further includes: a fifth transistor T5;
[0118] The gate of the fifth transistor T5 is electrically connected to the second reset signal line Reset2, the first terminal of the fifth transistor T5 is electrically connected to the second node N2, and the second terminal of the fifth transistor T5 is electrically connected to the second initialization signal line Vinit2 through the sixth adapter (e.g., Z6 in Figure 6).
[0119] The fifth adapter (e.g., Z5 in Figure 6), the sixth adapter (e.g., Z6 in Figure 6), and the second reset signal line Reset2 are located on the same layer.
[0120] In some embodiments of this disclosure, as shown in FIG6, the orthographic projection of the sixth adapter Z6 on the substrate 100 overlaps with the orthographic projection of the second initialization signal line Vinit2 on the substrate 100.
[0121] In some embodiments of this disclosure, as shown in FIG6, the second initialization signal line Vinit2 and the second plate C1-2 of the first capacitor are located on the same layer.
[0122] In some embodiments of this disclosure, as shown in FIG5, the array substrate further includes a light-emitting device L. The first electrode of the light-emitting device L is electrically connected to the second node N2, and the second electrode of the light-emitting device L is electrically connected to the second power signal line VSS. Exemplarily, the light-emitting device L can be an electroluminescent diode. For example, the light-emitting device L can include at least one of the following: organic light-emitting diode (OLED), quantum dot light-emitting diode (QLED), micro light-emitting diode (Micro LED), and mini light-emitting diode (Mini LED). Exemplarily, the light-emitting device L can include an anode, a light-emitting layer, and a cathode stacked together. Further, the light-emitting layer can also include film layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. Of course, in practical applications, the specific structure of the light-emitting device L can be determined according to the needs of the actual application, and is not limited here.
[0123] In some embodiments of this disclosure, as shown in FIG6, the first power signal line VDD, the first light emission control signal line EM1, the first scan signal line Gate1, the first reset signal line Reset1, the first initialization signal line Vinit1, the second light emission control signal line EM2, the second reset signal line Reset2, and the second initialization signal line Vinit2 all extend along the first direction F1.
[0124] The first power signal line VDD, the first light emission control signal line EM1, the first scan signal line Gate1, the first reset signal line Reset1, the first initialization signal line Vinit1, the second light emission control signal line EM2, the second reset signal line Reset2, and the second initialization signal line Vinit2 are arranged sequentially at intervals along the second direction F2;
[0125] The first direction F1 and the second direction F2 are intersected.
[0126] For example, as shown in FIG7, the first conductive layer 102 may include: a first power signal line VDD, a first electrode C2-1 of a second capacitor, a first electrode C1-1 of a first capacitor, and a first initialization signal line Vinit1.
[0127] For example, as shown in Figure 7, the first power signal line VDD is integrated with the first plate C2-1 of the second capacitor; the first plate C1-1 of the first capacitor and the first plate C2-1 of the second capacitor are spaced apart along the second direction F2; the first plate C1-1 of the first capacitor and the first initialization signal line Vinit1 are spaced apart along the second direction F2.
[0128] For example, as shown in FIG8, the second conductive layer 104 may include: the second electrode C2-2 of the second capacitor, the second electrode C1-2 of the first capacitor, and the second initialization signal line Vinit2.
[0129] For example, as shown in Figure 8, the second plate C2-2 of the second capacitor, the second plate C1-2 of the first capacitor, and the second initialization signal line Vinit2 are arranged sequentially at intervals along the second direction F2.
[0130] For example, as shown in FIG9, the semiconductor layer 106 may include: an active layer T0-O for driving transistors, an active layer T1-O for a first transistor, an active layer T2-O for a second transistor, an active layer T3-O for a third transistor, an active layer T4-O for a fourth transistor, an active layer T5-O for a fifth transistor, and a third plate C1-3 for a first capacitor.
[0131] For example, the active layer T0-O of the driving transistor and the active layer T3-O of the third transistor are integrated; the active layer T4-O of the fourth transistor and the active layer T5-O of the fifth transistor are integrated.
[0132] In the practical example of this disclosure, the source or drain region in the active layer of the first transistor can be reused as the third plate of the first capacitor. This arrangement can increase the capacitance of the first capacitor while saving the space occupied by the first capacitor, thereby improving space utilization.
[0133] For example, as shown in FIG10, the third conductive layer 108 may include: the gate T0-G of the driving transistor, the gate T1-G of the first transistor, the gate T2-G of the second transistor, the gate T3-G of the third transistor, the gate T4-G of the fourth transistor, the gate T5-G of the fifth transistor, the first light emission control signal line EM1, the first scan signal line Gate1, the first reset signal line Reset1, the second light emission control signal line EM2, the second reset signal line Reset2, the first adapter Z1, the second adapter Z2, the third adapter Z3, the fourth adapter Z4, the fifth adapter Z5, and the sixth adapter Z6.
[0134] It should be noted that the first light emission control signal line EM1 is multiplexed as the gate T3-G of the third transistor, the first scan signal line Gate1 is multiplexed as the gate T2-G of the second transistor, the first reset signal line Reset1 is multiplexed as the gate T1-G of the first transistor, the second light emission control signal line EM2 is multiplexed as the gate T4-G of the fourth transistor, and the second reset signal line Reset2 is multiplexed as the gate T5-G of the fifth transistor.
[0135] In this embodiment, multiple transition sections, gates of multiple transistors, a first light-emitting control signal line, a first scan signal line, a first reset signal line, a second light-emitting control signal line, and a second reset signal line are all disposed on the third conductive layer, which greatly improves the utilization rate of the third conductive layer, thereby saving space, reducing the number of film layers, reducing process complexity and process cost, and improving production efficiency.
[0136] Furthermore, in the practical example of this disclosure, the resistance of the conductive material used in the third conductive layer is less than that of the conductive material used in the second conductive layer, which can reduce the switching resistance of the transition part, avoid signal loss, improve signal transmission efficiency, and thus improve the display effect.
[0137] For example, as shown in FIG11, the fourth conductive layer 110 may include: a data signal line DA, a first initialization signal line Vinit1, a second power signal line VSS, and a second initialization signal line Vinit2.
[0138] For example, as shown in Figure 11, the data signal line DA, the first initialization signal line Vinit1, the second power signal line VSS, and the second initialization signal line Vinit2 all extend along the second direction F2 and are arranged at intervals along the first direction F1.
[0139] It should be noted that the first initialization signal line Vinit1 in the fourth conductive layer 110 can be electrically connected to the first initialization signal line Vinit1 in the first conductive layer 102 through the third adapter Z3, so that the first initialization signal line Vinit1 is arranged in a grid pattern in its orthographic projection on the substrate. This arrangement is beneficial to the stability of signal transmission. The second initialization signal line Vinit2 in the fourth conductive layer 110 can be electrically connected to the second initialization signal line Vinit2 in the second conductive layer 104 through the sixth adapter Z6, so that the second initialization signal line Vinit2 is arranged in a grid pattern in its orthographic projection on the substrate. This arrangement is also beneficial to the stability of signal transmission.
[0140] For example, a schematic diagram of the superimposed layout of the first conductive layer 102 and the second conductive layer 104 is shown in Figure 12.
[0141] Figure 13 shows an exemplary layout of the superimposed first conductive layer 102, second conductive layer 104, and semiconductor layer 106.
[0142] For example, a schematic diagram of the superimposed layout of the first conductive layer 102, the second conductive layer 104, the semiconductor layer 106, and the third conductive layer 108 is shown in Figure 14.
[0143] Figure 15 shows schematic diagrams of other pixel circuit structures provided in this disclosure, which are modifications of the implementation methods described above. The differences between this embodiment and the above embodiments will be described below, while the similarities will not be repeated.
[0144] In some embodiments of this disclosure, the gate of the first transistor T1 is electrically connected to the first reset signal line Reset1, the first terminal of the first transistor T1 is electrically connected to the first power supply signal line VDD, and the second terminal of the first transistor T1 is electrically connected to the gate of the driving transistor T0. This arrangement can save signals, reduce wiring complexity, and facilitate design.
[0145] The method for fabricating an array substrate provided in this disclosure includes: sequentially forming a first conductive layer, a second conductive layer, a semiconductor layer and a third conductive layer on a substrate to form a pixel circuit located on the substrate.
[0146] The first conductive layer includes the first electrode of the first capacitor; the second conductive layer includes the second electrode of the first capacitor; the semiconductor layer includes the active layer of the driving transistor; and the third conductive layer includes the gate, the first junction portion, and the second junction portion of the driving transistor.
[0147] Based on the same inventive concept, embodiments of the present invention also provide a display device, including the display panel described above in the embodiments of the present invention. The principle by which this display device solves the problem is similar to that of the aforementioned display panel; therefore, the implementation of this display device can refer to the implementation of the aforementioned display panel, and the repeated parts will not be described again here.
[0148] This disclosure provides a display device comprising: an array substrate including a plurality of pixel units arranged in an array, each pixel unit including a plurality of sub-pixels. Exemplarily, each pixel unit includes a plurality of sub-pixels. For example, a pixel unit may include red sub-pixels, green sub-pixels, and blue sub-pixels, allowing for color mixing of red, green, and blue to achieve color display. Alternatively, a pixel unit may include red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels, allowing for color mixing of red, green, blue, and white to achieve color display. Of course, in practical applications, the emission color of the sub-pixels in a pixel unit can be designed and determined according to the actual application environment, and is not limited here.
[0149] In this embodiment of the disclosure, each sub-pixel includes a pixel circuit, and the pixel circuit includes a driving transistor and a light-emitting device to drive the light-emitting device to emit light, thereby enabling the display panel to perform the function of displaying an image.
[0150] In specific implementations, in the embodiments of the present invention, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting the present invention.
[0151] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.
[0152] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Therefore, if these modifications and variations to the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include these modifications and variations.
Claims
1. An array substrate, wherein, include: The substrate includes multiple pixel circuits; The pixel circuit includes: a driving transistor and a first capacitor; the gate of the driving transistor is electrically connected to the first plate of the first capacitor through a first adapter, the first electrode of the driving transistor is electrically connected to a first node, and the second electrode of the driving transistor is electrically connected to the second plate of the first capacitor through a second adapter. The first transition portion, the gate of the driving transistor, and the second transition portion are disposed on the same layer.
2. The array substrate as claimed in claim 1, wherein, The first adapter, the first electrode of the first capacitor, and the second electrode of the first capacitor overlap each other in their orthogonal projections onto the substrate.
3. The array substrate as claimed in claim 1, wherein, The second adapter, the first electrode of the first capacitor, and the second electrode of the first capacitor overlap each other in their orthogonal projections onto the substrate.
4. The array substrate as claimed in claim 1, wherein, The orthographic projection of the second adapter on the substrate does not overlap with the orthographic projection of the first adapter and the gate of the driving transistor on the substrate.
5. The array substrate according to any one of claims 1-4, wherein, The pixel circuit also includes: a second capacitor; The first plate of the second capacitor is electrically connected to the first power signal line, and the second plate of the second capacitor is electrically connected to the second plate of the first capacitor through the second adapter. The second adapter is located on the same layer as the first adapter.
6. The array substrate as claimed in claim 5, wherein, The first plate of the second capacitor, the first plate of the first capacitor, and the first power signal line are located on the same layer. The second plate of the second capacitor is located on the same layer as the second plate of the first capacitor.
7. The array substrate as claimed in claim 5, wherein, The projection of the second adapter onto the substrate overlaps with the projections of the first electrode of the second capacitor and the second electrode of the second capacitor onto the substrate.
8. The array substrate as claimed in claim 5, wherein, The first plate of the second capacitor, the second plate of the second capacitor, and the gate of the driving transistor overlap each other in their orthogonal projections onto the substrate.
9. The array substrate according to any one of claims 6-8, wherein, The pixel circuit further includes: a first transistor; The gate of the first transistor is electrically connected to the first reset signal line, the first terminal of the first transistor is electrically connected to the first initialization signal line through the third adapter, and the second terminal of the first transistor is electrically connected to the gate of the driving transistor through the first adapter. The third adapter, the first reset signal line, and the first adapter are located on the same layer.
10. The array substrate as claimed in claim 9, wherein, The projection of the third adapter onto the substrate overlaps with the projection of the first initialization signal line onto the substrate.
11. The array substrate as claimed in claim 9, wherein, The first initialization signal line and the first power signal line are located on the same layer.
12. The array substrate as claimed in claim 9, wherein, The first capacitor further includes a third plate; the second plate of the first transistor is multiplexed as the third plate of the first capacitor, and the third plate is electrically connected to the first plate of the first capacitor through the first adapter.
13. The array substrate according to any one of claims 6-8, wherein, The pixel circuit further includes: a second transistor; The gate of the second transistor is electrically connected to the first scan signal line, the first terminal of the second transistor is electrically connected to the gate of the driving transistor through the first adapter, and the second terminal of the second transistor is electrically connected to the data signal line. The first scan signal line and the first adapter are located on the same layer, while the first scan signal line and the data signal line are located on different layers.
14. The array substrate according to any one of claims 6-8, wherein, The pixel circuit also includes: a third transistor; The gate of the third transistor is electrically connected to the first light-emitting control signal line, the first electrode of the third transistor is electrically connected to the first power signal line through the fourth adapter, and the second electrode of the third transistor is electrically connected to the first node. The first adapter, the fourth adapter, and the first light emission control signal line are located on the same layer.
15. The array substrate as claimed in claim 14, wherein, The orthographic projection of the fourth adapter onto the substrate overlaps with the orthographic projection of the first power signal line onto the substrate.
16. The array substrate according to any one of claims 6-8, wherein, The pixel circuit also includes: a fourth transistor; The gate of the fourth transistor is electrically connected to the second light-emitting control signal line, the first electrode of the fourth transistor is electrically connected to the second plate of the first capacitor through the fifth adapter, and the second electrode of the fourth transistor is electrically connected to the second node. The first adapter, the fifth adapter, and the second light emission control signal line are located on the same layer.
17. The array substrate as claimed in claim 16, wherein, The fifth adapter is located between the first reset signal line and the first initialization signal line in the orthographic projection of the substrate.
18. The array substrate of claim 16, wherein, The pixel circuit also includes: a fifth transistor; The gate of the fifth transistor is electrically connected to the second reset signal line, the first terminal of the fifth transistor is electrically connected to the second node, and the second terminal of the fifth transistor is electrically connected to the second initialization signal line through the sixth adapter. The fifth adapter, the sixth adapter, and the second reset signal line are located on the same layer.
19. The array substrate of claim 18, wherein, The projection of the sixth adapter onto the substrate overlaps with the projection of the second initialization signal line onto the substrate.
20. The array substrate of claim 18, wherein, The second initialization signal line is located on the same layer as the second plate of the first capacitor.
21. The array substrate according to any one of claims 1-20, wherein, The first power signal line, the first light emission control signal line, the first scan signal line, the first reset signal line, the first initialization signal line, the second light emission control signal line, the second reset signal line, and the second initialization signal line all extend along the first direction; The first power signal line, the first light emission control signal line, the first scan signal line, the first reset signal line, the first initialization signal line, the second light emission control signal line, the second reset signal line, and the second initialization signal line are arranged at intervals along the second direction. The first direction and the second direction are intersected.
22. A display device, wherein, Includes the array substrate as described in any one of claims 1-21.
23. A method for manufacturing an array substrate as described in any one of claims 1-21, wherein, include: A first conductive layer, a second conductive layer, a semiconductor layer, and a third conductive layer are sequentially formed on the substrate to form a pixel circuit located on the substrate. Wherein, the first conductive layer includes the first electrode of the first capacitor; the second conductive layer includes the second electrode of the first capacitor; the semiconductor layer includes the active layer of the driving transistor; and the third conductive layer includes the gate of the driving transistor, the first transition portion, and the second transition portion.