Transistor, display panel, and method for manufacturing transistor

Abstract

Embodiments of the present application provide a transistor, a display panel, and a method for manufacturing a transistor, aiming at improving the use performance of a display panel. The transistor is applied to an array substrate of the display panel, and the transistor comprises: a buffer layer; an active layer disposed on the buffer layer and comprising a semiconductor portion, wherein the semiconductor portion comprises a channel region and non-channel regions, and the at least two non-channel regions are disposed on two sides of the channel region; a first insulating layer, disposed on the side of the active layer away from the buffer layer; and a first conductive layer, disposed on the side of the first insulating layer away from the active layer, the first conductive layer comprising a first gate, wherein the orthographic projection of the channel region on the buffer layer at least partially overlaps the orthographic projection of the first gate on the buffer layer, and a resistance value of at least one non-channel region ranges from 500 Ω to 3,000 Ω.

Description

Transistors, display panels, and methods for fabricating transistors

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202510073029.0, filed on January 16, 2025, entitled “Transistor, Display Panel and Method of Manufacturing Transistor,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of display component technology, and in particular to a transistor, a display panel, and a method for manufacturing the transistor. Background Technology

[0004] Organic light-emitting diodes (OLEDs) and flat panel displays based on light-emitting diodes (LEDs) are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body, and wide range of applications, becoming the mainstream of display devices.

[0005] However, the performance of current OLED display products needs to be improved. Summary of the Invention

[0006] This application provides a transistor, a display panel, and a method for manufacturing the transistor, aiming to improve the performance of the display panel.

[0007] An embodiment of the first aspect of this application provides a transistor for an array substrate of a display panel. The transistor includes: a buffer layer; an active layer disposed on the buffer layer and including a semiconductor portion, the semiconductor portion including a channel region and a non-channel region, at least two non-channel regions being disposed on both sides of the channel region; a first insulating layer disposed on the side of the active layer opposite to the buffer layer; and a first conductive layer disposed on the side of the first insulating layer opposite to the active layer, the first conductive layer including a first gate; wherein the orthographic projection of the channel region on the buffer layer and the orthographic projection of the first gate on the buffer layer at least partially overlap, and the resistance value of at least one non-channel region is 500Ω to 3000Ω.

[0008] An embodiment of the second aspect of this application also provides an array substrate including transistors from any of the first aspect embodiments described above.

[0009] An embodiment of the third aspect of this application provides a display panel including an array substrate of any of the second aspects described above.

[0010] An embodiment of the fourth aspect of this application provides a method for fabricating a transistor, comprising:

[0011] A semiconductor material layer is disposed on one side of the buffer layer, and the semiconductor material layer is patterned to form an active layer. The active layer includes a semiconductor part, which includes a channel region and non-channel regions located on both sides of the channel region.

[0012] A first insulating layer is provided on the side of the active layer that is away from the buffer layer;

[0013] A first conductive material layer is disposed on the side of the first insulating layer away from the active layer, and the first conductive material layer is patterned to form a first conductive layer. The first conductive layer includes a first gate, and the orthogonal projection of the channel region in the buffer layer and the orthogonal projection of the first gate in the buffer layer at least partially overlap.

[0014] Among them, the resistance value of at least one non-channel region is 500Ω to 3000Ω.

[0015] In the transistor provided in this application embodiment, the transistor includes a buffer layer, an active layer, a first insulating layer, and a first conductive layer. The buffer layer provides support and buffering for the transistor device. A semiconductor portion is disposed within the active layer, the semiconductor portion including a channel region and a non-channel region, and the conduction of charge carriers between the non-channel regions is realized through the conduction of the channel region. The first insulating layer ensures the insulation performance between the first conductive layer and the active layer. The first conductive layer includes a first gate, and the orthographic projection of the channel region onto the buffer layer and the orthographic projection of the first gate onto the buffer layer at least partially overlap, so that the first gate can control whether the channel region is turned on or off. The resistance value of at least one non-channel region is 500Ω to 3000Ω. When the resistance value of the non-channel region is within the above range, when the channel region is turned on and the charge carriers in the non-channel region move to the channel region, the carrier concentration in the channel region can be effectively controlled, ensuring the device characteristics of the transistor, improving the transistor yield, and thus improving the performance of the display panel when the transistor is used. Attached Figure Description

[0016] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, wherein the same or similar reference numerals denote the same or similar features.

[0017] Figure 1 is a schematic diagram of a transistor structure provided in an embodiment of this application;

[0018] Figure 2 is a cross-sectional view at point AA in Figure 1, as shown in the example.

[0019] Figure 3 is a cross-sectional view at point AA in Figure 1 in another example;

[0020] Figure 4 is a cross-sectional view of point AA in Figure 1 in another example;

[0021] Figure 5 is a cross-sectional view of point AA in Figure 1 in another example;

[0022] Figure 6 is a schematic diagram of the driving circuit structure of an array substrate provided in an embodiment of this application;

[0023] Figure 7 is a schematic diagram of the pixel circuit structure of an array substrate provided in an embodiment of this application;

[0024] Figure 8 is a schematic diagram of the connection of test components of an array substrate provided in an embodiment of this application;

[0025] Figure 9 is a schematic flowchart of a transistor fabrication method provided in an embodiment of this application;

[0026] Figures 10 to 12 are schematic diagrams of the fabrication process of a transistor provided in an embodiment of this application;

[0027] Figure 13 is a schematic flowchart of a transistor fabrication method according to another embodiment of this application;

[0028] Figure 14 is a schematic diagram of the fabrication process of a transistor according to another embodiment of this application. Detailed Implementation

[0029] The features and exemplary embodiments of various aspects of this application will now be described in detail. Numerous specific details are set forth in the following detailed description to provide a comprehensive understanding of this application. However, it will be apparent to those skilled in the art that this application can be implemented without requiring some of these specific details. The following description of embodiments is merely intended to provide a better understanding of this application by illustrating examples. In the accompanying drawings and the following description, at least some well-known structures and techniques are not shown to avoid unnecessarily obscuring the application; and, for clarity, the dimensions of some structures may be exaggerated. Furthermore, the features, structures, or characteristics described below can be combined in any suitable manner in one or more embodiments.

[0030] In the description of this application, it should be noted that, unless otherwise stated, "a plurality of" means two or more; the terms "upper," "lower," "left," "right," "inner," "outer," etc., indicating orientation or positional relationships are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0031] The directional terms appearing in the following description refer to the directions shown in the figures and are not intended to limit the specific structure of the embodiments of this application. It should also be noted in the description of this application that, unless otherwise explicitly specified and limited, the terms "installation" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0032] The display panel includes light-emitting units and driving circuits for driving the light-emitting units to emit light. The driving circuits include multiple transistors, which control the flow of current, thereby controlling whether the light-emitting units emit light. The characteristics of the transistors have a significant impact on the performance of the display panel. Transistors include metal-oxide transistors (MOTs) and low-temperature polycrystalline silicon (LTPS) transistors. MOTs typically use metal oxides such as indium gallium zinc oxide (IGZO) as semiconductor materials. These materials have high electron mobility, good transparency, and stability. LTS transistors use polycrystalline silicon (poly-Si) as the semiconductor material. Polycrystalline silicon has even higher carrier mobility, but it requires crystallization at lower temperatures to avoid damaging the underlying flexible substrate.

[0033] While low-temperature polysilicon (LTPS) transistors offer the advantage of high mobility, their fabrication process is complex and manufacturing costs are high. Metal-oxide-semiconductor (MODS) transistors (MOS) are constantly striving for even higher mobility to replace LTPS. However, the applicant has discovered that high-mobility MODS transistors are prone to negative bias conduction problems. This is primarily because increased MODS mobility is accompanied by a significant increase in carrier concentration within the channel region. Therefore, controlling the conductor formation in the non-channel region 212 is difficult to maintain within a fixed area, easily affecting the carrier concentration in the channel region. This leads to a reduction in the effective channel length, ultimately resulting in a threshold voltage negative bias conduction problem.

[0034] To address the aforementioned technical problems, this application is proposed. To better understand this application, the transistors, display panels, and transistor fabrication methods of embodiments of this application will be described in detail below with reference to Figures 1 to 14.

[0035] Please refer to Figures 1 and 2 together. Figure 1 is a top view of a transistor 10 provided in an embodiment of this application. Figure 2 is a cross-sectional view at point AA in Figure 1.

[0036] As shown in Figure 1, the transistor 10 provided in this application is used in the array substrate of a display panel. The transistor 10 includes: a buffer layer 100; an active layer 200 disposed on the buffer layer 100 and including a semiconductor portion 210, the semiconductor portion 210 including a channel region 211 and a non-channel region 212, at least two non-channel regions 212 being disposed on both sides of the channel region 211; a first insulating layer 300 disposed on the side of the active layer 200 away from the buffer layer 100; and a first conductive layer 400 disposed on the side of the first insulating layer 300 away from the active layer 200, the first conductive layer 400 including a first gate 410; wherein, the orthographic projection of the channel region 211 on the buffer layer 100 and the orthographic projection of the first gate 410 on the buffer layer 100 at least partially overlap, and the resistance value of at least one non-channel region 212 is 500Ω to 3000Ω.

[0037] In the transistor 10 provided in this embodiment, the transistor 10 includes a buffer layer 100, an active layer 200, a first insulating layer 300, and a first conductive layer 400. The buffer layer 100 provides support and buffering for the transistor 10. A semiconductor portion 210 is disposed within the active layer 200, and the semiconductor portion 210 includes a channel region 211 and a non-channel region 212. The conduction of charge carriers between the non-channel regions 212 is achieved through the conduction of the channel region 211. The first insulating layer 300 ensures the insulation performance between the first conductive layer 400 and the active layer 200. The first conductive layer 400 includes a first gate 410, and the orthographic projection of the channel region 211 onto the buffer layer 100 and the orthographic projection of the first gate 410 onto the buffer layer 100 at least partially overlap, so that the first gate 410 can control whether the channel region 211 is turned on or off. At least one non-channel region 212 has a resistance value of 500Ω to 3000Ω. When the resistance value of the non-channel region 212 is within the above range, when the channel region 211 is turned on and the carriers in the non-channel region 212 move to the channel region 211, the carrier concentration in the channel region 211 can be effectively controlled, ensuring the device characteristics of the transistor 10, improving the yield of the transistor 10, and thus improving the performance of the display panel when the transistor 10 is used.

[0038] Furthermore, in the embodiments of this application, when the transistor 10 is a metal-oxide transistor 10, when the resistance value of at least one non-channel region 212 is 500Ω to 3000Ω, the carrier concentration in the channel region 211 is within a suitable range, thereby ensuring the effective channel length and improving the threshold voltage negative bias conduction problem.

[0039] Optionally, the resistance value of at least one non-channel region 212 can be 500Ω, 800Ω, 960Ω, 1500Ω, 2100Ω, 3000Ω, etc.

[0040] Optionally, the active layer 200 includes two non-channel regions 212, which are located on either side of the channel region 211 in a first direction. The first direction can be the length direction of the channel region 211. Optionally, one of the two non-channel regions 212 can be a source region 212a, and the other a drain region 212b.

[0041] Optionally, the orthographic projection of the channel region 211 onto the buffer layer 100 and the orthographic projection of the first gate 410 onto the buffer layer 100 overlap. For example, when the first gate 410 is used as a mask to conduct the semiconductor portion 210, the portion covered by the first gate 410 is the channel region 211, and the portion not covered by the first gate 410 is conducted as the non-channel region 212. In this case, the orthographic projections of the channel region 211 and the first gate 410 overlap.

[0042] In some alternative embodiments, the resistance value of at least one non-channel region 212 is 900Ω to 2500Ω. For example, the resistance value of at least one non-channel region 212 can be 900Ω, 850Ω, 980Ω, 1520Ω, 2150Ω, 2500Ω, etc.

[0043] In these alternative embodiments, when the resistance value of the non-channel region 212 is further limited to the above range, it can both improve the situation where the resistance value of the non-channel region 212 is too large and the carrier concentration in the channel region 211 is too low, affecting the mutual conduction between the non-channel regions 212; and improve the situation where the resistance value of the non-channel region 212 is too small and the carrier concentration in the channel region 211 is too high, affecting the effective channel length of the channel region 211 and causing the threshold voltage negative bias conduction problem.

[0044] In some optional embodiments, the length of the orthographic projection of the channel region 211 onto the buffer layer 100 in the first direction is less than 4 micrometers. For example, the length of the orthographic projection of the channel region 211 onto the buffer layer 100 in the first direction is 3.5 micrometers, 3.0 micrometers, 2.5 micrometers, 2.3 micrometers, 1.8 micrometers, etc. Referring to the above, at least two non-channel regions 212 are respectively disposed on both sides of the channel region 211 in the first direction.

[0045] In this embodiment, when the length of the orthogonal projection of the channel region 211 onto the buffer layer 100 in the first direction is within the aforementioned range, the length of the channel region 211 is relatively small. Since this embodiment sets the resistance range of the non-channel region 212 within a suitable range, and the carrier concentration within the channel region 211 is within a suitable range, even with a smaller channel length, the effective channel length of the channel region 211 can be guaranteed, ensuring device performance. Furthermore, a shorter channel length can improve mobility.

[0046] Optionally, the length of the orthographic projection of the channel region 211 onto the buffer layer 100 in the first direction is less than 3 micrometers. For example, the length of the orthographic projection of the channel region 211 onto the buffer layer 100 in the first direction is 2.8 micrometers, 2.6 micrometers, 2.5 micrometers, 2.3 micrometers, 1.8 micrometers, etc. The shorter length of the channel region 211 results in a higher mobility for the channel region 211.

[0047] Optionally, the orthographic projection of the semiconductor portion 210 onto the buffer layer 100 is a first rectangle, which extends along a first direction. The orthographic projection of the channel region 211 onto the buffer layer 100 is a second rectangle, and the orthographic projection of the non-channel region 212 onto the buffer layer 100 is a third rectangle. The second rectangle and two third rectangles located on either side of the second rectangle in the first direction combine to form the first rectangle. The distance between the two opposite sides of the second rectangle in the first direction can be the length of the channel region 211 described above.

[0048] In some alternative embodiments, the width of the channel region 211 projected onto the buffer layer 100 in the second direction is greater than or equal to the length of the channel region 211 projected onto the buffer layer 100 in the first direction. The second direction intersects the first direction, for example, the second direction is perpendicular to the first direction.

[0049] In these alternative embodiments, the channel region 211 has a large width, so that the channel region 211 has a suitable distribution area to ensure the normal conduction of the source region 212a and the drain region 212b.

[0050] Optionally, the distance between the two opposite sides of the second rectangle in the second direction is the width of the channel region 211.

[0051] In some optional embodiments, the two non-channel regions 212 include a source region 212a and a drain region 212b respectively disposed on both sides of the channel region 211, and the resistance value of the source region 212a and / or the drain region 212b is 500Ω to 3000Ω, so that the carrier concentration of the channel region 211 is within a suitable range.

[0052] Optionally, the resistance values ​​of the source region 212a and the drain region 212b are both 500Ω to 3000Ω to further improve the performance of the channel region 211 and enhance the uniformity of the transistor 10 device.

[0053] Optionally, transistor 10 further includes a source 510 and a drain 520, with the source 510 electrically connected to the source region 212a and the drain region 212b electrically connected to the drain 520. When the channel region 211 is turned on, the source 510 and the drain 520 can be interconnected through the source region 212a, the channel region 211, and the drain region 212b, thereby enabling current to flow between the source 510 and the drain 520.

[0054] Optionally, transistor 10 further includes a second insulating layer 600, which is located on the side of the first conductive layer 400 opposite to the active layer 200. The source 510 and drain 520 are located on the side of the second insulating layer 600 opposite to the first conductive layer 400. The second insulating layer 600 is disposed between the source 510, drain 520 and the first conductive layer 400 to improve the short-circuit connection problem between the source 510, drain 520 and the first gate 410.

[0055] In some alternative embodiments, the carrier mobility of the channel region 211 is greater than 20 cm⁻¹. 2 / Vs. For example, the carrier mobility of channel region 211 is 21cm. 2 / Vs、28cm 2 / Vs、35cm 2 / Vs、46cm 2 / Vs、50cm 2 / Vs etc.

[0056] In these optional embodiments, the high carrier mobility of the channel region 211 improves the performance of the transistor 10, giving it advantages such as fast response, reduced latency, and lower power consumption. Furthermore, in this embodiment, since the resistance of the non-channel region 212 is within a suitable range, and the carrier concentration within the channel region 211 is also within a suitable range, even with a high carrier mobility in the channel region 211, the channel region 211 can still maintain a suitable effective length, ensuring device performance.

[0057] Optionally, the carrier mobility of channel region 211 is greater than 30 cm⁻¹. 2 / Vs. For example, the carrier mobility of channel region 211 is 31 cm⁻¹. 2 / Vs、35cm 2 / Vs、38cm 2 / Vs、45cm 2 / Vs、50cm 2 / Vs, etc. In these alternative embodiments, the channel region 211 has a higher carrier mobility, which can further improve the performance of the transistor 10 device, giving the transistor 10 advantages such as fast response, reduced latency, and lower power consumption.

[0058] Preferably, the carrier mobility of the channel region 211 is less than 50 cm⁻¹. 2 / Vs. For example, the carrier mobility of channel region 211 is 31cm² / Vs, 35cm² / Vs, 38cm² / Vs, 45cm² / Vs, and 49cm² / Vs. 2 / Vs.

[0059] In these alternative embodiments, the carrier mobility of the channel region 211 is within a suitable range to mitigate the impact of an excessively high carrier mobility on the effective length of the channel region 211.

[0060] In some alternative embodiments, as shown in Figures 1 and 5, transistor 10 further includes a second conductive layer 700 located between active layer 200 and buffer layer 100. The second conductive layer 700 includes a second gate 710, and the orthographic projection of channel region 211 onto buffer layer 100 and the orthographic projection of gate 710 onto buffer layer 100 at least partially overlap.

[0061] In these optional embodiments, a second gate 710 is provided in the second conductive layer 700 of the transistor 10, that is, gates are provided on both sides of the channel region 211 in the third direction. The transistor 10 is a dual-gate transistor 10, which can improve the control capability of the gate of the transistor 10 and achieve fine adjustment and other purposes.

[0062] Optionally, the orthogonal projection of the channel region 211 onto the buffer layer 100 lies within the orthogonal projection of the second gate 710 onto the buffer layer 100. This improves the control capability of the second gate 710 over the channel region 211.

[0063] In some optional embodiments, as shown in FIG2, the channel region 211 is a single-layer structure, that is, the channel region 211 includes three film layers disposed in the third direction. Alternatively, as shown in FIG3 and FIG4, the channel region 211 includes multiple sub-layers 211a stacked in the direction away from the buffer layer 100. That is, the channel region 211 includes multiple sub-layers 211a stacked in the third direction, and the performance of the channel region 211 can be improved by controlling the materials of different sub-layers 211a.

[0064] Optionally, as shown in Figure 3, the semiconductor portion 210 can be fabricated in layers, and the non-channel region 212 can also include multiple sub-layers 211a. Alternatively, as shown in Figure 4, the non-channel region 212 is a single-layer structure, and the channel region 211 includes multiple sub-layers 211a.

[0065] In some alternative embodiments, the material of the buffer layer 100 includes at least one of silicon oxide, silicon oxynitride, and silicon nitride. This gives the buffer layer 100 good insulation and buffering properties.

[0066] In some alternative embodiments, the material of the semiconductor section 210 includes at least one of indium gallium zinc oxide and low-temperature polycrystalline oxide. That is, the transistor 10 can be a metal oxide transistor or a low-temperature polycrystalline silicon transistor.

[0067] In some alternative embodiments, the semiconductor portion 210 is made of at least one of indium, gallium, and zinc. That is, the semiconductor portion 210 can be a metal-oxide-semiconductor transistor, giving the transistor 10 advantages such as ease of fabrication. Indium, gallium, and zinc are metal materials with good mobility and low cost.

[0068] Optionally, the material of the semiconductor section 210 may include indium; for example, the material of the semiconductor section may include InO. x x is one of 1, 2, or 3. That is, the material of the semiconductor section 210 may include monoindium, binary indium, or ternary indium.

[0069] Optionally, the material of the semiconductor section 210 may include indium and gallium; for example, the material of the semiconductor section may include InGaO. x x is one of 1, 2, or 3. That is, the material of the semiconductor section 210 may include monoindium, binary indium, or ternary indium. Alternatively, the material of the semiconductor section 210 may include monogamium, binary gallium, or ternary gallium.

[0070] Optionally, the material of the semiconductor section 210 may include indium and zinc; for example, the material of the semiconductor section may include InZnO. x x is one of 1, 2, or 3. That is, the material of the semiconductor section 210 may include monoindium, binary indium, or ternary indium. Alternatively, the material of the semiconductor section 210 may include monozinc, binary zinc, or ternary zinc.

[0071] Optionally, the material of the semiconductor section 210 may include indium, gallium, and zinc; for example, the material of the semiconductor section may include InGaZnO. x x is one of 1, 2, or 3. That is, the material of the semiconductor section 210 may include monoin, binary indium, or ternary indium. Alternatively, the material of the semiconductor section 210 may include monogamium, binary gallium, or ternary gallium, or the material of the semiconductor section 210 may include monozinc, binary zinc, or ternary zinc.

[0072] Optionally, in addition to indium, gallium, and zinc, other trace elements may be doped into the semiconductor section 210.

[0073] In some alternative embodiments, the orthographic projection of the channel region 211 onto the substrate lies within the orthographic projection of the first gate 410 onto the substrate. This allows the first gate 410 to precisely control the channel region 211.

[0074] As shown in Figures 6 and 7, an embodiment of the second aspect of this application also provides an array substrate, which includes a substrate and a driving circuit 20 disposed on the substrate. The driving circuit 20 includes a transistor 10 from any of the embodiments of the first aspect described above. Since the array substrate of this application includes the transistor 10 described above, the array substrate of this embodiment has the beneficial effects of the transistor 10 in any of the embodiments described above, which will not be repeated here.

[0075] Optionally, the array substrate is used for the display panel and is disposed on the non-display side of the display panel. Optionally, the array substrate may also include devices such as capacitors. The capacitor includes a first electrode and a second electrode disposed opposite to each other. The first electrode can be disposed in the same layer as the first gate 410, that is, the first electrode can be located in the first conductive layer 400. The second electrode can be disposed in the same layer as the source 510 and the drain 520. Alternatively, the array substrate further includes a third conductive layer, which is located between the conductive layer containing the source 510 and the drain 520 and the first conductive layer 400, with the second electrode located in the third conductive layer.

[0076] As shown in Figure 7, the driving circuit 20 may include a pixel circuit 23 and a gate driving circuit 20. The gate driving circuit 20 may include a gate driving transistor 22. The pixel circuit 23 may include a switching transistor 21 (S-TFT), a driving transistor 10 (D-TFT), and a capacitor (C). The driving transistor 10 (D-TFT) is connected between the power signal line (VDD) and the light-emitting element (EL). The gate of the switching transistor 21 (S-TFT) is connected to the scan signal line (Scan). One of the source 510 and drain 520 of the switching transistor 21 (S-TFT) is connected to the data signal line (Data), and the other of the source 510 and drain 520 of the switching transistor 21 (S-TFT) is connected to the gate of the driving transistor 10 (D-TFT). When both the scan signal line (Scan) and the data signal line (Data) have driving signals, the source 510 and drain 520 of the switching transistor 21 (S-TFT) are turned on, the gate of the driving transistor 10 (D-TFT) controls the source 510 and drain 520 of the driving transistor 10 (D-TFT) to be turned on, and the power signal line (VDD) and the light-emitting element (EL) are turned on, thereby driving the light-emitting element (EL) to emit light.

[0077] In some alternative embodiments, as shown in FIG8, the array substrate further includes a test component 30, the semiconductor portion 210 includes a first end 213 and a second end 214 opposite to each other in its extension direction, the test component 30 is connected between the first end 213 and the second end 214, and the test component 30 is used to obtain the resistance of the semiconductor portion 210.

[0078] In these alternative embodiments, the array substrate further includes a test component 30 connected between the two ends of the semiconductor section 210, so that the test component 30 can obtain the resistance of the semiconductor section 210 to determine whether the resistance meets the device requirements.

[0079] Optionally, when the array substrate includes multiple transistors 10, the semiconductor portions 210 of the multiple transistors 10 can be connected in series. For example, the semiconductor portions 210 of the multiple transistors 10 can be connected in series to form a single structure and have a first end 213 and a second end 214 disposed opposite to each other. The test component 30 is connected between the first end 213 and the second end 214 after being connected in series, so that the test component 30 can obtain the resistance of the multiple semiconductor portions 210. Alternatively, the test component 30 can be connected to both ends of any semiconductor portion 210.

[0080] In some alternative embodiments, the driving circuit 20 includes a switching transistor 21 and a gate driving transistor 22, wherein the switching transistor 21 and / or the gate driving transistor 22 are transistors 10 of any of the first aspects of the embodiments described above.

[0081] In these alternative embodiments, the switching transistor 21 and the gate driving transistor 22 have higher requirements for the devices. The switching transistor 21 and / or the gate driving transistor 22 are transistors 10 in any of the first aspects of the above embodiments, which can improve the yield and performance of the switching transistor 21 and / or the gate driving transistor 22, thereby improving the performance of the display panel.

[0082] Optionally, the driving circuit 20 may also include a driving transistor 10, a compensation transistor 10, a light-emitting control transistor 10, etc. The driving transistor 10, the compensation transistor 10, and the light-emitting control transistor 10 may also be transistors 10 of any of the first aspects of the above embodiments, so as to improve the yield and performance of the array substrate.

[0083] An embodiment of the third aspect of this application also provides a display panel, including the array substrate of any of the second aspect embodiments described above. Since the display panel of this embodiment includes the aforementioned array substrate, it possesses the beneficial effects of the array substrate, which will not be elaborated further here.

[0084] Optionally, the display panel further includes a planarization layer, a first electrode layer, a pixel definition layer, a second electrode layer, and an encapsulation layer sequentially stacked on the array substrate. The first electrode layer includes a plurality of first electrodes distributed in an array, and the pixel definition layer includes a pixel defining portion and a pixel opening, with a light-emitting unit disposed within the pixel opening. Each first electrode is exposed through its respective pixel opening, and each first electrode cooperates with the second electrode layer to drive the light-emitting unit to emit light. The first electrode is electrically connected to the driving circuit 20, for example, the first electrode is electrically connected to the driving transistor 10.

[0085] This application also provides a display device, including the display panel of any of the above embodiments. Since the display device provided in this application includes the display panel of any of the above embodiments, it possesses the beneficial effects of the display panel of any of the above embodiments, which will not be elaborated further here.

[0086] The display devices in this application include, but are not limited to, mobile phones, personal digital assistants (PDAs), tablet computers, e-books, televisions, access control systems, smart landline phones, control consoles, and other devices with display functions.

[0087] As shown in Figure 9, an embodiment of the fourth aspect of this application also provides a method for fabricating a transistor 10. The transistor 10 can be any of the transistors provided in the first aspect embodiment described above. Referring to Figures 1 to 5, the method for fabricating the transistor 10 includes:

[0088] Step S01: As shown in Figure 10, a semiconductor material layer is disposed on one side of the buffer layer 100, and the semiconductor material layer is patterned to form an active layer 200. The active layer 200 includes a semiconductor portion 210, which includes a channel region 211 and non-channel regions 212 located on both sides of the channel region 211.

[0089] Step S02: As shown in Figure 11, a first insulating layer 300 is provided on the side of the active layer 200 that is away from the buffer layer 100.

[0090] Step S03: As shown in FIG12, a first conductive material layer is disposed on the side of the first insulating layer 300 away from the active layer 200, and the first conductive material layer is patterned to form a first conductive layer 400. The first conductive layer 400 includes a first gate 410, and the orthographic projection of the channel region 211 on the buffer layer 100 and the orthographic projection of the first gate 410 on the buffer layer 100 at least partially overlap.

[0091] Among them, the resistance value of at least one non-channel region 212 is 500Ω to 3000Ω.

[0092] In the transistor 10 fabrication method provided in this application embodiment, firstly, an active layer 200 is fabricated on a buffer layer 100 in step S01. The buffer layer 100 provides a supporting buffer for the transistor 10. A semiconductor portion 210 is disposed within the active layer 200, the semiconductor portion 210 including a channel region 211 and a non-channel region 212, and the conduction of charge carriers between the non-channel regions 212 is realized through the conduction of the channel region 211. Then, a first insulating layer 300 is fabricated on the active layer 200 in step S02, and a first conductive layer 400 is fabricated on the first insulating layer 300 in step S03. The first insulating layer 300 ensures the insulation performance between the first conductive layer 400 and the active layer 200. The first conductive layer 400 includes a first gate 410, and the orthographic projection of the channel region 211 on the buffer layer 100 and the orthographic projection of the first gate 410 on the buffer layer 100 at least partially overlap, so that the first gate 410 can control whether the channel region 211 is turned on or off. At least one non-channel region 212 has a resistance value of 500Ω to 3000Ω. When the resistance value of the non-channel region 212 is within the above range, when the channel region 211 is turned on and the carriers in the non-channel region 212 move to the channel region 211, the carrier concentration in the channel region 211 can be effectively controlled, ensuring the device characteristics of the transistor 10, improving the yield of the transistor 10, and thus improving the performance of the display panel when the transistor 10 is used.

[0093] In some optional embodiments, as shown in FIG13, the method for fabricating transistor 10 further includes:

[0094] Step S04: Ion implantation is performed on the semiconductor section 210 from the side of the first conductive layer 400 away from the first insulating layer 300.

[0095] In this embodiment of the application, ion implantation is performed on the semiconductor section 210 in step S04. Due to the presence of the first gate 410 in the first conductive layer 400, the first gate 410 blocks the channel region 211, and ions can be implanted into the non-channel region 212 to achieve conductivity in the non-channel region 212.

[0096] Optionally, the ion implantation energy is 5KV to 75KV. When the ion implantation energy is within the above range, the non-channel region 212 has a suitable resistance range, making it easy to control the resistance value of the non-channel region 212 between 500Ω and 3000Ω.

[0097] Optionally, the ion implantation dose is 1*10 11 cm 3 ~1*10 15 cm 3When the ion implantation dose is within the above range, it can improve the situation where the non-channel region 212 resistance is too high due to too low implantation dose, or the non-channel region 212 resistance is too low due to too high implantation dose, thus affecting device performance.

[0098] In some alternative embodiments, step S04 may be followed by:

[0099] Step S05: Anneal the semiconductor section 210 at a temperature of 200°C to 400°C and / or for a time of 10 mins to 2 hours.

[0100] In the above embodiment, after ion implantation of the semiconductor section 210, the semiconductor section 210 is annealed. When the annealing temperature and / or annealing time are within the above range, the resistance of the non-channel region 212 can be controlled between 500Ω and 3000Ω.

[0101] Optionally, in step S05, the annealing temperature is 200℃~400℃, and the annealing time is 10mins~2hr. This is to further ensure that the resistance of the non-channel region 212 is between 500Ω and 3000Ω.

[0102] In some alternative embodiments, in step S02: a chemical vapor deposition process is used to form the first insulating layer 300.

[0103] Optionally, the material of the first insulating layer 300 includes silicon oxide, and the chemical vapor deposition gas precursor includes silane gas and nitrous oxide, wherein the ratio of silane gas to nitrous oxide gas is 0.1 to 0.01.

[0104] Optionally, the working pressure for chemical vapor deposition is 100 Pa to 300 Pa.

[0105] Optionally, the operating power of chemical vapor deposition is 0.5kW to 10kW.

[0106] In these alternative embodiments, preparing the first insulating layer 300 by chemical vapor deposition can improve the density and insulation performance of the first insulating layer 300. In the chemical vapor deposition process, by adjusting the precursor, operating pressure, and operating power, the performance of the non-channel region 212 can be affected, so that when the non-channel region 212 is subsequently conductiveized, its resistance can be maintained between 500Ω and 3000Ω.

[0107] In some optional embodiments, the method for fabricating transistor 10 further includes:

[0108] Step S06: As shown in Figure 14, a second insulating layer 600 is provided on the side of the first conductive layer 400 that is opposite to the first insulating layer 300.

[0109] Optionally, a chemical vapor deposition process can be used to form the second insulating layer 600.

[0110] Optionally, the material of the second insulating layer 600 includes silicon oxide, and the gas precursor for chemical vapor deposition includes silane gas and nitrous oxide, wherein the ratio of silane gas to nitrous oxide gas is 0.1 to 0.01.

[0111] Optionally, the working pressure for chemical vapor deposition is 100 Pa to 300 Pa.

[0112] Optionally, the operating power of chemical vapor deposition is 0.5kW to 10kW.

[0113] In these optional embodiments, firstly, providing a second insulating layer 600 can improve the short-circuit connection between the first conductive layer 400 and other conductive layers. Preparing the second insulating layer 600 by chemical vapor deposition can improve its density and insulation performance. In the chemical vapor deposition process, by adjusting the precursor, operating pressure, and operating power, the performance of the non-channel region 212 can be affected, so that when the non-channel region 212 is subsequently conductor-conductively converted, its resistance can be maintained between 500Ω and 3000Ω.

[0114] Optionally, after step S06, the aforementioned source electrode 510 and drain electrode 520 may be prepared on the second insulating layer 600.

[0115] Optionally, prior to step S01, a second conductive layer 700 may be formed on the buffer layer 100, the second conductive layer 700 including the aforementioned second gate 710. A third insulating layer 800 may also be formed on the second conductive layer 700. In step S01, an active layer 200 may be formed on the third insulating layer 800.

[0116] Although this application has been described with reference to preferred embodiments, various modifications can be made thereto and components can be replaced with equivalents without departing from the scope of this application. In particular, the technical features mentioned in the various embodiments can be combined in any manner, provided there is no structural conflict. This application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A transistor array substrate for a display panel, comprising: Buffer layer; An active layer is disposed on the buffer layer and includes a semiconductor portion, the semiconductor portion including a channel region and a non-channel region, and at least two of the non-channel regions are disposed on both sides of the channel region; A first insulating layer is disposed on the side of the active layer opposite to the buffer layer; A first conductive layer is disposed on the side of the first insulating layer away from the active layer, and the first conductive layer includes a first gate. Wherein, the orthographic projection of the channel region on the buffer layer and the orthographic projection of the first gate on the buffer layer at least partially overlap, and the resistance value of at least one of the non-channel regions is 500Ω to 3000Ω.

2. The transistor according to claim 1, wherein, The resistance of at least one of the non-channel regions is 900Ω to 2500Ω.

3. The transistor according to claim 1, wherein, The length of the channel region projected onto the buffer layer in the first direction is less than 4 micrometers, and at least two of the non-channel regions are located on both sides of the channel region in the first direction.

4. The transistor according to claim 3, wherein, The width of the channel region's orthographic projection onto the buffer layer in the second direction is greater than or equal to the length of the channel region's orthographic projection onto the buffer layer in the first direction, and the second direction intersects the first direction.

5. The transistor according to claim 1, wherein, The two non-channel regions include a source region and a drain region located on both sides of the channel region, and the resistance value of the source region and / or the drain region is 500Ω to 3000Ω.

6. The transistor according to claim 1, wherein, The carrier mobility in the channel region is greater than 20 cm⁻¹ 2 / Vs, or, the carrier mobility in the channel region is less than 50 cm⁻¹. 2 / Vs.

7. The transistor of claim 1, further comprising a second conductive layer located between the active layer and the buffer layer, the second conductive layer including a second gate, wherein the orthographic projection of the channel region on the buffer layer and the orthographic projection of the second gate on the buffer layer at least partially overlap.

8. The transistor according to claim 1, wherein, The channel region is a single-layer structure, or the channel region includes multiple sub-layers stacked in a direction away from the buffer layer.

9. The transistor according to claim 1, wherein, The material of the buffer layer includes at least one of silicon oxide, silicon oxynitride, and silicon nitride; or The semiconductor component is made of at least one of indium, gallium, and zinc.

10. The transistor according to claim 9, wherein, The semiconductor component is made of InO. x x is one of 1, 2, or 3; Alternatively, the material of the semiconductor portion may include InGaO. x x is one of 1, 2, or 3; Alternatively, the material of the semiconductor portion may include InZnO. x x is one of 1, 2, or 3; Alternatively, the material of the semiconductor portion may include InGaZnO. x x is one of 1, 2, or 3.

11. The transistor of claim 1, wherein, The channel region is projected onto the substrate in a direction that lies within the projection of the first gate onto the substrate.

12. An array substrate, comprising a substrate and a driving circuit disposed on the substrate, the driving circuit comprising a transistor according to any one of claims 1-11.

13. The array substrate according to claim 12, wherein, It also includes a test component, wherein the semiconductor portion includes a first end and a second end opposite to each other in its extension direction, the test component being connected between the first end and the second end, the test component being used to obtain the resistance of the semiconductor portion.

14. The array substrate according to claim 12, wherein, The driving circuit includes a switching transistor and a gate driving transistor, wherein the switching transistor and / or the gate driving transistor are transistors as described in any one of claims 1-11.

15. A display panel comprising the array substrate according to any one of claims 12-14.

16. A method for fabricating a transistor, comprising: A semiconductor material layer is disposed on one side of the buffer layer, and the semiconductor material layer is patterned to form an active layer. The active layer includes a semiconductor portion, and the semiconductor portion includes a channel region and non-channel regions located on both sides of the channel region. A first insulating layer is provided on the side of the active layer opposite to the buffer layer; A first conductive material layer is disposed on the side of the first insulating layer away from the active layer, and the first conductive material layer is patterned to form a first conductive layer. The first conductive layer includes a first gate, and the orthogonal projection of the channel region on the buffer layer and the orthogonal projection of the first gate on the buffer layer at least partially overlap. Wherein, the resistance value of at least one of the non-channel regions is 500Ω to 3000Ω.

17. The method according to claim 16, wherein, Also includes: Ion implantation is performed on the semiconductor portion from the side of the first conductive layer that is away from the first insulating layer. The ion implantation energy is 5KV to 75KV, and / or the ion implantation dose is 1*102. 11 cm 3 ~1*10 15 cm 3 .

18. The method according to claim 17, wherein, The step of ion implanting the semiconductor portion from the side of the first conductive layer away from the first insulating layer further includes: The semiconductor part is annealed at a temperature of 200°C to 400°C and / or for a time of 10 mins to 2 hours.

19. The method of claim 16, wherein, In the step of setting the first insulating layer on the side of the active layer opposite to the buffer layer: The first insulating layer is formed using a chemical vapor deposition process. The material of the first insulating layer includes silicon oxide, and the chemical vapor deposition gas precursor includes silane gas and nitrous oxide, wherein the ratio of silane gas to nitrous oxide gas is 0.1 to 0.

01. The working pressure of chemical vapor deposition is 100 Pa to 300 Pa, and / or the working power of chemical vapor deposition is 0.5 kW to 10 kW.

20. The method of claim 16, further comprising: A second insulating layer is provided on the side of the first conductive layer that is opposite to the first insulating layer; The second insulating layer is formed using a chemical vapor deposition process. The material of the second insulating layer includes silicon oxide, and the gas precursor for chemical vapor deposition includes silane gas and nitrous oxide, wherein the ratio of silane gas to nitrous oxide gas is 0.1 to 0.

01. The working pressure of chemical vapor deposition is 100 Pa to 300 Pa, and / or the working power of chemical vapor deposition is 0.5 kW to 10 kW.

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