Data processing method and apparatus, electronic device, medium, and program product

Abstract

The present application relates to the technical field of electronic devices, and discloses a data processing method and apparatus, an electronic device, a medium, and a program product. The data processing method comprises: controlling a central processing unit (CPU) to send a data copy command to a universal flash storage (UFS), the data copy command being used for indicating a source address and a destination address for data copying; and controlling the UFS to, in response to the data copy command, copy data from the source address to the destination address.

Description

Data processing methods, apparatus, electronic equipment, media and program products

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202510067320.7, filed in China on January 16, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application belongs to the field of electronic equipment technology, and specifically relates to a data processing method, apparatus, electronic equipment, medium, and program product. Background Technology

[0004] In mobile phone user scenarios, data copying is a very common operation. In the current data copying process, the Central Processing Unit (CPU) sends a command to read data from location 1 of Universal Flash Storage (UFS) to Low Power Double Data Rate (LPDDR). The data itself is not modified and is only rewritten back to location 2 of UFS. This process actually causes redundant input output (IO) read and write processes, resulting in low data copying efficiency. Summary of the Invention

[0005] This application provides a data processing method, apparatus, electronic device, medium, and program product to improve data copying efficiency.

[0006] To solve the above-mentioned technical problems, this application is implemented as follows:

[0007] In a first aspect, embodiments of this application provide a data processing method, including:

[0008] The central processing unit (CPU) sends a data copy command to the general-purpose flash memory (UFS); the data copy command indicates the source address and destination address of the data copy.

[0009] The UFS is controlled to respond to the data copy command and copy the data from the source address to the destination address.

[0010] Optionally, the data copy command includes source address information and destination address information; the source address information includes the source address, or the source address and the amount of data corresponding to the source address; the destination address information includes the destination address, or the destination address and the amount of data corresponding to the destination address.

[0011] Optionally, the number of source address information is one, and the number of destination address information is one.

[0012] Optionally, the number of source address information is one, and the number of destination address information is at least two.

[0013] Optionally, the number of source address information is at least two, and the number of destination address information is one.

[0014] Optionally, the number of source address information is at least two, and the at least two source address information includes first source address information and second source address information;

[0015] The number of destination address information is at least two, and the at least two destination address information includes first destination address information and second destination address information;

[0016] The first source address information and the first destination address information have a copy relationship;

[0017] There is a copy relationship between the second source address information and the second destination address information.

[0018] Optionally, the source address information includes a source address and the amount of data corresponding to the source address, and the destination address information includes a destination address and the amount of data corresponding to the destination address, wherein the sum of the amounts of data corresponding to at least two source addresses is equal to the amount of data corresponding to the destination address.

[0019] Optionally, the source address information includes a source address and the amount of data corresponding to the source address, the destination address information includes a destination address and the amount of data corresponding to the destination address, the amount of data corresponding to the first source address information is equal to the amount of data between the first destination address information, and the amount of data corresponding to the second source address information is equal to the amount of data between the second destination address information.

[0020] Optionally, the number of source addresses is at least one, and the number of destination addresses is at least one;

[0021] The step of controlling the UFS to respond to the data copy command and copy data from the source address to the destination address includes:

[0022] The UFS is controlled to respond to the data copy command and read data from each of the source addresses;

[0023] The UFS is controlled to copy the data read from each of the source addresses to the corresponding destination addresses.

[0024] Optionally, before the central processing unit (CPU) sends a data copy command to the general-purpose flash memory (UFS) controller, the method further includes:

[0025] The CPU is controlled to verify the validity of the data copy command.

[0026] The control central processing unit (CPU) sends a data copy command to the general-purpose flash memory (UFS) controller, including:

[0027] If the data copy command is valid, the control CPU sends the data copy command to the UFS controller.

[0028] Optionally, the control CPU performs a validity check on the data copy command, including:

[0029] The CPU is controlled to perform validity checks on at least one of the following data copy commands:

[0030] Is the amount of data corresponding to the source address equal to the amount of data corresponding to the destination address?

[0031] Is the total length of the command format corresponding to the data copy command the same as the length of the command constructed from the source address information and the destination address information?

[0032] Whether the source address and destination address are valid, the validity of the source address and destination address includes at least one of the following: the address is not negative, and it does not exceed the maximum address range of UFS.

[0033] Optionally, the method further includes:

[0034] The UFS is controlled to return the data copy result to the CPU;

[0035] If the data copy result includes abnormal information, the CPU is controlled to perform error handling operations corresponding to the abnormal information.

[0036] Optionally, in an incremental upgrade scenario, controlling the CPU to perform error handling operations corresponding to the exception information includes:

[0037] The CPU is controlled to remap the partition and the upgrade progress is synchronized with the kernel, enabling the kernel to perform the upgrade process.

[0038] Optionally, in the case of incremental upgrades, before the control central processing unit (CPU) sends a data copy command to the general-purpose flash memory (UFS) controller, the method further includes:

[0039] Control the CPU to sort operations, placing all data copy operations involved in the incremental upgrade process after non-data copy operations;

[0040] The control central processing unit (CPU) sends a data copy command to the general-purpose flash memory (UFS) controller, including:

[0041] After performing the non-data copy operation, the control CPU sends a data copy command to the UFS.

[0042] Optionally, the UFS includes a UFS controller and a data storage unit; wherein the UFS controller is configured to read data from the source address of the data storage unit in response to the data copy command, and write the read data to the target address of the data storage unit.

[0043] Secondly, embodiments of this application provide a data processing apparatus, including:

[0044] The first control module is used to control the central processing unit (CPU) to send data copy commands to the general-purpose flash memory (UFS) controller; the data copy commands are used to indicate the source address and destination address of the data copy.

[0045] The second control module is used to control the UFS controller to copy data from the source address to the destination address in response to the data copy command.

[0046] Optionally, the data copy command includes source address information and destination address information; the source address information includes the source address, or the source address and the amount of data corresponding to the source address; the destination address information includes the destination address, or the destination address and the amount of data corresponding to the destination address.

[0047] Thirdly, embodiments of this application also provide an electronic device, including a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps described in the first aspect.

[0048] Fourthly, embodiments of this application also provide a readable storage medium on which a program or instructions are stored, which, when executed by a processor, implement the steps described in the first aspect.

[0049] Fifthly, embodiments of this application also provide a computer program product, including computer instructions, which, when executed by a processor, implement the steps described in the first aspect.

[0050] In a sixth aspect, embodiments of this application provide a chip, the chip including a processor and a communication interface, the communication interface being coupled to the processor, the processor being used to run programs or instructions to implement the method as described in the first aspect.

[0051] In this embodiment, by controlling the CPU to send a copy command carrying the source address and destination address to the UFS, the UFS can be controlled to directly obtain data from the indicated source address and copy it to the location indicated by the destination address. This reduces the signaling interaction process during data copying and improves data copying efficiency. Attached Figure Description

[0052] Figure 1 is a flowchart illustrating the data processing method according to an embodiment of this application;

[0053] Figure 2 is a schematic diagram of the architecture of an embodiment of this application;

[0054] Figure 3 is a schematic diagram of the data copying process according to an embodiment of this application;

[0055] Figure 4 is a schematic diagram of the entry format;

[0056] Figure 5 is a schematic diagram of the command format;

[0057] Figure 6 is a schematic diagram showing the specific information of the data copy command;

[0058] Figure 7 is a schematic diagram of the read and write sequence;

[0059] Figure 8 is a schematic diagram of the incremental upgrade process;

[0060] Figure 9 is a schematic diagram of the exception handling process during incremental upgrade;

[0061] Figure 10 is a schematic diagram of the data processing apparatus according to an embodiment of this application;

[0062] Figure 11 is a schematic diagram of the structure of an electronic device according to an embodiment of this application;

[0063] Figure 12 is a second schematic diagram of the structure of an electronic device according to an embodiment of this application. Detailed Implementation

[0064] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0065] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0066] The relevant technologies of this application will be described below.

[0067] The specific data copying process for data copying scenarios mainly includes:

[0068] 1. The Central Processing Unit (CPU) in the mobile phone's System-on-Chip (SOC) sends a read command to the underlying Universal Flash Storage (UFS) controller;

[0069] 2. The UFS controller reads data from data location 1;

[0070] 3. UFS returns data and stores it in memory at Low Power Double Data Rate (LPDDR);

[0071] 4. Based on the data in memory, the CPU sends a write command to UFS location 1;

[0072] 5. The UFS controller receives the command and writes the data to position 2, completing the data copy from position 1 to position 2 (the NAND array is the data storage unit).

[0073] The data processing methods, apparatus, electronic devices, media, and program products provided in this application will be described in detail below with reference to the accompanying drawings and through specific embodiments and application scenarios.

[0074] As shown in Figure 1, this application provides a data processing method applied to an electronic device, including:

[0075] Step 101: Control the central processing unit (CPU) to send a data copy command to the general-purpose flash memory (UFS); the data copy command is used to indicate the source address and destination address of the data copy.

[0076] Step 102: Control the UFS to respond to the data copy command and copy the data from the source address to the destination address.

[0077] It should be noted that, in this embodiment of the application, the CPU is controlled to send a copy command carrying the source address and destination address to the UFS, thereby controlling the UFS to directly obtain data from the indicated source address and copy it to the location indicated by the destination address. This reduces the signaling interaction process during data copying, saves data copying time, improves data copying efficiency, and also reduces system power consumption.

[0078] Alternatively, the CPU refers to the CPU located in the SOC.

[0079] Alternatively, in one implementation, as shown in Figure 2, UFS200 includes:

[0080] UFS controller 210, data storage unit 220;

[0081] The UFS controller 210 is used to receive the data copy command, and in response to the data copy command, read data from the source address of the data storage unit 220 and write the read data to the target address of the data storage unit 220.

[0082] It should be noted that, for CPU100, it sends a data copy command to UFS200; UFS200 receives the data copy command and, in response to the data copy command, copies the data at the source address to the destination address; specifically, the UFS controller 210 receives the data copy command, and UFS controller 210 directly reads the data from the corresponding position in the data storage unit 220 based on the received data copy command and copies the read data to the new position, thereby realizing that the data is copied only within the UFS, avoiding the bit flip problem that may be caused by reading the data out, thus improving the stability of the copied data.

[0083] Optionally, the multiple data storage units 220 can be understood as NAND arrays.

[0084] Optionally, in one implementation, the data copy command includes source address information and destination address information; the source address information includes a source address, or a source address and the amount of data corresponding to the source address; the destination address information includes a destination address, or a destination address and the amount of data corresponding to the destination address.

[0085] It should be noted that the source address information mentioned in the embodiments of this application can be understood as a source entry. Each source entry includes a source address (usually corresponding to the starting address of the source address) or a source address and the amount of data corresponding to the source address (i.e., data size). The destination address information can be understood as a destination entry. The destination entry includes a destination address (usually corresponding to the starting address of the destination address) or a destination address and the amount of data corresponding to the destination address (i.e., data size).

[0086] Optionally, both the source address and the destination address refer to UFS addresses.

[0087] Alternatively, the source address information and destination address information can be implemented in the following ways:

[0088] Implementation scenario 1: The number of source address information is one, and the number of destination address information is one.

[0089] Implementation scenario two: The number of source address information is one, and the number of destination address information is at least two.

[0090] Implementation scenario 3: The number of source address information is at least two, and the number of destination address information is one.

[0091] It should be noted that, in this implementation, optionally, the source address information includes the source address and the amount of data corresponding to the source address, and the destination address information includes the destination address and the amount of data corresponding to the destination address, wherein the sum of the amounts of data corresponding to at least two source addresses is equal to the amount of data corresponding to the destination address.

[0092] Implementation scenario four: The number of source address information is at least two, including a first source address information and a second source address information; the number of destination address information is at least two, including a first destination address information and a second destination address information; there is a copy relationship between the first source address information and the first destination address information; there is a copy relationship between the second source address information and the second destination address information.

[0093] Optionally, the copy relationship between the first source address information and the first destination address information can be understood as copying the data at the source address indicated in the first source address information to the destination address indicated in the first destination address information; the copy relationship between the second source address information and the second destination address information can be understood as copying the data at the source address indicated in the second source address information to the destination address indicated in the second destination address information.

[0094] Optionally, in this implementation, the source address information includes the source address and the amount of data corresponding to the source address, the destination address information includes the destination address and the amount of data corresponding to the destination address, the amount of data corresponding to the first source address information is equal to the amount of data between the first destination address information, and the amount of data corresponding to the second source address information is equal to the amount of data between the second destination address information.

[0095] Optionally, in one implementation, the number of source addresses is at least one, and the number of destination addresses is at least one; controlling the UFS to respond to the data copy command and copy data from the source address to the destination address includes:

[0096] The UFS is controlled to respond to the data copy command and read data from each of the source addresses;

[0097] The UFS is controlled to copy the data read from each of the source addresses to the corresponding destination addresses.

[0098] For example, in implementation scenario two, UFS responds to the data copy command by reading data from the source address. It can copy the data read from the source address to each destination address, meaning each destination address corresponds to all the data read from the source address. Alternatively, it can copy the data read from the source address in parts to all destination addresses, meaning each destination address corresponds to a portion of the data read from the source address.

[0099] Optionally, in one implementation, before the central processing unit (CPU) sends a data copy command to the general-purpose flash memory (UFS) controller, the method further includes:

[0100] The CPU is controlled to verify the validity of the data copy command.

[0101] The control central processing unit (CPU) sends a data copy command to the general-purpose flash memory (UFS) controller, including:

[0102] If the data copy command is valid, the control CPU sends the data copy command to the UFS controller.

[0103] This situation can be understood as follows: before controlling the CPU to send a data copy command to the UFS, it is necessary to ensure that the copy command is accurate. Therefore, it is necessary to first verify the validity of the information used to construct the data copy command. Only after the validity verification is passed can the CPU be controlled to send the data copy command to the UFS.

[0104] Optionally, in one implementation, the control CPU performs a validity check on the data copy command, including:

[0105] The CPU is controlled to perform validity checks on at least one of the following data copy commands:

[0106] A11. Is the amount of data corresponding to the source address equal to the amount of data corresponding to the destination address?

[0107] It should be noted that if the amount of data corresponding to the source address is equal to the amount of data corresponding to the destination address, the validity verification passes; otherwise, the validity verification fails.

[0108] A12. Whether the total length of the command format corresponding to the data copy command is the same as the length of the command constructed from the source address information and the destination address information;

[0109] It should be noted that the system pre-sets the command format for each command, which corresponds to a specific total length (which can be understood as bit length). In this case, the system verifies whether the information constituting the data copy command is equal to the total length corresponding to the pre-set command format. If they are equal, the validity verification passes; otherwise, the validity verification fails.

[0110] A13. Whether the source address and destination address are valid, the validity of the source address and destination address includes at least one of the following: the address is not negative, and it does not exceed the maximum address range of UFS.

[0111] Optionally, in one implementation, the method further includes:

[0112] The UFS is controlled to return the data copy result to the CPU;

[0113] If the data copy result includes abnormal information, the CPU is controlled to perform error handling operations corresponding to the abnormal information.

[0114] It should be noted that if UFS successfully completes the data copy, the data copy result reported by UFS to the CPU indicates that the data copy is complete. If UFS fails to complete the data copy, the data copy result reported by UFS to the CPU includes exception information. Optionally, the CPU will store the error execution code corresponding to each exception information. The CPU only needs to execute the corresponding error handling code according to the corresponding exception information.

[0115] For example, if the error message is "UFS busy", the CPU can send the data copy command to the UFS again after receiving the error message; if the error message is "UFS failed to execute the copy command", the CPU will send a copy failure message to the user after receiving the error message.

[0116] The following example illustrates the specific implementation process of this application embodiment, taking the example of a user wanting to copy the content of file1 (UFS address 1, data length 1) and the content of file2 (UFS address 2, data length 2) together to file3 (UFS address 3).

[0117] As shown in Figure 3, the specific implementation process includes:

[0118] Step 301: The CPU obtains the source address and destination address of the required data copy and assembles the source entry and destination entry.

[0119] The entry contains the starting UFS address and the amount of data, and its format is shown in Figure 4. Optionally, the source entry and the destination entry use the same format, and multiple entries are allowed for each.

[0120] Based on the example user copy requirement, a total of 1 destination entry and 2 source entries are needed. The destination entry contains information about UFS address 3, data length 1, and data length 2. The source entry 1 contains information about UFS address 1 and data length 1, and the source entry 2 contains information about UFS address 2 and data length 2.

[0121] Step 302: Control the CPU to execute code to assemble data in a command format (for recognition by the UFS controller; Figure 5 shows an example of a command format, which does not constitute a limitation on the command format), and perform validity verification on the copy command. If the verification passes, send the data copy command to the UFS.

[0122] The validity check of the copy command includes at least one of the following: whether the amount of data corresponding to the source address is equal to the amount of data corresponding to the destination address; whether the total length of the command format corresponding to the data copy command is the same as the length of the command constructed from the source address information and the destination address information; and whether the source address and destination address are valid (valid source address and destination address include at least one of the following: the address is not negative and does not exceed the maximum address range of UFS). After the verification passes, the CPU sends the data copy command to the UFS controller.

[0123] Optionally, based on the example user copy requirements, the CPU should transmit the following detailed information about the data copy command to the UFS controller: one destination entry, two source entries, and corresponding values ​​are assigned. The contents of the entries are sequentially from 1 to n (n≥1).

[0124] Step 303: Control the UFS controller to receive the data copy command and parse the information of the source entry and destination entry. After parsing, control the UFS controller to read all the data from the source entry in the data storage unit inside the UFS, and then write it to each destination entry in sequence. After completing the reading and writing, control the UFS controller to return the execution result to the CPU.

[0125] It should be noted that since there may be multiple entries, they must be written in the order they are passed in. The reading and writing order is shown in Figure 7.

[0126] Step 304: Control the UFS controller to return the data copy result to the CPU.

[0127] If the copy is successfully completed, the data copy result indicates that the copy is complete; if the copy is not completed, the UFS controller will return an exception message. The CPU receives the exception message and executes the pre-set error handling code. Different error codes can be handled differently (for example, if UFS returns busy, the CPU can resend the command after receiving it; if UFS fails to execute the command, the CPU will inform the user that the copy failed after receiving it).

[0128] It should be noted that the data copy operation in this application embodiment can reduce the path of the underlying UFS data stream in the copy scenario, and complete the data copy directly inside the UFS, thereby reducing copy time and power consumption, and improving user experience. In addition, this data copy method eliminates the need to read data from UFS to LPDDR, thereby avoiding the bit flip problem that may exist in LPDDR and improving the stability of copied data. This data copy method also does not destroy the source data position, so it will not cause user source data to be corrupted. It should also be noted that this application embodiment supports passing multiple destination addresses and multiple source addresses in a single command to meet the complex copy scenarios where the destination addresses are continuous or non-contiguous.

[0129] Optionally, the aforementioned data copying operation can also be introduced in incremental upgrade scenarios of electronic devices. Optionally, in this application scenario, controlling the CPU to execute the error handling operation corresponding to the abnormal information includes:

[0130] The CPU is controlled to remap the partition and the upgrade progress is synchronized with the kernel, enabling the kernel to perform the upgrade process.

[0131] In this case, it can be understood that if the data copying method based on the embodiment of this application fails to copy the data normally, the CPU needs to remap the partition and then notify the kernel of the upgrade progress so that the kernel can perform the upgrade process.

[0132] Optionally, it should also be noted that, in the incremental upgrade scenario, in this embodiment of the application, before the central processing unit (CPU) sends the data copy command to the general-purpose flash memory (UFS) controller, the method further includes:

[0133] Control the CPU to sort operations, placing all data copy operations involved in the incremental upgrade process after non-data copy operations;

[0134] The control central processing unit (CPU) sends a data copy command to the general-purpose flash memory (UFS) controller, including:

[0135] After performing the non-data copy operation, the control CPU sends a data copy command to the UFS.

[0136] In other words, in incremental upgrade scenarios, non-data copy operations are performed first, and data copy operations are performed only after the non-data copy operations are completed. This can prevent data corruption and ensure the accuracy of incremental upgrades.

[0137] The incremental upgrade process of data copying using the embodiments of this application is illustrated below with an example.

[0138] As shown in Figure 8, the specific implementation process includes:

[0139] Step 801: Parse the incoming incremental upgrade package to obtain the source address, destination address, and the corresponding amount of data to be written.

[0140] Optionally, the source and destination addresses of a static partition both come from the upgrade package; the source address of a dynamic partition comes from the upgrade package, and the destination address is provided by a global location variable maintained during the upgrade process. The global location variable is calculated from a virtual offset and the actual physical address mapping table of the destination device.

[0141] Step 802: Perform all non-data copy operations during the upgrade.

[0142] This section requires that the data copy operation be placed last in the upgrade package. This is because when the kernel writes non-data copy operations, there is no order in which they are performed, which may overwrite the data written to the partition during the data copy operation, thus causing data corruption. Therefore, the CPU needs to sort the operations and place the data copy operation after the non-data copy operation. The non-data copy operation is executed first, and then the data copy operation is executed uniformly.

[0143] Optionally, for static partitions, the upgrade operation can be performed normally. For dynamic partitions, it is necessary to record the actual destination address of the data being written in real time, and to refresh the disk after writing to ensure that the data is persisted. Subsequent data copy operations will continue to write data based on the recorded address.

[0144] Step 803: Perform the initialization operation in the data copy operation.

[0145] These initialization operations may include obtaining the source and destination partition mapping table and calculating the starting address, as well as the logical unit number of the partition corresponding to the UFS.

[0146] Step 804: Select the destination entry.

[0147] The destination entry can include the starting UFS address and data size. The destination entry for a single command is selected based on factors such as highest execution efficiency (fewest command issuances, maximum information carried per command), no lag during execution (command execution time), and the size of the input data copy operation.

[0148] Because the destination address of a dynamic partition during an upgrade is different from that of a static partition, which has a continuous physical address and does not require recording metadata, the data format and physical address information of the destination address must be considered when selecting the destination entry for a single deployment.

[0149] Step 805: Select the matching source entry based on the destination entry.

[0150] The matching logic is the same for static and dynamic partitions, matching sequentially according to the information in the upgrade package. For example, here are some examples of destination and source entries:

[0151] In the example, for (A, B), A is the virtual address offset and B is the size of the data to be written. If the destination entry selected in step 804 is (2832, 512), then based on the above example, the source entries are (2832, 500) and (1618, 12).

[0152] Step 806: Control the CPU to verify the validity of the data copy command for the assembly. If the verification is successful, control the CPU to send the data copy command to the UFS controller.

[0153] This part of the static partition is the same as the dynamic partition. The data sent to the UFS controller includes all destination entry information, source entry information, total data length, etc.

[0154] It should be noted that the CPU allows multiple processes to send data copy operations simultaneously.

[0155] Step 807: After receiving the command sent by the system, the UFS controller parses the data and completes the data copy operation inside the device, and controls the UFS controller to return the data copy result to the CPU.

[0156] Step 808: The CPU receives the data copy result returned by UFS and continues to perform the upgrade operations.

[0157] For example, writing metadata for upgrade operations and executing the next upgrade operation.

[0158] Step 809: After all upgrade data copy operations are completed, remap the partition to synchronize the progress of the new scheme to the kernel.

[0159] Furthermore, the kernel will continue to perform verification and data merging. It should be noted that the kernel execution process is consistent with the relevant technologies, and will not be elaborated here.

[0160] It should be noted that if UFS execution encounters an exception, the CPU will parse the exception information returned by UFS and follow the pre-defined exception handling process, as shown in Figure 9. The specific implementation process includes:

[0161] Step 901, data copying process;

[0162] Step 901 is similar to steps 805-807 described above, and will not be repeated here.

[0163] Step 902: Control the CPU to determine whether the data copy operation is abnormal;

[0164] If an error occurs, proceed to step 903; if the execution is successful, return to step 901.

[0165] Step 903: Control the CPU to remap all partitions and synchronize the upgrade progress to the kernel;

[0166] Step 904: The control kernel re-executes the current operation in the traditional manner and continues execution based on the current upgrade.

[0167] It should be noted that this method ensures that the upgrade will not fail directly due to the failure of the copy command, and this solution will continue to perform the upgrade based on the previous progress, ensuring upgrade efficiency and making it imperceptible to the user.

[0168] It should be noted that the incremental upgrade scheme of this application embodiment can reduce the path of data copying in the underlying UFS data stream during the upgrade, and complete the data copying directly inside UFS. The size of a single command can be increased, and hash verification is removed. Based on the above three points, the user upgrade time can be reduced. At the same time, the data does not need to be read from UFS to LPDDR, which can improve the data copying efficiency, reduce the power consumption of the user upgrade, and avoid the bit flip problem that may exist in LPDDR, thus improving the stability of copied data.

[0169] It should be noted that the data processing method provided in this application embodiment can be executed by a data processing device or a control module within that data processing device for executing the data processing method. This application embodiment uses the execution of the data processing method by a data processing device as an example to illustrate the data processing method provided in this application embodiment.

[0170] As shown in Figure 10, at least one embodiment of this application also provides a data processing apparatus 1000, applied to an electronic device, the apparatus comprising:

[0171] The first control module 1001 is used to control the central processing unit (CPU) to send a data copy command to the general-purpose flash memory (UFS) controller; the data copy command is used to indicate the source address and destination address of the data copy.

[0172] The second control module 1002 is used to control the UFS controller to copy data from the source address to the destination address in response to the data copy command.

[0173] Optionally, the data copy command includes source address information and destination address information; the source address information includes the source address, or the source address and the amount of data corresponding to the source address; the destination address information includes the destination address, or the destination address and the amount of data corresponding to the destination address.

[0174] Optionally, the number of source address information is one, and the number of destination address information is one.

[0175] Optionally, the number of source address information is one, and the number of destination address information is at least two.

[0176] Optionally, the number of source address information is at least two, and the number of destination address information is one.

[0177] Optionally, the number of source address information is at least two, and the at least two source address information includes first source address information and second source address information;

[0178] The number of destination address information is at least two, and the at least two destination address information includes first destination address information and second destination address information;

[0179] The first source address information and the first destination address information have a copy relationship;

[0180] There is a copy relationship between the second source address information and the second destination address information.

[0181] Optionally, the source address information includes a source address and the amount of data corresponding to the source address, and the destination address information includes a destination address and the amount of data corresponding to the destination address, wherein the sum of the amounts of data corresponding to at least two source addresses is equal to the amount of data corresponding to the destination address.

[0182] Optionally, the source address information includes a source address and the amount of data corresponding to the source address, the destination address information includes a destination address and the amount of data corresponding to the destination address, the amount of data corresponding to the first source address information is equal to the amount of data between the first destination address information, and the amount of data corresponding to the second source address information is equal to the amount of data between the second destination address information.

[0183] Optionally, the number of source addresses is at least one, and the number of destination addresses is at least one;

[0184] The second control module 1002 includes:

[0185] A first control unit is configured to control the UFS to read data from each of the source addresses in response to the data copy command;

[0186] The second control unit is used to control the UFS to copy the data read from each of the source addresses to the corresponding destination addresses.

[0187] Optionally, before the first control module 1001 controls the central processing unit (CPU) to send a data copy command to the general-purpose flash memory (UFS) controller, the device further includes:

[0188] The third control module is used to control the CPU to verify the validity of the data copy command.

[0189] The first control module 1001 is used for:

[0190] If the data copy command is valid, the control CPU sends the data copy command to the UFS controller.

[0191] Optionally, the third control module is used for:

[0192] The CPU is controlled to perform validity checks on at least one of the following data copy commands:

[0193] Is the amount of data corresponding to the source address equal to the amount of data corresponding to the destination address?

[0194] Is the total length of the command format corresponding to the data copy command the same as the length of the command constructed from the source address information and the destination address information?

[0195] Whether the source address and destination address are valid, the validity of the source address and destination address includes at least one of the following: the address is not negative, and it does not exceed the maximum address range of UFS.

[0196] Optionally, the device further includes:

[0197] The fourth control module is used to control the UFS to return the data copy result to the CPU;

[0198] The fifth control module is used to control the CPU to perform error handling operations corresponding to the abnormal information when the data copy result includes abnormal information.

[0199] Optionally, in the case of incremental upgrades, the fifth control module is used to:

[0200] The CPU is controlled to remap the partition and the upgrade progress is synchronized with the kernel, enabling the kernel to perform the upgrade process.

[0201] Optionally, in the case of incremental upgrades, before the first control module 1001 controls the central processing unit (CPU) to send a data copy command to the general-purpose flash memory (UFS) controller, the device further includes:

[0202] The sixth control module is used to control the CPU to sort operations, arranging all data copy operations included in the incremental upgrade process after non-data copy operations;

[0203] The first control module 1001 is used for:

[0204] After performing the non-data copy operation, the control CPU sends a data copy command to the UFS.

[0205] Optionally, the UFS includes a UFS controller and a data storage unit; wherein the UFS controller is configured to read data from the source address of the data storage unit in response to the data copy command, and write the read data to the target address of the data storage unit.

[0206] It should be noted that this device embodiment corresponds to the above method, and all implementation methods in the above method embodiment are applicable to this device embodiment and can achieve the same technical effect.

[0207] The data processing device in this application embodiment can be a device, or a component, integrated circuit, or chip in a terminal. The device can be a mobile electronic device or a non-mobile electronic device. For example, mobile electronic devices can be mobile phones, tablets, laptops, PDAs, in-vehicle electronic devices, wearable devices, ultra-mobile personal computers (UMPCs), netbooks, or personal digital assistants (PDAs), etc., while non-mobile electronic devices can be servers, network-attached storage (NAS), personal computers (PCs), televisions (TVs), ATMs, or self-service machines, etc. This application embodiment does not impose specific limitations.

[0208] The data processing device in this application embodiment can be a device with an operating system. The operating system can be Android, iOS, or other possible operating systems; this application embodiment does not specifically limit the specific operating system.

[0209] The data processing apparatus provided in this application embodiment can implement the various processes implemented in the method embodiment of FIG1. ​​To avoid repetition, it will not be described again here.

[0210] The apparatus in this application embodiment controls the CPU to send a copy command carrying the source address and destination address to the UFS, thereby controlling the UFS to directly obtain data from the indicated source address and copy it to the location indicated by the destination address. This reduces the signaling interaction process during data copying, saves data copying time, improves data copying efficiency, and also reduces system power consumption.

[0211] Optionally, as shown in FIG11, this application embodiment also provides an electronic device 1100, including a processor 1101, a memory 1102, and a program or instructions stored in the memory 1102 and executable on the processor 1101. When the program or instructions are executed by the processor 1101, they implement the various processes of the above-described data processing method embodiment and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0212] It should be noted that the electronic devices in the embodiments of this application include the mobile electronic devices and non-mobile electronic devices described above.

[0213] Figure 12 is a schematic diagram of the hardware structure of an electronic device that implements an embodiment of this application.

[0214] The electronic device 1200 includes, but is not limited to, components such as: radio frequency unit 1201, network module 1202, audio output unit 1203, input unit 1204, sensor 1205, display unit 1206, user input unit 1207, interface unit 1208, memory 1209, and processor 1210.

[0215] Those skilled in the art will understand that the electronic device 1200 may also include a power supply (such as a battery) for powering various components. The power supply can be logically connected to the processor 1210 through a power management system, thereby enabling functions such as managing charging, discharging, and power consumption through the power management system. The electronic device structure shown in Figure 12 does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown, or combine certain components, or have different component arrangements, which will not be elaborated here.

[0216] The processor 1210 is used for:

[0217] The central processing unit (CPU) sends a data copy command to the general-purpose flash memory (UFS) controller; the data copy command indicates the source address and destination address of the data copy.

[0218] The UFS controller is controlled to respond to the data copy command and copy the data from the source address to the destination address.

[0219] Optionally, the data copy command includes source address information and destination address information; the source address information includes the source address, or the source address and the amount of data corresponding to the source address; the destination address information includes the destination address, or the destination address and the amount of data corresponding to the destination address.

[0220] Optionally, the number of source address information is one, and the number of destination address information is one.

[0221] Optionally, the number of source address information is one, and the number of destination address information is at least two.

[0222] Optionally, the number of source address information is at least two, and the number of destination address information is one.

[0223] Optionally, the number of source address information is at least two, and the at least two source address information includes first source address information and second source address information;

[0224] The number of destination address information is at least two, and the at least two destination address information includes first destination address information and second destination address information;

[0225] The first source address information and the first destination address information have a copy relationship;

[0226] There is a copy relationship between the second source address information and the second destination address information.

[0227] Optionally, the source address information includes a source address and the amount of data corresponding to the source address, and the destination address information includes a destination address and the amount of data corresponding to the destination address, wherein the sum of the amounts of data corresponding to at least two source addresses is equal to the amount of data corresponding to the destination address.

[0228] Optionally, the source address information includes a source address and the amount of data corresponding to the source address, the destination address information includes a destination address and the amount of data corresponding to the destination address, the amount of data corresponding to the first source address information is equal to the amount of data between the first destination address information, and the amount of data corresponding to the second source address information is equal to the amount of data between the second destination address information.

[0229] Optionally, the number of source addresses is at least one, and the number of destination addresses is at least one;

[0230] The processor 1210 is used for:

[0231] The UFS is controlled to respond to the data copy command and read data from each of the source addresses;

[0232] The UFS is controlled to copy the data read from each of the source addresses to the corresponding destination addresses.

[0233] Optionally, the processor 1210 is further configured to:

[0234] The CPU is controlled to verify the validity of the data copy command.

[0235] The processor 1210 is used for:

[0236] If the data copy command is valid, the control CPU sends the data copy command to the UFS controller.

[0237] Optionally, the processor 1210 is configured to:

[0238] The CPU is controlled to perform validity checks on at least one of the following data copy commands:

[0239] Is the amount of data corresponding to the source address equal to the amount of data corresponding to the destination address?

[0240] Is the total length of the command format corresponding to the data copy command the same as the length of the command constructed from the source address information and the destination address information?

[0241] Whether the source address and destination address are valid, the validity of the source address and destination address includes at least one of the following: the address is not negative, and it does not exceed the maximum address range of UFS.

[0242] Optionally, the processor 1210 is further configured to:

[0243] The UFS is controlled to return the data copy result to the CPU;

[0244] If the data copy result includes abnormal information, the CPU is controlled to perform error handling operations corresponding to the abnormal information.

[0245] Optionally, in the case of incremental upgrades, the processor 1210 is used to:

[0246] The CPU is controlled to remap the partition and the upgrade progress is synchronized with the kernel, enabling the kernel to perform the upgrade process.

[0247] Optionally, in the case of incremental upgrades, the processor 1210 is further configured to:

[0248] Control the CPU to sort operations, placing all data copy operations involved in the incremental upgrade process after non-data copy operations;

[0249] The processor 1210 is used for:

[0250] After performing the non-data copy operation, the control CPU sends a data copy command to the UFS.

[0251] Optionally, the UFS includes a UFS controller and a data storage unit; wherein the UFS controller is configured to read data from the source address of the data storage unit in response to the data copy command, and write the read data to the target address of the data storage unit.

[0252] It should be noted that, in this embodiment of the application, the CPU is controlled to send a copy command carrying the source address and destination address to the UFS, thereby controlling the UFS to directly obtain data from the indicated source address and copy it to the location indicated by the destination address. This reduces the signaling interaction process during data copying, saves data copying time, improves data copying efficiency, and also reduces system power consumption.

[0253] It should be understood that, in this embodiment, the input unit 1204 may include a graphics processing unit (GPU) 12041 and a microphone 12042. The GPU 12041 processes image data of still images or videos obtained by an image capture device (such as a camera) in video capture mode or image capture mode. The display unit 1206 may include a display panel 12061, which may be configured in the form of a liquid crystal display, an organic light-emitting diode, etc. The user input unit 1207 includes a touch panel 12071 and other input devices 12072. The touch panel 12071 is also called a touch screen. The touch panel 12071 may include a touch detection device and a touch controller. Other input devices 12072 may include, but are not limited to, physical keyboards, function keys (such as volume control buttons, power buttons, etc.), trackballs, mice, joysticks, etc., which will not be described in detail here. The memory 1209 can be used to store software programs and various data, including but not limited to applications and operating systems. Processor 1210 may integrate an application processor and a modem processor. The application processor mainly handles the operating system, user interface, and applications, while the modem processor mainly handles wireless communication. It is understood that the modem processor may also not be integrated into processor 1210.

[0254] This application also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the various processes of the above-described data processing method embodiments and achieve the same technical effects. To avoid repetition, they will not be described again here.

[0255] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0256] This application embodiment also provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the various processes of the above data processing method embodiments and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0257] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0258] This application also provides a computer program / program product, which is stored in a storage medium and executed by at least one processor to implement the various processes of the above-described data processing method embodiments, and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0259] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0260] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the related technology, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0261] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A data processing method, comprising: Controls the central processing unit (CPU) to send data copy commands to the general-purpose flash memory (UFS); The data copy command is used to indicate the source address and destination address of the data to be copied; The UFS is controlled to respond to the data copy command and copy the data from the source address to the destination address.

2. The method according to claim 1, wherein, The data copy command includes source address information and destination address information; the source address information includes the source address, or the source address and the amount of data corresponding to the source address; the destination address information includes the destination address, or the destination address and the amount of data corresponding to the destination address.

3. The method according to claim 2, wherein, The number of source address information is one, and the number of destination address information is one.

4. The method according to claim 2, wherein, The number of source address information is one, and the number of destination address information is at least two.

5. The method according to claim 2, wherein, The number of source address information is at least two, and the number of destination address information is one.

6. The method according to claim 2, wherein, The number of source address information is at least two, and the at least two source address information includes first source address information and second source address information; The number of destination address information is at least two, and the at least two destination address information includes first destination address information and second destination address information; The first source address information and the first destination address information have a copy relationship; There is a copy relationship between the second source address information and the second destination address information.

7. The method according to claim 5, wherein, The source address information includes the source address and the amount of data corresponding to the source address, and the destination address information includes the destination address and the amount of data corresponding to the destination address, wherein the sum of the amounts of data corresponding to at least two source addresses is equal to the amount of data corresponding to the destination address.

8. The method according to claim 6, wherein, The source address information includes the source address and the amount of data corresponding to the source address, and the destination address information includes the destination address and the amount of data corresponding to the destination address. The amount of data corresponding to the first source address information is equal to the amount of data between the first destination address information, and the amount of data corresponding to the second source address information is equal to the amount of data between the second destination address information.

9. The method according to claim 2, wherein, The number of source addresses is at least one, and the number of destination addresses is at least one; The step of controlling the UFS to respond to the data copy command and copy data from the source address to the destination address includes: The UFS is controlled to respond to the data copy command and read data from each of the source addresses; The UFS is controlled to copy the data read from each of the source addresses to the corresponding destination addresses.

10. The method according to claim 2, wherein, Before the central processing unit (CPU) sends a data copy command to the general-purpose flash memory (UFS) controller, the method further includes: The CPU is controlled to verify the validity of the data copy command. The control central processing unit (CPU) sends a data copy command to the general-purpose flash memory (UFS) controller, including: If the data copy command is valid, the control CPU sends the data copy command to the UFS controller.

11. The method according to claim 10, wherein, The control CPU performs validity verification on the data copy command, including: The CPU is controlled to perform validity checks on at least one of the following data copy commands: Is the amount of data corresponding to the source address equal to the amount of data corresponding to the destination address? Is the total length of the command format corresponding to the data copy command the same as the length of the command constructed from the source address information and the destination address information? Whether the source address and destination address are valid, the validity of the source address and destination address includes at least one of the following: the address is not negative, and it does not exceed the maximum address range of UFS.

12. The method according to claim 1, further comprising: The UFS is controlled to return the data copy result to the CPU; If the data copy result includes abnormal information, the CPU is controlled to perform error handling operations corresponding to the abnormal information.

13. The method according to claim 12, wherein, In an incremental upgrade scenario, controlling the CPU to perform error handling operations corresponding to the exception information includes: The CPU is controlled to remap the partition and the upgrade progress is synchronized with the kernel, enabling the kernel to perform the upgrade process.

14. The method according to claim 1, wherein, In the scenario of incremental upgrades, before the central processing unit (CPU) sends a data copy command to the general-purpose flash memory (UFS) controller, the method further includes: Control the CPU to sort operations, placing all data copy operations involved in the incremental upgrade process after non-data copy operations; The control central processing unit (CPU) sends a data copy command to the general-purpose flash memory (UFS) controller, including: After performing the non-data copy operation, the control CPU sends a data copy command to the UFS.

15. The method according to claim 1, wherein, The UFS includes a UFS controller and a data storage unit; wherein, the UFS controller is used to read data from the source address of the data storage unit in response to the data copy command, and write the read data to the target address of the data storage unit.

16. A data processing apparatus, comprising: The first control module is used to control the central processing unit (CPU) to send data copy commands to the general-purpose flash memory (UFS) controller. The data copy command is used to indicate the source address and destination address of the data to be copied; The second control module is used to control the UFS controller to copy data from the source address to the destination address in response to the data copy command.

17. The apparatus according to claim 16, wherein, The data copy command includes source address information and destination address information; the source address information includes the source address, or the source address and the amount of data corresponding to the source address; the destination address information includes the destination address, or the destination address and the amount of data corresponding to the destination address.

18. An electronic device comprising a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the data processing method as claimed in any one of claims 1-15.

19. A readable storage medium storing a program or instructions that, when executed by a processor, implement the steps of the data processing method as claimed in any one of claims 1-15.

20. A computer program product comprising computer instructions that, when executed by a processor, implement the steps of the data processing method as claimed in any one of claims 1-15.

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