Pixel circuit and driving method therefor, display panel, and display device

Abstract

The present application discloses a pixel circuit and a driving method therefor, a display panel, and a display device. The pixel circuit comprises a driving module, a voltage control module, and a light-emitting module; the driving module and the voltage control module are connected between a first power supply line and a first end of the light-emitting module; a second end of the light-emitting module is connected to a second power supply line; the driving module is used for driving the light-emitting module to emit light; and the voltage control module is used for controlling, when a display gray scale is less than a preset gray scale, the voltage of the end of the driving module connected to the voltage control module. The technical solution of the present application can improve the display brightness at a low gray scale, thereby improving the display effect.

Description

Pixel circuits and their driving methods, display panels and display devices

[0001] This application claims priority to Chinese Patent Application No. 202510072801.7, filed with the Chinese Patent Office on January 16, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, such as a pixel circuit and its driving method, a display panel, and a display device. Background Technology

[0003] With the continuous development of display technology, people have increasingly higher requirements for display quality.

[0004] Currently, the display panels in related technologies suffer from poor display quality. Summary of the Invention

[0005] This application provides a pixel circuit and its driving method, a display panel, and a display device to improve display performance.

[0006] According to one aspect of this application, a pixel circuit is provided, comprising: a driving module, a voltage control module, and a light-emitting module;

[0007] The driving module and the voltage control module are connected between the first power line and the first end of the light-emitting module. The second end of the light-emitting module is connected to the second power line. The driving module is configured to drive the light-emitting module to emit light. The voltage control module is configured to control the voltage at one end of the connection between the driving module and the voltage control module when the displayed grayscale is less than a preset grayscale.

[0008] According to another aspect of this application, a driving method for a pixel circuit is provided. The pixel circuit includes a driving module, a voltage control module, and a light-emitting module. The driving method for the pixel circuit includes:

[0009] During the light-emitting stage, the control driving module drives the light-emitting module to emit light; wherein, when the displayed gray level is less than the preset gray level, the control voltage control module controls the voltage at one end of the connection between the driving module and the voltage control module.

[0010] According to another aspect of this application, a display panel is provided, the display panel comprising:

[0011] Substrate;

[0012] The active layer is located on one side of the substrate;

[0013] A multilayer conductive layer is stacked on the side of the active layer away from the substrate;

[0014] At least one pixel circuit, the pixel circuit including a driving module, a voltage control module and a light-emitting module, wherein the driving module includes a first transistor, the voltage control module includes a second transistor, and the light-emitting module includes a light-emitting diode;

[0015] The multilayer conductive layer includes a first conductive layer, the gate of the first transistor and the gate of the second transistor are both located in the first conductive layer, and the orthogonal projection of the gate of the second transistor on the substrate is located between the orthogonal projection of the gate of the first transistor on the substrate and the orthogonal projection of the first electrode of the light-emitting diode on the substrate.

[0016] According to another aspect of this application, a display device is provided, which includes the display panel provided in any embodiment of this application. Attached Figure Description

[0017] Figure 1 is a schematic diagram of a pixel circuit provided in an embodiment of this application;

[0018] Figure 2 is a schematic diagram of another pixel circuit provided in an embodiment of this application;

[0019] Figure 3 is a schematic diagram of another pixel circuit provided in an embodiment of this application;

[0020] Figure 4 is a schematic diagram of another pixel circuit provided in an embodiment of this application;

[0021] Figure 5 is a schematic diagram of another pixel circuit provided in an embodiment of this application;

[0022] Figure 6 is a schematic diagram of another pixel circuit provided in an embodiment of this application;

[0023] Figure 7 is a schematic diagram of another pixel circuit provided in an embodiment of this application;

[0024] Figure 8 is a schematic diagram of another pixel circuit provided in an embodiment of this application;

[0025] Figure 9 is a schematic diagram of the driving timing of a pixel circuit provided in an embodiment of this application;

[0026] Figure 10 is a schematic diagram of another pixel circuit provided in an embodiment of this application;

[0027] Figure 11 is a schematic diagram of another pixel circuit provided in an embodiment of this application;

[0028] Figure 12 is a schematic diagram of the driving timing of another pixel circuit provided in an embodiment of this application;

[0029] Figure 13 is a schematic diagram of grayscale expansion provided in an embodiment of this application;

[0030] Figure 14 is a schematic diagram of another pixel circuit provided in an embodiment of this application;

[0031] Figure 15 is a schematic diagram of another pixel circuit provided in an embodiment of this application;

[0032] Figure 16 is a schematic diagram of another pixel circuit provided in an embodiment of this application;

[0033] Figure 17 is a schematic diagram of another pixel circuit provided in an embodiment of this application;

[0034] Figure 18 is a schematic diagram of another pixel circuit provided in an embodiment of this application;

[0035] Figure 19 is a schematic diagram of another pixel circuit provided in an embodiment of this application;

[0036] Figure 20 is a schematic diagram of the driving timing of another pixel circuit provided in an embodiment of this application;

[0037] Figure 21 is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0038] Figure 22 is a schematic diagram of another display panel provided in an embodiment of this application;

[0039] Figure 23 is a schematic diagram of another display panel provided in an embodiment of this application;

[0040] Figure 24 is a schematic diagram of the structure of a display device provided in an embodiment of this application;

[0041] Figure 25 is a flowchart of a pixel circuit driving method provided in an embodiment of this application. Detailed Implementation

[0042] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0043] Display panels typically include pixel circuits, which consist of a driving module and light-emitting devices (LEDs). The driving module drives the LEDs to emit light, and the driving current directly affects the brightness of the LEDs. In recent years, with the emergence of high-voltage LEDs such as multilayer LEDs and quantum dot LEDs, the difference in anode voltage between the LEDs in black and bright states has become significant. When displaying low grayscale levels, the anode voltage of the LEDs is very low, resulting in a large voltage difference across the driving module. This leads to increased leakage current in the driving module, which in turn affects the brightness of low grayscale levels and reduces the display effect.

[0044] This application provides a pixel circuit to improve black state brightness, thereby achieving a black state display effect. Figure 1 is a schematic diagram of the structure of a pixel circuit provided in this application embodiment. Referring to Figure 1, the pixel circuit provided in this application embodiment includes a driving module 110, a voltage control module 120, and a light-emitting module 130. The driving module 110 and the voltage control module 120 are connected between a first power line L1 and a first end of the light-emitting module 130. The second end of the light-emitting module 130 is connected to a second power line L2. The driving module 110 is used to drive the light-emitting module 130 to emit light. The voltage control module 120 is used to control the voltage at one end of the connection between the driving module 110 and the voltage control module 120 when the displayed gray level is less than a preset gray level, so as to limit the current flowing to the light-emitting module 130.

[0045] For example, a preset grayscale can be used to divide low grayscale and medium-high grayscale. When the currently displayed grayscale is less than the preset grayscale, it can be characterized as the currently displayed grayscale being low grayscale; when the currently displayed grayscale is greater than or equal to the preset grayscale, it can be characterized as the currently displayed grayscale being medium-high grayscale.

[0046] The pixel circuit also includes a data writing module 140, which is used to transmit data voltage Vdata to the driving module 110. Different display gray levels correspond to different data voltages Vdata.

[0047] When the displayed grayscale is medium to high grayscale, the data writing module 140 writes the data voltage Vdata corresponding to the current displayed grayscale to the control terminal of the driving module 110. The driving module 110 generates a large driving current. The voltage control module 120 remains in the conducting state under the voltage of the second terminal N2 of the driving module 110. The driving module 110 drives the light-emitting module 130 to emit light, thereby realizing the medium to high grayscale display.

[0048] When the grayscale level is low, the data voltage Vdata corresponding to the current grayscale level is written to the control terminal of the drive module 110 through the data writing module 140. The drive module 110 generates a small drive current, and the voltage control module 120 is turned off or semi-conducted under the voltage of the second terminal N2 of the drive module 110, so as to realize the low grayscale display.

[0049] The technical solution provided in this application embodiment adds a voltage control module 120 to the connection path between the driving module 110 and the light-emitting module 130 to cut off the direct connection between the driving module 110 and the light-emitting module 130. The voltage control module 120 controls the voltage at the end connected to the driving module 110 and the voltage control module 120 when the displayed grayscale is less than the preset grayscale. This can raise the voltage at the end connected to the driving module 110 and the voltage control module 120, thereby reducing the voltage difference between the first terminal N1 and the second terminal N2 of the driving module 110. This reduces the leakage current of the driving module 110 at low grayscale and limits the current flowing to the light-emitting module 130, thereby improving the display brightness at low grayscale and improving the display effect.

[0050] Figure 2 is a schematic diagram of another pixel circuit provided in an embodiment of this application. Referring to Figure 2, based on the above embodiment, optionally, when the displayed gray level is less than a preset gray level, the transistors included in the voltage control module are in the cutoff region or subthreshold region. For example, the driving module 110 includes a first transistor M1, the voltage control module 120 includes a second transistor M2, and the light-emitting module 130 includes a light-emitting diode D1. The second terminal of the first transistor M1 is connected to the first terminal of the second transistor M2, and the second terminal of the second transistor M2 is connected to the first terminal (anode) of the light-emitting diode D1. Taking the first transistor M1 and the second transistor M2 as examples where both are P-type transistors, the first terminal is the source and the second terminal is the drain.

[0051] The control terminal of the voltage control module 120 is connected to the first voltage signal line, which transmits the first voltage V1. When the displayed grayscale is less than a preset grayscale, the first voltage V1 is greater than the voltage at the first terminal of the light-emitting module 130. The absolute value of the difference between the first voltage V1 and the voltage at one end of the driving module 110 is less than the absolute value of the threshold voltage of the voltage control module 120. One end of the driving module 110 is the end connected to the voltage control module 120. That is, by setting the first voltage V1, the voltage difference between the first voltage V1 and the voltage at the second terminal N2 of the driving module 110 is less than the threshold voltage Vth2 of the second transistor M2, thereby making the second transistor M2 in the subthreshold region. At low grayscale, the gate voltage of the second transistor M2 is fixed at the first voltage V1. Due to the inherent characteristics of the subthreshold region, the voltage of the first terminal (source) of the second transistor M2 is limited to a relatively stable range. Therefore, the change in the voltage of the first terminal of the second transistor M2 (i.e., the voltage of the second terminal N2 of the driving module 110) is less than V1-Vth2. Even if the voltage of the first terminal of the light-emitting diode D1 is small at low grayscale, it will not significantly lower the voltage of the first terminal of the second transistor M2, thereby increasing the voltage of the second terminal N2 of the driving module 110, and further reducing the voltage difference between the first terminal N1 and the second terminal N2 of the driving module 110, which is beneficial to reducing the leakage current of the driving module 110.

[0052] Optionally, in this embodiment, the preset grayscale can be 16 grayscale or 32 grayscale. When the displayed grayscale is 0, a black screen is displayed, i.e., it is in a black state.

[0053] The technical solution provided in this embodiment sets a first voltage V1 connected to the control terminal of the voltage control module 120. When the displayed grayscale is less than a preset grayscale, the second transistor included in the voltage control module 120 is placed in the subthreshold region. This limits the voltage of the second terminal N2 of the driving module 110 to a relatively stable range, preventing it from dropping to the voltage of the first electrode of the light-emitting diode D1. This, in turn, increases the voltage of the second terminal N2 of the driving module 110, reduces the voltage difference between the first terminal N1 and the second terminal N2 of the driving module 110, and lowers the leakage current of the driving module 110. When displaying a black screen, the low leakage current of the driving module 110 ensures the display effect and prevents the black from being insufficiently black.

[0054] Optionally, when a black screen is displayed, the second transistor M2 included in the voltage control module 120 can also be in the cutoff region, which can also increase the voltage of the second terminal N2 of the drive module 110. The principle is similar to that of the second transistor M2 being in the subthreshold region, and will not be described in detail here.

[0055] Optionally, when the displayed grayscale is greater than or equal to the preset grayscale, the transistors included in the voltage control module 120 are in the linear region or saturation region, the absolute value of the difference between the first voltage V1 and the voltage at one end of the driving module 110 is greater than or equal to the absolute value of the threshold voltage of the voltage control module 120, and one end of the driving module 110 is the end connected to the voltage control module 120.

[0056] For example, when the displayed grayscale is greater than or equal to the preset grayscale, the driving current generated by the driving module 110 is large, and the voltage of the second terminal N2 of the driving module 110 is large, so that the absolute value of the gate-source voltage of the second transistor M2 included in the voltage control module 120 is much greater than the absolute value of the threshold voltage Vth2 of the second transistor M2. The second transistor M2 is in a fully conducting state and will not affect the normal display process.

[0057] Optionally, in this embodiment, the first voltage V1 can be a DC voltage. By reasonably configuring the voltage value of the first voltage V1, the second transistor M2 can be placed in the subthreshold region during low grayscale display, thereby increasing the voltage of the second terminal N2 of the driving module 110. Furthermore, it can be placed in the linear region or saturation region during medium-to-high grayscale display, without affecting the normal display of medium-to-high grayscale levels.

[0058] Figure 3 is a schematic diagram of another pixel circuit provided in an embodiment of this application. Referring to Figure 3, based on the above embodiment, the pixel circuit optionally further includes a first light-emitting control module 161 and a second light-emitting control module 160. The control terminal of the first light-emitting control module 161 is connected to a first light-emitting control signal line, and the control terminal of the second light-emitting control module 160 is connected to a second light-emitting control signal line. The first end of the first light-emitting control module 161 is connected to a first power supply line L1, and the second end of the first light-emitting control module 161 is connected to the first end N1 of the driving module 110. The second end N2 of the driving module 110 is connected to the first end of the voltage control module 120, and the second end of the voltage control module 120 is connected to the first end of the second light-emitting control module 160. The second end of the second light-emitting control module 160 is connected to the first end of the light-emitting module 130. The first light-emitting control signal line is used to transmit a first light-emitting control signal EM1, and the second light-emitting control signal line is used to transmit a second light-emitting control signal EM2. The first light-emitting control module 161 and the second light-emitting control module 160 are used to conduct during the light-emitting phase to control the light-emitting module 130 to emit light.

[0059] Figure 4 is a schematic diagram of another pixel circuit provided in an embodiment of this application. Referring to Figure 4, the voltage control module 120 can also be connected between the second light-emitting control module 160 and the light-emitting module 130. For example, the first end of the first light-emitting control module 161 is connected to the first power line L1, the second end of the first light-emitting control module 161 is connected to the first end N1 of the driving module 110, the second end N2 of the driving module 110 is connected to the first end of the second light-emitting control module 160, the second end of the second light-emitting control module 160 is connected to the first end of the voltage control module 120, and the second end of the voltage control module 120 is connected to the first end of the light-emitting module 130.

[0060] The pixel circuits shown in Figure 3 and Figure 4 operate on the same principle: when displaying low grayscale, the voltage at the second terminal N2 of the driving module 110 is increased by adjusting the first voltage V1, thereby reducing leakage current in the driving module 110. In the pixel circuits shown in Figures 3 and 4, the first transistor M1 included in the driving module 110 is either a P-type or an N-type transistor, and the second transistor M2 included in the voltage control module 120 is a P-type transistor. When the first transistor M1 is a P-type transistor, the first terminal N1 of the driving module 110 is the source of the first transistor M1, and the second terminal N2 of the driving module 110 is the drain of the first transistor M1. When the first transistor M1 is an N-type transistor, the first terminal N1 of the driving module 110 is the drain of the first transistor M1, and the second terminal N2 of the driving module 110 is the source of the first transistor M1.

[0061] Figure 5 is a schematic diagram of another pixel circuit provided in an embodiment of this application, and Figure 6 is a schematic diagram of another pixel circuit provided in an embodiment of this application. Referring to Figures 5 and 6, the second transistor M2 included in the voltage control module 120 can also be an N-type transistor. When the second transistor M2 is an N-type transistor, the voltage control module 120 is connected between the first power line L1 and the first terminal N1 of the driving module 110. For example, as shown in Figure 5, the first terminal of the first light-emitting control module 161 is connected to the first power line L1, the second terminal of the first light-emitting control module 161 is connected to the first terminal of the voltage control module 120, the second terminal of the voltage control module 120 is connected to the first terminal N1 of the driving module 110, the second terminal N2 of the driving module 110 is connected to the first terminal of the second light-emitting control module 160, and the second terminal of the second light-emitting control module 160 is connected to the first terminal of the light-emitting module 130. For example, as shown in Figure 6, the first end of the voltage control module 120 is connected to the first power line L1, the second end of the voltage control module 120 is connected to the first end of the first light-emitting control module 161, the second end of the first light-emitting control module 161 is connected to the first end N1 of the drive module 110, the second end of the drive module 110 is connected to the first end of the second light-emitting control module 160, and the second end of the second light-emitting control module 160 is connected to the first end of the light-emitting module 130.

[0062] When the second transistor M2 is an N-type transistor, the first transistor M1 is also an N-type transistor. In this case, the first terminal N1 of the driving module 110 is the drain of the first transistor M1, and the second terminal N2 of the driving module 110 is the source of the first transistor M1.

[0063] In this embodiment, when the second transistor M2 is connected between the first power line L1 and the first terminal N1 of the driving module 110, since the second transistor M2 is an N-type transistor, the first voltage V1 is positive. Furthermore, at low grayscale, the difference between the first voltage V1 and the voltage at the first terminal N1 of the driving module 110 is less than the threshold voltage Vth2 of the second transistor M2, ensuring that the second transistor M2 is in the subthreshold region. By adjusting the first voltage V1, the voltage change at the second terminal (source) of the second transistor M2 can be less than V1 + Vth2, preventing the voltage at the second terminal of the second transistor M2 from rising to the first power supply voltage VDD. That is, the voltage at the first terminal N1 of the driving module 110 is less than the first power supply voltage VDD, which helps reduce the voltage difference between the first terminal N1 and the second terminal N2 of the driving module 110, thereby reducing leakage current in the driving module 110 and achieving low grayscale display. This also avoids the phenomenon of insufficient black levels.

[0064] Figure 7 is a schematic diagram of another pixel circuit provided in an embodiment of this application, and Figure 8 is a schematic diagram of another pixel circuit provided in an embodiment of this application. These correspond to the overall structure of the pixel circuit when the first transistor M1 is a P-type transistor. Referring to Figures 7 and 8, the pixel circuit provided in this embodiment further includes a first initialization module 170. The control terminal of the first initialization module 170 is connected to a first scan signal line, the first terminal of the first initialization module 170 is connected to a second voltage signal line, and the second terminal of the first initialization module 170 is connected to the first terminal of the light-emitting module 130. The first scan signal line is used to transmit a first scan signal S1, and the first initialization module 170 is used to transmit the second initialization voltage Vref2 transmitted on the second voltage signal line to the first terminal of the light-emitting module 130 in response to the first scan signal S1, thereby initializing the light-emitting module 130.

[0065] The pixel circuit also includes a data writing module 140. The control terminal of the data writing module 140 is connected to the second scan signal line. The data writing module 140 is connected to the driving module 110 and is used to write the data voltage Vdata to the control terminal G of the driving module 110. The pixel circuit also includes a compensation module 180. The control terminal of the compensation module 180 is connected to the second scan signal line and is connected between the second terminal N2 of the driving module 110 and the control terminal G. The compensation module 180 is used to compensate the threshold voltage of the driving module 110. The data writing module 140 is connected to the first terminal N1 of the driving module 110, and the second scan signal line is used to transmit the second scan signal S2.

[0066] The pixel circuit also includes a storage module 150, which is connected to the control terminal G of the drive module 110.

[0067] The pixel circuit also includes a second initialization module 190. The control terminal of the second initialization module 190 is connected to the third scan signal line, the first terminal of the second initialization module 190 is connected to the third voltage signal line, and the second terminal of the second initialization module 190 is connected to the control terminal G of the drive module 110. The third scan signal line is used to transmit the third scan signal S3, and the second initialization module 190 is used to transmit the first initialization voltage Vref1 on the third voltage signal line to the control terminal G of the drive module 110 in response to the third scan signal S3.

[0068] For example, the first light-emitting control module 161 includes a third transistor M3, and the second light-emitting control module 160 includes a fourth transistor M4. The gate of the third transistor M3 is connected to a first light-emitting control signal line, and the first terminal of the third transistor M3 is connected to a first power supply line L1. The first terminal of the first transistor M1 serves as the first terminal N1 of the driving module 110 and is connected to the second terminal of the third transistor M3. The second terminal of the first transistor M1 serves as the second terminal N2 of the driving module 110 and is connected to the first terminal of the second transistor M2 (as shown in Figure 7). The second terminal of the second transistor M2 is connected to the first terminal of the fourth transistor M4. The second terminal of the fourth transistor M4 is connected to the first terminal of the light-emitting diode D1. The second terminal of the light-emitting diode D1 is connected to a second power supply line L2. The gate of the second transistor M2 is connected to a first voltage signal line, and the gate of the fourth transistor M4 is connected to a second light-emitting control signal line. Alternatively, the second terminal of the first transistor M1 serves as the second terminal N2 of the driving module 110 and is connected to the first terminal of the fourth transistor M4 (as shown in Figure 8). The second terminal of the fourth transistor M4 is connected to the first terminal of the second transistor M2, and the second terminal of the second transistor M2 is connected to the first terminal of the light-emitting diode D1.

[0069] The first initialization module 170 includes a fifth transistor M5. The gate of the fifth transistor M5 is connected to the first scan signal line, the first terminal of the fifth transistor M5 is connected to the second voltage signal line, and the second terminal of the fifth transistor M5 is connected to the first terminal of the light-emitting diode D1. The data writing module 140 includes a sixth transistor M6, the compensation module 180 includes a seventh transistor M7, and the storage module 150 includes a storage capacitor C1. The gates of both the sixth transistor M6 and the seventh transistor M7 are connected to the second scan signal line. The first terminal of the sixth transistor M6 is connected to the data line, and the second terminal of the sixth transistor M6 is connected to the first terminal N1 of the driving module 110. The first terminal of the seventh transistor M7 is connected to the second terminal N2 of the driving module 110, and the second terminal of the seventh transistor M7 is connected to the control terminal G of the driving module 110. The storage capacitor C1 is connected between the first power supply line L1 and the control terminal G of the driving module 110. The second initialization module 190 includes an eighth transistor M8. The gate of the eighth transistor M8 is connected to the third scan signal line, the first terminal of the eighth transistor M8 is connected to the third voltage signal line, and the second terminal of the eighth transistor M8 is connected to the control terminal G of the driving module 110.

[0070] Optionally, in this embodiment, as shown in FIG8, the first light emission control signal line can be multiplexed as the second light emission control signal line, and the first light emission control signal EM1 can be multiplexed as the second light emission control signal EM2. The second scan signal line or the third scan signal line can be multiplexed as the first scan signal line, and the second scan signal S2 or the third scan signal S3 can be multiplexed as the first scan signal S1.

[0071] Figure 9 is a schematic diagram of the driving timing of a pixel circuit provided in an embodiment of this application. It can be applied to the pixel circuit shown in Figures 7-8. For example, referring to Figure 8, taking the third scan signal S3 multiplexed as the first scan signal S1 and the first light emission control signal EM1 multiplexed as the second light emission control signal EM2 as an example, the working process of the pixel circuit provided in this embodiment includes an initialization stage T1, a data writing stage T2 and a light emission stage T3.

[0072] During the initialization phase T1, the second scan signal S2 is at a high level, the third scan signal S3 is at a low level, the first light emission control signal EM1 is at a high level, the fifth transistor M5 and the eighth transistor M8 are turned on, the second initialization voltage Vref2 is transmitted to the first terminal of the light emission diode D1 through the fifth transistor M5 to initialize the first terminal of the light emission diode D1; the first initialization voltage Vref1 is transmitted to the gate of the first transistor M1 through the eighth transistor M8 to initialize the gate of the first transistor M1 and turn on the first transistor M1.

[0073] During the data writing phase T2, the second scan signal S2 is low, the third scan signal S3 is high, the first light emission control signal EM1 is high, and the sixth transistor M6 and the seventh transistor M7 are turned on. The data voltage Vdata is transmitted to the gate of the first transistor M1 via the sixth transistor M6, the first transistor M1, and the seventh transistor M7 until the gate voltage of the first transistor M1 reaches Vdata + Vth1, at which point the first transistor M1 is turned off. Here, Vth1 is the threshold voltage of the first transistor. Simultaneously with writing the data voltage Vdata to the gate of the first transistor M1, the threshold voltage Vth1 of the first transistor M1 is compensated.

[0074] During the light-emitting stage T3, the second scan signal S2 is at a low level, the third scan signal S3 is at a low level, the first light-emitting control signal EM1 is at a low level, the third transistor M3 and the fourth transistor M4 are turned on, and the first transistor M1 generates a driving current to drive the light-emitting diode D1 to emit light.

[0075] When the displayed grayscale is lower than the preset grayscale, the driving current generated by the first transistor M1 is relatively small, and the voltage (anode voltage) at the first terminal of the light-emitting diode D1 is low. Under the action of the first voltage V1, the second transistor M2 is in the subthreshold region. Therefore, the voltage at the first terminal of the second transistor M2 is greater than V1-Vth2. Since the absolute value of the first voltage V1 is greater than the anode voltage at this time, the voltage at the second terminal N2 of the driving module 110 can be increased by configuring the first voltage V1 so that the absolute value of V1-Vth2 is still greater than the anode voltage, thereby reducing the leakage current of the first transistor M1. When displaying a black screen, this avoids the phenomenon that the black state is not dark enough.

[0076] When the displayed grayscale is higher than the preset grayscale, the driving current generated by the first transistor M1 is larger, which makes the voltage of the second terminal N2 of the driving module 110 larger. The second transistor M2 is in the linear region or saturation region and will not affect the light emission of the light-emitting diode D1.

[0077] Figure 10 is a schematic diagram of another pixel circuit provided in an embodiment of this application, and Figure 11 is a schematic diagram of another pixel circuit provided in an embodiment of this application. The difference between the structures shown in Figures 10 and 11 is that the connection relationship and channel type of the second transistor M2 are different. In the pixel circuit shown in Figure 10, the second transistor M2 is a P-type transistor, connected between the second terminal N2 of the driving module 110 and the first terminal of the light-emitting module 130; in the pixel circuit shown in Figure 11, the second transistor M2 is an N-type transistor, connected between the first power line L1 and the first terminal N1 of the driving module 110. Referring to Figures 10 and 11, the overall structure of the pixel circuit when the first transistor M1 is an N-type transistor can be seen. The compensation module 180 is connected between the first terminal N1 of the driving module 110 and the control terminal G. The control terminal of the compensation module 180 is connected to the first scan signal line. The data writing module 140 is connected between the data line and the second terminal N2 of the driving module 110. The control terminal of the data writing module 140 is connected to the second scan signal line. The storage module 150 is connected between the control terminal G of the driving module 110 and the first terminal of the light-emitting module 130. Here, there is no need to set up a third initialization module 190; the initialization of the control terminal G of the drive module 110 can be achieved through the first power supply voltage VDD. Specifically, the gate of the sixth transistor M6 is connected to the second scan signal line, the gate of the seventh transistor M7 is connected to the first scan signal line, the first electrode of the sixth transistor M6 is connected to the data line, the second electrode of the sixth transistor M6 is connected to the second terminal N2 of the drive module 110, the first electrode of the seventh transistor M7 is connected to the first terminal N1 of the drive module 110, and the second electrode of the seventh transistor M7 is connected to the control terminal G of the drive module 110. The storage capacitor C1 is connected between the first terminal of the light-emitting module 130 and the control terminal G of the drive module 110.

[0078] Figure 12 is a schematic diagram of the driving timing of another pixel circuit provided in an embodiment of this application, which can be applied to the pixel circuits shown in Figures 10 and 11. Referring to Figures 10-12, in the initialization stage T1, the second scan signal S2 is high, the first scan signal S1 is low, the first light emission control signal EM1 is low, the second light emission control signal EM2 is high, the third transistor M3, the fifth transistor M5, and the seventh transistor M7 are turned on, and the second initialization voltage Vref2 is transmitted to the first terminal of the light-emitting diode D1 through the fifth transistor M5 to initialize the first terminal of the light-emitting diode D1; the first power supply voltage VDD is transmitted to the gate of the first transistor M1 through the third transistor M3 and the seventh transistor M7 to initialize the gate of the first transistor M1 and turn on the first transistor M1. When the first light emission control signal EM1 changes from low to high, the third transistor M3 is turned off. The data writing stage T2 and the light emission stage T3 are similar to those described in the above embodiments and will not be repeated. In this embodiment, when the first transistor M1 is an N-type transistor, the second transistor M2 can be selected as an N-type transistor, which is beneficial for the pixel circuit to work stably under full grayscale.

[0079] Figure 13 is a schematic diagram of grayscale expansion provided in an embodiment of this application, which corresponds to the pixel circuit shown in Figure 8. As can be seen from Figure 13, under low grayscale (i.e., the displayed grayscale is less than the preset grayscale), the expansion can be good (e.g., 32 grayscale, 16 grayscale, 8 grayscale, 4 grayscale, 2 grayscale, 1 grayscale, etc.). Under medium-high grayscale (i.e., the displayed grayscale is greater than or equal to the preset grayscale), the displayed grayscale can also be expanded well (e.g., 255 grayscale, 128 grayscale, 64 grayscale, etc.).

[0080] Figure 14 is a schematic diagram of another pixel circuit provided in an embodiment of this application. Referring to Figure 14, based on the pixel circuit shown in Figure 1, the first control terminal of the voltage control module 120 is connected to the second light emission control signal line, and the second control terminal of the voltage control module 120 is connected to the control terminal G of the driving module 110. The threshold voltage of the voltage control module 120 is adjusted by the voltage of the second control terminal, thereby adjusting the conduction state of the voltage control module 120. For example, when the displayed grayscale is less than the preset grayscale, the voltage control module 120 is adjusted to be in a semi-conducting state, thereby raising the voltage of the second terminal N2 of the driving module 110 to reduce the voltage difference between the first terminal N1 and the second terminal N2 of the driving module 110. This helps to reduce the leakage current of the driving module 110 and avoids the phenomenon of insufficient black when displaying a black screen.

[0081] Referring again to Figure 14, the pixel circuit also includes a first light-emitting control module 161. The control terminal of the first light-emitting control module 161 is connected to the first light-emitting control signal line. The first end of the first light-emitting control module 161 is connected to the first power supply line L1. The second end of the first light-emitting control module 161 is connected to the first end N1 of the driving module 110. The second end N2 of the driving module 110 is connected to the first end of the voltage control module 120. The second end of the voltage control module 120 is connected to the first end of the light-emitting module 130.

[0082] The first light-emitting control signal line is used to transmit the first light-emitting control signal EM1, and the second light-emitting control signal line is used to transmit the second light-emitting control signal EM2. The first light-emitting control signal line can be multiplexed as the second light-emitting control signal line.

[0083] Figure 15 is a schematic diagram of another pixel circuit provided in an embodiment of this application. Referring to Figure 15, based on the above embodiment, optionally, the driving module 110 includes a first transistor M1, the voltage control module 120 includes a second transistor M2, the first light-emitting control module 161 includes a third transistor M3, the light-emitting module 130 includes a light-emitting diode D1, the gate of the third transistor M3 is connected to the first light-emitting control signal line, the first terminal of the third transistor M3 is connected to the first power supply line L1, the first terminal of the first transistor M1 is connected to the second terminal of the third transistor M3 as the first terminal N1 of the driving module 110, the second terminal of the first transistor M1 is connected to the first terminal of the second transistor M2 as the second terminal N2 of the driving module 110, the second terminal of the second transistor M2 is connected to the first terminal of the light-emitting diode D1, the second terminal of the light-emitting diode D1 is connected to the second power supply line L2, the first gate of the second transistor M2 is connected to the second light-emitting control signal line, and the second gate of the second transistor M2 is connected to the gate of the first transistor M1.

[0084] For example, taking both the first transistor M1 and the second transistor M2 as P-type transistors, the first gate of the second transistor M2 is the top gate, and the second gate of the second transistor M2 is the bottom gate. During the data writing stage, the data voltage Vdata is written to the gate of the first transistor M1 via the data writing module 140. During the display stage, when the displayed grayscale is less than a preset grayscale, for example, when displaying a black screen, the gate voltage of the first transistor M1 is positive. Under the influence of the gate voltage of the first transistor M1, the threshold voltage Vth2 of the second transistor M2 is negatively biased. With the second light-emitting control signal EM2 connected to the first gate of the second transistor M2 fixed, the conduction level of the second transistor M2 can be reduced, and the second transistor M2 operates in the subthreshold region. Therefore, the voltage at the first terminal of the second transistor M2 is limited to a relatively stable range and will not drop to the voltage at the first terminal of the light-emitting diode D1, thereby increasing the voltage at the second terminal N2 of the driving module 110, reducing the voltage difference between the first terminal N1 and the second terminal N2 of the driving module 110, and reducing the leakage current of the driving module 110.

[0085] Optionally, in this embodiment, the second transistor M2 is a vertical dual-gate transistor, and the channel type of the first transistor M1 is the same as that of the second transistor M2.

[0086] In other embodiments, both the first transistor M1 and the second transistor M2 can be N-type transistors. Figure 16 is a schematic diagram of another pixel circuit provided in an embodiment of this application. Referring to Figure 16, the control terminal of the first light-emitting control module 161 is connected to the first light-emitting control signal line, the first terminal of the voltage control module 120 is connected to the first power supply line L1, the second terminal of the voltage control module 120 is connected to the first terminal N1 of the driving module 110, the second terminal of the driving module 110 is connected to the first terminal of the first light-emitting control module 161, and the second terminal of the first light-emitting control module 161 is connected to the first terminal of the light-emitting module 130. The first control terminal of the voltage control module 120 is connected to the second light-emitting control signal line, and the second control terminal of the voltage control module 120 is connected to the control terminal G of the driving module 110.

[0087] For example, the driving module 110 includes a first transistor M1, the voltage control module 120 includes a second transistor M2, the first light-emitting control module 161 includes a third transistor M3, and the light-emitting module 130 includes a light-emitting diode D1. The first gate of the second transistor M2 is connected to a second light-emitting control signal line, the second gate of the second transistor M2 is connected to the gate of the first transistor M1, the first electrode of the second transistor M2 is connected to a first power supply line L1, the first electrode of the first transistor M1 serves as the first terminal N1 of the driving module 110 and is connected to the second electrode of the second transistor M2, the second electrode of the first transistor M1 serves as the second terminal N2 of the driving module 110 and is connected to the first electrode of the third transistor M3, the second electrode of the third transistor M3 is connected to the first electrode of the light-emitting diode D1, and the second electrode of the light-emitting diode D1 is connected to the second power supply line L2. The first light-emitting control signal line can be multiplexed as the second light-emitting control signal line. The specific working principle of this circuit is similar to that of the first transistor M1 being a P-type transistor, and will not be described in detail here.

[0088] Figure 17 is a schematic diagram of another pixel circuit provided in an embodiment of this application. Referring to Figure 17, the connection relationship of the data writing module 140, storage module 150, compensation module 180, first initialization module 170 and second initialization module 190 is the same as that shown in Figure 7. The pixel circuit shown in Figure 17 is also applicable to the driving timing shown in Figure 9. The specific working process of the initialization stage and the data writing stage will not be described in detail.

[0089] During the light-emitting stage, when the displayed grayscale is lower than the preset grayscale, the gate voltage of the first transistor M1 is relatively large, which is a positive voltage, causing the threshold voltage of the second transistor M2 to be negatively biased. Combined with the first light-emitting control signal EM1, this keeps the second transistor M2 in the subthreshold region. Therefore, the voltage at the first terminal of the second transistor M2 is greater than V2-Vth2, where the second voltage V2 is the effective level of the first light-emitting control signal EM1. The absolute value of the second voltage V2 is greater than the anode voltage at this time. By configuring the second voltage V2, the absolute value of V2-Vth2 can still be greater than the anode voltage, thereby increasing the voltage at the second terminal N2 of the driving module 110, and thus reducing the leakage current of the first transistor M1. When displaying a black screen, this avoids the phenomenon of insufficient blackness.

[0090] When the displayed grayscale is higher than the preset grayscale, the gate voltage of the first transistor M1 is smaller and is a negative voltage, which makes the threshold voltage of the second transistor M2 positively biased. The second transistor M2 is in the linear region or saturation region and will not affect the light emission of the light-emitting diode D1.

[0091] In other embodiments, when the first transistor M1 and the second transistor M2 are N-type transistors (the first light emission control signal EM1 and the second light emission control signal EM2 are independent of each other), the connection relationship of the data writing module 140, the storage module 150, the compensation module 180, and the first initialization module 170 is the same as the architecture shown in FIG11. The operation process of this pixel circuit is similar to the operation process when the second transistor M2 is a P-type transistor, except that the conduction level and the data voltage Vdata are opposite.

[0092] In the pixel circuit shown in Figure 17, the level of the first light emission control signal EM1 is different from the levels of the first scan signal S1, the second scan signal S2, and the third scan signal S3. By cooperating with the independent level of the first light emission control signal EM1 and the bottom gate of the second transistor M2, the switching state of the second transistor M2 in low grayscale and medium-high grayscale can be optimized.

[0093] Figure 18 is a schematic diagram of another pixel circuit provided in an embodiment of this application. Referring to Figure 18, based on the embodiment described in Figure 1, optionally, the voltage control module 120 includes a first sub-control module 121 and a second sub-control module 122. The control terminal of the first sub-control module 121 is connected to a first light emission control signal line, and the control terminal of the second sub-control module 122 is connected to a second light emission control signal line. The first end of the first sub-control module 121 is connected to a first power supply line L1, and the second end of the first sub-control module 121 is connected to the first end N1 of the driving module 110. The second end N2 of the driving module 110 is connected to the first end of the second sub-control module 122, and the second end of the second sub-control module 122 is connected to the first end of the light emission module 130.

[0094] When the displayed grayscale is less than the preset grayscale, the transistors included in the first sub-control module 121 and / or the second sub-control module 122 are in the subthreshold region to raise the voltage of the second terminal N2 of the driving module 110, thereby reducing the voltage difference between the first terminal N1 and the second terminal N2 of the driving module 110, reducing the leakage current of the driving module 110, ensuring good display effect at low grayscale, and avoiding the phenomenon that the black state is not black enough.

[0095] Figure 19 is a schematic diagram of another pixel circuit provided in an embodiment of this application. Referring to Figure 19, based on the above embodiment, optionally, the driving module 110 includes a first transistor M1, the first sub-control module 121 includes a ninth transistor M9, the second sub-control module 122 includes a tenth transistor M10, the light-emitting module 130 includes a light-emitting diode D1, the gate of the ninth transistor M9 is connected to a first light-emitting control signal line, the first terminal of the ninth transistor M9 is connected to a first power supply line L1, the second terminal of the ninth transistor M9 is connected to the first terminal of the first transistor M1, the second terminal of the first transistor M1 is connected to the first terminal of the tenth transistor M10, the second terminal of the tenth transistor M10 is connected to the first terminal of the light-emitting diode D1, the second terminal of the light-emitting diode D1 is connected to a second power supply line L2, and the gate of the tenth transistor M10 is connected to a second light-emitting control signal line.

[0096] The pixel circuit also includes a first initialization module 170. The control terminal of the first initialization module 170 is connected to a first scan signal line, the first terminal of the first initialization module 170 is connected to a second voltage signal line, and the second terminal of the first initialization module 170 is connected to the first terminal of the light-emitting module 130. The first initialization module 170 includes a fifth transistor M5. The gate of the fifth transistor M5 is connected to the first scan signal line, the first electrode of the fifth transistor M5 is connected to the second voltage signal line, and the second electrode of the fifth transistor M5 is connected to the first electrode of the light-emitting diode D1.

[0097] The absolute value of the effective level of the first light emission control signal EM1 transmitted on the first light emission control signal line is less than the absolute value of the effective level of the first scan signal S1 transmitted on the first scan signal line; and / or, the absolute value of the effective level of the second light emission control signal EM2 transmitted on the second light emission control signal line is less than the absolute value of the effective level of the first scan signal S1 transmitted on the first scan signal line.

[0098] For example, the ninth transistor M9 and the tenth transistor M10 have the same channel type, such as both being P-type transistors. The fifth transistor M5 is also a P-type transistor. The fifth transistor M5, the ninth transistor M9, and the tenth transistor M10 are all turned on at low level and turned off at high level. In this embodiment, the absolute value of the effective level (low level) of the first light emission control signal EM1 is less than the absolute value of the effective level (low level) of the first scan signal S1; or, the absolute value of the effective level (low level) of the second light emission control signal EM2 is less than the absolute value of the effective level (low level) of the first scan signal S1; or, the absolute value of the effective level (low level) of the first light emission control signal EM1 is less than the absolute value of the effective level (low level) of the first scan signal S1, and the absolute value of the effective level (low level) of the second light emission control signal EM2 is less than the absolute value of the effective level (low level) of the first scan signal S1. Therefore, at low grayscale, the conduction level of the ninth transistor M9 and / or the tenth transistor M10 can be lower than that of the fifth transistor M5. That is, the ninth transistor M9 and / or the tenth transistor M10 are in the subthreshold region, which can also raise the voltage of the second terminal N2 of the driving module 110 or lower the voltage of the first terminal N1 of the driving module 110, thereby reducing the voltage difference between the first terminal N1 and the second terminal N2 of the driving module 110, which is beneficial to reducing the leakage current of the driving module 110.

[0099] The pixel circuit also includes a data writing module 140, whose control terminal is connected to the second scan signal line and is connected to the driving module 110. The data writing module 140 is used to write the data voltage Vdata to the control terminal G of the driving module 110. The pixel circuit also includes a compensation module 180, whose control terminal is connected to the second scan signal line and is connected between the second terminal N2 and the control terminal G of the driving module 110. The compensation module 180 is used to compensate the threshold voltage of the driving module 110.

[0100] The absolute value of the effective level of the second scanning signal S2 is the same as the absolute value of the effective level of the second light-emitting control signal EM2 transmitted on the second light-emitting control signal line, or the absolute value of the effective level of the second scanning signal S2 is the same as the absolute value of the effective level of the first light-emitting control signal EM1 transmitted on the first light-emitting control signal line.

[0101] For example, setting the absolute value of the effective level of the second scan signal S2 to be the same as the absolute value of the effective level of the first light emission control signal EM1 or the second light emission control signal EM2 can avoid the phenomenon of excessive coupling of the seventh transistor M7 included in the compensation module 180 due to the jump of the second scan signal S2 caused by the effective level of the second scan signal S2 being too low. This is beneficial to improving the stability of the voltage at the control terminal G of the drive module 110 and improving the uniformity of the display.

[0102] The pixel circuit also includes a storage module 150, which is connected to the control terminal G of the driving module 110; the data writing module 140 includes a sixth transistor M6, the compensation module 180 includes a seventh transistor M7, the storage module 150 includes a storage capacitor C1, the gates of the sixth transistor M6 and the seventh transistor M7 are both connected to the second scan signal line, the first terminal of the sixth transistor M6 is connected to the data line, the second terminal of the sixth transistor M6 is connected to the first terminal N1 of the driving module 110, the first terminal of the seventh transistor M7 is connected to the second terminal N2 of the driving module 110, the second terminal of the seventh transistor M7 is connected to the control terminal G of the driving module 110, and the storage capacitor C1 is connected between the first power line L1 and the control terminal G of the driving module 110.

[0103] The pixel circuit also includes a second initialization module 190. The control terminal of the second initialization module 190 is connected to the third scan signal line, the first terminal of the second initialization module 190 is connected to the third voltage signal line, and the second terminal of the second initialization module 190 is connected to the control terminal G of the drive module 110. The second initialization module 190 includes an eighth transistor M8. The gate of the eighth transistor M8 is connected to the third scan signal line, the first terminal of the eighth transistor M8 is connected to the third voltage signal line, and the second terminal of the eighth transistor M8 is connected to the control terminal G of the drive module 110. The first scan signal S1 can be multiplexed into a third scan signal S3.

[0104] Figure 20 is a schematic diagram of the driving timing of another pixel circuit provided in an embodiment of this application, which can be applied to the pixel circuit shown in Figure 19. Referring to Figure 20, the working process of the pixel circuit includes an initialization stage T1, a data writing stage T2, and a light emission stage T3. The working process of the initialization stage T1 and the data writing stage T2 is the same as the working process described in the above embodiment, and will not be repeated here.

[0105] In this embodiment, during the light-emitting stage T3, the first scan signal S1, the second scan signal S2, and the third scan signal S3 are at high levels, while the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are at low levels. The ninth transistor M9 and the tenth transistor M10 are turned on. When the displayed grayscale is less than a preset grayscale, the driving current generated by the first transistor M1 is relatively small. By adjusting the effective level of the second light-emitting control signal EM2 to VGL (VGL is greater than the effective level of the third scan signal S3, VGLL), the tenth transistor M10 can be configured to operate in the subthreshold region, thereby increasing the voltage at the second terminal N2 of the driving module 110 to reduce the leakage current of the driving module 110.

[0106] In other embodiments, the effective level of the first light emission control signal EM1 can be adjusted, or the effective levels of the first light emission control signal EM1 and the second light emission control signal EM2 can be adjusted simultaneously, achieving the same effect as in the above embodiments, which will not be described again here.

[0107] Optionally, the first transistor M1 can also be an N-type transistor, in which case the connection relationship of the data writing module 140, storage module 150, compensation module 180, and first initialization module 170 is the same as the architecture shown in Figure 11.

[0108] Optionally, in the pixel circuit shown in Figure 19, the first light emission control signal EM1 can be multiplexed as the second light emission control signal EM2, and the third scan signal S3 can be multiplexed as the first scan signal S1. That is, the first light emission control signal line is multiplexed as the second light emission control signal line, and the third scan signal line is multiplexed as the first scan signal line, which helps to save the number of signal lines and thus improve the resolution (Pixels Per Inch, PPI).

[0109] Optionally, the effective level of the second scan signal S2 can be the same as the effective level of the third scan signal S3, both being VGLL. Alternatively, the effective level of the second scan signal S2 can also be the same as the effective level of the first light emission control signal EM1, both being VGL.

[0110] Optionally, the technical solutions provided in this application can be applied not only to the pixel circuit based on the 7T1C architecture of low temperature poly-silicon (LTPS) in the above embodiments, but also to the pixel circuit based on 8T1C (adding a transistor that applies a bias voltage to the source of the driving transistor on the basis of 7T1C) or the 7T1C architecture of low temperature polycrystalline oxide (LTPO), with the same effect.

[0111] Optionally, this application provides a pixel circuit driving method. Referring to Figures 1 and 25, the pixel circuit driving method provided in this embodiment includes:

[0112] S1. During the light-emitting stage, the control drive module drives the light-emitting module to emit light;

[0113] S2. When the displayed gray level is less than the preset gray level, the control voltage control module controls the voltage at the end where the drive module is connected to the voltage control module.

[0114] The technical solution provided in this application adds a voltage control module to the connection path between the driving module and the light-emitting module to cut off the direct connection between the driving module and the light-emitting module. When the displayed grayscale is less than a preset grayscale, the voltage control module controls the voltage at the end connected to the driving module and the voltage control module, thereby increasing the voltage at the end connected to the driving module and the voltage control module, thereby reducing the voltage difference between the first and second ends of the driving module, and thus reducing the leakage current of the driving module at low grayscale, thereby improving the display brightness at low grayscale and improving the display effect.

[0115] Optionally, referring to Figure 2, the voltage control module 120 includes transistors, such as a second transistor M2. The specific steps for controlling the voltage control module 120 to turn off include:

[0116] The transistor in the control voltage control module responds to the signal at the control terminal of the control voltage control module in the subthreshold region.

[0117] Optionally, the pixel circuit driving method provided in this embodiment further includes:

[0118] During the non-light-emitting phase, the transistors in the control voltage control module are in the cutoff region in response to the signal at the control terminal of the control voltage control module.

[0119] For example, referring to Figure 2, the control terminal of the voltage control module 120 is connected to a first voltage signal line, which is used to transmit a first voltage V1. When the displayed grayscale is less than a preset grayscale, the first voltage V1 is greater than the voltage at the first terminal of the light-emitting module 130. The absolute value of the difference between the first voltage V1 and the voltage at one end of the driving module 110 is less than the absolute value of the threshold voltage of the voltage control module 120. One end of the driving module 110 is the end connected to the voltage control module 120. That is, by setting the first voltage V1, the voltage difference between the first voltage V1 and the voltage at the second terminal N2 of the driving module 110 is less than the threshold voltage Vth2 of the second transistor M2, thereby making the second transistor M2 in the subthreshold region. At low grayscale, the gate voltage of the second transistor M2 is fixed at the first voltage V1. Due to the inherent characteristics of the subthreshold region, the voltage of the first terminal (source) of the second transistor M2 is limited to a relatively stable range. Therefore, the change in the voltage of the first terminal of the second transistor M2 (i.e., the voltage of the second terminal N2 of the driving module 110) is less than V1-Vth2. Even if the voltage of the first terminal of the light-emitting diode D1 is small at low grayscale, it will not significantly lower the voltage of the first terminal of the second transistor M2, thereby increasing the voltage of the second terminal N2 of the driving module 110, and further reducing the voltage difference between the first terminal N1 and the second terminal N2 of the driving module 110, which is beneficial to reducing the leakage current of the driving module 110.

[0120] When the displayed grayscale is greater than or equal to the preset grayscale, the driving current generated by the driving module 110 is large, and the voltage of the second terminal N2 of the driving module 110 is large. This makes the absolute value of the gate-source voltage of the second transistor M2 included in the voltage control module 120 much larger than the absolute value of the threshold voltage Vth2 of the second transistor M2. The second transistor M2 is in a fully conducting state and will not affect the normal display process.

[0121] Optionally, when the displayed gray level is greater than 0 and less than the preset gray level, the transistor in the control voltage control module responds to the signal at the control terminal of the control voltage control module in the subthreshold region.

[0122] When the grayscale level is 0, the transistor in the control voltage control module is in the cutoff region in response to the signal at the control terminal of the control voltage control module.

[0123] Optionally, embodiments of this application also provide a display panel, which includes the pixel circuit provided in any embodiment of this application. Therefore, the display panel also possesses the effects described in any of the above embodiments. Figure 21 is a schematic structural diagram of a display panel provided in an embodiment of this application. Referring to Figures 2 and 21, the display panel provided in this embodiment includes:

[0124] Substrate (not shown in the figure);

[0125] Active layer 60 is located on one side of the substrate;

[0126] A multilayer conductive layer is stacked on the side of the active layer 60 away from the substrate;

[0127] At least one pixel circuit, the pixel circuit including a driving module 110, a voltage control module 120 and a light-emitting module 130, wherein the driving module 110 includes a first transistor M1, the voltage control module 120 includes a second transistor M2, and the light-emitting module 130 includes a light-emitting diode D1.

[0128] The multilayer conductive layer includes a first conductive layer. The gate G1 of the first transistor M1 and the gate of the second transistor M2 are both located in the first conductive layer. The orthogonal projection of the gate of the second transistor M2 on the substrate is located between the orthogonal projection of the gate G1 of the first transistor M1 on the substrate and the orthogonal projection of the first electrode 51 of the light-emitting diode D1 on the substrate.

[0129] In this embodiment, the first terminal 51 of the light-emitting diode D1 is connected to the second terminal of the second transistor M2 through a via 52. Placing the second transistor M2 close to the first terminal 51 of the light-emitting diode D1 helps reduce parasitic capacitance and optimizes the layout.

[0130] Figure 22 is a schematic diagram of another display panel structure provided in an embodiment of this application, and Figure 23 is a schematic diagram of another display panel structure provided in an embodiment of this application. Figure 23 is a cross-sectional structure of the display panel shown in Figure 22 obtained along the cutting line AA'. Referring to Figures 8, 22 and 23, based on the above embodiments, optionally, the active layer 60 includes a first active layer 601, the channel region of the first transistor M1 is located in the first active layer 601, and the orthogonal projection of the gate G1 of the first transistor M1 on the substrate 10 at least partially covers the orthogonal projection of the channel region of the first transistor M1 on the substrate 10.

[0131] The pixel circuit also includes a storage module 150, which includes a storage capacitor C1 connected to the gate G1 of the first transistor M1. Therefore, the gate G1 of the first transistor M1 can serve as one plate of the storage capacitor C1. For example, the storage capacitor C1 includes a first plate 31 and a second plate 32, and the gate G1 of the first transistor M1 is reused as the first plate 31 of the storage capacitor C1. The first plate 31 and the second plate 32 of the storage capacitor C1 are located on different conductive layers.

[0132] Optionally, the pixel circuit further includes a first light-emitting control module 161 and a second light-emitting control module 160. The first light-emitting control module 161 includes a third transistor M3, and the second light-emitting control module 160 includes a fourth transistor M4. The active layer 60 further includes a second active layer 602 and a third active layer 603. The channel region of the third transistor M3 is located in the second active layer 602, and the channel region of the fourth transistor M4 is located in the third active layer 603. The orthogonal projection of the gate of the third transistor M3 onto the substrate 10 at least partially covers the orthogonal projection of the channel region of the third transistor M3 onto the substrate 10, and the orthogonal projection of the gate of the fourth transistor M4 onto the substrate 10 at least partially covers the orthogonal projection of the channel region of the fourth transistor M4 onto the substrate 10.

[0133] Optionally, referring to Figures 21 to 23, the display panel further includes a first voltage signal line 22 located in the first conductive layer. The first voltage signal line 22 overlaps with the third active layer 603 to form a second transistor M2. The orthogonal projection of the first voltage signal line 22 on the substrate 10 at least partially covers the orthogonal projection of the channel region of the second transistor M2 on the substrate 10.

[0134] For example, the display panel provided in this embodiment further includes a first light-emitting control signal line 21, which extends along a first direction X and intersects with the second active layer 602 and the third active layer 603. The first light-emitting control signal line 21 overlaps with the second active layer 602 to form a third transistor M3, and the first light-emitting control signal line 21 overlaps with the third active layer 603 to form a fourth transistor M4. The orthogonal projection of the gate of the second transistor M2 on the substrate 10 is located on the side of the orthogonal projection of the gate of the fourth transistor M4 on the substrate 10 that is away from the orthogonal projection of the gate G1 of the first transistor M1 on the substrate 10.

[0135] Optionally, the orthographic projection of the first light-emitting control signal line 21 on the substrate 10 is located between the orthographic projection of the first voltage signal line 22 on the substrate 10 and the orthographic projection of the gate G1 of the first transistor M1 on the substrate 10. In this embodiment, the first voltage signal line 22 extends along the first direction X, and the second active layer 602 extends along the second direction Y, with the first direction X intersecting the second direction Y. By placing the second transistor M2 between the fourth transistor M4 and the first electrode 51 of the light-emitting diode D1, the first voltage signal line 22 does not need to cross the first active layer 601. That is, the orthographic projection of the first voltage signal line 22 on the substrate 10 does not overlap with the orthographic projection of the second active layer 602 on the substrate 10, thus avoiding any adverse effects on the layout of the third transistor M3 and the fourth transistor M4, which is beneficial for optimizing the layout.

[0136] Optionally, the pixel circuit further includes a first initialization module 170, which includes a fifth transistor M5. The channel region of the fifth transistor M5 is located in the third active layer 603. The display panel also includes a first scan signal line 23, the orthographic projection of the first scan signal line 23 on the substrate 10 at least partially covering the orthographic projection of the channel region of the fifth transistor M5 on the substrate 10. The first scan signal line 23 is located in the first conductive layer and extends along the first direction X. The first scan signal line 23 overlaps with the third active layer 603 to form the fifth transistor M5.

[0137] The display panel also includes a second voltage signal line 71 and a connecting line 72. The multilayer conductive layer also includes a second conductive layer and a third conductive layer. An interlayer insulating layer 13 is disposed between the second conductive layer and the third conductive layer. A capacitor dielectric layer is disposed between the second conductive layer and the first conductive layer. A gate insulating layer is disposed between the first conductive layer and the active layer 60. The second voltage signal line 71 is located on the second conductive layer, and the connecting line 72 is located on the third conductive layer. The second voltage signal line 71 is connected to one end of the connecting line 72 through a via, and the third active layer 603 is connected to the other end of the connecting line 72 through a via, thereby realizing the connection between the second voltage signal line 71 and the fifth transistor M5. The second voltage signal line 71 is used to transmit the second initialization voltage Vref2, and transmits the second initialization voltage Vref2 to the first electrode 51 of the light-emitting diode D1 through the fifth transistor M5.

[0138] Optionally, the second voltage signal line 71 extends along the first direction X, and the connecting line 72 extends along the second direction Y.

[0139] Optionally, the orthogonal projection of the first scan signal line 23 on the substrate 10 is located between the orthogonal projection of the first voltage signal line 22 on the substrate 10 and the orthogonal projection of the second voltage signal line 71 on the substrate 10, and the orthogonal projection of the first scan signal line 23 on the substrate 10 is located on the side of the orthogonal projection of the first voltage signal line 22 on the substrate 10 that is far away from the orthogonal projection of the gate G1 of the first transistor M1 on the substrate 10.

[0140] In this embodiment, the channel region of the first transistor M1 is located in the first active layer 601, the channel region of the second transistor M2 is located in the third active layer 603, the channel region of the third transistor M3 is located in the second active layer 602, the channel region of the fourth transistor M4 is located in the third active layer 603, and the channel region of the fifth transistor M5 is located in the third active layer 603. The first active layer 601, the second active layer 602, and the third active layer 603 are on the same layer and connected. The second active layer 602 and the third active layer 603 both extend along the second direction Y, and the first active layer 601 extends along the first direction X. The second active layer 602 and the third active layer 603 are located on different sides of the first active layer 601 to facilitate layout.

[0141] In Figure 23, along the second direction Y, the active layer 60 shown in the dashed box below the first light emission control signal line 21 is the channel region of the fourth transistor M4, the active layer 60 shown in the dashed box below the first voltage signal line 22 is the channel region of the second transistor M2, and the active layer 60 shown in the dashed box below the first scan signal line 23 is the channel region of the fifth transistor M5.

[0142] Optionally, referring again to FIG22, the display panel provided in this embodiment further includes a data line 41 and a first power line L1, both of which are located on the third conductive layer. The layout of the sixth transistor M6 included in the data writing module 140, the seventh transistor included in the compensation module 180, and the eighth transistor M8 included in the second initialization module 190 can be found in descriptions in related technologies and will not be repeated here.

[0143] Optionally, this application embodiment also provides a display device, which includes the display panel provided in any embodiment of this application. Therefore, the display device also has the effects described in any of the above embodiments. Figure 24 is a structural schematic diagram of a display device provided in an embodiment of this application. In this embodiment, the display device 200 can be a mobile phone or any electronic product with display function, including but not limited to the following categories: display panels in products such as televisions, laptops, desktop monitors, tablets, digital cameras, smart bracelets, smart glasses, in-vehicle displays, medical devices, industrial control equipment, and touch interactive terminals. This application embodiment does not make any special limitations on this.

[0144] It should be understood that the various processes shown above can be used to rearrange, add, or delete steps. For example, the multiple steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this application can be achieved, and this is not limited herein.

Claims

1. A pixel circuit, comprising: The module consists of a driver module, a voltage control module, and a light-emitting module. The driving module and the voltage control module are connected between the first power line and the first end of the light-emitting module, and the second end of the light-emitting module is connected to the second power line. The driving module is configured to drive the light-emitting module to emit light, and the voltage control module is configured to control the voltage at one end of the connection between the driving module and the voltage control module when the displayed grayscale is less than a preset grayscale.

2. The pixel circuit according to claim 1, wherein, When the displayed grayscale is less than the preset grayscale, the transistors included in the voltage control module are in the subthreshold region; The preset grayscale is 32 grayscale levels; or the preset grayscale is 16 grayscale levels.

3. The pixel circuit according to claim 2, wherein, When the displayed grayscale is greater than or equal to the preset grayscale, the transistors included in the voltage control module are in the linear region or the saturation region.

4. The pixel circuit according to claim 1, wherein, The control terminal of the voltage control module is connected to the first voltage signal line, and the first voltage signal line is configured to transmit the first voltage. When the displayed grayscale is less than the preset grayscale, the absolute value of the difference between the first voltage and the voltage at one end of the driving module is less than the absolute value of the threshold voltage of the voltage control module, and one end of the driving module is the end connected to the voltage control module. When the displayed grayscale is greater than or equal to the preset grayscale, the absolute value of the difference between the first voltage and the voltage at one end of the driving module is greater than or equal to the absolute value of the threshold voltage of the voltage control module, and one end of the driving module is the end connected to the voltage control module.

5. The pixel circuit according to claim 4 further includes a first light-emitting control module and a second light-emitting control module, wherein the control terminal of the first light-emitting control module is connected to a first light-emitting control signal line, and the control terminal of the second light-emitting control module is connected to a second light-emitting control signal line. A first terminal of the first light-emitting control module is connected to the first power supply line; a second terminal of the first light-emitting control module is connected to the first terminal of the driving module; a second terminal of the driving module is connected to the first terminal of the voltage control module; a second terminal of the voltage control module is connected to the first terminal of the second light-emitting control module; and a second terminal of the second light-emitting module is connected to the first terminal of the light-emitting module; or... The first end of the first light-emitting control module is connected to the first power line, the second end of the first light-emitting control module is connected to the first end of the driving module, the second end of the driving module is connected to the first end of the second light-emitting control module, the second end of the second light-emitting control module is connected to the first end of the voltage control module, and the second end of the voltage control module is connected to the first end of the light-emitting module. The driving module includes a first transistor, the voltage control module includes a second transistor, the first light-emitting control module includes a third transistor, the second light-emitting control module includes a fourth transistor, the light-emitting module includes a light-emitting diode (LED), the gate of the third transistor is connected to the first light-emitting control signal line, the first terminal of the third transistor is connected to the first power supply line, the first terminal of the first transistor serves as the first terminal of the driving module and is connected to the second terminal of the third transistor, the second terminal of the first transistor serves as the second terminal of the driving module and is connected to the first terminal of the second transistor, the second terminal of the second transistor is connected to the first terminal of the fourth transistor, the second terminal of the fourth transistor is connected to the first terminal of the LED, the second terminal of the LED is connected to the second power supply line, the gate of the second transistor is connected to the first voltage signal line, and the gate of the fourth transistor is connected to the second light-emitting control signal line; or... The gate of the third transistor is connected to the first light-emitting control signal line, the first terminal of the third transistor is connected to the first power supply line, the first terminal of the first transistor is connected to the second terminal of the third transistor as the first terminal of the driving module, the second terminal of the first transistor is connected to the first terminal of the fourth transistor as the second terminal of the driving module, the second terminal of the fourth transistor is connected to the first terminal of the second transistor, the second terminal of the second transistor is connected to the first terminal of the light-emitting diode, and the second terminal of the light-emitting diode is connected to the second power supply line.

6. The pixel circuit according to claim 4 further includes a first light-emitting control module and a second light-emitting control module, wherein the control terminal of the first light-emitting control module is connected to a first light-emitting control signal line, and the control terminal of the second light-emitting control module is connected to a second light-emitting control signal line. A first terminal of the first light-emitting control module is connected to the first power supply line; a second terminal of the first light-emitting control module is connected to the first terminal of the voltage control module; a second terminal of the voltage control module is connected to the first terminal of the drive module; a second terminal of the drive module is connected to the first terminal of the second light-emitting control module; and a second terminal of the second light-emitting module is connected to the first terminal of the light-emitting module; or... The first end of the voltage control module is connected to the first power line, the second end of the voltage control module is connected to the first end of the first light-emitting control module, the second end of the first light-emitting control module is connected to the first end of the driving module, the second end of the driving module is connected to the first end of the second light-emitting control module, and the second end of the second light-emitting module is connected to the first end of the light-emitting module. The driving module includes a first transistor, the voltage control module includes a second transistor, the first light-emitting control module includes a third transistor, the second light-emitting control module includes a fourth transistor, the light-emitting module includes a light-emitting diode (LED), the gate of the third transistor is connected to the first light-emitting control signal line, the first terminal of the third transistor is connected to the first power supply line, the second terminal of the third transistor is connected to the first terminal of the second transistor, the first terminal of the first transistor serves as the first terminal of the driving module and is connected to the second terminal of the second transistor, the second terminal of the first transistor serves as the second terminal of the driving module and is connected to the first terminal of the fourth transistor, the second terminal of the fourth transistor is connected to the first terminal of the LED, the second terminal of the LED is connected to the second power supply line, the gate of the second transistor is connected to the first voltage signal line, and the gate of the fourth transistor is connected to the second light-emitting control signal line; or... The driving module includes a first transistor, the voltage control module includes a second transistor, the first light-emitting control module includes a third transistor, the second light-emitting control module includes a fourth transistor, the light-emitting module includes a light-emitting diode, the gate of the third transistor is connected to the first light-emitting control signal line, the first terminal of the second transistor is connected to the first power supply line, the second terminal of the second transistor is connected to the first terminal of the third transistor, the first terminal of the first transistor serves as the first terminal of the driving module and is connected to the second terminal of the third transistor, the second terminal of the first transistor serves as the second terminal of the driving module and is connected to the first terminal of the fourth transistor, the second terminal of the fourth transistor is connected to the first terminal of the light-emitting diode, and the second terminal of the light-emitting diode is connected to the second power supply line.

7. The pixel circuit according to claim 1 further includes a first light-emitting control module, wherein the control terminal of the first light-emitting control module is connected to a first light-emitting control signal line, the first end of the first light-emitting control module is connected to the first power line, the second end of the first light-emitting control module is connected to the first end of the driving module, the second end of the driving module is connected to the first end of the voltage control module, and the second end of the voltage control module is connected to the first end of the light-emitting module. The driving module includes a first transistor, the voltage control module includes a second transistor, the first light-emitting control module includes a third transistor, the light-emitting module includes a light-emitting diode, the gate of the third transistor is connected to the first light-emitting control signal line, the first terminal of the third transistor is connected to the first power supply line, the first terminal of the first transistor serves as the first end of the driving module and is connected to the second terminal of the third transistor, the second terminal of the first transistor serves as the second end of the driving module and is connected to the first terminal of the second transistor, the second terminal of the second transistor is connected to the first terminal of the light-emitting diode, the second terminal of the light-emitting diode is connected to the second power supply line, the first gate of the second transistor is connected to the second light-emitting control signal line, and the second gate of the second transistor is connected to the gate of the first transistor.

8. The pixel circuit according to claim 1 further includes a first light-emitting control module, wherein the control terminal of the first light-emitting control module is connected to a first light-emitting control signal line, the first terminal of the voltage control module is connected to the first power supply line, the second terminal of the voltage control module is connected to the first terminal of the driving module, the second terminal of the driving module is connected to the first terminal of the first light-emitting control module, and the second terminal of the first light-emitting control module is connected to the first terminal of the light-emitting module. The driving module includes a first transistor, the voltage control module includes a second transistor, the first light-emitting control module includes a third transistor, the light-emitting module includes a light-emitting diode, the first gate of the second transistor is connected to the second light-emitting control signal line, the second gate of the second transistor is connected to the gate of the first transistor, the first electrode of the second transistor is connected to the first power line, the first electrode of the first transistor serves as the first terminal of the driving module and is connected to the second electrode of the second transistor, the second electrode of the first transistor serves as the second terminal of the driving module and is connected to the first electrode of the third transistor, the second electrode of the third transistor is connected to the first electrode of the light-emitting diode, and the second electrode of the light-emitting diode is connected to the second power line.

9. The pixel circuit according to claim 5, wherein, The first transistor is a P-type transistor. The pixel circuit also includes a first initialization module. The control terminal of the first initialization module is connected to a first scan signal line, the first terminal of the first initialization module is connected to a second voltage signal line, and the second terminal of the first initialization module is connected to the first terminal of the light-emitting module. The first initialization module includes a fifth transistor, the gate of which is connected to the first scan signal line, the first terminal of which is connected to the second voltage signal line, and the second terminal of which is connected to the first terminal of the light-emitting diode; Alternatively, the pixel circuit may further include a data writing module, a compensation module, and a storage module; The control terminal of the data writing module is connected to the second scan signal line, the data writing module is connected to the first terminal of the drive module, and the data writing module is configured to write data voltage to the control terminal of the drive module. The control terminal of the compensation module is connected to the second scan signal line, the compensation module is connected between the second terminal of the drive module and the control terminal, and the compensation module is configured to compensate the threshold voltage of the drive module. The storage module is connected between the control terminal of the drive module and the first power line; The data writing module includes a sixth transistor, the compensation module includes a seventh transistor, the storage module includes a storage capacitor, the gate of the sixth transistor and the gate of the seventh transistor are both connected to the second scan signal line, the first terminal of the sixth transistor is connected to the data line, the second terminal of the sixth transistor is connected to the first terminal of the driving module, the first terminal of the seventh transistor is connected to the second terminal of the driving module, the second terminal of the seventh transistor is connected to the control terminal of the driving module, and the storage capacitor is connected between the first power line and the control terminal of the driving module. Alternatively, the pixel circuit may further include a second initialization module, wherein the control terminal of the second initialization module is connected to a third scan signal line, the first terminal of the second initialization module is connected to a third voltage signal line, and the second terminal of the second initialization module is connected to the control terminal of the drive module; The second initialization module includes an eighth transistor, the gate of which is connected to the third scan signal line, the first terminal of which is connected to the third voltage signal line, and the second terminal of which is connected to the control terminal of the drive module.

10. The pixel circuit according to claim 5 or 6, wherein, The first transistor is an N-type transistor. The pixel circuit also includes a first initialization module. The control terminal of the first initialization module is connected to a first scan signal line, the first terminal of the first initialization module is connected to a second voltage signal line, and the second terminal of the first initialization module is connected to the first terminal of the light-emitting module. The first initialization module includes a fifth transistor, the gate of which is connected to the first scan signal line, the first terminal of which is connected to the second voltage signal line, and the second terminal of which is connected to the first terminal of the light-emitting diode; Alternatively, the pixel circuit may further include a data writing module, a compensation module, and a storage module; The control terminal of the data writing module is connected to the second scan signal line, the data writing module is connected to the second terminal of the driving module, and the data writing module is configured to write data voltage to the control terminal of the driving module. The control terminal of the compensation module is connected to the first scan signal line, the compensation module is connected between the first terminal and the control terminal of the drive module, and the compensation module is configured to compensate the threshold voltage of the drive module. The storage module is connected between the control terminal of the driving module and the first terminal of the light-emitting module; The data writing module includes a sixth transistor, the compensation module includes a seventh transistor, and the storage module includes a storage capacitor. The gate of the sixth transistor is connected to the second scan signal line, the gate of the seventh transistor is connected to the first scan signal line, the first terminal of the sixth transistor is connected to the data line, the second terminal of the sixth transistor is connected to the second terminal of the driving module, the first terminal of the seventh transistor is connected to the first terminal of the driving module, the second terminal of the seventh transistor is connected to the control terminal of the driving module, and the storage capacitor is connected between the first terminal of the light-emitting module and the control terminal of the driving module.

11. The pixel circuit according to claim 1, wherein, The voltage control module includes a first sub-control module and a second sub-control module. The control terminal of the first sub-control module is connected to a first light-emitting control signal line, and the control terminal of the second sub-control module is connected to a second light-emitting control signal line. The first end of the first sub-control module is connected to the first power line, and the second end of the first sub-control module is connected to the first end of the driving module. The second end of the driving module is connected to the first end of the second sub-control module, and the second end of the second sub-control module is connected to the first end of the light-emitting module. Wherein, when the displayed grayscale is less than the preset grayscale, the transistors included in at least one of the first sub-control module or the second sub-control module are in the subthreshold region; The driving module includes a first transistor, the first sub-control module includes a ninth transistor, the second sub-control module includes a tenth transistor, the light-emitting module includes a light-emitting diode, the gate of the ninth transistor is connected to the first light-emitting control signal line, the first terminal of the ninth transistor is connected to the first power supply line, the second terminal of the ninth transistor is connected to the first terminal of the first transistor, the second terminal of the first transistor is connected to the first terminal of the tenth transistor, the second terminal of the tenth transistor is connected to the first terminal of the light-emitting diode, the second terminal of the light-emitting diode is connected to the second power supply line, and the gate of the tenth transistor is connected to the second light-emitting control signal line.

12. The pixel circuit according to claim 11 further includes a first initialization module, wherein the control terminal of the first initialization module is connected to a first scan signal line, the first terminal of the first initialization module is connected to a second voltage signal line, and the second terminal of the first initialization module is connected to the first terminal of the light-emitting module. The first initialization module includes a fifth transistor, the gate of which is connected to the first scan signal line, the first terminal of which is connected to the second voltage signal line, and the second terminal of which is connected to the first terminal of the light-emitting diode; Alternatively, the pixel circuit may further include a data writing module, a compensation module, and a storage module; The control terminal of the data writing module is connected to the second scan signal line, the data writing module is connected to the drive module, and the data writing module is configured to write data voltage to the control terminal of the drive module. The control terminal of the compensation module is connected to the second scan signal line, and the compensation module is connected between the second terminal and the control terminal of the drive module; or the control terminal of the compensation module is connected to the first scan signal line, and the compensation module is connected between the first terminal and the control terminal of the drive module. The compensation module is configured to compensate the threshold voltage of the drive module. The storage module is connected to the control terminal of the drive module.

13. The pixel circuit according to claim 12, wherein, The absolute value of the effective level of the first light emission control signal transmitted on the first light emission control signal line is less than the absolute value of the effective level of the first scan signal transmitted on the first scan signal line; and / or, the absolute value of the effective level of the second light emission control signal transmitted on the second light emission control signal line is less than the absolute value of the effective level of the first scan signal transmitted on the first scan signal line. The absolute value of the effective level of the second scan signal transmitted on the second scan signal line is the same as the absolute value of the effective level of the second light emission control signal transmitted on the second light emission control signal line, or the absolute value of the effective level of the second scan signal is the same as the absolute value of the effective level of the first light emission control signal transmitted on the first light emission control signal line.

14. The pixel circuit according to claim 12, wherein, The first transistor is a P-type transistor. The data writing module includes a sixth transistor, the compensation module includes a seventh transistor, and the storage module includes a storage capacitor. The gates of the sixth transistor and the seventh transistor are both connected to the second scan signal line. The first terminal of the sixth transistor is connected to the data line, the second terminal of the sixth transistor is connected to the first terminal of the driving module, the first terminal of the seventh transistor is connected to the second terminal of the driving module, and the second terminal of the seventh transistor is connected to the control terminal of the driving module. The storage capacitor is connected between the first power line and the control terminal of the driving module. The pixel circuit further includes a second initialization module, the control terminal of the second initialization module is connected to a third scan signal line, the first terminal of the second initialization module is connected to a third voltage signal line, and the second terminal of the second initialization module is connected to the control terminal of the drive module. The second initialization module includes an eighth transistor, the gate of which is connected to the third scan signal line, the first terminal of which is connected to the third voltage signal line, and the second terminal of which is connected to the control terminal of the drive module.

15. The pixel circuit according to claim 12, wherein, The first transistor is an N-type transistor; the data writing module includes a sixth transistor, the compensation module includes a seventh transistor, the storage module includes a storage capacitor, the gate of the sixth transistor is connected to the second scan signal line, the gate of the seventh transistor is connected to the first scan signal line, the first terminal of the sixth transistor is connected to the data line, the second terminal of the sixth transistor is connected to the second terminal of the driving module, the first terminal of the seventh transistor is connected to the first terminal of the driving module, the second terminal of the seventh transistor is connected to the control terminal of the driving module, and the storage capacitor is connected between the first terminal of the light-emitting module and the control terminal of the driving module.

16. A driving method for a pixel circuit, the pixel circuit comprising a driving module, a voltage control module, and a light-emitting module; The driving method for the pixel circuit includes: During the light-emitting phase, the driving module is controlled to drive the light-emitting module to emit light; wherein, when the displayed grayscale is less than the preset grayscale, the voltage control module is controlled to control the voltage at one end of the connection between the driving module and the voltage control module.

17. The driving method for the pixel circuit according to claim 16, wherein, The voltage control module includes a transistor, and controlling the voltage at one end of the drive module connected to the voltage control module includes: The transistors in the voltage control module are controlled to be in the subthreshold region in response to the signal from the control terminal of the voltage control module; Alternatively, the control of the voltage control module by the voltage control module to control the voltage at one end of the drive module connected to the voltage control module includes: When the displayed grayscale is greater than 0 grayscale and less than the preset grayscale, the transistor in the voltage control module is controlled to respond to the signal at the control terminal of the voltage control module and be in the subthreshold region. When the displayed grayscale is 0, the transistor in the voltage control module is controlled to be in the cutoff region in response to the signal from the control terminal of the voltage control module.

18. A display panel, comprising: Substrate; An active layer is located on one side of the substrate; A multilayer conductive layer is stacked on the side of the active layer away from the substrate; At least one pixel circuit, the pixel circuit including a driving module, a voltage control module and a light-emitting module, wherein the driving module includes a first transistor, the voltage control module includes a second transistor, and the light-emitting module includes a light-emitting diode; The multilayer conductive layer includes a first conductive layer, the gate of the first transistor and the gate of the second transistor are both located in the first conductive layer, and the orthogonal projection of the gate of the second transistor on the substrate is located between the orthogonal projection of the gate of the first transistor on the substrate and the orthogonal projection of the first electrode of the light-emitting diode on the substrate.

19. The display panel according to claim 18, wherein, The active layer includes a first active layer, the channel region of the first transistor is located in the first active layer, and the orthographic projection of the gate of the first transistor on the substrate at least partially covers the orthographic projection of the channel region of the first transistor on the substrate. The pixel circuit further includes a first light-emitting control module and a second light-emitting control module. The first light-emitting control module includes a third transistor, and the second light-emitting control module includes a fourth transistor. The active layer further includes a second active layer and a third active layer. The channel region of the third transistor is located in the second active layer, and the channel region of the fourth transistor is located in the third active layer. The orthogonal projection of the gate of the third transistor on the substrate at least partially covers the orthogonal projection of the channel region of the third transistor on the substrate, and the orthogonal projection of the gate of the fourth transistor on the substrate at least partially covers the orthogonal projection of the channel region of the fourth transistor on the substrate. The first active layer, the second active layer, and the third active layer are on the same layer and connected. The second active layer extends along the second direction, and the third active layer extends along the second direction. The second active layer and the third active layer are located on different sides of the first active layer. The orthogonal projection of the gate of the second transistor onto the substrate is located on the side where the orthogonal projection of the gate of the fourth transistor onto the substrate is away from the orthogonal projection of the gate of the first transistor onto the substrate; The display panel further includes a first voltage signal line, the first voltage signal line being located in the first conductive layer, and the orthogonal projection of the first voltage signal line on the substrate at least partially covering the orthogonal projection of the channel region of the second transistor on the substrate; The channel region of the second transistor is located in the third active layer; The orthographic projection of the first voltage signal line on the substrate does not overlap with the orthographic projection of the second active layer on the substrate; The first voltage signal line extends along a first direction, which intersects with the second direction.

20. The display panel according to claim 19 further includes a first light-emitting control signal line, wherein the first light-emitting control signal line is disposed intersecting with the second active layer and the third active layer; The orthographic projection of the first light-emitting control signal line on the substrate is located between the orthographic projection of the first voltage signal line on the substrate and the orthographic projection of the gate of the first transistor on the substrate; The first light emission control signal line extends along the first direction; The pixel circuit further includes a first initialization module, the first initialization module includes a fifth transistor, the channel region of the fifth transistor is located in the third active layer, and the display panel further includes a first scan signal line, the orthographic projection of the first scan signal line on the substrate at least partially covers the orthographic projection of the channel region of the fifth transistor on the substrate. Alternatively, the display panel may further include a second voltage signal line and a connecting line, and the multilayer conductive layer may further include a second conductive layer and a third conductive layer, with the second voltage signal line located on the second conductive layer and the connecting line located on the third conductive layer. The second voltage signal line is connected to one end of the connecting line through a via, and the third active layer is connected to the other end of the connecting line through a via. The second voltage signal line extends along the first direction, and the connecting line extends along the second direction; The orthographic projection of the first scan signal line on the substrate is located between the orthographic projections of the first voltage signal line on the substrate and the orthographic projections of the second voltage signal line on the substrate, and the orthographic projection of the first scan signal line on the substrate is located on the side of the orthographic projection of the first voltage signal line on the substrate that is away from the orthographic projection of the gate of the first transistor on the substrate.

21. A display device comprising the display panel according to any one of claims 18-20.

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