Encoding method and communication apparatus

Abstract

Provided in the present application are an encoding method and a communication apparatus. In the method, a first base matrix used by a transmitter device or a receiver device comprises a plurality of regions; a shift value corresponding to each of the plurality of regions satisfies a rule of the corresponding region; the rule is a relationship between a first shift value and a second shift value; the first shift value is a shift value of a non-zero element in a first sub-region in one region among the plurality of regions; the second shift value is a shift value of another non-zero element in the first sub-region; and the one region comprises a plurality of first sub-regions. The transmitter device or the receiver device uses the first base matrix to perform encoding or decoding. On the basis of the solution in the embodiments of the present application, the shift values in each first sub-region in a first base matrix satisfy a certain relationship therebetween, the shift value design solution for the first base matrix is simple, and a check matrix obtained on the basis of the first base matrix has stable girth properties, a good code distance and a better decoding performance.

Description

Encoding methods and communication devices

[0001] This application claims priority to Chinese Patent Application No. 202510073623.X, filed on January 15, 2025, entitled "Encoding Method and Communication Apparatus", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of channel coding, and more specifically, to a coding method and a communication apparatus. Background Technology

[0003] Low-density parity-check (LDPC) codes are linear block codes with sparse parity-check matrices. LDPC codes not only exhibit good performance approaching the Shannon limit, but also have low decoding complexity and flexible structure. Therefore, they have been widely used in some communication systems.

[0004] To better support high-throughput scenarios, LDPC codes also need to support longer code lengths. To address this issue, a double-lifting scheme is proposed. Specifically, the first lift transforms each element of the original LDPC base matrix into a 2x2 matrix, and the second lift transforms each element of the LDPC base matrix after the first lift into a ZcxZc matrix. The double-lifting scheme uses more shift values, and the current shift value table cannot meet the increased demand for shift values. Summary of the Invention

[0005] This application provides an encoding method and a communication device that can accommodate the design of more translation values ​​for the base matrix and ensure the stable performance of the obtained parity-check matrix.

[0006] Firstly, an encoding method is provided, which can be executed by a transmitting device or a module applied to the transmitting device (e.g., a processor, chip, circuit, etc., or a logic module, hardware, and / or software capable of implementing all or part of the functions of the transmitting device). The method may include: the transmitting device encoding the information bits to be encoded based on a first basis matrix to obtain a first codeword sequence; wherein the first basis matrix includes multiple regions, and the shift value corresponding to each region satisfies a rule for the corresponding region, the rule being the relationship between a first shift value and a second shift value, the first shift value being the shift value of a non-zero element of a first sub-region within one of the multiple regions, and the second shift value being the shift value of another non-zero element of the first sub-region, the region including multiple first sub-regions; the transmitting device outputs the first codeword sequence.

[0007] Specifically, the first sub-region mentioned above is a non-zero matrix. For example, the first sub-region is... or

[0008] Optionally, each of the above multiple regions may also include multiple second sub-regions, which are zero matrices.

[0009] Based on the above scheme, the translation values ​​of each first sub-region in the first basis matrix satisfy a certain relationship. The design scheme of the translation values ​​of the first basis matrix is ​​simple, and the parity check matrix obtained based on the first basis matrix has stable loop properties, good code distance, and better decoding performance.

[0010] In conjunction with the first aspect, in some implementations of the first aspect, the aforementioned multiple regions include any one or more of the following regions: a region consisting of all information columns and all core rows of the first base matrix; a region consisting of all information columns and some core rows of the first base matrix; a region consisting of all core columns and all extended rows of the first base matrix; a region consisting of all core columns and some extended rows of the first base matrix; a region consisting of all core columns and consecutive extended rows of the first base matrix; a region consisting of punched columns of the first base matrix; a region consisting of any even-numbered row with the largest row weight of the first base matrix; or a region consisting of any even-numbered column with the largest column weight of the first base matrix.

[0011] For example, the region consisting of all information columns and all core rows of the first base matrix is ​​the first region among multiple regions, and the remaining region of the first base matrix is ​​the second region among multiple regions.

[0012] For example, the region consisting of all information columns and some core rows of the first base matrix is ​​the first region among multiple regions, and the remaining region of the first base matrix is ​​the second region among multiple regions.

[0013] Based on the above scheme, the translation values ​​of the first sub-region in different regions can satisfy different relationships. This scheme can avoid the bad structure caused by the single rule for generating translation values ​​and has better error correction performance.

[0014] In conjunction with the first aspect, in some implementations of the first aspect, the above rule is: q = f(p).

[0015] Where f() is a linear or nonlinear function, p represents the first translation value mentioned above, and q represents the second translation value mentioned above.

[0016] For example, the first rule satisfied by the translation value of the first region in multiple regions can be denoted as q1 = f(p1), the second rule satisfied by the translation value of the second region in multiple regions can be denoted as q2 = f(p2), the third rule satisfied by the translation value of the third region in multiple regions can be denoted as q3 = f(p3), the fourth rule satisfied by the translation value of the fourth region in multiple regions can be denoted as q4 = f(p4), ...

[0017] Based on the above scheme, the translation values ​​of the first sub-region in different regions can satisfy a linear or non-linear relationship, which can ensure the good loop properties and code distance of the parity check matrix.

[0018] In conjunction with the first aspect, in some implementations of the first aspect, the above q = f(p) can specifically be any of the following terms: q = p + β; q = p + γ*h(Z) c ); q=α*p; q=α*p+β;

[0019] Where α, β, and γ are constants, h(Z) c ) is a linear or nonlinear function with independent variable Zc, where Zc is the lifting size of each element in the first basis matrix, and G(i) is a linear or nonlinear function with independent variable i, where i is a natural number.

[0020] In conjunction with the first aspect, in some implementations of the first aspect, the first translation value is a translation value of a non-zero element of a first sub-region in one of the multiple regions, and the second translation value is a translation value of another non-zero element of the first sub-region, including: the first translation value is a translation value of a non-zero element in the first column of the first sub-region, and the second translation value is a translation value of a non-zero element in the second column of the first sub-region; or, the first translation value is a translation value of a non-zero element in the second column of the first sub-region, and the second translation value is a translation value of a non-zero element in the first column of the first sub-region.

[0021] Based on the above scheme, the element positions corresponding to the required translation values ​​are fixed positions in each first sub-region, which makes the loop property of the parity check matrix stable and the code distance good, thus ensuring decoding performance.

[0022] In conjunction with the first aspect, in some implementations of the first aspect, the aforementioned first basis matrix is ​​generated based on a second basis matrix, which further includes multiple second sub-regions. Each first sub-region in the first basis matrix is ​​generated based on a non-zero element of the second basis matrix, and each second sub-region in the first basis matrix is ​​generated based on a zero element of the second basis matrix. All elements of the second sub-region are zero elements.

[0023] Based on the above scheme, the obtained first base matrix can support longer code lengths and can be applied to scenarios with higher throughput.

[0024] In conjunction with the first aspect, in some implementations of the first aspect, the aforementioned first sub-region is generated based on the first non-zero element in the second basis matrix, and the aforementioned first translation value and / or the aforementioned second translation value are translation values ​​of the first non-zero element.

[0025] For example, when the translation values ​​of the non-zero elements in the first sub-region are all the same, the first translation value and the second translation value are equal, and both the first translation value and the second translation value are translation values ​​of the first non-zero element.

[0026] For example, when the translation values ​​of the non-zero elements in the first sub-region are not the same, the first translation value and the second translation value are not equal, and the first translation value or the second translation value is the translation value of the first non-zero element.

[0027] Based on the above scheme, a simple calculation can be performed on the original translation value table to obtain the translation values ​​of all non-zero elements of the first basis matrix, without the need to store a new translation value table.

[0028] In conjunction with the first aspect, in some implementations of the first aspect, the region consisting of all core check columns and all core rows of the aforementioned first basis matrix is ​​formed by... and Composed of; and / or, the region consisting of all extended parity columns and all extended rows of the aforementioned first base matrix is ​​composed of and Composed of; and / or, the region composed of all information columns and all extended rows of the aforementioned first base matrix, or the region composed of all information columns and some extended rows of the aforementioned first base matrix, or the region composed of all information columns and consecutive partially extended rows of the aforementioned first base matrix, is composed of and Composed of.

[0029] Based on the above scheme, some adjacent rows of the first basis matrix can be orthogonal, resulting in high decoding parallelism and reduced decoding latency.

[0030] Secondly, a decoding method is provided, which can be executed by a receiving device or a module applied to the receiving device (e.g., a processor, chip, circuit, etc., or a logic module, hardware, and / or software capable of implementing all or part of the functions of the receiving device). The method may include: the receiving device acquiring a sequence to be decoded; the receiving device decoding the sequence to be decoded based on a first basis matrix to obtain a decoded sequence; wherein the first basis matrix includes multiple regions, and the translation value corresponding to each region satisfies a rule for that region, the rule being the relationship between a first translation value and a second translation value, where the first translation value is the translation value of a non-zero element of a first sub-region within the first region, and the second translation value is the translation value of another non-zero element of the first sub-region, and the region includes multiple first sub-regions; and the receiving device outputting the decoded sequence.

[0031] Specifically, the first sub-region mentioned above is a non-zero matrix. For example, the first sub-region is... or

[0032] Optionally, each of the above multiple regions may also include multiple second sub-regions, which are zero matrices.

[0033] Based on the above scheme, the translation values ​​of each first sub-region in the first basis matrix satisfy a certain relationship. The design scheme of the translation value of the first basis matrix is ​​simple, and the parity check matrix obtained based on the first translation value has stable loop properties, good code rate, and better decoding performance.

[0034] In conjunction with the second aspect, in some implementations of the second aspect, the aforementioned multiple regions include any one or more of the following regions: a region consisting of all information columns and all core rows of the first base matrix; a region consisting of all information columns and some core rows of the first base matrix; a region consisting of all core columns and all extended rows of the first base matrix; a region consisting of all core columns and some extended rows of the first base matrix; a region consisting of all core columns and consecutive extended rows of the first base matrix; a region consisting of punched columns of the first base matrix; a region consisting of any even-numbered row with the largest row weight of the first base matrix; or a region consisting of any even-numbered column with the largest column weight of the first base matrix.

[0035] For example, the region consisting of all information columns and all core rows of the first base matrix is ​​the first region among multiple regions, and the remaining region of the first base matrix is ​​the second region among multiple regions.

[0036] For example, the region consisting of all information columns and some core rows of the first base matrix is ​​the first region among multiple regions, and the remaining region of the first base matrix is ​​the second region among multiple regions.

[0037] Based on the above scheme, the translation values ​​of the first sub-region in different regions can satisfy different relationships. This scheme can avoid the bad structure caused by the single rule for generating translation values ​​and has better error correction performance.

[0038] In conjunction with the second aspect, in some implementations of the second aspect, the above rule is: q = f(p).

[0039] Where f() is a linear or nonlinear function, p represents the first translation value mentioned above, and q represents the second translation value mentioned above.

[0040] For example, the first rule satisfied by the translation value of the first region in multiple regions can be denoted as q1 = f(p1), the second rule satisfied by the translation value of the second region in multiple regions can be denoted as q2 = f(p2), the third rule satisfied by the translation value of the third region in multiple regions can be denoted as q3 = f(p3), the fourth rule satisfied by the translation value of the fourth region in multiple regions can be denoted as q4 = f(p4), ...

[0041] Based on the above scheme, the translation values ​​of the first sub-region in different regions can satisfy a linear or non-linear relationship, which can guarantee the loop property of the parity check matrix.

[0042] In conjunction with the second aspect, in some implementations of the second aspect, the above q = f(p) specifically takes any of the following terms: q = p + β; q = p + γ*h(Z) c ); q=α*p; q=α*p+β;

[0043] Where α, β, and γ are constants, h(Z) c ) is a linear or nonlinear function with independent variable Zc, where Zc is the lifting size of each element in the first basis matrix, and G(i) is a linear or nonlinear function with independent variable i, where i is a natural number.

[0044] In conjunction with the second aspect, in some implementations of the second aspect, the first translation value is a translation value of a non-zero element of a first sub-region in one of the multiple regions, and the second translation value is a translation value of another non-zero element of the first sub-region, including: the first translation value is a translation value of a non-zero element in the first column of the first sub-region, and the second translation value is a translation value of a non-zero element in the second column of the first sub-region; or, the first translation value is a translation value of a non-zero element in the second column of the first sub-region, and the second translation value is a translation value of a non-zero element in the first column of the first sub-region.

[0045] Based on the above scheme, the element positions corresponding to the required translation values ​​are fixed positions in each first sub-region, which makes the loop property of the parity check matrix stable and the code distance good, thus ensuring decoding performance.

[0046] In conjunction with the second aspect, in some implementations of the second aspect, the aforementioned first basis matrix is ​​generated based on the second basis matrix, which further includes multiple second sub-regions. Each first sub-region in the first basis matrix is ​​generated based on a non-zero element of the second basis matrix, and each second sub-region in the first basis matrix is ​​generated based on a zero element of the second basis matrix. All elements of the second sub-region are zero elements.

[0047] Based on the above scheme, the obtained first base matrix can support longer code lengths and can be applied to scenarios with higher throughput.

[0048] In conjunction with the second aspect, in some implementations of the second aspect, the aforementioned first sub-region is generated based on the first non-zero element in the second basis matrix, and the aforementioned first translation value and / or the aforementioned second translation value are translation values ​​of the first non-zero element.

[0049] For example, when the translation values ​​of the non-zero elements in the first sub-region are all the same, the first translation value and the second translation value are equal, and both the first translation value and the second translation value are translation values ​​of the first non-zero element.

[0050] For example, when the translation values ​​of the non-zero elements in the first sub-region are not the same, the first translation value and the second translation value are not equal, and the first translation value or the second translation value is the translation value of the first non-zero element.

[0051] Based on the above scheme, a simple calculation can be performed on the original translation value table to obtain the translation values ​​of all non-zero elements of the first basis matrix, without the need to store a new translation value table.

[0052] In conjunction with the second aspect, in some implementations of the second aspect, the region consisting of all core check columns and all core rows of the aforementioned first base matrix is ​​formed by... and Composed of; and / or, the region consisting of all extended parity columns and all extended rows of the aforementioned first base matrix is ​​composed of and Composed of; and / or, the region composed of all information columns and all extended rows of the aforementioned first base matrix, or the region composed of all information columns and some extended rows of the aforementioned first base matrix, or the region composed of all information columns and consecutive partially extended rows of the aforementioned first base matrix, is composed of and Composed of.

[0053] Based on the above scheme, some adjacent rows of the first basis matrix can be orthogonal, resulting in high decoding parallelism and reduced decoding latency.

[0054] Thirdly, a communication device is provided, which has the function of implementing the method in the first aspect or any possible implementation of the first aspect. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above-described function.

[0055] Fourthly, a communication device is provided, which has the function of implementing the method in the second aspect or any possible implementation of the second aspect. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above-described function.

[0056] Fifthly, a communication device is provided, comprising at least one processor configured to cause the communication device to execute the method of the first aspect or any possible implementation thereof; or to execute the method of the second aspect or any possible implementation thereof. Optionally, the at least one processor is coupled to at least one memory for storing computer programs or instructions, and the at least one processor is configured to call and run the computer program or instructions from the at least one memory, causing the communication device to execute the method of the first aspect or any possible implementation thereof; or to execute the method of the second aspect or any possible implementation thereof. Optionally, the at least one processor may be included in the communication device or may be configured outside the communication device. Optionally, the communication device further includes the at least one memory. Optionally, the communication device further includes at least one communication interface. As an example, the communication interface may include an input interface and / or an output interface, or may be an interface circuit.

[0057] Sixthly, a communication device is provided, comprising a communication interface and a circuit. The communication interface is configured to receive a signal to be processed and transmit the signal to the circuit. The circuit is configured to process the signal to perform a method as described in the first aspect or any possible implementation thereof; or to perform a method as described in the second aspect or any possible implementation thereof. Optionally, the communication interface is further configured to output a signal processed by the circuit. Optionally, the signal may include information and / or data. Optionally, the communication device may be a chip (e.g., a baseband chip) or a chip system.

[0058] A seventh aspect provides a computer-readable storage medium storing computer program code or instructions that, when executed on a computer, cause the method of the first aspect or any possible implementation thereof to be implemented; or, the method of the second aspect or any possible implementation thereof to be implemented.

[0059] Eighthly, a computer program product is provided, the computer program product comprising computer program code or instructions, which, when executed on a computer, cause the method in the first aspect or any possible implementation thereof to be implemented; or, as in the second aspect or any possible implementation thereof, the method to be implemented.

[0060] Ninth aspect, a wireless communication system is provided, including the communication device as described in the third aspect and the communication device as described in the fourth aspect. Attached Figure Description

[0061] Figure 1 is a schematic diagram of a network architecture to which embodiments of this application can be applied.

[0062] Figure 2 is a schematic diagram of the parity check matrix H of an LDPC.

[0063] Figure 3 shows the Tanner plot of the parity-check matrix H of an LDPC.

[0064] Figure 4 is a schematic diagram of the structure of the parity check matrix.

[0065] Figure 5 is a schematic diagram of the information transmission process.

[0066] Figure 6 is a schematic flowchart of an encoding method and a decoding method 600 provided in this application.

[0067] Figure 7 is a schematic diagram of an example of an exponential matrix corresponding to a first basis matrix provided in this application.

[0068] Figure 8 shows the performance simulation results provided in this application.

[0069] Figure 9 is a schematic structural diagram of the communication device 10 provided in this application.

[0070] Figure 10 is a schematic structural diagram of another communication device 20 provided in this application.

[0071] Figure 11 is a schematic structural diagram of the chip 30 provided in this application. Detailed Implementation

[0072] To facilitate understanding of the embodiments of this application, the following points will be explained before introducing the embodiments of this application.

[0073] In the embodiments of this application, "instruction" can include direct instruction, indirect instruction, explicit instruction, and implicit instruction. When describing a certain instruction information for instructing A, it can be understood that the instruction information carries A, which can be a direct instruction of A or an indirect instruction of A. Indirect instruction can refer to directly instructing B through the instruction information, and the correspondence between B and A, to achieve the purpose of instructing A through the instruction information. The correspondence between B and A can be predefined by the protocol, pre-stored, or obtained through configuration between network elements. The various numerical designations such as "first," "second," etc., are only for descriptive convenience and are not used to limit the scope of the embodiments of this application, such as distinguishing different messages, different information, different parameters, different ranges, etc. "Predefined" can be achieved by pre-saving corresponding codes, tables, or other methods that can be used to instruct relevant information in the device; this application does not limit its specific implementation. The "protocol" involved can refer to standard protocols in the field of communication, such as the Long Term Evolution (LTE) protocol, the New Radio (NR) protocol, and related protocols applied to future communication systems; this application does not limit this. The words “exemplary,” “for example,” and “an example” are used to indicate that something is an example, illustration, or description. Any embodiment or design described as an “example” in this application should not be construed as being more preferred or advantageous than other embodiments or designs. The terms “comprising,” “including,” “having,” and variations thereof all mean “including but not limited to,” unless otherwise specifically emphasized. “At least one” means one or more, and “more than one” means two or more. “And / or” describes the relationship between related objects, indicating that three relationships may exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. “At least one of the following” or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, and c can mean: a, or, b, or, c, or, a and b, or, a and c, or, b and c, or, a, b, and c. Where a, b, and c can be single or multiple. Descriptions relating to device A sending messages, information, or data to device B, and device B receiving messages, information, or data from device A, aim to specify which device the message, information, or data is intended for, without specifying whether the transmission is direct or indirect via other devices. Descriptions such as "when," "under," "if," and "if" indicate that the device will take appropriate action under certain objective circumstances, not a time limit, nor do they require the device to perform a judgment action during implementation, nor do they imply any other limitations.

[0074] Furthermore, the network architecture and business scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0075] The following describes a communication system to which embodiments of this application can be applied.

[0076] The embodiments of this application can be applied to various communication systems, including but not limited to: 5th generation (5G) systems, LTE systems, Long Term Evolution-Advanced (LTE-A) systems, LTE Frequency Division Duplex (FDD) systems, LTE Time Division Duplex (TDD) systems, etc. They can also be applied to future communication systems, such as 6th generation mobile communication systems. Furthermore, they can be applied to device-to-device (D2D) communication, vehicle-to-everything (V2X) communication, machine-to-machine (M2M) communication, machine-type communication (MTC), Internet of Things (IoT) communication systems, narrowband Internet of Things (NB-IoT) systems, or other communication systems. Furthermore, it can be extended to similar wireless communication systems, such as Wireless-Fidelity (WiFi), Worldwide Interoperability for Microwave Access (WIMAX), and communication systems related to the 3rd Generation Partnership Project (3GPP), without limitation.

[0077] A communication system applicable to embodiments of this application may include one or more transmitting devices and one or more receiving devices. Optionally, one of the transmitting device and the receiving device may be a terminal device, and the other may be a network device. Optionally, both the transmitting device and the receiving device may be terminal devices. Optionally, both the transmitting device and the receiving device may be network devices. Exemplarily, the transmitting device may be an encoding device, and the receiving device may be a decoding device.

[0078] Figure 1 is a schematic diagram of a network architecture applicable to an embodiment of this application. As shown in Figure 1, the embodiments of this application can be applied to both uplink and downlink data transmission. Figure 1 only uses uplink or downlink data transmission between one network device and two terminal devices (such as terminal device 1 and terminal device 2) as an example. In uplink data transmission, the sending device is the terminal device and the receiving device is the network device; conversely, in downlink data transmission, the sending device is the network device and the receiving device is the terminal device. Furthermore, the applicability of the embodiments of this application in other communication scenarios is not limited; for example, they can also be applied to sidelink communication.

[0079] The terminal equipment in this application can also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, mobile terminal (MT), remote station, remote terminal, mobile device, user terminal, terminal, drone, wireless communication equipment, user agent, or user device, etc. The terminal equipment in the embodiments of this application can be a device that provides voice and / or data connectivity to a user, and can be used to connect people, objects, and machines, such as handheld devices with wireless connectivity, vehicle-mounted devices, etc. The terminal devices in the embodiments of this application may be mobile phones, tablets, laptops, handheld computers, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, etc.

[0080] The network equipment in this application can be a device with wireless transceiver capabilities, which can be a device that provides wireless communication services. It is usually located on the network side, including but not limited to next-generation base stations (gNodeB, gNB) in 5G systems, base stations in sixth-generation mobile communication systems, base stations in future mobile communication systems, or access nodes in wireless fidelity (WiFi) systems, evolved node B (eNB), radio network controller (RNC), node B (NB), base station controller (BSC), home base station (e.g., home evolved NodeB or home Node B, HNB), base band unit (BBU), transmission reception point (TRP), transmitting point (TP), base transceiver station (BTS), satellites, drones, etc. in long term evolution (LTE) systems. In a network architecture, network equipment may include centralized unit (CU) nodes, distributed unit (DU) nodes, RAN equipment including CU and DU nodes, RAN equipment including control plane CU nodes, user plane CU nodes, and DU nodes, or, in a cloud radio access network (CRAN) scenario, wireless controllers, relay stations, vehicle-mounted equipment, and wearable devices. Furthermore, a base station may be a macro base station, micro base station, relay node, donor node, or a combination thereof. A base station may also refer to a communication module, modem, or chip installed within the aforementioned equipment or apparatus. A base station may also be a mobile switching center and equipment performing base station functions in D2D, V2X, and M2M communications, or equipment performing base station functions in future communication systems. A base station can support networks using the same or different access technologies, without limitation.

[0081] Unless otherwise specified, the means for implementing the functions of a terminal device or network device in this application can refer to the terminal device or network device itself, or it can refer to a means that enables the terminal device or network device to implement the functions, such as a chip system or chip, specifically a system-on-a-chip (SoC) or a modem. This means can be installed in the terminal device or network device. In the embodiments of this application, the chip system can be composed of chips, or it can include chips and other discrete devices.

[0082] For example, some embodiments in this document use a 5G system as an example to illustrate specific solution details. When this solution is used in other communication systems, such as LTE systems or future communication systems, the messages, channels, or information in the solution can be replaced with messages, channels, or information in other communication systems that can achieve the corresponding functions, and this application does not limit this.

[0083] Furthermore, the embodiments of this application can be applied to various application scenarios, such as high-throughput scenarios, high-reliability scenarios, low-latency scenarios, high-reliability low-latency scenarios, or low-power scenarios. Among them, high-throughput scenarios can be, for example, enhanced mobile broadband (eMBB) scenarios, high-reliability low-latency scenarios can be, for example, URLLC (ultra-reliable low-latency communication) scenarios, and low-power scenarios can be, for example, M2M scenarios, MTC scenarios, or IoT scenarios.

[0084] To facilitate understanding of the embodiments of this application, several concepts or terms involved in the embodiments of this application are briefly described. The concepts or terms described below are based on the concepts or terms specified in the agreement, but do not mean that the embodiments of this application can only be applied to existing systems. The concepts or terms involved in the embodiments of this application can be applied to future systems. Furthermore, the specific names of the concepts or terms (e.g., concepts or terms involving functional descriptions) can be adjusted as the system develops in the future.

[0085] 1. LDPC code

[0086] LDPC codes are a type of linear block code. A linear block code divides the information sequence to be encoded into groups of q bits each. The encoder then performs linear operations on these q information bits to obtain m parity bits. These q information bits are then combined with the m parity bits to obtain a codeword of length n = q + m. The mapping from q information bits to an n-bit codeword is typically represented by a corresponding parity check matrix H. Based on the parity check matrix H, a codeword sequence can be generated to complete the encoding process. After the codeword sequence is transmitted through the channel, a decoding device decodes the received signal to determine the original information bits.

[0087] The parity-check matrix H of an LDPC is a sparse matrix. The number of zero elements in the parity-check matrix H is far greater than the number of non-zero elements; in other words, the row weight (or column weight) of the parity-check matrix is ​​far less than the number of elements in each row (or column) of the LDPC matrix. Specifically, an LDPC code with an information bit length of q and a code length of n can be uniquely determined by its parity-check matrix H.

[0088] In 1981, Tanner represented the parity-check matrix H graphically, and this type of graph is now called a Tanner graph. There is a one-to-one correspondence between the Tanner graph and the parity-check matrix. A Tanner graph consists of two types of vertices: one type represents codeword bits and is called variable nodes, and the other type consists of parity nodes, representing parity constraints. Each parity node represents a parity constraint, which will be explained below with reference to Figures 2 and 3.

[0089] Figure 2 is a schematic diagram of the parity check matrix H of an LDPC.

[0090] In Figure 2, {V i} represents the set of variable nodes (VN), {C i} represents the set of check nodes (CNs). Each row of the check matrix H represents a check equation, and each check equation corresponds to a check node. Each column represents a codeword bit, and each codeword bit corresponds to a variable node. In Figure 2, there are 8 variable nodes and 4 check nodes. If a codeword bit is included in the corresponding check equation, a line is used to connect the involved variable nodes and check nodes to obtain the Tanner graph.

[0091] Figure 3 is a Tanner plot of the parity-check matrix H of an LDPC.

[0092] As shown in Figure 3, the Tanner graph represents the parity-check matrix of the LDPC. For example, for a parity-check matrix H of size m rows and n columns, the Tanner graph contains two types of nodes: n variable nodes and m parity nodes. The n variable nodes correspond to the n columns of the parity-check matrix H, and the m parity nodes correspond to the m rows of the parity-check matrix H. A cycle in the Tanner graph is composed of interconnected vertices, with one vertex serving as both the start and end point of the cycle, and each node is visited only once. The variable nodes in the Tanner graph correspond to each column of the parity-check matrix H, which is equivalent to each codeword bit in the LDPC. The parity nodes in the Tanner graph correspond to each row of the parity-check matrix H, which is equivalent to the parity bit in the LDPC. The connection between the two types of nodes corresponds to the value of an element in the H matrix. If there is a connection between the i-th parity node and the j-th variable node, the element (i, j) in the H matrix has a value of 1; otherwise, the corresponding element is 0. The connection between variable nodes and parity nodes can also be called an edge. The existence of a connection between the validation node and the variable node can also be described as: the validation node and the variable node are connected or have an edge. The connection between the validation node and the variable node can include either the presence of an edge or the absence of an edge.

[0093] 2. QC-LDPC code

[0094] QC-LDPC codes are a type of structured LDPC codes. Due to the unique structure of their parity-check matrix, encoding can be implemented using a simple feedback shift register, reducing the encoding complexity of LDPC codes. In practice, QC-LDPC codes are represented using a base grape (BG), where elements are either 0 or 1. Expanding the 1s and 0s in the BG yields a parity-check matrix H, which can be used for encoding or decoding. In the embodiments of this application, the BG can be written in matrix form, referred to as the base matrix H in this application. BG Basis matrix H BG An element of 0 indicates that there are no edges in the base graph, while a value of 1 indicates that there are edges in the base graph (or that the corresponding check is associated with the corresponding variable). NR LDPC codes involve multiple base graph selection; currently, the standard stores two base graphs, BG1 and BG2. BG2 is used when the information length is less than or equal to 292, or when the information length is less than or equal to 3824 and the code rate is less than or equal to 2 / 3, or when the code rate is less than or equal to 0.25; otherwise, BG1 is used. The following section discusses the base matrix H. BG The expansion process is described.

[0095] Based on the basis matrix H BG And by increasing the lifting size Zc, the basis matrix H can be... BGThe matrix is ​​expanded into a complete parity-check matrix for encoding or decoding. In this application, Zc can also be referred to as the expansion factor, boosting factor, expansion value, expansion coefficient, boosting size, etc. The expansion process involves boosting all elements of the base matrix into a Zc*Zc square matrix. Specifically, 0 is boosted to a Zc*Zc zero matrix, and 1 is boosted to an identity matrix. This identity matrix is ​​then cyclically shifted based on the shifting value (SV) corresponding to 1. This cyclic shift can be left or right, and this application does not limit this. It can be understood that each 1 in the base matrix corresponds to a shifting value. For example, boosting 1 to a 4×4 identity matrix with shifting values ​​of 0, 1, 2, and 3, and a cyclic shift to the right, is illustrated below:

[0096] (1) When the translation value is 0 (i.e., remains unchanged), the matrix after right circular shift is:

[0097] (2) When the translation value is 1, the matrix after the right circular shift is:

[0098] (3) When the translation value is 2, the matrix after the right circular shift is:

[0099] (4) When the translation value is 3, the matrix after the right circular shift is:

[0100] Alternatively, it can be understood that the complete parity check matrix H can be derived from an exponential matrix H. b H indicates b Each element in the matrix corresponds to a Zc*Zc submatrix. Each element indicates the number of times the corresponding submatrix has been cyclically shifted by the identity matrix. Therefore, the storage space required for the complete parity check matrix H is greatly reduced. (Exponential matrix H) b The elements in it can also be called QC blocks.

[0101] For example, the exponent matrix H of the QC-LDPC code b As shown below:

[0102] It can be seen that the exponent matrix H b The size is 4 rows and 24 columns, and the exponent matrix H b Each element i in the matrix represents a square matrix of order Z. Let represent a cyclic shift matrix, where i represents the cyclic shift value of the cyclic shift matrix, and i is an integer. Additionally, the exponent matrix H... b In this context, "-1" represents a zero matrix and "0" represents the identity matrix.

[0103] For example, As shown below:

[0104] Optional, exponent matrix H b In addition to "-1", zero elements in the matrix can also be represented in other ways, such as using "-" or null values ​​to represent a matrix of all zeros.

[0105] It is understandable that the above exponent matrix H b The matrix corresponding to the positions greater than or equal to 0 that are changed to 1 and the positions of -1 that are changed to 0 is the base matrix. The 1s in the base matrix are then expanded into a cyclic shift matrix based on the corresponding elements of the exponent matrix, and the 0s are expanded into a 0 matrix of the corresponding size. After expansion, the parity check matrix is ​​obtained.

[0106] 3. Non-zero elements and zero elements

[0107] In this application, zero elements in the check matrix indicate that there is no connection between the variable node and the check node. Non-zero elements in the check matrix indicate that there is a connection between the variable node and the check node.

[0108] This application does not limit the specific representation of zero and non-zero elements. For example, in the exponential matrix H b In a matrix, "-1" can be used to represent a zero element, and "non-negative value" can be used to represent a non-zero element. Similarly, in a parity check matrix H, "0" can be used to represent a zero element, and "1" can be used to represent a non-zero element.

[0109] For ease of description, the LDPC basis matrix below uses "0" to represent zero elements and "1" to represent non-zero elements.

[0110] 4. Basic Structure of Basis Matrices

[0111] As shown in Figure 4(a), the base matrix can include a high-rate region, an all-zero region, an incremental redundancy region, and a raptor-like region. The high-rate region can include parts A and B as shown in Figure 4(b), where part A corresponds to information bits (or information digits, etc.), and part B is a square matrix corresponding to core parity bits (or core parity digits). Part B can also be the region corresponding to parity columns with a column weight greater than 1 within the high-rate region. The all-zero region can correspond to part C in Figure 4(b) and is an all-zero matrix. The incremental redundancy region can correspond to part D in Figure 4(b). The raptor-like region can correspond to part E in Figure 4(b) and can be an identity matrix or a lower triangular matrix, corresponding to the parity bits of the low-rate extension.

[0112] The LDPC code base matrix shown in Figure 4 adopts a "raptor-like" structure, which can be gradually extended from a high-rate kernel matrix to a low-rate matrix, thus flexibly supporting encoding at various code rates. In practical use, as shown in Figure 4(a), the first X rows and the first Y columns of the base matrix can be extracted. As the code rate decreases, X and Y gradually increase, and the area of ​​the matrix used also gradually expands. The difference between X and Y represents the number of information columns.

[0113] The LDPC basis matrix truncated at any bit rate can be represented by a parity-check matrix H, which can also be represented by an exponent matrix H. b Therefore, the structure of the LDCP basis matrix, the structure of the parity-check matrix H, and the structure of the exponent matrix H are related. b The structure is similar, and will not be elaborated here.

[0114] 5. Core matrix, core rows, core columns

[0115] Core line: This is the line corresponding to the core check bit. In other words, the core line is the line corresponding to the high bitrate region, or the line corresponding to part A, or the line corresponding to part B.

[0116] Core columns: These can include all information columns and all core check columns. In other words, core columns are the columns corresponding to high bitrate areas, or the columns corresponding to part A plus part B.

[0117] The kernel matrix is ​​the portion consisting of all the kernel rows and columns of the LDPC base matrix or LDPC parity-check matrix. In other words, the kernel matrix is ​​the high-bitrate region of the LDPC base matrix or LDPC parity-check matrix, or a matrix composed of part A and part B.

[0118] 6. Extended columns, non-extended columns, extended rows, and non-extended rows

[0119] For LDPC codes, each additional extension node adds one row and one column to the actual matrix used. In this application, these added row and column are referred to as extension columns and extension rows, respectively. Extension columns are the columns corresponding to the extension nodes; in other words, extension columns correspond to the extended parity bits. Columns other than extension columns are non-extension columns. Rows other than extension rows are non-extension rows. Taking Figure 4 as an example, columns C and E are extension columns, and rows D and E are extension rows.

[0120] As mentioned above, based on the basis matrix H BG And by increasing the lifting size Zc, the basis matrix H can be... BGThis is expanded into a complete parity-check matrix H. We use two base maps, BG1 and BG2, from the current standard as examples. The following terminology is not limited to BG1 and BG2, but also applies to the base maps in this embodiment. BG1 has a size of 46*68, and the base matrix H is truncated from BG1 based on a certain code rate. BG The size is denoted as X*Y, and the basis matrix H BG Rows 1 through 4 are the core rows and the base matrix H. BG Rows 5 through X are the extended rows and the base matrix H. BG Columns 1 through 22 are information columns and the basis matrix H. BG Columns 23 to 26 are the core check columns and the base matrix H. BG Columns 27 through Y are extended check columns. Based on this base matrix H BG The extended verification matrix H consists of rows 1 to 4*Zc as core rows, rows 4*Zc+1 to X*Zc as extension rows, columns 1 to 22*Zc as information columns, columns 22*Zc+1 to 26*Zc as core verification columns, and columns 26*Zc+1 to Y*Zc as extension verification columns.

[0121] That is, the basis matrix H BG The rows after the expansion of the core rows are still called the core rows of the parity-check matrix and the basis matrix H. BG The rows after the expansion are still called the expanded rows of the parity-check matrix, the basis matrix H. BG The expanded columns of the information column are still called the information columns of the parity check matrix, the basis matrix H. BG The columns after the core check column is expanded are still called the information columns of the check matrix, the basis matrix H. BG The extended parity columns, after expansion, are still called the extended parity columns of the parity matrix. The base matrix H... BG It may also be possible to first expand it into other basis matrices (denoted as BG0), and then expand it again into a complete parity-check matrix, for example, basis matrix H. BG The extension process to BG0 involves changing the basis matrix H. BG Each element in BG0 is promoted to a k*k matrix. Rows 1 to 4*k of BG0 are the core rows, rows 4*k+1 to X*k are the extended rows, columns 1 to 22*k are the information columns, columns 22*k+1 to 26*k are the core verification columns, and columns 26*k+1 to Y*k are the extended verification columns. For example, k can be equal to 2.

[0122] Similarly, BG2 has a size of 42*52, and the basis matrix H is truncated from BG2 based on a certain code rate. BG The size is denoted as X*Y, and the basis matrix H BG Rows 1 through 4 are the core rows and the base matrix H.BG Rows 5 through X are the extended rows and the base matrix H. BG Columns 1 through 10 are information columns and the basis matrix H. BG Columns 11 through 14 are the core check columns and the base matrix H. BG Columns 15 through Y are extended check columns. Based on this base matrix H BG The extended parity-check matrix H has the following columns: rows 1 to 4*Zc (core rows), rows 4*Zc+1 to X*Zc (extension rows), columns 1 to 10*Zc (information columns), columns 10*Zc+1 to 14*Zc (core parity columns), and columns 14*Zc+1 to Y*Zc (extension parity columns). This is equivalent to the base matrix H. BG The rows after the expansion of the core rows are still called the core rows of the parity-check matrix and the basis matrix H. BG The rows after the expansion are still called the expanded rows of the parity-check matrix, the basis matrix H. BG The expanded columns of the information column are still called the information columns of the parity check matrix, the basis matrix H. BG The columns after the core check column is expanded are still called the information columns of the check matrix, the basis matrix H. BG The extended parity columns, after expansion, are still called the extended parity columns of the parity matrix. The base matrix H... BG It may also be possible to first expand it into other basis matrices (denoted as BG0), and then expand it again into a complete parity-check matrix, for example, basis matrix H. BG The extension process to BG0 involves changing the basis matrix H. BG Each element in BG0 is promoted to a k*k matrix. Rows 1 to 4*k of BG0 are the core rows, rows 4*k+1 to X*k are the extended rows, columns 1 to 10*k are the information columns, columns 10*k+1 to 14*k are the core verification columns, and columns 14*k+1 to Y*k are the extended verification columns. For example, k can be equal to 2.

[0123] The structural division of the base matrix shown in Figure 4, consisting of parts A, B, C, D, and E, is also applicable to BG0 and the parity check matrix based on the base matrix extension.

[0124] Furthermore, in this application, the portion consisting of non-extended columns can also be called the core portion, and the portion consisting of extended columns can also be called the extended portion. Taking Figure 4 as an example, the portion consisting of A, B, and D is the core portion, and the portion consisting of C and E is the extended portion.

[0125] 7. Drilling Column

[0126] In LDPC codes, bits corresponding to punctured columns are not transmitted. Punctured columns can be either information columns or parity columns. Furthermore, columns in LDPC codes that are not punctured are also called non-punctured columns. Similarly, non-punctured columns can be either information columns or parity columns.

[0127] Generally, the punched columns for BG1 and BG2 are column 1 and column 2, respectively.

[0128] 8. Calculate the lifting size (Zc) and shifting value.

[0129] The storage content of the 5G LDPC code regarding shift values ​​includes: (1) a list of lifting sizes; and (2) a list of shift values ​​that correspond one-to-one with the rows of the lifting size list.

[0130] For example, the list of lifting dimensions is shown in Table 1.

[0131] Table 1

[0132] The j-th row of the size list includes Where a j ∈{2,3,5,7,9,11,13,15}, max(k j )∈{7,7,6,5,5,5,4,4}; The row indices of the lift dimension list correspond one-to-one with the column indices of the translation value list, that is, each row of the lift dimension list corresponds to a set of translation values.

[0133] For example, the list of translation values ​​is shown in Table 2.

[0134] Table 2

[0135] Basis matrix H BG A non-zero element corresponds to one translation value. For example, the basis matrix H... BG The non-zero element in row 0 and column 0 of the matrix has a translation value of 211 when the lifting size set index is 0. The basis matrix H... BG The non-zero element in the 1st row and 6th column of the matrix has a translation value of 66 when the lifting size set index is 3. The basis matrix H... BG The non-zero element in the 2nd row and 9th column corresponds to a translation value of 206 when the size set index is 7.

[0136] Specifically, during LDPC encoding, the lift size is first determined, and then the corresponding translation value is determined based on the selected lift size to construct the parity check matrix. For example, if the determined lift size is 40, and the lift size set index corresponding to 40 in Table 1 is 2, then the parity check matrix can be constructed based on the translation value in the column corresponding to lift size set index = 2 in Table 2.

[0137] 9. Message length, code length, and code rate

[0138] The information length is the length of the information bits to be encoded (i.e., the number of bits contained). This length can be the length of the payload information bits, or the length of the payload information bits after adding cyclic redundancy check (CRC) bits. This application does not impose any specific restrictions.

[0139] Code length refers to the length of the bit sequence to be transmitted, which can be the transmitted bit sequence corresponding to the modulated symbol.

[0140] Bitrate refers to the ratio of information length to bit length.

[0141] Optionally, the above three values ​​can be pre-configured by higher-layer signaling, medium access control (MAC) layer, or downlink physical layer signals, or they can be directly obtained and calculated by the transceiver. For example, the code length can be determined by the frame structure, number of layers, and modulation scheme of the encoded and transmitted information bit sequence; the code rate can be indicated in the above manner or given in the modulation and coding scheme (MCS).

[0142] 10. Information Transmission Process

[0143] Figure 5 is a schematic diagram of the information transmission process applicable to this application. As shown in Figure 5, information is sent from the source, undergoes source coding, channel coding, modulation, air interface transmission, demodulation, channel decoding, and source recovery, and finally reaches the destination, completing the transmission of information from the source to the destination. The processing shown in the upper layer of Figure 5 (including source coding, channel coding, and modulation) is performed at the coding device, while the processing shown in the lower layer (including demodulation, channel decoding, and source recovery) is performed at the decoding device. The embodiments of this application mainly involve the source coding, channel coding, channel decoding, and source recovery shown in Figure 5.

[0144] To better support high-throughput scenarios, LDPC codes also need to support longer code lengths. To address this issue, a double-lifting scheme is proposed. Specifically, the first lift transforms each element of the original base matrix into a 2x2 matrix, and the second lift transforms each element of the base matrix after the first lift into a ZcxZc matrix. The double-lifting scheme uses more shift values, and the current shift value table cannot meet the increased shift value requirements. Therefore, this application proposes an encoding and decoding method that can accommodate more shift values ​​in the base matrix while ensuring the stable performance of the obtained parity-check matrix.

[0145] Figure 6 is a schematic flowchart of an encoding and decoding method 600 provided in this application. The method includes the following steps.

[0146] It is understood that method 600 can be executed by both the sending device and the receiving device. Unless otherwise specified, "sending device" or "receiving device" can refer to the sending device or receiving device itself, or it can refer to a device that enables the sending device or receiving device to perform this function. For ease of description, the following text will use "sending device" and "receiving device" to describe it. The sending device can be a terminal device or a network device, and the receiving device can be a terminal device or a network device.

[0147] S610, the transmitting device encodes the information bits to be encoded based on the first base matrix to obtain the first codeword sequence.

[0148] Specifically, the first basis matrix mentioned above includes multiple regions, and the translation value corresponding to each region satisfies the rules of the corresponding region.

[0149] Specifically, the above rule is the relationship between the first translation value and the second translation value. The first translation value is the translation value of a non-zero element of the first sub-region in one of the above multiple regions, and the second translation value is the translation value of another non-zero element of the first sub-region.

[0150] For example, the first sub-region described above is a k*k non-zero matrix, where k is a positive integer. As an example, when k equals 2, the first sub-region is... or

[0151] The following section uses the first region among multiple regions as an example to describe the first rule that the translation value of the first region satisfies.

[0152] For example, the first rule can be expressed by the following Formula 1: q1 = f(p1) Formula 1

[0153] Where f() is a linear or nonlinear function, p1 represents the first translation value, and q1 represents the second translation value.

[0154] Formula 1 above should hold modulo Zc. Alternatively, if there exists any integer n such that q1 = f(p1 ± n * Zc) holds, or if there exists any integer n such that q1 ± n * Zc = f(p1) holds, this also falls within the scope of protection of this application.

[0155] For example, the above q1 = f(p1) can specifically be any of the following:

[0156] (1) q1 = p1 + β;

[0157] (2) q1=p1+γ*h(Z) c );

[0158] (3) q1 = α*p1;

[0159] (4) q1 = α*p1 + β;

[0160] (5)

[0161] Where α, β, and γ are constants, h(Z) c ) is a linear or nonlinear function with independent variable Zc, where Zc is the lifting dimension of each element in the first basis matrix, and G(i) is a linear or nonlinear function with independent variable i, where i is a natural number.

[0162] For example, the above h(Z) c ) = Zc.

[0163] For example, G(i) = i-1 above.

[0164] The above (1), (2), (3), (4) or (5) shown in this application are only some specific examples of Formula 1 above. This application does not limit the specific form of Formula 1 above.

[0165] Optionally, the first translation value can be the translation value of the non-zero element in the first column of the first sub-region, and the second translation value can be the translation value of the non-zero element in the second column of the first sub-region; or, the first translation value can be the translation value of the non-zero element in the second column of the first sub-region, and the second translation value can be the translation value of the non-zero element in the first column of the first sub-region.

[0166] Optionally, the first region described above may further include multiple second sub-regions. For example, the second sub-region is a k*k zero matrix. As an example, when k equals 2, the second sub-region is...

[0167] The rules for the translation values ​​of other regions among the above-mentioned regions can also refer to the first rule for the translation values ​​of the first region, and this application does not limit this.

[0168] For example, the translation values ​​corresponding to each of the above multiple regions satisfy different rules, or there are two regions among the above multiple regions whose translation values ​​satisfy the same rules.

[0169] Specifically, the multiple regions of the first basis matrix can be divided in various ways, and this application does not limit this.

[0170] For example, the aforementioned multiple regions may include any one or more of the following regions: a region consisting of all information columns and all core rows of the first base matrix; a region consisting of all information columns and some core rows of the first base matrix; a region consisting of all core columns and all extended rows of the first base matrix; a region consisting of all core columns and some extended rows of the first base matrix (the extended rows may be non-contiguous or contiguous); a region consisting of the punched columns of the first base matrix; a region consisting of any even-numbered row with the largest row weight of the first base matrix; or a region consisting of any even-numbered row with the largest column weight of the first base matrix. This application does not limit the scope of these regions.

[0171] Figure 7 shows an example of the exponent matrix corresponding to the first basis matrix, where the first sub-region of the first basis matrix is... or The second subregion of the first basis matrix is Each element in the exponent matrix shown in Figure 7 represents the translation value of the corresponding element in the first basis matrix. The exponent matrix corresponding to the first basis matrix shown in Figure 7 can be a partial content extracted from the exponent matrix corresponding to the complete first basis matrix. As shown in Figure 7, Figure 7 shows the contents of rows 1 to 46 and columns 1 to 52 of the exponent matrix. In the exponent matrix shown in Figure 7, "-1" indicates that the corresponding element in the first basis matrix is ​​zero and there is no translation value; "non-negative value" indicates that the corresponding element in the first basis matrix is ​​non-zero.

[0172] For example, the element "115" in the first row and first column of the exponent matrix shown in Figure 7 is the translation value of the non-zero element in the first row and first column of the first base matrix, and the element "76" in the third row and first column of the exponent matrix shown in Figure 7 is the translation value of the non-zero element in the third row and first column of the first base matrix.

[0173] The first base matrix corresponding to the exponent matrix shown in Figure 7 has rows 1 to 8 as information rows, columns 1 to 44 as information columns, and columns 45 to 52 as core verification columns.

[0174] Optionally, the first base matrix may also include extended rows and extended check columns. Rows 9 to 46 in Figure 7 are the extended rows of the first base matrix, and the extended check columns of the first base matrix are not shown in Figure 7.

[0175] As shown in Figure 7, the translation values ​​of the two non-zero elements in each first sub-region of the region formed by rows 3 to 8 and columns 1 to 44 of the first basis matrix are different, while the translation values ​​of the two non-zero elements in each first sub-region of the remaining regions of the first basis matrix are the same. Therefore, the division of the multiple regions shown in Figure 7 can be as follows: the region formed by rows 3 to 8 and columns 1 to 44 of the first basis matrix is ​​at least one of the multiple regions, and the remaining regions of the first basis matrix are the other regions of the multiple regions.

[0176] Example 1: The number of multiple regions is 2.

[0177] The first region is formed by rows 3 to 8 and columns 1 to 44 of the first base matrix, and the remaining regions of the first base matrix form the second region among the multiple regions.

[0178] For example, the first rule of the first region can be any one of (1), (2), (3), (4), or (5) above. For example, the first rule of the first region shown in Figure 7 involves α, β, γ, h(Z) c The values ​​of G(i) make q1≠p1.

[0179] For example, the second rule for the second region can also be any one of (1), (2), (3), (4), or (5) above. For instance, the second rule for the second region shown in Figure 7 involves α, β, γ, h(Z). c The values ​​of G(i) make q2 = p2.

[0180] Example 2: The number of multiple regions is 4.

[0181] The first region is formed by rows 3 and 4 and columns 1 to 44 of the first base matrix; the second region is formed by rows 5 and 6 and columns 1 to 44 of the first base matrix; the third region is formed by rows 7 and 8 and columns 1 to 44 of the first base matrix; and the remaining regions of the first base matrix form the fourth region.

[0182] For example, the first rule of the first region can be any one of (1), (2), (3), (4), or (5) above. For example, the first rule of the first region shown in Figure 7 involves α, β, γ, h(Z) cThe values ​​of G(i) make q1≠p1.

[0183] For example, the second rule for the second region can be any one of (1), (2), (3), (4), or (5) above. For instance, the second rule for the second region shown in Figure 7 involves α, β, γ, h(Z). c The values ​​of G(i) make q2≠p2.

[0184] For example, the third rule of the third region can be any one of (1), (2), (3), (4), or (5) above. For example, the third rule of the third region shown in Figure 7 involves α, β, γ, h(Z). c The values ​​of G(i) make q3≠p3.

[0185] For example, the fourth rule of the fourth region can also be any one of (1), (2), (3), (4), or (5) above. For example, the fourth rule of the fourth region shown in Figure 7 involves α, β, γ, h(Z) c The values ​​of G(i) make q4 = p4.

[0186] Optionally, method 600 may also include the step of obtaining the first basis matrix described above.

[0187] For example, the first basis matrix involved in this application may be predefined or pre-stored.

[0188] Alternatively, the first basis matrix involved in this application may be generated based on the second basis matrix. For example, each first sub-region in the first basis matrix is ​​generated based on a non-zero element in the second basis matrix, and each second sub-region in the first basis matrix is ​​generated based on a zero element in the second basis matrix.

[0189] For example, the second basis matrix mentioned above may be a basis matrix truncated from BG1 or BG2.

[0190] Specifically, each non-zero element in the second basis matrix corresponds to a translation value. The translation value corresponding to each non-zero element in the second basis matrix can be obtained from the lifting size list shown in Table 1 and the translation value list shown in Table 2, which will not be elaborated here.

[0191] If each first sub-region in the first basis matrix is ​​obtained based on a non-zero element in the second basis matrix, for example, if the first sub-region in the first basis matrix is ​​generated based on the first non-zero element in the second basis matrix, and if the translation values ​​of the non-zero elements in the first sub-region are not the same, then the translation value of a non-zero element in the first sub-region is the translation value of the first non-zero element. In other words, the first translation value or the second translation value is the translation value of the first non-zero element. If the translation values ​​of the non-zero elements in the first sub-region are the same, then the translation values ​​of the non-zero elements in the first sub-region are both the translation value of the first non-zero element. In other words, the first translation value and the second translation value are both the translation values ​​of the first non-zero element.

[0192] For example, if the first sub-region in the first basis matrix is ​​obtained based on the first non-zero element in the i-th row and j-th column of the second basis matrix, then the first sub-region is... Then, the four elements of the first sub-region are respectively located in the (2i-1)th row and (2j-1)th column, (2i-1)th row and (2j)th column, (2i)th row and (2j-1)th column, and (2i)th row and (2j)th column of the first base matrix. The elements in the (2i-1)th row and (2j-1)th column and the elements in the (2i)th row and (2j)th column of the first base matrix are non-zero elements, and the elements in the (2i-1)th row and (2j)th column and the elements in the (2i)th row and (2j-1)th column of the first base matrix are zero elements. The translation value of the element in the (2i-1)th row and (2j-1)th column of the first base matrix can be the same as the translation value of the first non-zero element in the (i)th row and (j)th column of the second base matrix; or, the translation value of the element in the (2i-1)th row and (2j-1)th column of the first base matrix can be different from the translation value of the first non-zero element in the (i)th row and (2j)th column of the second base matrix. The translation value of the element in column -1 is the translation value of the first non-zero element in the i-th row and j-th column of the second basis matrix. The translation value of the element in the 2i-th row and 2j-th column of the first basis matrix and the translation value of the element in the 2i-1-th row and 2j-1-th column of the first basis matrix satisfy any one of (1), (2), (3), (4) or (5) above; or, the translation value of the element in the 2i-1-th row and 2j-1-th column of the first basis matrix and the translation value of the non-zero element in the 2i-th row and 2j-th column of the first basis matrix are not the same. The translation value of the element in the 2i-th row and 2j-th column of the first basis matrix is ​​the translation value of the first non-zero element in the i-th row and j-th column of the second basis matrix. The translation value of the element in the 2i-1-th row and 2j-1-th column of the first basis matrix and the translation value of the element in the 2i-th row and 2j-th column of the first basis matrix satisfy any one of (1), (2), (3), (4) or (5) above.

[0193] Optionally, the region consisting of all core check columns and all core rows of the first base matrix in this application is formed by... and The first subregion, or the region composed of all core check columns and all core rows of the first base matrix of this application, is... Alternatively, part B of the first basis matrix of this application is... and Composed of.

[0194] Optionally, the region consisting of all extended parity columns and all extended rows of the first base matrix in this application is formed by... and The first sub-region of the region composed of all extended parity columns and all extended rows of the first base matrix of this application is... Alternatively, the E part of the first basis matrix of this application is composed of and Composed of.

[0195] Optionally, the region consisting of all information columns and all extended rows of the first base matrix, or the region consisting of all information columns and some extended rows of the first base matrix, or the region consisting of all information columns and consecutive partially extended columns of the first base matrix, is formed by... and The region composed of, or the region composed of all information columns and all extended rows of the first base matrix of this application, or the region composed of all information columns and some extended rows of the first base matrix, or the region composed of all information columns and consecutive partially extended rows of the first base matrix, is each of the first sub-regions. Alternatively, the D portion of the first base matrix of this application, or a portion of the rows in the D portion, or consecutive rows in the D portion, is formed by... and Composed of.

[0196] In one example, the first sub-region of part A of the first basis matrix can be or The first sub-region of all parts of the first basis matrix except for part A is...

[0197] Specifically, the transmitting device can generate a first parity check matrix based on the aforementioned first base matrix, and use the first parity check matrix to encode the information bits to be encoded. For example, each non-zero element in the first base matrix is ​​first promoted to a Zc*Zc identity matrix in the first parity check matrix, and then the identity matrix is ​​cyclically shifted according to the shift value corresponding to each non-zero element in the first base matrix; each zero element in the first base matrix is ​​promoted to a Zc*Zc zero matrix in the first parity check matrix.

[0198] S620, the transmitting device outputs the first codeword sequence mentioned above.

[0199] After encoding is complete, the sending device outputs the first codeword sequence.

[0200] Optionally, method 600 may also include a decoding method on the decoding side. The following description refers to S630 to S640.

[0201] S630, the receiving device acquires the sequence to be decoded.

[0202] The sequence to be decoded can refer to the first codeword sequence output by the encoding side, which is received at the decoding side after transmission through the channel.

[0203] S640, the receiving device decodes the above-mentioned sequence to be decoded based on the first base matrix to obtain the decoded sequence.

[0204] Specifically, the receiving device can generate a first parity check matrix based on a first base matrix, and use the first parity check matrix to decode the sequence to be decoded. For example, each non-zero element in the first base matrix is ​​first promoted to a Zc*Zc identity matrix in the first parity check matrix, and then the identity matrix is ​​cyclically shifted according to the translation value corresponding to each non-zero element in the first base matrix; each zero element in the first base matrix is ​​promoted to a Zc*Zc zero matrix in the first parity check matrix.

[0205] Specifically, the determination of the translation value of each non-zero element in the first basis matrix can refer to the determination of the translation value of each non-zero element in the first basis matrix in S610 above, and will not be repeated here.

[0206] S650, the receiving device outputs the decoded sequence.

[0207] The design scheme for the translation value of the first base matrix provided by the above encoding method and decoding method 600 is simple, and the parity check matrix obtained based on the first base matrix has stable cyclic properties, good code distance, and better decoding performance.

[0208] Figure 8 shows the performance simulation results provided by the embodiments of this application. The simulation results shown in Figure 8 were obtained when the number of iteration rounds was 20 and the code rate was 22 / (20 + the number of rows of BG1 used). Figure 8 shows the performance simulation results when the number of rows of BG1 used was 4 to 13, corresponding to a code rate range of 11 / 12 to 2 / 3. In Figure 8(a), the horizontal axis represents the number of rows of BG1 used, and the vertical axis represents the signal-to-noise ratio (SNR) corresponding to a block error rate (BLER) of 1e-2. The dashed lines in Figure 8(a) represent the decoding performance of decoding with the existing NR basis matrix, and the solid lines in Figure 8(a) represent the decoding performance of decoding with the first basis matrix of this application. In Figure 8(b), the horizontal axis represents the number of rows of BG1 used, and the vertical axis represents the difference in SNR between the implementation lines of the first basis matrix and the dashed lines of the NR basis matrix in Figure 8(a). If the difference in SNR is less than 0, it indicates that the decoding performance of the first basis matrix in this scheme has an advantage over that of the NR basis matrix. As can be seen from Figure 8, the decoding performance of the first basis matrix provided in this embodiment is better than that of the NR LDPC basis matrix.

[0209] The communication device provided in this application is described below.

[0210] Figure 9 is a schematic structural diagram of the communication device 10 provided in this application. The communication device 10 can be a transmitting device, or a device applied to the transmitting device that can realize the corresponding functions of the transmitting device in the method embodiments of this application, such as a chip, processor, or circuit. Alternatively, the communication device 10 can be a receiving device, or a device applied to the receiving device that can realize the corresponding functions of the receiving device in the method embodiments of this application, such as a chip, processor, or circuit.

[0211] Optionally, the communication device 10 includes a processing module 11, which may be a processor, a processing board, a processing unit, or a processing device, etc. When the communication device 10 is a transmitting device or a device applied to a transmitting device, the processing module 11 is used to acquire a first base matrix and to encode the information bits to be encoded based on the first base matrix. Specific processes can be found in the detailed descriptions of the corresponding steps in the method embodiments, and will not be repeated here. When the communication device 10 is a receiving device or a device applied to a receiving device, the processing module 11 is used to acquire a first base matrix and to decode the sequence to be decoded based on the first base matrix, etc. Specific processes can be found in the detailed descriptions of the corresponding steps in the method embodiments, and will not be repeated here.

[0212] Optionally, the communication device 10 further includes a communication module 12, which may also be referred to as a transceiver module, transceiver, transceiver unit, or transceiver device, etc., for performing receiving (or input) and / or sending (or output) operations. For example, when the communication device 10 is a transmitting device or a device applied to a transmitting device, the communication module 12 can be used to output the first codeword sequence obtained by the processing module 11 through encoding. Similarly, when the communication device 10 is a receiving device or a device applied to a receiving device, the communication module 12 can be used to acquire the sequence to be decoded and send the sequence to be decoded to the processing module 11; and output the decoded sequence obtained by the processing module 11 after decoding the sequence to be decoded. In addition, the aforementioned communication module and / or processing module can be implemented by virtual modules. For example, the processing module can be implemented by a software functional unit or a virtual device, and the communication module can be implemented by a software function or a virtual device. Alternatively, the processing module or communication module can also be implemented by a physical device, for example, if the device is implemented using a chip / circuit (e.g., an integrated circuit or logic circuit). The communication module may be an input / output circuit and / or a communication interface, performing input operations (corresponding to the aforementioned receiving operation) and output operations (corresponding to the aforementioned sending operation); the processing module is an integrated processor, microprocessor, or circuit (e.g., integrated circuit, logic circuit, etc.).

[0213] The module division in this application is illustrative and represents only one logical functional division. In actual implementation, other division methods are possible. Furthermore, the functional modules in the various examples of this application can be integrated into a single processor, exist as separate physical entities, or be integrated into a single module. The integrated modules described above can be implemented in hardware, as software functional modules, or a combination of hardware and software.

[0214] Figure 10 is a schematic structural diagram of another communication device 20 provided in this application. The communication device 20 can be used to implement the functions of any communication device (e.g., a terminal device or a network device) in the communication system described in the foregoing examples. The communication device 20 may include at least one processor 21. Optionally, the processor 21 (or processing device) is coupled to a memory, which may be located within the communication device, integrated with the processor, or located outside the communication device. For example, the communication device 20 may also include at least one memory 22. The memory 22 stores computer programs, instructions, or data necessary for implementing any of the above method embodiments; the processor 21 may execute the computer programs, instructions, or data stored in the memory 22 to perform the corresponding functions of the transmitting or receiving device in any of the above embodiments.

[0215] Optionally, the communication device 20 may further include a communication interface 23, through which the communication device 20 can interact with other devices. For example, the communication interface 23 may be a transceiver, circuit, bus, module, pin, or other type of communication interface. When the communication device 20 is a chip-based device or circuit, the communication interface 23 in the device 20 may also be an input / output circuit, capable of inputting information (or receiving information) and / or outputting information (or sending information). The processor may be an integrated circuit or logic circuit, etc., and the processor can determine the output information based on the input information.

[0216] The coupling in this application refers to indirect coupling or communication connection between devices, units, or modules, which can be electrical, mechanical, or other forms, used for information exchange between devices, units, or modules. Processor 21 may operate in conjunction with memory 22 and communication interface 23. This application does not limit the connection medium between the aforementioned processor 21, memory 22, and communication interface 23.

[0217] Figure 11 is a schematic structural diagram of the chip 30 provided in this application. The chip 30 includes a circuit 31 and a communication interface 32. The circuit 31 can be a logic circuit, an integrated circuit, etc., and the communication interface 32 can also be called an input / output circuit, input / output interface, interface circuit, etc., which can input information (or receive information) or output information (or send information). The chip 30 can execute the methods executed by the encoding-side device or the decoding-side device in the various embodiments of this application.

[0218] In addition, this application also provides a computer-readable storage medium storing computer instructions, which, when executed on a computer, cause the operations and / or processes performed by the sending or receiving device in the various method embodiments of this application to be executed.

[0219] This application also provides a computer program product, which includes computer program code or instructions. When the computer program code or instructions are run on a computer, the operations and / or processes performed by the sending end device or the receiving end device in the various method embodiments of this application are executed.

[0220] Furthermore, this application also provides a chip including a processor. A memory for storing a computer program is provided independently of the chip, and the processor is used to execute the computer program stored in the memory, so that operations and / or processes performed by a transmitting or receiving device in any method embodiment are executed. Further, the chip may also include a communication interface. The communication interface may be an input / output interface or an interface circuit, etc. Further, the chip may also include the memory.

[0221] This application provides a communication system, including the transmitting end device and the receiving end device in the above method embodiments.

[0222] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0223] The processor in this application embodiment has signal processing capabilities and can be a central processing unit (CPU), or a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component. It can implement or execute the methods, steps, and logic block diagrams disclosed in this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in this application can be directly embodied in the execution of the hardware processor, or executed by a combination of hardware and software modules within the processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above methods.

[0224] In the embodiments of this application, the memory can be volatile memory or non-volatile memory, or it can include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0225] The technical solutions provided in this application can be implemented in whole or in part through software, hardware, firmware, or any combination thereof. When implemented using software, they can be implemented in whole or in part as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a terminal device, an access network device, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., digital video discs (DVDs)), or semiconductor media, etc.

[0226] The term "comprising" and any variations thereof used in the embodiments of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the steps or units listed, but may optionally include other steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0227] In this application, examples may reference each other without logical contradiction. For example, methods and / or terms between method embodiments may reference each other, functions and / or terms between device embodiments may reference each other, and functions and / or terms between device examples and method examples may reference each other.

[0228] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0229] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0230] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0231] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0232] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

Claims

1. An encoding method, characterized in that, include: The information bits to be encoded are encoded based on the first base matrix to obtain a first codeword sequence; wherein, the first base matrix includes multiple regions, and the translation value corresponding to each region satisfies the rule of the corresponding region, the rule being the relationship between the first translation value and the second translation value, the first translation value being the translation value of a non-zero element of a first sub-region in one of the multiple regions, and the second translation value being the translation value of another non-zero element of the first sub-region, wherein one region includes multiple first sub-regions; Output the first codeword sequence.

2. The method according to claim 1, characterized in that, The plurality of regions includes any one or more of the following regions: the region consisting of all information columns and all core rows of the first base matrix; the region consisting of all information columns and some core rows of the first base matrix; the region consisting of all core columns and all extended rows of the first base matrix; the region consisting of all core columns and some extended rows of the first base matrix; the region consisting of all core columns and consecutive extended rows of the first base matrix; the region consisting of punched columns of the first base matrix; the region consisting of any even-numbered row with the largest row weight of the first base matrix; or the region consisting of any even-numbered column with the largest column weight of the first base matrix.

3. The method according to claim 1 or 2, characterized in that, The first sub-region is or 4. The method according to any one of claims 1 to 3, characterized in that, The rule is: q = f(p) Where f() is a linear or nonlinear function, p represents the first translation value, and q represents the second translation value.

5. The method according to claim 4, characterized in that, The q = f(p) can be any of the following terms: q = p + β; q = p + γ*h(Z) c ); q=α*p; q=α*p+β; Where α, β, and γ are constants, h(Z) c ) is a linear or nonlinear function with independent variable Zc, where Zc is the lifting size of each element in the first basis matrix, and G(i) is a linear or nonlinear function with independent variable i, where i is a natural number.

6. The method according to any one of claims 3 to 5, characterized in that, The first translation value is the translation value of a non-zero element of a first sub-region within one of the plurality of regions, and the second translation value is the translation value of another non-zero element of the first sub-region, including: The first shift value is the shift value of the non-zero element in the first column of the first sub-region, and the second shift value is the shift value of the non-zero element in the second column of the first sub-region; or, The first shift value is the shift value of the non-zero element in the second column of the first sub-region, and the second shift value is the shift value of the non-zero element in the first column of the first sub-region.

7. The method according to any one of claims 4 to 6, characterized in that, The first basis matrix is ​​generated based on the second basis matrix. The first basis matrix also includes multiple second sub-regions. Each first sub-region in the first basis matrix is ​​generated based on a non-zero element in the second basis matrix. Each second sub-region in the first basis matrix is ​​generated based on a zero element in the second basis matrix. All elements in each second sub-region are zero elements.

8. The method according to claim 7, characterized in that, The first sub-region is generated based on the first non-zero element in the second basis matrix, and the first translation value and / or the second translation value is the translation value of the first non-zero element.

9. The method according to any one of claims 3 to 8, characterized in that, The region consisting of all core check columns and all core rows of the first base matrix is ​​composed of and Composed of; And / or, The region consisting of all extended parity columns and all extended rows of the first base matrix is ​​composed of and Composed of; And / or, The region consisting of all information columns and all extended rows of the first base matrix, or the region consisting of all information columns and some extended rows of the first base matrix, or the region consisting of all information columns and consecutive extended rows of the first base matrix, is formed by... and Composed of.

10. A decoding method, characterized in that, include: Obtain the sequence to be decoded; The sequence to be decoded is decoded based on a first basis matrix to obtain a decoded sequence; wherein, the first basis matrix includes multiple regions, and the translation value corresponding to each region satisfies the rule of the corresponding region, the rule being the relationship between a first translation value and a second translation value, the first translation value being the translation value of a non-zero element of a first sub-region in one of the multiple regions, and the second translation value being the translation value of another non-zero element of the first sub-region, wherein one region includes multiple first sub-regions; Output the decoded sequence.

11. The method according to claim 10, characterized in that, The plurality of regions includes any one or more of the following regions: the region consisting of all information columns and all core rows of the first base matrix; the region consisting of all information columns and some core rows of the first base matrix; the region consisting of all core columns and all extended rows of the first base matrix; the region consisting of all core columns and some extended rows of the first base matrix; the region consisting of all core columns and consecutive extended rows of the first base matrix; the region consisting of punched columns of the first base matrix; the region consisting of any even-numbered row with the largest row weight of the first base matrix; or the region consisting of any even-numbered column with the largest column weight of the first base matrix.

12. The method according to claim 10 or 11, characterized in that, The first sub-region is or 13. The method according to any one of claims 10 to 12, characterized in that, The rule is: q = f(p) Where f() is a linear or nonlinear function, p represents the first translation value, and q represents the second translation value.

14. The method according to claim 13, characterized in that, The q = f(p) can be any of the following terms: q = p + β; q = p + γ*h(Z) c ); q=α*p; q=α*p+β; Where α, β, and γ are constants, h(Z) c ) is a linear or nonlinear function with independent variable Zc, where Zc is the lifting size of each element in the first basis matrix, and G(i) is a linear or nonlinear function with independent variable i, where i is a natural number.

15. The method according to any one of claims 12 to 14, characterized in that, The first translation value is the translation value of a non-zero element of a first sub-region within one of the plurality of regions, and the second translation value is the translation value of another non-zero element of the first sub-region, including: The first shift value is the shift value of the non-zero element in the first column of the first sub-region, and the second shift value is the shift value of the non-zero element in the second column of the first sub-region; or, The first shift value is the shift value of the non-zero element in the second column of the first sub-region, and the second shift value is the shift value of the non-zero element in the first column of the first sub-region.

16. The method according to any one of claims 13 to 15, characterized in that, The first basis matrix is ​​generated based on the second basis matrix. The first basis matrix also includes multiple second sub-regions. Each first sub-region in the first basis matrix is ​​generated based on a non-zero element in the second basis matrix. Each second sub-region in the first basis matrix is ​​generated based on a zero element in the second basis matrix. All elements in each second sub-region are zero elements.

17. The method according to claim 16, characterized in that, The first sub-region is generated based on the first non-zero element in the second basis matrix, and the first translation value and / or the second translation value is the translation value of the first non-zero element.

18. The method according to any one of claims 12 to 17, characterized in that, The region consisting of all core check columns and all core rows of the first base matrix is ​​composed of and Composed of; And / or, The region consisting of all extended parity columns and all extended rows of the first base matrix is ​​composed of and Composed of; And / or, The region consisting of all information columns and all extended rows of the first base matrix, or the region consisting of all information columns and some extended rows of the first base matrix, or the region consisting of all information columns and consecutive extended rows of the first base matrix, is formed by... and Composed of.

19. A communication device, characterized in that, The system includes a communication interface and circuitry. The communication interface is used to acquire information required to perform the method as described in any one of claims 1-9, and to send the information to the circuitry, which is used to perform the method as described in any one of claims 1-9 based on the received information; or... The communication interface is used to acquire information required to perform the method as described in any one of claims 10-18, and to send the information to the circuit, which is used to perform the method as described in any one of claims 10-18 based on the received information.

20. A communication device, characterized in that, The device includes a processor coupled to a memory, the processor being configured to execute a computer program or instructions stored in the memory to cause the communication device to perform the method as described in any one of claims 1-18.

21. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed on a computer, implement the method as described in any one of claims 1-18.

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