Encoding method and decoding method

Abstract

Provided in the present application are an encoding method and a decoding method. In the method, a transmitter device may map a check bit sequence in a first codeword sequence after LDPC encoding into a new check bit sequence, and output a second codeword sequence after mapping; a decoding matrix used when a receiver device performs LDPC decoding on a sequence to be decoded is obtained by merging rows of a first base matrix, and the manner for merging the rows of the first base matrix corresponds to the manner for mapping the check bit sequence in the first codeword sequence by the transmitter device. In the embodiments of the present application, the second codeword sequence still includes check information of a check bit sequence before mapping, and the decoding matrix may still include element information of the first base matrix, which can ensure that error correction performance is improved. Moreover, in the embodiments of the present application, the number of rows of a decoding matrix used on a decoding side is less than the number of rows of the first base matrix, and thus the number of decoding iterations can be reduced.

Description

Encoding methods and decoding methods

[0001] This application claims priority to Chinese patent application filed on January 15, 2025, with application number 202510068681.3 and entitled "Encoding Method and Decoding Method", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of channel coding, and more specifically, to an encoding method and a decoding method. Background Technology

[0003] Low-density parity-check (LDPC) codes are linear block codes with sparse parity-check matrices. LDPC codes not only exhibit good performance approaching the Shannon limit, but also have low decoding complexity and flexible structure. Therefore, they have been widely used in some communication systems.

[0004] However, LDPC codes still suffer from slow decoding convergence speed and high decoding iteration cycles in high-throughput scenarios. Summary of the Invention

[0005] This application provides an encoding method and a decoding method that can increase the convergence speed of LDPC codes in high-throughput scenarios and ensure error correction performance with a low number of decoding iterations.

[0006] Firstly, an encoding method is provided, which can be executed by a transmitting device or a module applied to the transmitting device (e.g., a processor, chip, circuit, etc., or a logic module, hardware, and / or software capable of implementing all or part of the functions of the transmitting device). The method may include: the transmitting device performing LDPC encoding on the information bits to be encoded based on a first parity check matrix to obtain a first codeword sequence, the first codeword sequence including an information bit sequence and a first parity check bit sequence; the transmitting device mapping the first parity check bit sequence to a second parity check bit sequence; and the transmitting device outputting a second codeword sequence, the second codeword sequence including the aforementioned information bit sequence and the aforementioned second parity check bit sequence.

[0007] The above method further maps the parity bit sequence in the first codeword sequence after LDPC encoding. The mapped parity bit sequence can still contain the parity information of the parity bit sequence before mapping, and the length of the parity bit sequence of the output second codeword sequence can be flexibly designed. This method can improve the decoding performance under high code rate and low iteration number.

[0008] In conjunction with the first aspect, in some implementations of the first aspect, the aforementioned first check bit sequence includes a first core check bit sequence, which is the check bits corresponding to all core rows of the aforementioned first check matrix.

[0009] The above method further maps the core parity bit sequence in the first codeword sequence after LDPC encoding, which can improve the error correction performance in higher code rate scenarios and reduce the number of decoding iterations in higher code rate scenarios.

[0010] In conjunction with the first aspect, in some implementations of the first aspect, the aforementioned first check bit sequence consists of A segments of check bit sequences, wherein the length of the i-th segment of the A-segment check bit sequence is k. i *Zc, the second parity bit sequence mentioned above consists of B parity bit sequences, each of which has a length of Zc. Any parity bit sequence in the B parity bit sequence is obtained based on at least one parity bit sequence in the A parity bit sequence, where 1≤i≤A, and A, B, k i It is a positive integer.

[0011] The above method can merge any row check equation into one row, making the mapping method more flexible and improving decoding performance under high code rate and low iteration rounds.

[0012] In conjunction with the first aspect, in some implementations of the first aspect, the length of the i-th parity bit sequence in the aforementioned A-segment parity bit sequence is k. i *Zc, including: the length of each parity bit sequence in segment A is Zc.

[0013] In conjunction with the first aspect, in some implementations of the first aspect, the aforementioned B segment parity bit sequence includes a parity bit sequence #1B, which is determined based on parity bit sequence #1A and parity bit sequence #2A. Specifically, parity bit sequence #1A is a segment of the aforementioned A segment parity bit sequence or is obtained by cyclic shifting a segment of the aforementioned A segment parity bit sequence, and / or, parity bit sequence #2A is another segment of the aforementioned A segment parity bit sequence or is obtained by cyclic shifting another segment of the aforementioned A segment parity bit sequence.

[0014] The above method can merge two lines of parity check equations into one line. Combined with the corresponding operations on the decoding side, it can improve the efficiency of information transmission between bits during the decoding process and reduce the number of iterations.

[0015] In conjunction with the first aspect, in some implementations of the first aspect, the parity bit sequence #1B is determined based on the parity bit sequence #1A and the parity bit sequence #2A, including: the parity bit sequence #1B is obtained by performing an XOR operation on the parity bit sequence #1A and the parity bit sequence #2A.

[0016] In conjunction with the first aspect, in some implementations of the first aspect, the aforementioned B segment parity bit sequence includes a parity bit sequence #2B, which is determined based on parity bit sequences #3A, #4A, and #5A. Specifically, parity bit sequence #3A is a segment of the aforementioned A segment parity bit sequence, or parity bit sequence #3A is obtained by cyclic shifting a segment of the aforementioned A segment parity bit sequence; and / or, parity bit sequence #4A is another segment of the aforementioned A segment parity bit sequence, or parity bit sequence #4A is obtained by cyclic shifting another segment of the aforementioned A segment parity bit sequence; and / or, parity bit sequence #5A is yet another segment of the aforementioned A segment parity bit sequence, or parity bit sequence #5A is obtained by cyclic shifting yet another segment of the aforementioned A segment parity bit sequence.

[0017] The above method can merge the three-line parity equation into one line, which can further improve the efficiency of information transmission between bits and reduce the number of iterations during the decoding process.

[0018] In conjunction with the first aspect, in some implementations of the first aspect, the parity bit sequence #2B is determined based on the parity bit sequence #3A, the parity bit sequence #4A, and the parity bit sequence #5A, including: the parity bit sequence #2B is obtained by performing an XOR operation on the parity bit sequence #3A, the parity bit sequence #4A, and the parity bit sequence #5A.

[0019] In conjunction with the first aspect, in certain implementations of the first aspect, the first parity bit sequence in the aforementioned A-segment parity bit sequence is XORed with the second parity bit sequence in the aforementioned A-segment parity bit sequence to obtain a first sequence; the third parity bit sequence in the aforementioned A-segment parity bit sequence is XORed with the fourth parity bit sequence in the aforementioned A-segment parity bit sequence to obtain a second sequence; the fifth parity bit sequence in the aforementioned A-segment parity bit sequence is XORed with the sixth parity bit sequence in the aforementioned A-segment parity bit sequence to obtain a third sequence; the seventh parity bit sequence in the aforementioned A-segment parity bit sequence is XORed with the eighth parity bit sequence in the aforementioned A-segment parity bit sequence to obtain a fourth sequence; and the second parity bit sequence in the aforementioned A-segment parity bit sequence... The parity bit sequence is XORed with the fourth parity bit sequence in the aforementioned A-segment parity bit sequence to obtain the fifth sequence. The sixth parity bit sequence is XORed with the eighth parity bit sequence in the aforementioned A-segment parity bit sequence to obtain the sixth sequence. The second parity bit sequence is XORed with the eighth parity bit sequence in the aforementioned A-segment parity bit sequence to obtain the seventh sequence. The eighth parity bit sequence in the aforementioned A-segment parity bit sequence is the eighth sequence. The aforementioned B-segment parity bit sequence includes some or all of the sequences from the aforementioned first sequence, second sequence, third sequence, fourth sequence, fifth sequence, sixth sequence, seventh sequence, and eighth sequence.

[0020] The second parity bit sequence in the above method is flexibly selected from the multiple mapped sequences. The length of the second parity bit sequence can be flexibly adjusted, thereby supporting a variety of different code rates and being compatible with more communication scenarios.

[0021] In conjunction with the first aspect, in certain implementations of the first aspect, the first parity bit sequence in the aforementioned A-segment parity bit sequence is XORed with the second parity bit sequence in the aforementioned A-segment parity bit sequence to obtain a first sequence; the third parity bit sequence in the aforementioned A-segment parity bit sequence is XORed with the fourth parity bit sequence in the aforementioned A-segment parity bit sequence to obtain a second sequence; the fifth parity bit sequence in the aforementioned A-segment parity bit sequence is XORed with the sixth parity bit sequence in the aforementioned A-segment parity bit sequence to obtain a third sequence; and the seventh parity bit sequence in the aforementioned A-segment parity bit sequence is XORed with the eighth parity bit sequence in the aforementioned A-segment parity bit sequence to obtain a fourth sequence. The aforementioned B-segment parity bit sequence includes the first sequence, the second sequence, the third sequence, and the fourth sequence.

[0022] The above method can support high bitrate scenarios and improve decoding performance under high bitrate and low iteration rounds.

[0023] In conjunction with the first aspect, in some implementations of the first aspect, the second parity bit sequence in the aforementioned A-segment parity bit sequence is XORed with the fourth parity bit sequence in the aforementioned A-segment parity bit sequence to obtain the fifth sequence, and the aforementioned B-segment parity bit sequence also includes the fifth sequence.

[0024] In conjunction with the first aspect, in some implementations of the first aspect, the sixth parity bit sequence in the aforementioned A-segment parity bit sequence is XORed with the eighth parity bit sequence in the aforementioned A-segment parity bit sequence to obtain the sixth sequence, and the aforementioned B-segment parity bit sequence also includes the sixth sequence.

[0025] In conjunction with the first aspect, in some implementations of the first aspect, the second parity bit sequence in the aforementioned A-segment parity bit sequence is XORed with the eighth parity bit sequence in the aforementioned A-segment parity bit sequence to obtain the seventh sequence, and the aforementioned B-segment parity bit sequence also includes the seventh sequence.

[0026] The above methods support progressively lower bit rates, allowing for a variety of different bit rates and compatibility with more communication scenarios.

[0027] In conjunction with the first aspect, in some implementations of the first aspect, the 8th parity bit sequence in the aforementioned A-segment parity bit sequence is regarded as the eighth sequence, and the aforementioned B-segment parity bit sequence also includes the eighth sequence.

[0028] The second parity bit sequence in the above method contains a segment of the parity bit sequence from the first parity bit sequence. That is, during the mapping process, there is a segment of the parity bit sequence in the first parity bit sequence that does not need to participate in the XOR operation. This method can easily recover the original parity bit sequence from the second parity bit sequence.

[0029] In conjunction with the first aspect, in some implementations of the first aspect, the first parity bit sequence and the second parity bit sequence may further include a first extended parity bit sequence, which is the parity bit corresponding to the extended row of the first parity matrix.

[0030] The above method is compatible with all communication scenarios from low bit rate to high bit rate, increasing the universality of this solution.

[0031] In conjunction with the first aspect, in some implementations of the first aspect, the length of the second codeword sequence is equal to the length of the first codeword sequence.

[0032] Secondly, a decoding method is provided, which can be executed by a receiving device or a module applied to the receiving device (e.g., a processor, chip, circuit, etc., or a logic module, hardware, and / or software capable of implementing all or part of the functions of the receiving device). The method may include: the receiving device acquiring a sequence to be decoded; the receiving device performing LDPC decoding on the sequence to be decoded based on a first decoding matrix to obtain a decoded sequence; the first decoding matrix being obtained by merging the rows of a first base matrix.

[0033] The above method can merge the core rows of the first base matrix to obtain the first decoding matrix. Using the first decoding matrix can improve the decoding performance in higher code rate scenarios and reduce the number of iteration rounds in higher code rate scenarios.

[0034] In conjunction with the second aspect, in some implementations of the second aspect, the rows of the aforementioned first basis matrix include the core rows of the first basis matrix.

[0035] In conjunction with the second aspect, in some implementations of the second aspect, the first base matrix consists of A rows, and the first decoding matrix consists of B rows, wherein the B rows are obtained based on at least one row of the A rows, and A and B are positive integers.

[0036] In conjunction with the second aspect, in some implementations of the second aspect, the aforementioned B rows include a row #1B, which is determined based on two rows from the A rows.

[0037] In conjunction with the second aspect, in some implementations of the second aspect, row #1B is determined based on two rows out of A rows, including: row #1B is obtained by performing an XOR operation on two rows out of A rows.

[0038] In conjunction with the second aspect, in some implementations of the second aspect, the aforementioned B rows include a row #2B, which is determined based on three rows from the A rows.

[0039] In conjunction with the second aspect, in some implementations of the second aspect, row #2B is determined based on three rows out of A, including: row #2B is obtained by performing an XOR operation on the three rows out of A.

[0040] In conjunction with the second aspect, in some implementations of the second aspect, the elements of the first row of the aforementioned A rows are XORed with the elements of the second row of the aforementioned A rows to obtain a first decoded row; the elements of the third row of the aforementioned A rows are XORed with the elements of the fourth row of the aforementioned A rows to obtain a second decoded row; the elements of the fifth row of the aforementioned A rows are XORed with the elements of the sixth row of the aforementioned A rows to obtain a third decoded row; and the elements of the seventh row of the aforementioned A rows are XORed with the elements of the eighth row of the aforementioned A rows to obtain a fourth decoded row. The aforementioned B rows include the first decoded row, the second decoded row, the third decoded row, and the fourth decoded row.

[0041] In conjunction with the second aspect, in some implementations of the second aspect, the elements of the first row of the aforementioned A rows are used as the first decoding row; the elements of the third row of the aforementioned A rows are XORed with the elements of the fourth row of the aforementioned A rows to obtain the second decoding row; the elements of the fifth row of the aforementioned A rows are XORed with the elements of the sixth row of the aforementioned A rows to obtain the third decoding row; the elements of the seventh row of the aforementioned A rows are XORed with the elements of the eighth row of the aforementioned A rows to obtain the fourth decoding row; the elements of the second row of the aforementioned A rows are used as the fifth decoding row; and the aforementioned B rows include the first decoding row, the second decoding row, the third decoding row, the fourth decoding row, and the fifth decoding row.

[0042] In conjunction with the second aspect, in some implementations of the second aspect, the elements of the first row of the aforementioned A rows are used as the first decoding row; the elements of the third row of the aforementioned A rows are XORed with the elements of the fourth row of the aforementioned A rows to obtain the second decoding row; the elements of the fifth row of the aforementioned A rows are used as the third decoding row; the elements of the seventh row of the aforementioned A rows are XORed with the elements of the eighth row of the aforementioned A rows to obtain the fourth decoding row; the elements of the second row of the aforementioned A rows are used as the fifth decoding row; the elements of the sixth row of the aforementioned A rows are used as the sixth decoding row; and the aforementioned B rows include the first decoding row, the second decoding row, the third decoding row, the fourth decoding row, the fifth decoding row, and the sixth decoding row.

[0043] In conjunction with the second aspect, in some implementations of the second aspect, the elements of the first row of the aforementioned A rows are used as the first decoding row; the elements of the third row of the aforementioned A rows are XORed with the elements of the fourth row of the aforementioned A rows to obtain the second decoding row; the elements of the fifth row of the aforementioned A rows are used as the third decoding row; the elements of the seventh row of the aforementioned A rows are used as the fourth decoding row; the elements of the second row of the aforementioned A rows are used as the fifth decoding row; the elements of the sixth row of the aforementioned A rows are used as the sixth decoding row; the elements of the eighth row of the aforementioned A rows are used as the seventh decoding row; and the aforementioned B rows include the first decoding row, the second decoding row, the third decoding row, the fourth decoding row, the fifth decoding row, the sixth decoding row, and the seventh decoding row.

[0044] In conjunction with the second aspect, in some implementations of the second aspect, the aforementioned first base matrix and the aforementioned first decoding matrix further include extended rows.

[0045] The beneficial effects of certain implementations of the second aspect mentioned above can be referred to the beneficial effects of certain implementations of the first aspect mentioned above, and will not be repeated here.

[0046] Thirdly, a communication device is provided, which has the function of implementing the method in the first aspect or any possible implementation of the first aspect. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above-described function.

[0047] Fourthly, a communication device is provided, which has the function of implementing the method in the second aspect or any possible implementation of the second aspect. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above-described function.

[0048] Fifthly, a communication device is provided, comprising at least one processor configured to cause the communication device to execute the method of the first aspect or any possible implementation thereof; or to execute the method of the second aspect or any possible implementation thereof. Optionally, the at least one processor is coupled to at least one memory for storing computer programs or instructions, and the at least one processor is configured to call and run the computer program or instructions from the at least one memory, causing the communication device to execute the method of the first aspect or any possible implementation thereof; or to execute the method of the second aspect or any possible implementation thereof. Optionally, the at least one processor may be included in the communication device or may be configured outside the communication device. Optionally, the communication device further includes the at least one memory. Optionally, the communication device further includes at least one communication interface. As an example, the communication interface may include an input interface and / or an output interface, or may be an interface circuit.

[0049] Sixthly, a communication device is provided, comprising a communication interface and a circuit. The communication interface is configured to receive a signal to be processed and transmit the signal to the circuit. The circuit is configured to process the signal to perform a method as described in the first aspect or any possible implementation thereof; or to perform a method as described in the second aspect or any possible implementation thereof. Optionally, the communication interface is further configured to output a signal processed by the circuit. Optionally, the signal may include information and / or data. Optionally, the communication device may be a chip (e.g., a baseband chip) or a chip system.

[0050] A seventh aspect provides a computer-readable storage medium storing computer program code or instructions that, when executed on a computer, cause the method of the first aspect or any possible implementation thereof to be implemented; or, the method of the second aspect or any possible implementation thereof to be implemented.

[0051] Eighthly, a computer program product is provided, the computer program product comprising computer program code or instructions, which, when executed on a computer, cause the method in the first aspect or any possible implementation thereof to be implemented; or, as in the second aspect or any possible implementation thereof, the method to be implemented.

[0052] A ninth aspect provides a wireless communication system, including a communication device as described in the third aspect and a communication device as described in the fourth aspect. Attached Figure Description

[0053] Figure 1 is a schematic diagram of a network architecture to which embodiments of this application can be applied.

[0054] Figure 2 is a schematic diagram of the parity check matrix H of an LDPC.

[0055] Figure 3 shows the Tanner plot of the parity-check matrix H of an LDPC.

[0056] Figure 4 is a schematic diagram of the structure of the parity check matrix.

[0057] Figure 5 is a schematic diagram of the information transmission process.

[0058] Figure 6 is a schematic flowchart of an encoding method 600 provided in this application.

[0059] Figure 7 is a schematic diagram illustrating an example of mapping the first core check bit sequence provided in this application.

[0060] Figure 8 is a schematic diagram of another example of mapping the first core check bit sequence provided in this application.

[0061] Figure 9 is a schematic flowchart of a decoding method 900 provided in this application.

[0062] Figure 10 is a schematic diagram of an example of a first basis matrix provided in this application.

[0063] Figure 11 is the exponent matrix corresponding to the first basis matrix shown in Figure 10.

[0064] Figure 12(a) is an example of a first decoding matrix provided in this application.

[0065] Figure 12(b) is the exponent matrix corresponding to the first decoding matrix shown in Figure 12(a).

[0066] Figure 13(a) is another example of the first decoding matrix provided in this application.

[0067] Figure 13(b) is the exponent matrix corresponding to the first decoding matrix shown in Figure 13(a).

[0068] Figure 14(a) is another example of the first decoding matrix provided in this application.

[0069] Figure 14(b) is the exponent matrix corresponding to the first decoding matrix shown in Figure 14(a).

[0070] Figure 15(a) is another example of the first decoding matrix provided in this application.

[0071] Figure 15(b) is the exponent matrix corresponding to the first decoding matrix shown in Figure 15(a).

[0072] Figure 16(a) is another example of the first decoding matrix provided in this application.

[0073] Figure 16(b) is the exponent matrix corresponding to the first decoding matrix shown in Figure 16(a).

[0074] Figure 17(a) is another example of the first decoding matrix provided in this application.

[0075] Figure 17(b) is the exponent matrix corresponding to the first decoding matrix shown in Figure 17(a).

[0076] Figure 18 shows the performance simulation results provided in this application.

[0077] Figure 19 is a schematic structural diagram of the communication device 10 provided in this application.

[0078] Figure 20 is a schematic structural diagram of another communication device 20 provided in this application.

[0079] Figure 21 is a schematic structural diagram of the chip 30 provided in this application. Detailed Implementation

[0080] To facilitate understanding of the embodiments of this application, the following points will be explained before introducing the embodiments of this application.

[0081] In the embodiments of this application, "instruction" can include direct instruction, indirect instruction, explicit instruction, and implicit instruction. When describing a certain instruction information for instructing A, it can be understood that the instruction information carries A, which can be a direct instruction of A or an indirect instruction of A. Indirect instruction can refer to directly instructing B through the instruction information, and the correspondence between B and A, to achieve the purpose of instructing A through the instruction information. The correspondence between B and A can be predefined by the protocol, pre-stored, or obtained through configuration between network elements. The various numerical designations such as "first," "second," etc., are only for descriptive convenience and are not used to limit the scope of the embodiments of this application, such as distinguishing different messages, different information, different parameters, different ranges, etc. "Predefined" can be achieved by pre-saving corresponding codes, tables, or other methods that can be used to instruct relevant information in the device; this application does not limit its specific implementation. The "protocol" involved can refer to standard protocols in the field of communication, such as the Long Term Evolution (LTE) protocol, the New Radio (NR) protocol, and related protocols applied to future communication systems; this application does not limit this. The words “exemplary,” “for example,” and “an example” are used to indicate that something is an example, illustration, or description. Any embodiment or design described as an “example” in this application should not be construed as being more preferred or advantageous than other embodiments or designs. The terms “comprising,” “including,” “having,” and variations thereof all mean “including but not limited to,” unless otherwise specifically emphasized. “At least one” means one or more, and “more than one” means two or more. “And / or” describes the relationship between related objects, indicating that three relationships may exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. “At least one of the following” or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, and c can mean: a, or, b, or, c, or, a and b, or, a and c, or, b and c, or, a, b, and c. Where a, b, and c can be single or multiple. Descriptions relating to device A sending messages, information, or data to device B, and device B receiving messages, information, or data from device A, aim to specify which device the message, information, or data is intended for, without specifying whether the transmission is direct or indirect via other devices. Descriptions such as "when," "under," "if," and "if" indicate that the device will take appropriate action under certain objective circumstances, not a time limit, nor do they require the device to perform a judgment action during implementation, nor do they imply any other limitations.

[0082] Furthermore, the network architecture and business scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0083] The following describes a communication system to which embodiments of this application can be applied.

[0084] The embodiments of this application can be applied to various communication systems, including but not limited to: 5th generation (5G) systems, LTE systems, Long Term Evolution-Advanced (LTE-A) systems, LTE Frequency Division Duplex (FDD) systems, LTE Time Division Duplex (TDD) systems, etc. They can also be applied to future communication systems, such as 6th generation mobile communication systems. Furthermore, they can be applied to device-to-device (D2D) communication, vehicle-to-everything (V2X) communication, machine-to-machine (M2M) communication, machine-type communication (MTC), Internet of Things (IoT) communication systems, narrowband Internet of Things (NB-IoT) systems, or other communication systems. Furthermore, it can be extended to similar wireless communication systems, such as Wireless-Fidelity (WiFi), Worldwide Interoperability for Microwave Access (WIMAX), and communication systems related to the 3rd Generation Partnership Project (3GPP), without limitation.

[0085] A communication system applicable to embodiments of this application may include one or more transmitting devices and one or more receiving devices. Optionally, one of the transmitting device and the receiving device may be a terminal device, and the other may be a network device. Optionally, both the transmitting device and the receiving device may be terminal devices. Optionally, both the transmitting device and the receiving device may be network devices. Exemplarily, the transmitting device may be an encoding device, and the receiving device may be a decoding device.

[0086] Figure 1 is a schematic diagram of a network architecture applicable to an embodiment of this application. As shown in Figure 1, the embodiments of this application can be applied to both uplink and downlink data transmission. Figure 1 only uses uplink or downlink data transmission between one network device and two terminal devices (such as terminal device 1 and terminal device 2) as an example. In uplink data transmission, the sending device is the terminal device and the receiving device is the network device; conversely, in downlink data transmission, the sending device is the network device and the receiving device is the terminal device. Furthermore, the applicability of the embodiments of this application in other communication scenarios is not limited; for example, they can also be applied to sidelink communication.

[0087] The terminal equipment in this application can also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, mobile terminal (MT), remote station, remote terminal, mobile device, user terminal, terminal, drone, wireless communication equipment, user agent, or user device, etc. The terminal equipment in the embodiments of this application can be a device that provides voice and / or data connectivity to a user, and can be used to connect people, objects, and machines, such as handheld devices with wireless connectivity, vehicle-mounted devices, etc. The terminal devices in the embodiments of this application may be mobile phones, tablets, laptops, handheld computers, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, etc.

[0088] The network equipment in this application can be a device with wireless transceiver capabilities, which can be a device that provides wireless communication services. It is usually located on the network side, including but not limited to next-generation base stations (gNodeB, gNB) in 5G systems, base stations in sixth-generation mobile communication systems, base stations in future mobile communication systems, or access nodes in wireless fidelity (WiFi) systems, evolved node B (eNB), radio network controller (RNC), node B (NB), base station controller (BSC), home base station (e.g., home evolved NodeB or home Node B, HNB), base band unit (BBU), transmission reception point (TRP), transmitting point (TP), base transceiver station (BTS), satellites, drones, etc. in long term evolution (LTE) systems. In a network architecture, network equipment may include centralized unit (CU) nodes, distributed unit (DU) nodes, RAN equipment including CU and DU nodes, RAN equipment including control plane CU nodes, user plane CU nodes, and DU nodes, or, in a cloud radio access network (CRAN) scenario, wireless controllers, relay stations, vehicle-mounted equipment, and wearable devices. Furthermore, a base station may be a macro base station, micro base station, relay node, donor node, or a combination thereof. A base station may also refer to a communication module, modem, or chip installed within the aforementioned equipment or apparatus. A base station may also be a mobile switching center and equipment performing base station functions in D2D, V2X, and M2M communications, or equipment performing base station functions in future communication systems. A base station can support networks using the same or different access technologies, without limitation.

[0089] Unless otherwise specified, the means for implementing the functions of a terminal device or network device in this application can refer to the terminal device or network device itself, or it can refer to a means that enables the terminal device or network device to implement the functions, such as a chip system or chip, specifically a system-on-a-chip (SoC) or a modem. This means can be installed in the terminal device or network device. In the embodiments of this application, the chip system can be composed of chips, or it can include chips and other discrete devices.

[0090] For example, some embodiments in this document use a 5G system as an example to illustrate specific solution details. When this solution is used in other communication systems, such as LTE systems or future communication systems, the messages, channels, or information in the solution can be replaced with messages, channels, or information in other communication systems that can achieve the corresponding functions, and this application does not limit this.

[0091] Furthermore, the embodiments of this application can be applied to various application scenarios, such as high-throughput scenarios, high-reliability scenarios, low-latency scenarios, high-reliability low-latency scenarios, or low-power scenarios. Among them, high-throughput scenarios can be, for example, enhanced mobile broadband (eMBB) scenarios, high-reliability low-latency scenarios can be, for example, URLLC (ultra-reliable low-latency communication) scenarios, and low-power scenarios can be, for example, M2M scenarios, MTC scenarios, or IoT scenarios.

[0092] To facilitate understanding of the embodiments of this application, several concepts or terms involved in the embodiments of this application are briefly described. The concepts or terms described below are based on the concepts or terms specified in the agreement, but do not mean that the embodiments of this application can only be applied to existing systems. The concepts or terms involved in the embodiments of this application can be applied to future systems. Furthermore, the specific names of the concepts or terms (e.g., concepts or terms involving functional descriptions) can be adjusted as the system develops in the future.

[0093] 1. LDPC code

[0094] LDPC codes are a type of linear block code. A linear block code divides the information sequence to be encoded into groups of q bits each. The encoder then performs linear operations on these q information bits to obtain m parity bits. These q information bits are then combined with the m parity bits to obtain a codeword of length n = q + m. The mapping from q information bits to an n-bit codeword is typically represented by a corresponding parity check matrix H. Based on the parity check matrix H, a codeword sequence can be generated to complete the encoding process. After the codeword sequence is transmitted through the channel, a decoding device decodes the received signal to determine the original information bits.

[0095] The parity-check matrix H of an LDPC is a sparse matrix. The number of zero elements in the parity-check matrix H is far greater than the number of non-zero elements; in other words, the row weight (or column weight) of the parity-check matrix is ​​far less than the number of elements in each row (or column) of the LDPC matrix. Specifically, an LDPC code with an information bit length of q and a code length of n can be uniquely determined by its parity-check matrix H.

[0096] In 1981, Tanner represented the parity-check matrix H graphically, and this type of graph is now called a Tanner graph. There is a one-to-one correspondence between the Tanner graph and the parity-check matrix. A Tanner graph consists of two types of vertices: one type represents codeword bits and is called variable nodes, and the other type consists of parity nodes, representing parity constraints. Each parity node represents a parity constraint, which will be explained below with reference to Figures 2 and 3.

[0097] Figure 2 is a schematic diagram of the parity check matrix H of an LDPC.

[0098] In Figure 2, {V i} represents the set of variable nodes (VN), {C i} represents the set of check nodes (CNs). Each row of the check matrix H represents a check equation, and each check equation corresponds to a check node. Each column represents a codeword bit, and each codeword bit corresponds to a variable node. In Figure 2, there are 8 variable nodes and 4 check nodes. If a codeword bit is included in the corresponding check equation, a line is used to connect the involved variable nodes and check nodes to obtain the Tanner graph.

[0099] Figure 3 is a Tanner plot of the parity-check matrix H of an LDPC.

[0100] As shown in Figure 3, the Tanner graph represents the parity-check matrix of the LDPC. For example, for a parity-check matrix H of size m rows and n columns, the Tanner graph contains two types of nodes: n variable nodes and m parity nodes. The n variable nodes correspond to the n columns of the parity-check matrix H, and the m parity nodes correspond to the m rows of the parity-check matrix H. A cycle in the Tanner graph is composed of interconnected vertices, with one vertex serving as both the start and end point of the cycle, and each node is visited only once. The variable nodes in the Tanner graph correspond to each column of the parity-check matrix H, which is equivalent to each codeword bit in the LDPC. The parity nodes in the Tanner graph correspond to each row of the parity-check matrix H, which is equivalent to the parity bit in the LDPC. The connection between the two types of nodes corresponds to the value of an element in the H matrix. If there is a connection between the i-th parity node and the j-th variable node, the element (i, j) in the H matrix has a value of 1; otherwise, the corresponding element is 0. The connection between variable nodes and parity nodes can also be called an edge. The existence of a connection between the validation node and the variable node can also be described as: the validation node and the variable node are connected or have an edge. The connection between the validation node and the variable node can include either the presence of an edge or the absence of an edge.

[0101] 2. Quasi-cyclic low-density parity check (QC-LDPC) code

[0102] QC-LDPC codes are a type of structured LDPC codes. Due to the unique structure of their parity-check matrix, encoding can be implemented using a simple feedback shift register, reducing the encoding complexity of LDPC codes. In practice, QC-LDPC codes are represented using a base grape (BG), where elements are either 0 or 1. Expanding the 1s and 0s in the BG yields a parity-check matrix H, which can be used for encoding or decoding. In the embodiments of this application, the BG can be written in matrix form, referred to as the base matrix H in this application. BG Basis matrix H BG An element of 0 indicates that there are no edges in the base graph, while a value of 1 indicates that there are edges in the base graph (or that the corresponding check is associated with the corresponding variable). NR LDPC codes involve multiple base graph selection; currently, the standard stores two base graphs, BG1 and BG2. BG2 is used when the information length is less than or equal to 292, or when the information length is less than or equal to 3824 and the code rate is less than or equal to 2 / 3, or when the code rate is less than or equal to 0.25; otherwise, BG1 is used. The following section discusses the base matrix H. BG The expansion process is described.

[0103] Based on the basis matrix H BGAnd by increasing the lifting size Zc, the basis matrix H can be... BG The matrix is ​​expanded into a complete parity-check matrix for encoding or decoding. In this application, Zc can also be referred to as the expansion factor, boosting factor, expansion value, expansion coefficient, boosting size, etc. The expansion process involves boosting all elements of the base matrix into a Zc*Zc square matrix. Specifically, 0 is boosted to a Zc*Zc zero matrix, and 1 is boosted to a Zc*Zc identity matrix. This identity matrix is ​​then cyclically shifted based on the shifting value (SV) corresponding to 1. This cyclic shift can be left or right, and this application does not limit this. It can be understood that each 1 in the base matrix corresponds to a shifting value. For example, boosting 1 to a 4×4 identity matrix with shifting values ​​of 0, 1, 2, and 3, and a cyclic shift to the right, is illustrated below:

[0104] (1) When the translation value is 0 (i.e., remains unchanged), the matrix after right circular shift is:

[0105] (2) When the translation value is 1, the matrix after the right circular shift is:

[0106] (3) When the translation value is 2, the matrix after the right circular shift is:

[0107] (4) When the translation value is 3, the matrix after the right circular shift is:

[0108] Alternatively, it can be understood that the complete parity check matrix H can be derived from an exponential matrix H. b H indicates b Each element in the matrix corresponds to a Zc*Zc submatrix, and each element value indicates the number of times the corresponding submatrix has been cyclically shifted by the identity matrix. Therefore, the storage space required for the complete parity check matrix H is greatly reduced. (Exponential matrix H) b The elements in it can also be called QC blocks.

[0109] For example, the exponent matrix H of the QC-LDPC code b As shown below:

[0110] It can be seen that the exponent matrix H b The size is 4 rows and 24 columns, and the exponent matrix H b Each element i in the matrix represents a square matrix of order Z. Let represent a cyclic shift matrix, where i represents the cyclic shift value of the cyclic shift matrix, and i is an integer. Additionally, the exponent matrix H... b In this context, "-1" represents a zero matrix and "0" represents the identity matrix.

[0111] For example, As shown below:

[0112] Optional, exponent matrix H b In addition to "-1", zero elements in the matrix can also be represented in other ways, such as using "-" or null values ​​to represent a matrix of all zeros.

[0113] It is understandable that the above exponent matrix H b The matrix corresponding to the positions greater than or equal to 0 that are changed to 1 and the positions of -1 that are changed to 0 is the base matrix. The 1s in the base matrix are then expanded into a cyclic shift matrix based on the corresponding elements of the exponent matrix, and the 0s are expanded into a 0 matrix of the corresponding size. After expansion, the parity check matrix is ​​obtained.

[0114] 3. Non-zero elements and zero elements

[0115] In this application, zero elements in the check matrix indicate that there is no connection between the variable node and the check node. Non-zero elements in the check matrix indicate that there is a connection between the variable node and the check node.

[0116] This application does not limit the specific representation of zero and non-zero elements. For example, in the exponential matrix H b In a matrix, "-1" can be used to represent zero elements, and "non-negative value" can be used to represent non-zero elements. Similarly, in a parity check matrix H, "0" can be used to represent zero elements, and "1" can be used to represent non-zero elements.

[0117] For ease of description, the LDPC basis matrix below uses "0" to represent zero elements and "1" to represent non-zero elements.

[0118] 4. Basic Structure of Basis Matrices

[0119] As shown in Figure 4(a), the base matrix can include a high-rate region, an all-zero region, an incremental redundancy region, and a raptor-like region. The high-rate region can include parts A and B as shown in Figure 4(b), where part A corresponds to information bits (or information digits, etc.), and part B is a square matrix corresponding to the core parity bits (or core parity digits). Part B can also be the region corresponding to parity columns with column weights greater than 1 in the high-rate region. The all-zero region can correspond to part C in Figure 4(b) and is an all-zero matrix. The incremental redundancy region can correspond to part D in Figure 4(b). The raptor-like region can correspond to part E in Figure 4(b) and can be an identity matrix or a lower triangular matrix, corresponding to the parity bits of the low-rate extension.

[0120] The LDPC code base matrix shown in Figure 4 adopts a "raptor-like" structure, which can be gradually extended from a high-rate kernel matrix to a low-rate matrix, thus flexibly supporting encoding at various code rates. In practical use, as shown in Figure 4(a), the first X rows and the first Y columns of the base matrix can be extracted. As the code rate decreases, X and Y gradually increase, and the area of ​​the matrix used also gradually expands. The difference between X and Y represents the number of information columns.

[0121] The LDPC basis matrix truncated at any bit rate can be represented by a parity-check matrix H, which can also be represented by an exponent matrix H. b Therefore, the structure of the LDPC basis matrix, the structure of the parity-check matrix H, and the structure of the exponent matrix H are related. b The structure is similar, and will not be elaborated here.

[0122] 5. Core matrix, core rows, core columns

[0123] Core line: This is the line corresponding to the core check bit. In other words, the core line is the line corresponding to the high bitrate region, or the line corresponding to part A, or the line corresponding to part B.

[0124] Core columns: These can include all information columns and all core check columns. In other words, core columns are the columns corresponding to high bitrate areas, or the columns corresponding to part A plus part B.

[0125] The kernel matrix is ​​the portion consisting of all the kernel rows and columns of the LDPC base matrix or LDPC parity-check matrix. In other words, the kernel matrix is ​​the high-bitrate region of the LDPC base matrix or LDPC parity-check matrix, or a matrix composed of part A and part B.

[0126] 6. Extended columns, non-extended columns, extended rows, and non-extended rows

[0127] For LDPC codes, each additional extension node adds one row and one column to the actual matrix used. In this application, these added row and column are referred to as extension columns and extension rows, respectively. Extension columns are the columns corresponding to the extension nodes; in other words, extension columns correspond to the extended parity bits. Columns other than extension columns are non-extension columns. Rows other than extension rows are non-extension rows. Taking Figure 4 as an example, columns C and E are extension columns, and rows D and E are extension rows.

[0128] As mentioned above, based on the basis matrix H BG And by increasing the lifting size Zc, the basis matrix H can be... BG This is expanded into a complete parity-check matrix H. Currently, the standard storage uses two basis maps, BG1 and BG2, where BG1 is 46*68 in size. The basis matrix H is extracted from BG1 based on a certain code rate. BG The size is denoted as X*Y, and the basis matrix H BG Rows 1 through 4 are the core rows and the base matrix H. BG Rows 5 through X are the extended rows and the base matrix H. BG Columns 1 through 22 are information columns and the basis matrix H. BG Columns 23 to 26 are the core check columns and the base matrix H. BG Columns 27 through Y are extended check columns. Based on this base matrix H BG The extended parity-check matrix H has the following columns: rows 1 to 4*Zc are the core rows; rows 4*Zc+1 to X*Zc are the extended rows; columns 1 to 22*Zc are the information columns; columns 22*Zc+1 to 26*Zc are the core parity columns; and columns 26*Zc+1 to Y*Zc are the extended parity columns. This is equivalent to the base matrix H. BG The rows after the expansion of the core rows can still be called the core rows of the parity check matrix, the basis matrix H. BG The rows after the expansion can still be called the expanded rows of the parity-check matrix, the basis matrix H. BG The expanded columns of the information column can still be called the information column of the parity check matrix, or the basis matrix H. BG The columns after the core check column is expanded can still be called the information columns of the check matrix, the basis matrix H. BGThe extended parity columns, after being extended, can still be called the extended parity columns of the parity matrix. The base matrix H... BG It may also be possible to first expand it into other basis matrices (denoted as BG0), and then expand it again into a complete parity-check matrix, for example, basis matrix H. BG The extension process to BG0 involves changing the basis matrix H. BG Each element in BG0 is promoted to a k*k matrix. Rows 1 to 4*k of BG0 are the core rows, rows 4*k+1 to X*k are the extended rows, columns 1 to 22*k are the information columns, columns 22*k+1 to 26*k are the core verification columns, and columns 26*k+1 to Y*k are the extended verification columns. For example, k can be equal to 2.

[0129] Similarly, BG2 has a size of 42*52, and the basis matrix H is truncated from BG2 based on a certain code rate. BG The size is denoted as X*Y, and the basis matrix H BG Rows 1 through 4 are the core rows and the base matrix H. BG Rows 5 through X are the extended rows and the base matrix H. BG Columns 1 through 10 are information columns and the basis matrix H. BG Columns 11 through 14 are the core check columns and the base matrix H. BG Columns 15 through Y are extended check columns. Based on this base matrix H BG The extended parity-check matrix H has the following columns: rows 1 to 4*Zc (core rows), rows 4*Zc+1 to X*Zc (extension rows), columns 1 to 10*Zc (information columns), columns 10*Zc+1 to 14*Zc (core parity columns), and columns 14*Zc+1 to Y*Zc (extension parity columns). This is equivalent to the base matrix H. BG The rows after the expansion of the core rows can still be called the core rows of the parity-check matrix, the basis matrix H. BG The rows after the expansion can still be called the expanded rows of the parity-check matrix, the basis matrix H. BG The expanded columns of the information column can still be called the information column of the parity check matrix, or the basis matrix H. BG The columns after the core check column is expanded can still be called the information columns of the check matrix, the basis matrix H. BG The extended parity columns, even after expansion, can still be called extended parity columns of the parity matrix. The base matrix H... BG It may also be possible to first expand it into other basis matrices (denoted as BG0), and then expand it again into a complete parity-check matrix, for example, basis matrix H. BG The extension process to BG0 involves changing the basis matrix H. BGEach element in BG0 is promoted to a k*k matrix. Rows 1 to 4*k of BG0 are the core rows, rows 4*k+1 to X*k are the extended rows, columns 1 to 10*k are the information columns, columns 10*k+1 to 14*k are the core verification columns, and columns 14*k+1 to Y*k are the extended verification columns. For example, k can be equal to 2.

[0130] Furthermore, in this application, the portion consisting of non-extended columns can also be called the core portion, and the portion consisting of extended columns can also be called the extended portion. Taking Figure 4 as an example, the portion consisting of A, B, and D is the core portion, and the portion consisting of C and E is the extended portion.

[0131] 7. Drilling Column

[0132] In LDPC codes, bits corresponding to punctured columns are not transmitted. Punctured columns can be either information columns or parity columns. Furthermore, columns in LDPC codes that are not punctured are also called non-punctured columns. Similarly, non-punctured columns can be either information columns or parity columns.

[0133] Generally, the punched columns for BG1 and BG2 are column 1 and column 2, respectively.

[0134] 8. Message length, code length, and code rate

[0135] The information length is the length of the information bits to be encoded (i.e., the number of bits contained). This length can be the length of the payload information bits, or the length of the payload information bits after adding cyclic redundancy check (CRC) bits. This application does not impose any specific restrictions.

[0136] Code length refers to the length of the bit sequence to be transmitted, which can be the transmitted bit sequence corresponding to the modulated symbol.

[0137] Bitrate refers to the ratio of information length to bit length.

[0138] Optionally, the above three values ​​can be pre-configured by higher-layer signaling, medium access control (MAC) layer, or downlink physical layer signals, or they can be directly obtained and calculated by the transceiver. For example, the code length can be determined by the frame structure, number of layers, and modulation scheme of the encoded and transmitted bit sequence; the code rate can be indicated in the above manner or given in the modulation and coding scheme (MCS) table.

[0139] 9. Information Transmission Process

[0140] Figure 5 is a schematic diagram of the information transmission process applicable to this application. As shown in Figure 5, information is sent from the source, undergoes source coding, channel coding, modulation, air interface transmission, demodulation, channel decoding, and source recovery, and finally reaches the destination, completing the transmission of information from the source to the destination. The processing shown in the upper layer of Figure 5 (including source coding, channel coding, and modulation) is performed at the coding device, while the processing shown in the lower layer (including demodulation, channel decoding, and source recovery) is performed at the decoding device. The embodiments of this application mainly involve the source coding, channel coding, channel decoding, and source recovery shown in Figure 5.

[0141] Current LDPC codes still suffer from slow decoding convergence speed and high decoding iteration count in high-throughput scenarios. In view of this, this application proposes an encoding and decoding method that can increase the convergence speed of LDPC codes in high-throughput scenarios and guarantee error correction performance with a low number of iterations.

[0142] Figure 6 is a schematic flowchart of an encoding method 600 provided in this application. The encoding method 600 includes the following steps.

[0143] It is understood that method 600 can be executed by the sending device. Unless otherwise specified, "sending device" can refer to the sending device itself or a device that enables the sending device to perform this function. For ease of description, the term "sending device" will be used uniformly below. The sending device can be a terminal device or a network device.

[0144] S610, the transmitting device performs LDPC encoding on the information bits to be encoded based on the first parity check matrix to obtain the first codeword sequence.

[0145] For example, the information bits to be encoded can be a source-encoded sequence of information bits.

[0146] Specifically, the first codeword sequence mentioned above includes an information bit sequence and a first check bit sequence.

[0147] Specifically, the first parity check matrix is ​​generated based on the first base matrix. For example, each non-zero element in the first base matrix is ​​first promoted to a Zc*Zc identity matrix in the first parity check matrix, and then the identity matrix is ​​cyclically shifted according to the translation value corresponding to each non-zero element in the first base matrix; each zero element in the first base matrix is ​​promoted to a Zc*Zc zero matrix in the first parity check matrix.

[0148] S620, the transmitting device maps the first parity bit sequence to the second parity bit sequence.

[0149] Specifically, the first parity bit sequence consists of A parity bit sequences, where the length of the i-th parity bit sequence in the A-sequence is k. i *Zc; The second parity bit sequence consists of a B-segment parity bit sequence.

[0150] Among them, A, B, k i It can be any positive integer; this application does not impose any restrictions on it.

[0151] For example, the mapping of the first parity bit sequence to the second parity bit sequence can be: any segment of the parity bit sequence in segment B is obtained based on at least one segment of the parity bit sequence in segment A.

[0152] In one example, the parity bit sequence B may include a parity bit sequence #1B, which is determined based on parity bit sequences #1A and #2A. For instance, this parity bit sequence #1B is obtained by performing an XOR operation on parity bit sequences #1A and #2A.

[0153] Among them, the parity bit sequence #1A is a parity bit sequence in the above-mentioned parity bit sequence A, or the parity bit sequence #1A is obtained by cyclic shifting a parity bit sequence in the parity bit sequence A; the parity bit sequence #2A is another parity bit sequence in the parity bit sequence A, or the parity bit sequence #2A is obtained by cyclic shifting another parity bit sequence in the parity bit sequence A.

[0154] In other words, two parity bit sequences in parity bit sequence A can be mapped to one parity bit sequence in parity bit sequence B.

[0155] Alternatively, the B segment parity bit sequence may contain multiple parity bit sequences, each of which is derived from two parity bit sequences in the A segment parity bit sequence.

[0156] In another example, the B segment of the parity bit sequence may also include a parity bit sequence #2B, which is determined based on parity bit sequences #3A, #4A, and #5A. For instance, this parity bit sequence #2B is obtained by performing an XOR operation on parity bit sequences #3A, #4A, and #5A.

[0157] Wherein, the parity bit sequence #3A is a parity bit sequence within segment A of the parity bit sequence, or parity bit sequence #3A is obtained by cyclic shifting a parity bit sequence within segment A of the parity bit sequence, and / or, parity bit sequence #4A is another parity bit sequence within segment A of the parity bit sequence, or parity bit sequence #4A is obtained by cyclic shifting another parity bit sequence within segment A of the parity bit sequence, and / or, parity bit sequence #5A is yet another parity bit sequence within segment A of the parity bit sequence, or parity bit sequence #5A is obtained by cyclic shifting yet another parity bit sequence within segment A of the parity bit sequence.

[0158] The other parity bit sequence in the above A-segment parity bit sequence is different from one of the parity bit sequences in the above A-segment parity bit sequence, and yet another parity bit sequence in the above A-segment parity bit sequence is different from another parity bit sequence in the above A-segment parity bit sequence. That is, the above parity bit sequence #3A, parity bit sequence #4A and parity bit sequence #5A are three different parity bit sequences in the above A-segment parity bit sequence.

[0159] In other words, the three parity bit sequences in parity bit sequence A can be mapped to one parity bit sequence in parity bit sequence B.

[0160] Alternatively, the B segment parity bit sequence may contain multiple parity bit sequences, each of which is derived from the three parity bit sequences in the A segment parity bit sequence.

[0161] In another example, any number of other parity bit sequences in the parity bit sequence A can be mapped to a parity bit sequence in the parity bit sequence B, and this application does not limit this.

[0162] Alternatively, the B segment parity bit sequence may contain multiple parity bit sequences, each of which is obtained based on the parity bit sequences of any number of other segments in the A segment parity bit sequence.

[0163] Alternatively, the parity bit sequence in segment B may contain one or more parity bit sequences, where one parity bit sequence is a parity bit sequence in segment A, or the multiple parity bit sequences are multiple parity bit sequences in segment A. In other words, one or more parity bit sequences in segment A may not participate in the XOR operation.

[0164] Specifically, the aforementioned first parity bit sequence includes a first core parity bit sequence, which consists of the parity bits corresponding to all core rows of the first parity matrix. In other words, the aforementioned A-segment parity bit sequence includes C-segment core parity bit sequences, where the length of each segment in the C-segment core parity bit sequence is Zc, and C is any positive integer less than A.

[0165] Optionally, the aforementioned first parity bit sequence may further include a first extended parity bit sequence, which is the parity bit corresponding to the extended row of the first parity matrix. In other words, the aforementioned A-segment parity bit sequence also includes D-segment extended parity bit sequences, where the length of each segment of the D-segment extended parity bit sequence is Zc, and D is a positive integer less than A.

[0166] For example, the transmitting device may map part or all of the first core check bit sequence to obtain the second check bit sequence. Alternatively, the transmitting device may map part or all of the first extended check bit sequence to obtain the second check bit sequence. Alternatively, the transmitting device may map part or all of the first core check bit sequence and part or all of the first extended check bit sequence to obtain the second check bit sequence; this application does not limit this approach.

[0167] The mapping process described above will be illustrated in detail below. In this illustration, the length of the information bits to be encoded can be denoted as K, the length of the first codeword sequence as N, the number of punctured columns in the first basis matrix as punc, and the length of the information padding bits as s. For example, the value of punc can be 0, 1, 2, etc., and the first codeword sequence is [d0, d1, d2, ..., d...]. N-1 The first codeword sequence [d0, d1, d2, ..., d] N-1 The information bit sequence in the image is [d0, d1, d2, ..., dK-punc*k*Zc-1], and the first check bit sequence is [dK-punc*k*Zc, d...]. K- punc*k*Zc+1、...、d N-1 ].

[0168] In this embodiment of the application, the first codeword sequence may include k in the form of... i *Zc codeword bits are denoted as D j Then the first codeword sequence can also be denoted as [D1, D2, D3, ..., D...]. (N+punc*Zc-1) / Zc ]. Among them, D j [d(j-1-punc)*Zc-s, d(j-1-punc)*Zc-s+1, ..., d(j-punc)*Zc-s-1].

[0169] For example, D1 = k1*Zc, D2 = k2*Zc, D3 = k3*Zc, ... k1, k2, k3... can be equal or unequal; this application does not limit this. i It can be equal to 1 / 2, 1, 2, 3, etc.

[0170] For example, the above-mentioned A-segment check bit sequence may include at least two check bit sequences of different lengths.

[0171] For example, the length of each parity bit sequence in the above A-segment parity bit sequence is k*Zc, where k is any positive integer.

[0172] For example, if the first basis matrix involved in this application is obtained by expanding each element in BG1 or BG2 into a k*k matrix, the value of k can be obtained accordingly.

[0173] Figure 7 shows a schematic diagram of an example of mapping the first core check bit sequence.

[0174] The parity bit sequence for segment A shown in Figure 7 is [D 45 D 46 D 47 D 48 D 49 D 50 D 51 D 52...... The first core check bit sequence is the first to eighth check bit sequences in segment A of the check bit sequence, and this first core check bit sequence is [D]. 45 D 46 D 47 D 48 D 49 D 50 D 51 D 52 ].

[0175] For example, the first parity bit sequence D in segment A of the parity bit sequence. 45 With the second parity bit sequence D 46 Performing an XOR operation yields the first sequence (as shown in Figure 7, D). 45 +D 46 For example, D 45 =[101110111010...1101]、D 46 =[100100101110...1011], D 45 The first codeword bit "1" and D 46The first codeword bit "1" is XORed to obtain the first codeword bit "0" of the first sequence, D. 45 The second codeword bit "0" and D 46 The second codeword bit "0" is XORed to obtain the second codeword bit "0", ..., D of the first sequence. 45 The last codeword bit "1" and D 46 The last codeword bit "1" is XORed with the first codeword bit "0" to obtain the last codeword bit "0" of the first sequence, thus obtaining the first sequence D. 45 +D 46 = [001010010100...0110]; The third parity bit sequence D in segment A of the parity bit sequence. 47 With the 4th parity bit sequence D 48 Performing an XOR operation yields the second sequence (as shown in Figure 7, D). 47 +D 48 ), D 47 With D 48 The way to perform XOR operation and D 45 With D 46 The method of performing the XOR operation is similar and will not be described in detail here; the 5th parity bit sequence D in segment A of the parity bit sequence. 49 With the 6th parity bit sequence D 50 Performing an XOR operation yields the third sequence (as shown in Figure 7, D). 49 +D 50 ), D 49 With D 50 The way to perform XOR operation and D 45 With D 46 The method for performing the XOR operation is similar and will not be elaborated here; the 7th parity bit sequence D in segment A of the parity bit sequence. 51 With the 8th parity bit sequence D 52 Performing the XOR operation yields the fourth sequence (as shown in Figure 7, D). 51 +D 52 ), D 51 With D 52 The way to perform XOR operation and D 45 With D 46 The method for performing the XOR operation is similar and will not be elaborated here.

[0176] Optionally, the first sequence mentioned above can also be the first parity bit sequence D based on the parity bit sequence A. 45 D' is obtained through cyclic shifting. 45 The second parity bit sequence D in the parity bit sequence A 46 The result obtained by performing an XOR operation, assuming D 45= [x1, x2, ... xZc], then D 45 D' obtained after looping 1 bit 45 =[x2,...xZc,x1]、D 45 D' obtained after looping 2 positions 45 =[x3,...,x1,x2]、...、D 45 D' obtained after cyclic Zc bits 45 = [x1, x2, ... xZc], this application does not limit the number of cyclic bits in the parity bit sequence. Other parity bit sequences are cyclically shifted in the same way as D. 45 The method for performing cyclic shifts is similar and will not be elaborated upon below.

[0177] Optionally, the first sequence mentioned above can also be the first parity bit sequence D based on the parity bit sequence A. 45 With the second parity bit sequence D 46 D' obtained through cyclic shifting 46 The result obtained by performing an XOR operation.

[0178] Optionally, the first sequence mentioned above can also be the first parity bit sequence D based on the parity bit sequence A. 45 D' obtained through cyclic shifting 45 With the second parity bit sequence D 46 D' obtained through cyclic shifting 46 The result obtained by performing an XOR operation.

[0179] The second, third, or fourth sequence described above can also be determined in a similar manner to the first sequence, which will not be elaborated here. For example, the second sequence described above can also be based on the third parity bit sequence D in the parity bit sequence A. 47 D' is obtained through cyclic shifting. 47 The fourth parity bit sequence D in the parity bit sequence of segment A. 48 The result obtained by performing an XOR operation, or alternatively, the second sequence described above could also be based on the third parity bit sequence D in the parity bit sequence A. 47 With the 4th parity bit sequence D 48 D' obtained through cyclic shifting 48 The result obtained by performing an XOR operation, or alternatively, the second sequence described above could also be based on the third parity bit sequence D in the parity bit sequence A. 47 D' obtained through cyclic shifting 45 With the 4th parity bit sequence D 48 D' obtained through cyclic shifting 48 The result obtained by performing an XOR operation.

[0180] Example 1: The B segment check bit sequence consists of the first sequence, the second sequence, the third sequence, and the fourth sequence mentioned above.

[0181] For example, the first parity bit sequence of segment B is the first sequence, the second parity bit sequence is the second sequence, the third parity bit sequence is the third sequence, and the fourth parity bit sequence is the fourth sequence.

[0182] Alternatively, the first parity bit sequence of the B-segment parity bit sequence may be any sequence among the first, second, third, and fourth sequences mentioned above; the second parity bit sequence of the B-segment parity bit sequence may be any sequence among the first, second, third, and fourth sequences except for the first parity bit sequence; the third parity bit sequence of the B-segment parity bit sequence may be any sequence among the first, second, third, and fourth sequences except for the first and second parity bit sequences; and the fourth parity bit sequence of the B-segment parity bit sequence may be the remaining sequence among the first, second, third, and fourth sequences except for the first, second, and third parity bit sequences. This application does not impose any limitations on this.

[0183] Optionally, the second parity bit sequence and the fourth parity bit sequence in segment A are XORed to obtain the fifth sequence (as shown in Figure 7, D). 46 +D 48 ), D 46 With D 48 The way to perform XOR operation and D 45 With D 46 The method for performing the XOR operation is similar and will not be elaborated here.

[0184] The fifth sequence mentioned above can also be determined in a similar way to the first sequence mentioned above, which will not be elaborated here.

[0185] Example 2: The B segment check bit sequence consists of the first sequence, the second sequence, the third sequence, the fourth sequence, and the fifth sequence mentioned above.

[0186] For example, the first parity bit sequence of segment B is the first sequence, the second parity bit sequence is the second sequence, the third parity bit sequence is the third sequence, the fourth parity bit sequence is the fourth sequence, and the fifth parity bit sequence is the fifth sequence.

[0187] Alternatively, the first parity bit sequence of the B-segment parity bit sequence can be any sequence among the first, second, third, fourth, and fifth sequences mentioned above; the second parity bit sequence of the B-segment parity bit sequence can be any sequence among the first, second, third, fourth, and fifth sequences except for the first parity bit sequence; and the third parity bit sequence of the B-segment parity bit sequence can be any sequence among the first, second, third, fourth, and fifth sequences except for the first and second parity bit sequences. The fourth parity bit sequence of the B-segment parity bit sequence is any sequence other than the first, second, third, fourth, and fifth sequences mentioned above, excluding the first, second, and third parity bit sequences. The fifth parity bit sequence of the B-segment parity bit sequence is the remaining sequence other than the first, second, third, fourth, and fourth parity bit sequences mentioned above. This application does not limit this.

[0188] Optionally, the sixth parity bit sequence in segment A is XORed with the eighth parity bit sequence to obtain the sixth sequence (as shown in Figure 7, D). 50 +D 52 ), D 50 With D 52 The way to perform XOR operation and D 45 With D 46 The method for performing the XOR operation is similar and will not be elaborated here.

[0189] The sixth sequence mentioned above can also be determined in a similar way to the first sequence mentioned above, which will not be elaborated here.

[0190] Example 3: The B segment check bit sequence consists of the first sequence, the second sequence, the third sequence, the fourth sequence, the fifth sequence, and the sixth sequence mentioned above.

[0191] For example, the first parity bit sequence of segment B is the first sequence, the second parity bit sequence is the second sequence, the third parity bit sequence is the third sequence, the fourth parity bit sequence is the fourth sequence, the fifth parity bit sequence is the fifth sequence, and the sixth parity bit sequence is the sixth sequence.

[0192] Alternatively, the first parity bit sequence of the B-segment parity bit sequence can be any sequence among the first, second, third, fourth, fifth, and sixth sequences mentioned above; the second parity bit sequence of the B-segment parity bit sequence can be any sequence among the first, second, third, fourth, fifth, and sixth sequences except for the first parity bit sequence; the third parity bit sequence of the B-segment parity bit sequence can be any sequence among the first, second, third, fourth, fifth, and sixth sequences except for the first and second parity bit sequences; and the fourth parity bit sequence of the B-segment parity bit sequence can be any sequence among the first, second, third, fourth, fifth, and sixth sequences except for the first and second parity bit sequences. The fifth sequence and the sixth sequence mentioned above are any sequences other than the first, second, and third parity bit sequences. The fifth parity bit sequence of the B-segment parity bit sequence is any sequence other than the first, second, third, fourth, fifth, and sixth sequences mentioned above, except for the first, second, third, and fourth parity bit sequences. The sixth parity bit sequence of the B-segment parity bit sequence is the remaining sequence other than the first, second, third, fourth, fifth, and sixth sequences mentioned above. This application does not limit this.

[0193] Optionally, the second parity bit sequence in segment A is XORed with the eighth parity bit sequence to obtain the seventh sequence (as shown in Figure 7, D). 46 +D 52 ), D 46 With D 52 The way to perform XOR operation and D 45 With D 46 The method for performing the XOR operation is similar and will not be elaborated here.

[0194] The seventh sequence mentioned above can also be determined in a similar way to the first sequence mentioned above, which will not be elaborated here.

[0195] Example 4: The B segment parity bit sequence consists of the first sequence, the second sequence, the third sequence, the fourth sequence, the fifth sequence, the sixth sequence, and the seventh sequence mentioned above.

[0196] For example, the first parity bit sequence of segment B is the first sequence, the second parity bit sequence is the second sequence, the third parity bit sequence is the third sequence, the fourth parity bit sequence is the fourth sequence, the fifth parity bit sequence is the fifth sequence, the sixth parity bit sequence is the sixth sequence, and the seventh parity bit sequence is the seventh sequence.

[0197] Alternatively, the first parity bit sequence of the B-segment parity bit sequence can be any sequence among the first, second, third, fourth, fifth, sixth, and seventh sequences mentioned above; the second parity bit sequence of the B-segment parity bit sequence can be any sequence among the first, second, third, fourth, fifth, sixth, and seventh sequences except for the first parity bit sequence; the third parity bit sequence of the B-segment parity bit sequence can be any sequence among the first, second, third, fourth, fifth, sixth, and seventh sequences except for the first and second parity bit sequences; the fourth parity bit sequence of the B-segment parity bit sequence can be any sequence among the first, second, third, fourth, fifth, sixth, and seventh sequences except for the first and second parity bit sequences; the fifth parity bit sequence of the B-segment parity bit sequence can be any sequence among the first, second, third, fourth, fifth, sixth, and seventh sequences except for the first, second, and third parity bit sequences; and the fifth parity bit sequence of the B-segment parity bit sequence can be any sequence among the first, second, third, fourth, fifth, sixth, and seventh sequences except for the first, second, and third parity bit sequences. The segment check bit sequence is any sequence other than the first, second, third, fourth, fifth, sixth, and seventh segments of the above-mentioned first, second, third, fourth, fifth, sixth, and seventh segments of the check bit sequence. The sixth segment check bit sequence of the B segment check bit sequence is any sequence other than the first, second, third, fourth, fifth, sixth, and seventh segments of the above-mentioned first, second, third, fourth, fifth, sixth, and seventh segments of the check bit sequence. The seventh segment check bit sequence of the B segment check bit sequence is the remaining sequence other than the first, second, third, fourth, fifth, sixth, and seventh segments of the check bit sequence. This application does not limit this.

[0198] Optionally, the 8th parity bit sequence in segment A is used as the 8th sequence (as shown in Figure 7, D). 52 ).

[0199] Example 5: The B segment parity bit sequence consists of the first sequence, the second sequence, the third sequence, the fourth sequence, the fifth sequence, the sixth sequence, the seventh sequence, and the eighth sequence mentioned above.

[0200] For example, the first parity bit sequence of segment B is the first sequence, the second parity bit sequence is the second sequence, the third parity bit sequence is the third sequence, the fourth parity bit sequence is the fourth sequence, the fifth parity bit sequence is the fifth sequence, the sixth parity bit sequence is the sixth sequence, the seventh parity bit sequence is the seventh sequence, and the eighth parity bit sequence is the eighth sequence.

[0201] Alternatively, the first parity bit sequence of the B-segment parity bit sequence can be any sequence among the first, second, third, fourth, fifth, sixth, seventh, and eighth sequences mentioned above; the second parity bit sequence of the B-segment parity bit sequence can be any sequence among the first, second, third, fourth, fifth, sixth, seventh, and eighth sequences except for the first parity bit sequence; and the third parity bit sequence of the B-segment parity bit sequence can be any sequence among the first, second, third, fourth, fifth, sixth, and seventh sequences mentioned above. The seventh and eighth sequences mentioned above are any sequences other than the first and second parity bit sequences. The fourth parity bit sequence of the B-segment parity bit sequence is any sequence other than the first, second, third, fourth, fifth, sixth, seventh, and eighth sequences mentioned above. The fifth parity bit sequence of the B-segment parity bit sequence is any sequence other than the first, second, third, fourth, fifth, sixth, seventh, and eighth sequences mentioned above. The sixth parity bit sequence of the B-segment parity bit sequence is any sequence other than the first, second, third, fourth, fifth, sixth, seventh, and eighth sequences mentioned above, excluding the first, second, third, fourth, and fifth parity bit sequences. The seventh parity bit sequence of the B-segment parity bit sequence is any sequence other than the first, second, third, fourth, fifth, sixth, and seventh sequences mentioned above. The eighth sequence mentioned above, excluding the first, second, third, fourth, fifth, and sixth parity bit sequences, is any sequence other than the first, second, third, fourth, fifth, sixth, seventh, and eighth sequences. The eighth parity bit sequence of the B sequence is any sequence other than the first, second, third, fourth, fifth, sixth, and seventh sequences mentioned above. This application does not limit this.

[0202] Figure 8 shows another example of mapping the first core check bit sequence.

[0203] The first, second, third, fourth, fifth, and eighth sequences shown in Figure 8 are the same as those shown in Figure 7 above. The difference between Figure 8 and Figure 7 is that the methods by which the sixth and seventh sequences are obtained in Figure 8 are different from those in Figure 7. The following only describes the differences between Figure 8 and Figure 7; for the similarities between Figure 8 and Figure 7, please refer to the corresponding content in Figure 7 above.

[0204] The sixth sequence shown in Figure 8 is the second parity bit sequence D in the parity bit sequence A. 46 D' obtained through cyclic shifting 46 The fourth parity bit sequence D in segment A of the parity bit sequence. 48 And the 8 parity bit sequences D in segment A of the parity bit sequence 52 The result obtained by performing an XOR operation, for example, D 46 =[100100101110...1011]、D 48 =[100110100111...0010]、D 52 =[000001101110...1001], D 46 After cycling through one position, we get D'. 46 =[001001011101...0111], D' 46 With D 48 First, perform an XOR operation to obtain the intermediate sequence = [101111111010...0101]. Then, AND this intermediate sequence with D. 52 Performing an XOR operation yields the sixth sequence D' 46 +D 48 +D 52 = [101110010100...1100].

[0205] The seventh sequence shown in Figure 8 is obtained by performing an XOR operation between the 6th and 8th parity bit sequences in the A-segment parity bit sequence (as shown in Figure 8, D). 50 +D 52 ).

[0206] S630, the transmitting device outputs a second codeword sequence, which includes the aforementioned information bit sequence and the aforementioned second check bit sequence.

[0207] By using the above encoding method 600, a mapping process for the parity bit sequence is added after LDPC encoding, which helps to improve the decoding performance under low iteration rounds and accelerate the convergence speed.

[0208] This application embodiment can also provide a decoding method 900 corresponding to the above-described encoding method 600. Figure 9 is a schematic flowchart of a decoding method 900 provided in this application. The decoding method 900 includes the following steps.

[0209] It is understood that method 900 can be executed by the receiving device. Unless otherwise specified, "receiving device" can refer to the receiving device itself or a device that enables the receiving device to perform this function. For ease of description, the term "receiving device" will be used uniformly below. The receiving device can be a terminal device or a network device.

[0210] S910, the receiving device acquires the sequence to be decoded.

[0211] For example, the above-mentioned sequence to be decoded may refer to the second codeword sequence output by the transmitting device and the received message at the receiving device after channel transmission.

[0212] S920, the receiving device performs LDPC decoding on the above-mentioned sequence to be decoded based on the first decoding matrix to obtain the decoded sequence.

[0213] Specifically, the first decoding sequence is obtained by merging the rows of the first base matrix.

[0214] Specifically, the first basis matrix consists of A rows, and the first decoding matrix consists of B rows.

[0215] Where A and B can be any positive integers, this application does not impose any restrictions on them.

[0216] For example, the first decoding matrix can be obtained by merging the rows of the first base matrix, where any one of the B rows is obtained by merging at least one row of the A rows.

[0217] For example, there is a row #1B in the B rows, which is obtained by performing an XOR operation on two rows in the A rows; or there is a row #2B in the B rows, which is obtained by performing an XOR operation on three rows in the A rows; or there are rows in the B rows obtained by performing an XOR operation on any number of other rows in the A rows. This application does not limit this.

[0218] Alternatively, there may be multiple rows in the B rows that are obtained by performing an XOR operation on two rows in the A rows, or multiple rows that are obtained by performing an XOR operation on three rows in the A rows, or multiple rows that are obtained by performing an XOR operation on any other number of rows in the A rows. This application does not limit the scope of these multiple rows.

[0219] Alternatively, there may be one or more rows in the B rows. The one row can be a single row from the A rows, or the multiple rows can be multiple rows from the A rows. In other words, one or more rows in the A rows may not participate in the XOR operation.

[0220] Specifically, the rows of the first basis matrix mentioned above include the core rows of the first basis matrix. In other words, the A rows mentioned above include C core rows, where C is any positive integer less than A.

[0221] Optionally, the rows of the first base matrix may also include extended rows of the first base matrix. In other words, the A rows may also include D extended rows, where D is a positive integer less than A.

[0222] For example, the receiving device may merge some or all rows of the core row of the first base matrix to obtain the first decoding matrix. Alternatively, the receiving device may merge some or all rows of the extended row of the first base matrix to obtain the first decoding matrix. Alternatively, the receiving device may merge some or all rows of the core row of the first base matrix and some or all rows of the extended row of the first base matrix to obtain the first decoding matrix; this application does not limit this approach.

[0223] Figure 10 shows a schematic diagram of an example first basis matrix. The first basis matrix shown in Figure 10 may be a partial content extracted from the complete first basis matrix, or the actual first basis matrix used may be extracted from the first basis matrix shown in Figure 10. This application does not limit this. Figure 10 shows the contents of rows 1 to 46 and columns 1 to 52 of the first basis matrix. Rows 1 to 8 of the first basis matrix shown in Figure 10 are core rows, rows 9 to 46 are extended rows, columns 1 to 44 are information columns, and columns 45 to 52 are core verification columns.

[0224] Figure 11 shows the exponential matrix corresponding to the first basis matrix shown in Figure 10. Each element in the exponential matrix in Figure 11 represents the translation value of the corresponding element in the first basis matrix shown in Figure 10. The exponential matrix in Figure 11 uses "-1" to indicate that the corresponding element in the first basis matrix shown in Figure 10 is a zero element and has no translation value; the exponential matrix in Figure 11 uses "non-negative value" to indicate that the corresponding element in the first basis matrix shown in Figure 10 is a non-zero element. For example, the translation value of the non-zero element "1" in the first row and first column of the first basis matrix shown in Figure 10 is the element "115" in the first row and first column of the exponential matrix shown in Figure 11; the translation value of the non-zero element "1" in the third row and first column of the first basis matrix shown in Figure 10 is the element "76" in the third row and first column of the exponential matrix shown in Figure 11.

[0225] The following section uses the first base matrix shown in Figure 10 as an example to illustrate in detail the merging process of the rows of the first base matrix to obtain the first decoding matrix.

[0226] Figures 12 to 15 shown below are the first decoding matrix and the exponent matrix designed based on the mapping result shown in Figure 7 above.

[0227] Figure 12(a) shows an example of the first decoding matrix.

[0228] Figure 12(a) shows a first decoding matrix with 4 rows, i.e., B equals 4.

[0229] For example, the elements of the first row of the aforementioned A rows are XORed with the elements of the second row of the A rows to obtain the first decoded row. For instance, the first element "1" of the first row of the A rows is XORed with the first element "0" of the second row of the A rows to obtain the first element "1" of the first decoded row; the second element "0" of the first row of the A rows is XORed with the second element "1" of the second row of the A rows to obtain the second element "1" of the first decoded row; ..., the 44th element of the first row of the A rows... XORing the element "1" with the 44th element "0" of the second row of A rows yields the 44th element "1" of the first decoded row, thus obtaining the element set of the first decoded row as 11111111001111000011111111110011110011111111; XORing the element of the third row of A rows with the element of the fourth row of A rows yields the second decoded row. For example, XORing the element "1" of the third row of A rows with the element "0" of the fourth row of A rows yields the second decoded row. The first element "1" of the second decoded line is obtained by performing a row XOR operation. The second element "0" of the third row and the second element "1" of the fourth row are then XORed together to obtain the second element "1" of the second decoded line. This process is repeated until the fourth element "0" of the third row and the fourth element "1" of the fourth row are XORed together to obtain the fourth element "1" of the second decoded line. Therefore, the elements of the second decoded line are 11001111111100111111001 111001111111100110011; The third decoded line is obtained by XORing the elements of the 5th row and the 6th row of the above A rows. For example, XORing the first element "1" of the 5th row and the first element "0" of the 6th row of the A rows yields the first element "1" of the third decoded line; XORing the second element "0" of the 5th row and the second element "1" of the 6th row of the A rows yields the second element "1" of the third decoded line; ...The 44th element "0" in the 5th row of A rows is XORed with the 44th element "0" in the 6th row of A rows to obtain the 44th element "0" in the third decoded row. Therefore, the elements of the third decoded row are 11111100111111111111110000111111001111111100. The elements in the 7th row of A rows are XORed with the elements in the 8th row of A rows to obtain the fourth decoded row. For example, the 1st element "0" in the 7th row of A rows is XORed with the 1st element "1" in the 8th row of A rows. The first element "1" of the fourth decoded line is obtained by performing an OR operation. The second element "1" of the seventh row of A rows and the second element "0" of the eighth row of A rows are then XORed to obtain the second element "1" of the fourth decoded line. This process is repeated, and the forty-fourth element "0" of the seventh row of A rows and the forty-fourth element "1" of the eighth row of A rows are then XORed to obtain the forty-fourth element "1" of the fourth decoded line. Therefore, the elements of the fourth decoded line are 1111001111001111110011111111110011111100111110011111001111.

[0230] The first decoding matrix includes the first decoding line, the second decoding line, the third decoding line, and the fourth decoding line mentioned above.

[0231] For example, the first row of the first decoding matrix is ​​the first decoding row, the second row is the second decoding row, the third row is the third decoding row, and the fourth row is the fourth decoding row, as shown in Figure 12(a).

[0232] Alternatively, the first row of the first decoding matrix may be any decoding row among the first, second, third, and fourth decoding rows; the second row of the first decoding matrix may be any decoding row among the first, second, third, and fourth decoding rows except for the first row of the first decoding matrix; the third row of the first decoding matrix may be any decoding row among the first, second, third, and fourth decoding rows except for the first and second rows of the first decoding matrix; and the fourth row of the first decoding matrix may be the remaining decoding rows among the first, second, third, and fourth decoding rows except for the first, second, and third rows of the first decoding matrix. This application does not limit this.

[0233] The columns corresponding to the first, second, third, and fourth decoding rows mentioned above are the information columns of the first decoding matrix. Additionally, the first decoding matrix also includes a check column. Columns 45 to 48 of the first decoding matrix shown in Figure 12(a) are check columns (or core check columns). The region formed by the check columns of the first decoding matrix satisfies a block IRA structure, meaning the number of non-zero elements satisfies the condition of a double diagonal matrix plus 1.

[0234] Figure 12(b) is the exponent matrix corresponding to the first decoding matrix shown in Figure 12(a). The first decoding matrix shown in Figure 12(a) is obtained by merging the rows of the first base matrix. When XOR operation is performed between elements, their shift values ​​are also added simultaneously, thus obtaining the exponent matrix corresponding to the first decoding matrix shown in Figure 12(b).

[0235] Figure 13(a) shows another example of the first decoding matrix.

[0236] Figure 13(a) shows a first decoding matrix with 5 rows, i.e., B equals 5.

[0237] For example, the elements of the first row of the aforementioned A rows are used as the first decoding row; the elements of the third row of the aforementioned A rows are XORed with the elements of the fourth row of the aforementioned A rows to obtain the second decoding row; the elements of the fifth row of the aforementioned A rows are XORed with the elements of the sixth row of the aforementioned A rows to obtain the third decoding row; the elements of the seventh row of the aforementioned A rows are XORed with the elements of the eighth row of the aforementioned A rows to obtain the fourth decoding row; and the elements of the second row of the aforementioned A rows are used as the fifth decoding row.

[0238] The first decoding matrix includes the first decoding line, the second decoding line, the third decoding line, the fourth decoding line, and the fifth decoding line mentioned above.

[0239] For example, the first row of the first decoding matrix is ​​the first decoding row, the second row is the second decoding row, the third row is the third decoding row, the fourth row is the fourth decoding row, and the fifth row is the fifth decoding row, as shown in Figure 13(a).

[0240] Alternatively, the first row of the first decoding matrix may be any decoding row among the aforementioned first, second, third, fourth, and fifth decoding rows; the second row of the first decoding matrix may be any decoding row among the aforementioned first, second, third, fourth, and fifth decoding rows, excluding the first row of the first decoding matrix; and the third row of the first decoding matrix may be any decoding row among the aforementioned first, second, third, fourth, and fifth decoding rows, excluding the first and second rows of the first decoding matrix. The fourth row of the first decoding matrix is ​​any decoding row other than the first, second, third, fourth, and fifth decoding rows of the first decoding matrix. The fifth row of the first decoding matrix is ​​the remaining decoding rows other than the first, second, third, fourth, and fifth decoding rows of the first decoding matrix. This application does not limit this.

[0241] The columns corresponding to the first, second, third, fourth, and fifth decoding rows mentioned above are the information columns of the first decoding matrix. Additionally, the first decoding matrix also includes a check column. Columns 45 to 49 of the first decoding matrix shown in Figure 13(a) are check columns (or core check columns). The region formed by the check columns of the first decoding matrix satisfies a block IRA structure, meaning the number of non-zero elements satisfies the condition of a double diagonal matrix plus 1.

[0242] Figure 13(b) is the exponent matrix corresponding to the first decoding matrix shown in Figure 13(a). The first decoding matrix shown in Figure 13(a) is obtained by merging the rows of the first base matrix. When an XOR operation is performed between elements, their shift values ​​are also added simultaneously. The shift values ​​of elements that have not undergone an XOR operation remain unchanged, thus obtaining the exponent matrix corresponding to the first decoding matrix shown in Figure 13(b).

[0243] Figure 14(a) shows another example of the first decoding matrix.

[0244] Figure 14(a) shows a first decoding matrix with 6 rows, i.e., B equals 6.

[0245] For example, the elements of the first row of the above A rows are used as the first decoding row; the elements of the third row of the above A rows are XORed with the elements of the fourth row of the above A rows to obtain the second decoding row; the elements of the fifth row of the above A rows are used as the third decoding row; the elements of the seventh row of the above A rows are XORed with the elements of the eighth row of the above A rows to obtain the fourth decoding row; the elements of the second row of the above A rows are used as the fifth decoding row; and the elements of the sixth row of the above A rows are used as the sixth decoding row.

[0246] The first decoding matrix includes the first decoding line, the second decoding line, the third decoding line, the fourth decoding line, the fifth decoding line, and the sixth decoding line mentioned above.

[0247] For example, the first row of the first decoding matrix is ​​the first decoding row, the second row is the second decoding row, the third row is the third decoding row, the fourth row is the fourth decoding row, the fifth row is the fifth decoding row, and the sixth row is the sixth decoding row, as shown in Figure 14(a).

[0248] Alternatively, the first row of the first decoding matrix may be any one of the aforementioned first, second, third, fourth, fifth, and sixth decoding rows; the second row of the first decoding matrix may be any one of the aforementioned first, second, third, fourth, fifth, and sixth decoding rows except for the first row of the first decoding matrix; the third row of the first decoding matrix may be any one of the aforementioned first, second, third, fourth, fifth, and sixth decoding rows except for the first row and the second row of the first decoding matrix; and the fourth row of the first decoding matrix may be any one of the aforementioned first, second, third, fourth, fifth, and sixth decoding rows except for the first row and the second row of the first decoding matrix; and the fourth row of the first decoding matrix may be any one of the aforementioned first, second, third, fourth, fifth, and sixth decoding rows. The six decoding rows are any decoding rows other than the first, second, and third rows of the first decoding matrix. The fifth row of the first decoding matrix is ​​any decoding row other than the first, second, third, fourth, fifth, and sixth decoding rows other than the first, second, third, and fourth rows of the first decoding matrix. The sixth row of the first decoding matrix is ​​the remaining decoding rows other than the first, second, third, fourth, fifth, and sixth decoding rows other than the first, second, third, fourth, and fifth rows of the first decoding matrix. This application does not limit this.

[0249] The columns corresponding to the first, second, third, fourth, fifth, and sixth decoding rows mentioned above are the information columns of the first decoding matrix. Additionally, the first decoding matrix also includes a parity column. Columns 45 to 50 of the first decoding matrix shown in Figure 14(a) are the parity column (or core parity column). The region formed by the parity columns of the first decoding matrix satisfies a block IRA structure, meaning the number of non-zero elements satisfies a double diagonal matrix plus 1.

[0250] Figure 14(b) is the exponent matrix corresponding to the first decoding matrix shown in Figure 14(a). The first decoding matrix shown in Figure 14(a) is obtained by merging the rows of the first base matrix. When an XOR operation is performed between elements, their shift values ​​are also added simultaneously. The shift values ​​of elements that have not undergone an XOR operation remain unchanged, thus obtaining the exponent matrix corresponding to the first decoding matrix shown in Figure 14(b).

[0251] Figure 15(a) shows another example of the first decoding matrix.

[0252] Figure 15(a) shows a first decoding matrix with 7 rows, i.e., B equals 7.

[0253] For example, the elements of the first row of the above A rows are used as the first decoding row; the elements of the third row of the above A rows are XORed with the elements of the fourth row of the above A rows to obtain the second decoding row; the elements of the fifth row of the above A rows are used as the third decoding row; the elements of the seventh row of the above A rows are used as the fourth decoding row; the elements of the second row of the above A rows are used as the fifth decoding row; the elements of the sixth row of the above A rows are used as the sixth decoding row; and the elements of the eighth row of the above A rows are used as the seventh decoding row.

[0254] The first decoding matrix includes the first decoding line, the second decoding line, the third decoding line, the fourth decoding line, the fifth decoding line, the sixth decoding line, and the seventh decoding line mentioned above.

[0255] For example, the first row of the first decoding matrix is ​​the first decoding row, the second row is the second decoding row, the third row is the third decoding row, the fourth row is the fourth decoding row, the fifth row is the fifth decoding row, the sixth row is the sixth decoding row, and the seventh row is the seventh decoding row, as shown in Figure 15(a).

[0256] Alternatively, the first row of the first decoding matrix may be any decoding row among the aforementioned first, second, third, fourth, fifth, sixth, and seventh decoding rows; the second row of the first decoding matrix may be any decoding row among the aforementioned first, second, third, fourth, fifth, sixth, and seventh decoding rows, excluding the first row of the first decoding matrix; and the third row of the first decoding matrix may be any decoding row among the aforementioned first, second, third, fourth, fifth, sixth, and seventh decoding rows, excluding the first row of the first decoding matrix; and the third row of the first decoding matrix may be any decoding row among the aforementioned first, second, and seventh decoding rows. The third, fourth, fifth, sixth, and seventh decoding rows are any decoding rows other than the first and second rows of the first decoding matrix. The fourth row of the first decoding matrix is ​​any decoding row other than the first, second, and third rows of the first decoding matrix. The fifth row of the first decoding matrix is ​​any decoding row other than the first, second, and third rows of the first decoding matrix. The code line, the second decoded line, the third decoded line, the fourth decoded line, the fifth decoded line, the sixth decoded line, and the seventh decoded line are any decoded line other than the first row, the second row, the third row, and the fourth row of the first decoded matrix. The sixth row of the first decoded matrix is ​​any decoded line other than the first row and the second row of the first decoded matrix. The first decoding matrix includes any decoding row other than the 3rd, 4th, and 5th rows of the first decoding matrix. The 7th row of the first decoding matrix is ​​the remaining decoding row among the first, second, third, fourth, fifth, sixth, and seventh decoding rows, excluding the 1st, 2nd, 3rd, 4th, 5th, and 6th rows of the first decoding matrix. This application does not limit this.

[0257] The columns corresponding to the first, second, third, fourth, fifth, sixth, and seventh decoding rows mentioned above are the information columns of the first decoding matrix. Additionally, the first decoding matrix also includes a parity column. Columns 45 to 51 of the first decoding matrix shown in Figure 15(a) are the parity column (or core parity column). The region formed by the parity columns of the first decoding matrix satisfies a block IRA structure, meaning the number of non-zero elements satisfies the condition of a double diagonal matrix plus 1.

[0258] Figure 15(b) is the exponent matrix corresponding to the first decoding matrix shown in Figure 15(a). The first decoding matrix shown in Figure 15(a) is obtained by merging the rows of the first base matrix. When an XOR operation is performed between elements, their shift values ​​are also added simultaneously. The shift values ​​of elements that have not undergone an XOR operation remain unchanged, thus obtaining the exponent matrix corresponding to the first decoding matrix shown in Figure 15(b).

[0259] Alternatively, the first decoding matrix can be the same as the first basis matrix, that is, B is equal to A.

[0260] For example, one or more first decoding matrices can be predefined or pre-stored for use during decoding. For instance, if the protocol specifies that the length of the parity bit sequence corresponding to the sequence to be decoded is 4*Zc, then a first decoding matrix with 4 rows can be stored (as shown in Figure 12(a)); if the protocol specifies that the length of the parity bit sequence corresponding to the sequence to be decoded is 5*Zc, then a first decoding matrix with 5 rows can be stored (as shown in Figure 13(a); if the protocol specifies that the length of the parity bit sequence corresponding to the sequence to be decoded is 6*Zc, then a first decoding matrix with 6 rows can be stored (as shown in Figure 14(a); if the protocol specifies that the length of the parity bit sequence corresponding to the sequence to be decoded is 7*Zc, then a first decoding matrix with 7 rows can be stored (as shown in Figure 15(a); if the protocol specifies that the length of the parity bit sequence corresponding to the sequence to be decoded is greater than or equal to 8*Zc, then a first base matrix can be stored.

[0261] Alternatively, the required first decoding matrix can be generated based on the first base matrix when decoding is required. For example, the receiving device can generate the first decoding matrix based on the length of the parity bit sequence corresponding to the sequence to be decoded. For example, when the length of the parity bit sequence corresponding to the sequence to be decoded is 4*Zc, the receiving device can generate a first decoding matrix with 4 rows based on the first base matrix (as shown in Figure 12(a)); when the length of the parity bit sequence corresponding to the sequence to be decoded is 5*Zc, the receiving device can generate a first decoding matrix with 5 rows based on the first base matrix (as shown in Figure 13(a)); when the length of the parity bit sequence corresponding to the sequence to be decoded is 6*Zc, the receiving device can generate a first decoding matrix with 6 rows based on the first base matrix (as shown in Figure 14(a)); when the length of the parity bit sequence corresponding to the sequence to be decoded is 7*Zc, the receiving device can generate a first decoding matrix with 7 rows based on the first base matrix (as shown in Figure 15(a)); when the length of the parity bit sequence corresponding to the matrix to be decoded is greater than or equal to 8*Zc, the first decoding matrix is ​​the same as the first base matrix (as shown in Figure 10).

[0262] Figures 16 and 17 below show the first decoding matrix and its exponent matrix designed based on the mapping result shown in Figure 8 above.

[0263] The first decoding matrix and its exponent matrix corresponding to the second parity bit sequence length of 4*Zc shown in Figure 8 can be referred to Figure 12(a) and Figure 12(b) above. The first decoding matrix and its exponent matrix corresponding to the second parity bit sequence length of 5*Zc shown in Figure 8 can be referred to Figure 13(a) and Figure 13(b) above. The following describes the first decoding matrix and its exponent matrix corresponding to the second parity bit sequence lengths of 6*Zc and 7*Zc shown in Figure 8.

[0264] Figure 16(a) shows an example of the first decoding matrix.

[0265] Figure 16(a) shows a first decoding matrix with 6 rows, i.e., B equals 6.

[0266] For example, the elements of the first row of the above A rows are used as the first decoding row; the elements of the third row of the above A rows are used as the second decoding row; the elements of the fifth row of the above A rows are XORed with the elements of the sixth row of the above A rows to obtain the third decoding row; the elements of the seventh row of the above A rows are XORed with the elements of the eighth row of the above A rows to obtain the fourth decoding row; the elements of the second row of the above A rows are used as the fifth decoding row; and the elements of the fourth row of the above A rows are used as the sixth decoding row.

[0267] The first decoding matrix includes the first decoding line, the second decoding line, the third decoding line, the fourth decoding line, the fifth decoding line, and the sixth decoding line mentioned above.

[0268] For example, the first row of the first decoding matrix is ​​the first decoding row, the second row is the second decoding row, the third row is the third decoding row, the fourth row is the fourth decoding row, the fifth row is the fifth decoding row, and the sixth row is the sixth decoding row, as shown in Figure 16(a).

[0269] Alternatively, the first row of the first decoding matrix may be any one of the aforementioned first, second, third, fourth, fifth, and sixth decoding rows; the second row of the first decoding matrix may be any one of the aforementioned first, second, third, fourth, fifth, and sixth decoding rows except for the first row of the first decoding matrix; the third row of the first decoding matrix may be any one of the aforementioned first, second, third, fourth, fifth, and sixth decoding rows except for the first row and the second row of the first decoding matrix; and the fourth row of the first decoding matrix may be any one of the aforementioned first, second, third, fourth, fifth, and sixth decoding rows except for the first row and the second row of the first decoding matrix; and the fourth row of the first decoding matrix may be any one of the aforementioned first, second, third, fourth, fifth, and sixth decoding rows. The six decoding rows are any decoding rows other than the first, second, and third rows of the first decoding matrix. The fifth row of the first decoding matrix is ​​any decoding row other than the first, second, third, fourth, fifth, and sixth decoding rows other than the first, second, third, and fourth rows of the first decoding matrix. The sixth row of the first decoding matrix is ​​the remaining decoding rows other than the first, second, third, fourth, fifth, and sixth decoding rows other than the first, second, third, fourth, and fifth rows of the first decoding matrix. This application does not limit this.

[0270] The columns corresponding to the first, second, third, fourth, fifth, and sixth decoding rows mentioned above are the information columns of the first decoding matrix. Additionally, the first decoding matrix also includes a parity column. Columns 45 to 50 of the first decoding matrix shown in Figure 16(a) are the parity column (or core parity column). The region formed by the parity columns of the first decoding matrix satisfies a block IRA structure, meaning the number of non-zero elements satisfies the condition of a double diagonal matrix plus 1.

[0271] Figure 16(b) is the exponent matrix corresponding to the first decoding matrix shown in Figure 16(a). The first decoding matrix shown in Figure 16(a) is obtained by merging the rows of the first base matrix. When an XOR operation is performed between elements, their shift values ​​are also added simultaneously. The shift values ​​of elements that have not undergone an XOR operation remain unchanged, thus obtaining the exponent matrix corresponding to the first decoding matrix shown in Figure 16(b).

[0272] Figure 17(a) shows another example of the first decoding matrix.

[0273] Figure 17(a) shows a first decoding matrix with 7 rows, i.e., B equals 7.

[0274] For example, the elements of the first row of the above A rows are used as the first decoding row; the elements of the third row of the above A rows are used as the second decoding row; the elements of the fifth row of the above A rows are used as the third decoding row; the elements of the seventh row of the above A rows and the elements of the eighth row of the above A rows are XORed to obtain the fourth decoding row; the elements of the second row of the above A rows are used as the fifth decoding row; the elements of the fourth row of the above A rows are used as the sixth decoding row; and the elements of the sixth row of the above A rows are used as the seventh decoding row.

[0275] The first decoding matrix includes the first decoding line, the second decoding line, the third decoding line, the fourth decoding line, the fifth decoding line, the sixth decoding line, and the seventh decoding line mentioned above.

[0276] For example, the first row of the first decoding matrix is ​​the first decoding row, the second row is the second decoding row, the third row is the third decoding row, the fourth row is the fourth decoding row, the fifth row is the fifth decoding row, the sixth row is the sixth decoding row, and the seventh row is the seventh decoding row, as shown in Figure 17(a).

[0277] Alternatively, the first row of the first decoding matrix may be any decoding row among the aforementioned first, second, third, fourth, fifth, sixth, and seventh decoding rows; the second row of the first decoding matrix may be any decoding row among the aforementioned first, second, third, fourth, fifth, sixth, and seventh decoding rows, excluding the first row of the first decoding matrix; and the third row of the first decoding matrix may be any decoding row among the aforementioned first, second, third, fourth, fifth, sixth, and seventh decoding rows, excluding the first row of the first decoding matrix; and the third row of the first decoding matrix may be any decoding row among the aforementioned first, second, and seventh decoding rows. The third, fourth, fifth, sixth, and seventh decoding rows are any decoding rows other than the first and second rows of the first decoding matrix. The fourth row of the first decoding matrix is ​​any decoding row other than the first, second, and third rows of the first decoding matrix. The fifth row of the first decoding matrix is ​​any decoding row other than the first, second, and third rows of the first decoding matrix. The code line, the second decoded line, the third decoded line, the fourth decoded line, the fifth decoded line, the sixth decoded line, and the seventh decoded line are any decoded line other than the first row, the second row, the third row, and the fourth row of the first decoded matrix. The sixth row of the first decoded matrix is ​​any decoded line other than the first row and the second row of the first decoded matrix. The first decoding matrix includes any decoding row other than the 3rd, 4th, and 5th rows of the first decoding matrix. The 7th row of the first decoding matrix is ​​the remaining decoding row among the first, second, third, fourth, fifth, sixth, and seventh decoding rows, excluding the 1st, 2nd, 3rd, 4th, 5th, and 6th rows of the first decoding matrix. This application does not limit this.

[0278] The columns corresponding to the first, second, third, fourth, fifth, sixth, and seventh decoding rows mentioned above are the information columns of the first decoding matrix. Additionally, the first decoding matrix also includes a parity column. Columns 45 to 51 of the first decoding matrix shown in Figure 17(a) are the parity column (or core parity column). The region formed by the parity columns of the first decoding matrix satisfies a block IRA structure, meaning the number of non-zero elements satisfies a double diagonal matrix plus 1.

[0279] Figure 17(b) is the exponent matrix corresponding to the first decoding matrix shown in Figure 17(a). The first decoding matrix shown in Figure 17(a) is obtained by merging the rows of the first base matrix. When an XOR operation is performed between elements, their shift values ​​are also added simultaneously. The shift values ​​of elements that have not undergone an XOR operation remain unchanged, thus obtaining the exponent matrix corresponding to the first decoding matrix shown in Figure 17(b).

[0280] For example, the first basis matrix involved in the embodiments of this application may be the first X rows and first Y columns truncated from BG1 or BG2. The translation value of each element of the first basis matrix can be determined by Table 1 and Table 2 below.

[0281] Table 1

[0282] The j-th row of the list of lifting dimensions shown in Table 1 above includes Where a j ∈{2,3,5,7,9,11,13,15}, max(k j )∈{7,7,6,5,5,5,4,4}; The row indices of the lift dimension list shown in Table 1 above correspond one-to-one with the column indices of the translation value list shown in Table 2 below, that is, the lift dimension in each row of the lift dimension list corresponds to a set of translation values.

[0283] Table 2

[0284] Each non-zero element in the first base matrix corresponds to a shift value. For example, the boost size can be determined based on parameters such as the target bit rate and bit length, and then the index of the boost size set to which the boost size belongs can be determined based on Table 1 above. Then, based on the index of the boost size set to which the boost size belongs, the shift value corresponding to the non-zero element in the i-th row and j-th column of the first base matrix can be determined from Table 2 above.

[0285] For example, the non-zero element in the first row and first column of the first base matrix has a translation value of 211 when the index of the lifting size set is 0, the non-zero element in the second row and seventh column of the first base matrix has a translation value of 66 when the index of the lifting size set is 3, and the non-zero element in the third row and tenth column of the first base matrix has a translation value of 206 when the index of the lifting size set is 7.

[0286] Alternatively, the first basis matrix involved in the embodiments of this application can be composed of multiple 2*2 non-zero matrices and multiple 2*2 zero matrices, where each of the multiple 2*2 non-zero matrices is... or Each of the multiple 2x2 zero matrices is: Figure 10 shows an example of a first basis matrix.

[0287] For example, the first basis matrix shown in Figure 10 can be predefined or pre-stored, or the first basis matrix shown in Figure 10 can be obtained by expanding BG1 or BG2. For example, each non-zero element in BG1 or BG2 is expanded into a 2*2 non-zero matrix in the first basis matrix, and each zero element in BG1 or BG2 is expanded into a 2*2 zero matrix in the first basis matrix, thus obtaining the first basis matrix shown in Figure 10.

[0288] The translation values ​​of the non-zero elements in the first column and the second column of each 2*2 non-zero matrix of the first basis matrix shown in Figure 10 can be the same or different, and this application does not limit this. For example, the first non-zero element in the i-th row and j-th column of BG1 or BG2 is expanded into a 2*2 first non-zero matrix in the first basis matrix, and the translation value of the first non-zero element can be determined according to Table 1 and Table 2 above. Then, the translation values ​​of the non-zero elements in the first column and the second column of the first non-zero matrix can both be the first translation value; or, the translation value of the non-zero element in the first column of the first non-zero matrix is ​​the first translation value, and the translation value of the non-zero element in the second column is determined based on the first translation value; or, the translation value of the non-zero element in the second column of the first non-zero matrix is ​​the first translation value, and the translation value of the non-zero element in the first column is determined based on the first translation value.

[0289] For example, if the translation value of a non-zero element of the first non-zero matrix is ​​the first translation value, then the translation value of the other non-zero element can be determined based on the following formula: q = f(p).

[0290] Where f() is a linear or nonlinear function, p represents the translation value of a non-zero element of the first non-zero matrix, and q represents the translation value of another non-zero element of the first non-zero matrix.

[0291] For example, the above q = f(p) can specifically be any of the following: q = p + β; q = p + γ*h(Z) c ); q=α*p; q=α*p+β;

[0292] Where α, β, and γ are constants, h(Z) c ) is a linear or nonlinear function with independent variable Zc, where Zc is the lifting dimension of each element in the first basis matrix, and G(i) is a linear or nonlinear function with independent variable i.

[0293] Specifically, the receiving device generates a second parity check matrix based on the first decoding matrix, and performs LDPC decoding on the sequence to be decoded based on the second parity check matrix to obtain the decoded sequence. For example, each non-zero element in the first decoding matrix is ​​first promoted to a Zc*Zc identity matrix in the second parity check matrix, and then the identity matrix is ​​cyclically shifted according to the shift value corresponding to each non-zero element in the first decoding matrix; each zero element in the first decoding matrix is ​​promoted to a Zc*Zc zero matrix in the second parity check matrix.

[0294] Figure 18 shows the performance simulation results provided by the embodiments of this application. The horizontal axis of Figure 18 represents the symbol signal-to-noise ratio (Es / N0), that is, the ratio of the energy (Es) of each symbol to the noise power spectral density (N0), and the vertical axis represents the block error rate (BLER). The simulation results shown in Figure 18 were obtained with 5 decoding iterations, 1024 quadrature amplitude modulation (QAM), and a code rate of 22 / 24. The dashed lines in Figure 18 represent the decoding performance of decoding the codeword sequence obtained through the LDPC encoding + mapping process of the embodiments of this application, and the solid lines in Figure 18 represent the decoding performance of decoding the codeword sequence obtained only through existing LDPC encoding. As can be seen from Figure 18, the decoding performance of the scheme of the embodiments of this application is significantly better than the decoding performance of the existing schemes.

[0295] The communication device provided in this application is described below.

[0296] Figure 19 is a schematic structural diagram of the communication device 10 provided in this application. The communication device 10 can be a transmitting device, or a device applied to the transmitting device that can realize the corresponding functions of the transmitting device in the method embodiments of this application, such as a chip, processor, or circuit. Alternatively, the communication device 10 can be a receiving device, or a device applied to the receiving device that can realize the corresponding functions of the receiving device in the method embodiments of this application, such as a chip, processor, or circuit.

[0297] Optionally, the communication device 10 includes a processing module 11, which may be a processor, a processing board, a processing unit, or a processing device, etc. When the communication device 10 is a transmitting device or a device applied to a transmitting device, the processing module 11 is used to perform LDPC encoding on the information bits to be encoded based on a first parity check matrix to obtain an information bit sequence and a first parity check bit sequence, and to map the first parity check bit sequence to a second parity check bit sequence, etc. Specific processes can be found in the detailed descriptions of the corresponding steps in the method embodiments, and will not be repeated here. When the communication device 10 is a receiving device or a device applied to a receiving device, the processing module 11 is used to perform LDPC decoding on the sequence to be decoded based on a first decoding matrix, etc. Specific processes can be found in the detailed descriptions of the corresponding steps in the method embodiments, and will not be repeated here.

[0298] Optionally, the communication device 10 further includes a communication module 12, which may also be referred to as a transceiver module, transceiver, transceiver unit, or transceiver device, etc., for performing receiving (or input) and / or sending (or output) operations. For example, when the communication device 10 is a transmitting device or a device applied to a transmitting device, the communication module 12 can be used to output the second codeword sequence obtained by the processing module 11. Similarly, when the communication device 10 is a receiving device or a device applied to a receiving device, the communication module 12 can be used to acquire the sequence to be decoded and send the sequence to be decoded to the processing module 11; and output the decoded sequence obtained after the processing module 11 decodes the sequence to be decoded. In addition, the aforementioned communication module and / or processing module can be implemented by virtual modules. For example, the processing module can be implemented by a software functional unit or a virtual device, and the communication module can be implemented by a software function or a virtual device. Alternatively, the processing module or communication module can also be implemented by a physical device, for example, if the device is implemented using a chip / circuit (e.g., an integrated circuit or logic circuit). The communication module may be an input / output circuit and / or a communication interface, performing input operations (corresponding to the aforementioned receiving operation) and output operations (corresponding to the aforementioned sending operation); the processing module is an integrated processor, microprocessor, or circuit (e.g., integrated circuit, logic circuit, etc.).

[0299] The module division in this application is illustrative and represents only one logical functional division. In actual implementation, other division methods are possible. Furthermore, the functional modules in the various examples of this application can be integrated into a single processor, exist as separate physical entities, or be integrated into a single module. The integrated modules described above can be implemented in hardware, as software functional modules, or a combination of hardware and software.

[0300] Figure 20 is a schematic structural diagram of another communication device 20 provided in this application. The communication device 20 can be used to implement the functions of any communication device (e.g., a terminal device or a network device) in the communication system described in the foregoing examples. The communication device 20 may include at least one processor 21. Optionally, the processor 21 (or processing device) is coupled to a memory, which may be located within the communication device, integrated with the processor, or located outside the communication device. For example, the communication device 20 may also include at least one memory 22. The memory 22 stores computer programs, instructions, or data necessary for implementing any of the above method embodiments; the processor 21 may execute the computer programs, instructions, or data stored in the memory 22 to perform the corresponding functions of the transmitting or receiving device in any of the above embodiments.

[0301] Optionally, the communication device 20 may further include a communication interface 23, through which the communication device 20 can interact with other devices. For example, the communication interface 23 may be a transceiver, circuit, bus, module, pin, or other type of communication interface. When the communication device 20 is a chip-based device or circuit, the communication interface 23 in the device 20 may also be an input / output circuit, capable of inputting information (or receiving information) and / or outputting information (or sending information). The processor may be an integrated circuit or logic circuit, etc., and the processor can determine the output information based on the input information.

[0302] The coupling in this application refers to indirect coupling or communication connection between devices, units, or modules, which can be electrical, mechanical, or other forms, used for information exchange between devices, units, or modules. Processor 21 may operate in conjunction with memory 22 and communication interface 23. This application does not limit the connection medium between the aforementioned processor 21, memory 22, and communication interface 23.

[0303] Figure 21 is a schematic structural diagram of the chip 30 provided in this application. The chip 30 includes a circuit 31 and a communication interface 32. The circuit 31 can be a logic circuit, an integrated circuit, etc., and the communication interface 32 can also be called an input / output circuit, input / output interface, interface circuit, etc., which can input information (or receive information) or output information (or send information). The chip 30 can execute the methods executed by the encoding-side device or the decoding-side device in the various embodiments of this application.

[0304] In addition, this application also provides a computer-readable storage medium storing computer instructions, which, when executed on a computer, cause the operations and / or processes performed by the sending or receiving device in the various method embodiments of this application to be executed.

[0305] This application also provides a computer program product, which includes computer program code or instructions. When the computer program code or instructions are run on a computer, the operations and / or processes performed by the sending end device or the receiving end device in the various method embodiments of this application are executed.

[0306] Furthermore, this application also provides a chip including a processor. A memory for storing a computer program is provided independently of the chip, and the processor is used to execute the computer program stored in the memory, so that operations and / or processes performed by a transmitting or receiving device in any method embodiment are executed. Further, the chip may also include a communication interface. The communication interface may be an input / output interface or an interface circuit, etc. Further, the chip may also include the memory.

[0307] This application provides a communication system, including the transmitting end device and the receiving end device in the above method embodiments.

[0308] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0309] The processor in this application embodiment has signal processing capabilities and can be a central processing unit (CPU), or a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component. It can implement or execute the methods, steps, and logic block diagrams disclosed in this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in this application can be directly embodied in the execution of the hardware processor, or executed by a combination of hardware and software modules within the processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above methods.

[0310] In the embodiments of this application, the memory can be volatile memory or non-volatile memory, or it can include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0311] The technical solutions provided in this application can be implemented in whole or in part through software, hardware, firmware, or any combination thereof. When implemented using software, they can be implemented in whole or in part as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a terminal device, an access network device, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., digital video discs (DVDs)), or semiconductor media, etc.

[0312] The term "comprising" and any variations thereof used in the embodiments of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the steps or units listed, but may optionally include other steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0313] In this application, examples may reference each other without logical contradiction. For example, methods and / or terms between method embodiments may reference each other, functions and / or terms between device embodiments may reference each other, and functions and / or terms between device examples and method examples may reference each other.

[0314] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0315] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0316] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0317] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0318] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

Claims

1. An encoding method, characterized in that, include: Based on the first parity check matrix, the information bits to be encoded are subjected to low-density parity check (LDPC) encoding to obtain a first codeword sequence, which includes an information bit sequence and a first parity bit sequence. Map the first parity bit sequence to the second parity bit sequence; Output a second codeword sequence, which includes the information bit sequence and the second check bit sequence.

2. The method according to claim 1, characterized in that, The first check bit sequence includes a first core check bit sequence, which is the check bits corresponding to all core rows of the first check matrix.

3. The method according to claim 1 or 2, characterized in that, The first check bit sequence consists of A segments of check bit sequences, where the length of the i-th segment of the A-segment check bit sequence is k. i *Zc, the second parity bit sequence consists of B segments of parity bit sequence. Any segment of the parity bit sequence in segment B is obtained based on at least one segment of the parity bit sequence in segment A. Where Zc is the lifting size of the first base matrix to the first parity-check matrix using LDPC encoding, 1≤i≤A, A, B, k i It is a positive integer.

4. The method according to claim 3, characterized in that, The length of the i-th parity bit sequence in segment A is n. i *Zc includes: the length of each parity bit sequence in the A-segment parity bit sequence is Zc.

5. The method according to claim 3 or 4, characterized in that, The B segment of the parity bit sequence includes a parity bit sequence #1B, which is determined based on parity bit sequence #1A and parity bit sequence #2A. in, The parity bit sequence #1A is a segment of the parity bit sequence in segment A, or the parity bit sequence #1A is obtained by cyclically shifting a segment of the parity bit sequence in segment A, and / or, The parity bit sequence #2A is another parity bit sequence in the parity bit sequence A, or the parity bit sequence #2A is obtained by cyclic shifting another parity bit sequence in the parity bit sequence A.

6. The method according to claim 5, characterized in that, The parity bit sequence #1B is determined based on the parity bit sequence #1A and the parity bit sequence #2A, including: the parity bit sequence #1B is obtained by performing an XOR operation on the parity bit sequence #1A and the parity bit sequence #2A.

7. The method according to any one of claims 3 to 6, characterized in that, The B segment of the parity bit sequence includes a parity bit sequence #2B, which is determined based on parity bit sequences #3A, #4A, and #5A. in, The parity bit sequence #3A is a segment of the parity bit sequence in segment A, or the parity bit sequence #3A is obtained by cyclically shifting a segment of the parity bit sequence in segment A, and / or, The parity bit sequence #4A is another parity bit sequence in the parity bit sequence A, or the parity bit sequence #4A is obtained by cyclic shifting another parity bit sequence in the parity bit sequence A, and / or, The parity bit sequence #5A is another parity bit sequence in the parity bit sequence A, or the parity bit sequence #5A is obtained by cyclic shifting another parity bit sequence in the parity bit sequence A.

8. The method according to claim 7, characterized in that, The parity bit sequence #2B is determined based on parity bit sequence #3A, parity bit sequence #4A, and parity bit sequence #5A, including: the parity bit sequence #2B is obtained by performing an XOR operation on the parity bit sequence #3A, the parity bit sequence #4A, and the parity bit sequence #5A.

9. The method according to any one of claims 3 to 6, characterized in that, The first parity bit sequence and the second parity bit sequence in the A-segment parity bit sequence are XORed to obtain a first sequence; the third parity bit sequence and the fourth parity bit sequence in the A-segment parity bit sequence are XORed to obtain a second sequence; the fifth parity bit sequence and the sixth parity bit sequence in the A-segment parity bit sequence are XORed to obtain a third sequence; and the seventh parity bit sequence and the eighth parity bit sequence in the A-segment parity bit sequence are XORed to obtain a third sequence. The first sequence is obtained by performing an XOR operation on the first column. The second and fourth parity bit sequences in the A-segment parity bit sequence are then XORed to obtain the fifth sequence. The sixth and eighth parity bit sequences in the A-segment parity bit sequence are then XORed to obtain the sixth sequence. The seventh sequence is obtained by performing an XOR operation on the second and eighth parity bit sequences in the A-segment parity bit sequence. The eighth parity bit sequence in the A-segment parity bit sequence is then used as the eighth sequence. The B-segment check bit sequence includes some or all of the sequences from the first sequence, the second sequence, the third sequence, the fourth sequence, the fifth sequence, the sixth sequence, the seventh sequence, and the eighth sequence.

10. The method according to any one of claims 3 to 6, characterized in that, The parity bit sequence A is XORed with the parity bit sequence B to obtain a first sequence; the parity bit sequence A is XORed with the parity bit sequence C to obtain a second sequence; the parity bit sequence A is XORed with the parity bit sequence C to obtain a third sequence; the parity bit sequence A is XORed with the parity bit sequence C to obtain a fourth sequence; and the parity bit sequence B includes the first sequence, the second sequence, the third sequence, and the fourth sequence.

11. The method according to claim 10, characterized in that, The second parity bit sequence in the parity bit sequence A is XORed with the fourth parity bit sequence in the parity bit sequence A to obtain the fifth sequence, and the parity bit sequence B also includes the fifth sequence.

12. The method according to claim 11, characterized in that, The sixth sequence is obtained by performing an XOR operation between the sixth and eighth parity bit sequences in the A-segment parity bit sequence, and the B-segment parity bit sequence also includes the sixth sequence.

13. The method according to claim 12, characterized in that, The seventh sequence is obtained by performing an XOR operation between the second parity bit sequence in the A segment parity bit sequence and the eighth parity bit sequence in the A segment parity bit sequence, and the B segment parity bit sequence also includes the seventh sequence.

14. The method according to claim 13, characterized in that, The 8th parity bit sequence in the A-segment parity bit sequence is called the 8th sequence, and the B-segment parity bit sequence also includes the 8th sequence.

15. The method according to any one of claims 1 to 14, characterized in that, The first parity bit sequence and the second parity bit sequence further include a first extended parity bit sequence, which is the parity bit corresponding to the extended row of the first parity matrix.

16. The method according to any one of claims 1 to 15, characterized in that, The length of the second codeword sequence is equal to the length of the first codeword sequence.

17. A decoding method, characterized in that, include: Obtain the sequence to be decoded; The sequence to be decoded is subjected to LDPC decoding based on the first decoding matrix to obtain the decoded sequence. The first decoding matrix is ​​obtained by merging the rows of the first base matrix.

18. The method according to claim 17, characterized in that, The rows of the first base matrix include the core rows of the first base matrix.

19. The method according to claim 17 or 18, characterized in that, The first base matrix consists of A rows, and the first decoding matrix consists of B rows. Each of the B rows is derived from at least one of the A rows. Where A and B are positive integers.

20. The method according to claim 19, characterized in that, The B rows include a row #1B, which is determined based on two rows from the A rows.

21. The method according to claim 20, characterized in that, The row #1B is determined based on two rows from the A rows, including: the row #1B is obtained by performing an XOR operation on the two rows from the A rows.

22. The method according to any one of claims 19 to 21, characterized in that, The B rows include a row #2B, which is determined based on three rows from the A rows.

23. The method according to claim 22, characterized in that, The row #2B is determined based on three rows from the A rows, including: the row #2B is obtained by performing an XOR operation on the three rows from the A rows.

24. The method according to any one of claims 19 to 21, characterized in that, The first decoded line is obtained by XORing the elements of the first row and the second row of the A rows; the second decoded line is obtained by XORing the elements of the third row and the fourth row of the A rows; the third decoded line is obtained by XORing the elements of the fifth row and the sixth row of the A rows; and the fourth decoded line is obtained by XORing the elements of the seventh row and the eighth row of the A rows. The B rows include the first decoding row, the second decoding row, the third decoding row, and the fourth decoding row.

25. The method according to any one of claims 19 to 21, characterized in that, The elements of the first row of the A rows are used as the first decoding row. The elements of the third row and the fourth row of the A rows are XORed to obtain the second decoding row. The elements of the fifth row and the sixth row of the A rows are XORed to obtain the third decoding row. The elements of the seventh row and the eighth row of the A rows are XORed to obtain the fourth decoding row. The elements of the second row of the A rows are used as the fifth decoding row. The B rows include the first decoding row, the second decoding row, the third decoding row, the fourth decoding row, and the fifth decoding row.

26. The method according to any one of claims 19 to 21, characterized in that, The elements of the first row of the A rows are used as the first decoding row. The elements of the third row and the elements of the fourth row of the A rows are XORed to obtain the second decoding row. The elements of the fifth row of the A rows are used as the third decoding row. The elements of the seventh row and the elements of the eighth row of the A rows are XORed to obtain the fourth decoding row. The elements of the second row of the A rows are used as the fifth decoding row. The elements of the sixth row of the A rows are used as the sixth decoding row. The B rows include the first decoding row, the second decoding row, the third decoding row, the fourth decoding row, the fifth decoding row, and the sixth decoding row.

27. The method according to any one of claims 19 to 21, characterized in that, The elements of the first row of the A rows are used as the first decoding row. The elements of the third row and the elements of the fourth row of the A rows are XORed to obtain the second decoding row. The elements of the fifth row of the A rows are used as the third decoding row. The elements of the seventh row of the A rows are used as the fourth decoding row. The elements of the second row of the A rows are used as the fifth decoding row. The elements of the sixth row of the A rows are used as the sixth decoding row. The elements of the eighth row of the A rows are used as the seventh decoding row. The B rows include the first decoding row, the second decoding row, the third decoding row, the fourth decoding row, the fifth decoding row, the sixth decoding row, and the seventh decoding row.

28. The method according to any one of claims 18 to 27, characterized in that, The first base matrix and the first decoding matrix also include extended rows.

29. A communication device, characterized in that, The system includes a communication interface and circuitry. The communication interface is used to acquire information required to perform the method as described in any one of claims 1-16, and to send the information to the circuitry, which is used to perform the method as described in any one of claims 1-16 based on the received information; or... The communication interface is used to acquire information required to perform the method as described in any one of claims 17-28, and to send the information to the circuit, which is used to perform the method as described in any one of claims 17-28 based on the received information.

30. A communication device, characterized in that, The device includes a processor coupled to a memory, the processor being configured to execute a computer program or instructions stored in the memory to cause the communication device to perform the method as described in any one of claims 1-28.

31. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed on a computer, implement the method as described in any one of claims 1-28.

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