Memory and manufacturing method therefor, and electronic device

Abstract

A memory and a manufacturing method therefor, and an electronic device. The memory comprises a first electrically conductive wire, a semiconductor pattern, a second electrically conductive wire, an electrically conductive component and an oxygen channel structure, wherein the first electrically conductive wire extends in a vertical direction on a substrate; the semiconductor pattern is coupled to the first electrically conductive wire, and the material of the semiconductor pattern comprises a metal oxide semiconductor material; the second electrically conductive wire extends in a horizontal direction and is coupled to a first end of the semiconductor pattern; the electrically conductive component is coupled to a second end of the semiconductor pattern, and the second end of the semiconductor pattern is opposite to the first end of the semiconductor pattern; and the oxygen channel structure comprises first insulating patterns and second insulating patterns, which are alternately arranged in the vertical direction, the first insulating patterns are disposed in the same layer as the semiconductor pattern and are in contact with the semiconductor pattern, and the materials of the first insulating patterns and the second insulating patterns each comprise an oxide.

Description

Memory and its manufacturing method, electronic devices

[0001] This application claims priority to Chinese Patent Application No. 202510074644.3, filed on January 17, 2025, entitled "Memory and Method of Manufacturing Thereof, Electronic Device", the entire contents of which are incorporated herein by reference. 1. Technical Field

[0002] This disclosure relates to the field of semiconductor technology, and more particularly to a memory, a method for manufacturing the same, and an electronic device. 2. Background Technology

[0003] To meet users' demands for high-performance electronic products, high-capacity semiconductor memories are required. To provide high-capacity semiconductor memories, increased integration density is necessary. Since the integration density of two-dimensional (2D) semiconductor memories is primarily determined by the area occupied by a single memory cell, there is a bottleneck in increasing the integration density of 2D semiconductor memories. Currently, three-dimensional (3D) semiconductor memories have been proposed, which increase storage capacity by stacking multiple memory cells vertically on a substrate. 3. Summary of the Invention

[0004] According to a first aspect of the present disclosure, a memory is provided, comprising: a first conductive line extending in a vertical direction on a substrate; a semiconductor pattern coupled to the first conductive line, wherein the semiconductor pattern is made of a metal oxide semiconductor material; a second conductive line extending in a first horizontal direction and coupled to a first end of the semiconductor pattern; a conductive component coupled to a second end of the semiconductor pattern, the second end of the semiconductor pattern being opposite to the first end; and an oxygen channel structure including a first insulating pattern and a second insulating pattern alternately arranged in the vertical direction, wherein the first insulating pattern is disposed in the same layer as the semiconductor pattern and is in contact with the semiconductor pattern, and the material of each of the first insulating pattern and the second insulating pattern comprises an oxide.

[0005] In some embodiments, the memory further includes: a first dielectric layer and a second dielectric layer alternately arranged along the vertical direction, wherein the first insulating pattern is disposed in the same layer as the first dielectric layer, the second insulating pattern is disposed in the same layer as the second dielectric layer, the material of the first dielectric layer includes a nitride, and the material of the second dielectric layer includes an oxide.

[0006] In some embodiments, the material of the second insulating pattern is the same as the material of the first insulating pattern.

[0007] In some embodiments, the materials of the first insulating pattern and the second insulating pattern are the same as the material of the second dielectric layer.

[0008] In some embodiments, the memory further includes: a first dielectric layer and a second dielectric layer alternately arranged along the vertical direction, wherein the first insulating pattern is disposed in the same layer as the first dielectric layer, the second insulating pattern is the portion of the second dielectric layer opposite to the first insulating pattern and the semiconductor pattern, and the material of the first dielectric layer includes a nitride.

[0009] In some embodiments, the material of the second insulating pattern is different from the material of the first insulating pattern.

[0010] In some embodiments, the conductive component includes at least one of a capacitor electrode and a third conductive line extending along a second horizontal direction, the second horizontal direction intersecting the first horizontal direction.

[0011] In some embodiments, the semiconductor pattern surrounds the first conductive line, and the first insulating pattern includes two sub-insulating patterns located on opposite sides of the semiconductor pattern, with a first end of the two sub-insulating patterns contacting the second conductive line and a second end of the two sub-insulating patterns contacting the conductive component.

[0012] In some embodiments, the second insulating pattern includes a closed loop pattern surrounding the first conductive wire.

[0013] According to a second aspect of the present disclosure, a method for manufacturing a memory is provided, comprising: forming a stacked structure on a substrate, wherein the stacked structure includes a first dielectric layer and a second dielectric layer alternately arranged in a vertical direction, the first dielectric layer being made of a nitride and the second dielectric layer being made of an oxide; etching the stacked structure to form a first opening, forming a second conductive line disposed in the same layer as the first dielectric layer through the first opening, wherein the second conductive line extends in a first horizontal direction; etching the stacked structure to form a second opening, forming a conductive component disposed in the same layer as the first dielectric layer through the second opening; etching the stacked structure to form a third opening, wherein the third opening is located between the first opening and the second opening, and exposes a portion of the sidewall of the second conductive line and a portion of the sidewall of the conductive component; forming a first sacrificial pattern and a second sacrificial pattern alternately arranged in the vertical direction through the third opening, wherein the first sacrificial pattern is disposed in the same layer as the first dielectric layer, the second sacrificial pattern is disposed in the same layer as the second dielectric layer, and the space occupied by the second sacrificial pattern communicates with the first opening and the second opening. The material of the second sacrificial pattern is different from that of the first sacrificial pattern; the first sacrificial pattern is replaced by a first insulating pattern, wherein the material of the first insulating pattern is oxide; a semiconductor layer covering the second conductive line, the conductive component, the first insulating pattern and the exposed sidewalls of the second sacrificial pattern, a gate dielectric layer covering the semiconductor layer and a first conductive line covering the gate dielectric layer are formed in the third opening, wherein the first conductive line extends vertically on the substrate, and the material of the semiconductor layer includes a metal oxide semiconductor material; the second sacrificial pattern is removed through the first opening and the second opening, and the exposed portion of the semiconductor layer is removed by lateral etching to form a lateral receiving trench, wherein the remaining portion of the semiconductor layer serves as a semiconductor pattern, and the semiconductor pattern is disposed in the same layer as the first insulating pattern; a second insulating pattern is formed in the lateral receiving trench, wherein the material of the second insulating pattern includes oxide, and the second insulating pattern and the first insulating pattern are alternately arranged along the vertical direction to form an oxygen channel structure; the semiconductor pattern is annealed through the oxygen channel structure in an oxygen atmosphere.

[0014] In some embodiments, the conductive component includes a first electrode of a capacitor, and the manufacturing method further includes forming a capacitor dielectric layer and a second electrode in the second opening, wherein the first electrode, the capacitor dielectric layer and the second electrode together form the capacitor.

[0015] In some embodiments, the conductive component includes a third conductive line extending along a second horizontal direction, which intersects the first horizontal direction.

[0016] In some embodiments, the material of the second insulating pattern is the same as the material of the first insulating pattern.

[0017] According to a third aspect of the present disclosure, a method for manufacturing a memory is provided, comprising: forming a stacked structure on a substrate, wherein the stacked structure includes a first dielectric layer and a second dielectric layer alternately arranged in a vertical direction, the first dielectric layer being made of a nitride and the second dielectric layer being made of an oxide; etching the stacked structure to form a first opening, forming a second conductive line disposed in the same layer as the first dielectric layer through the first opening, wherein the second conductive line extends in a first horizontal direction; etching the stacked structure to form a second opening, forming a conductive component disposed in the same layer as the first dielectric layer through the second opening; etching the stacked structure to form a third opening, wherein the third opening is located between the first opening and the second opening; laterally etching the first dielectric layer through the third opening to form a first receiving trench, wherein the first receiving trench exposes a portion of the sidewall of the second conductive line and a portion of the sidewall of the conductive component; and forming an initial insulating pattern in the first receiving trench. The initial insulating pattern is made of oxide and is made of a different material than the second dielectric layer. The initial insulating pattern is laterally etched through the third opening to form a second receiving trench, which exposes a portion of the sidewalls of the second conductive line and the conductive component. The remaining initial insulating pattern serves as the first insulating pattern. A semiconductor pattern is formed in the second receiving trench, the semiconductor pattern being made of metal oxide semiconductor material. The portion of the second dielectric layer opposite to the first insulating pattern and the semiconductor pattern serves as the second insulating pattern. The second insulating pattern and the first insulating pattern are alternately arranged along the vertical direction to form an oxygen channel structure. A gate dielectric layer covering the semiconductor pattern and a first conductive line covering the gate dielectric layer are formed in the third opening, the first conductive line extending vertically on the substrate. The semiconductor pattern is annealed through the oxygen channel structure in an oxygen atmosphere.

[0018] In some embodiments, the conductive component includes a first electrode of a capacitor, and the manufacturing method further includes: forming a capacitor dielectric layer and a second electrode in the second opening, wherein the first electrode, the capacitor dielectric layer, and the second electrode together form the capacitor.

[0019] In some embodiments, the conductive component includes a third conductive line extending along a second horizontal direction, the second horizontal direction intersecting the first horizontal direction.

[0020] In some embodiments, the material of the second insulating pattern is different from the material of the first insulating pattern.

[0021] According to a fourth aspect of the present disclosure, an electronic device is provided, including a processor and a memory provided in any embodiment of the present disclosure. The memory is coupled to the processor.

[0022] In the memory provided in the embodiments of this disclosure, the oxygen channel structure can be used to anneal the metal oxide semiconductor material in the semiconductor pattern at each level under an oxygen atmosphere, thereby helping to reduce oxygen vacancy defects in the metal oxide semiconductor material, reduce the leakage current of the transistor, and improve the performance of the memory. 4. Description of the attached drawings

[0023] Figure 1A is a schematic diagram of a partial planar structure of a three-dimensional memory;

[0024] Figure 1B is a schematic diagram of a cross section taken along line A1-A2 in Figure 1A;

[0025] Figure 1C is a schematic diagram of a cross section taken along line B1-B2 in Figure 1A;

[0026] Figure 2A is a partial planar structure diagram of a memory provided in some embodiments of this disclosure;

[0027] Figure 2B is a schematic diagram of a cross-section taken along lines A1-A2 and B1-B2 in Figure 2A;

[0028] Figure 2C is a schematic diagram of a cross-section taken along lines C1-C2 and D1-D2 in Figure 2A;

[0029] Figure 2D is a partial planar structure diagram of a memory provided in some other embodiments of this disclosure;

[0030] Figure 2E is a schematic diagram of a cross-section taken along lines A1-A2 and B1-B2 in Figure 2D;

[0031] Figure 2F shows another cross-section taken along lines C1-C2 and D1-D2 in Figure 2D;

[0032] Figures 3A-3C are schematic diagrams of a first stage of a manufacturing method provided in some embodiments of this disclosure;

[0033] Figures 4A-4C are schematic diagrams of another stage of a manufacturing method provided in some embodiments of this disclosure;

[0034] Figures 5A-5C are schematic diagrams of another stage of a manufacturing method provided in some embodiments of this disclosure;

[0035] Figures 6A-6C are schematic diagrams of another stage of a manufacturing method provided in some embodiments of this disclosure;

[0036] Figures 7A-7C are schematic diagrams of another stage of a manufacturing method provided in some embodiments of this disclosure;

[0037] Figures 8A-8C are schematic diagrams of another stage of a manufacturing method provided in some embodiments of this disclosure;

[0038] Figures 9A-9C are schematic diagrams of another stage of a manufacturing method provided in some embodiments of this disclosure;

[0039] Figures 10A-10C are schematic diagrams of a first stage of a manufacturing method provided in some other embodiments of this disclosure;

[0040] Figures 11A-11C are schematic diagrams of another stage of a manufacturing method provided in some other embodiments of this disclosure;

[0041] Figures 12A-12C are schematic diagrams of another stage of a manufacturing method provided in some other embodiments of this disclosure;

[0042] Figures 13A-13C are schematic diagrams of another stage of a manufacturing method provided in some other embodiments of this disclosure;

[0043] Figures 14A-14C are schematic diagrams of another stage of a manufacturing method provided in some other embodiments of this disclosure;

[0044] Figures 15A-15C are schematic diagrams of another stage of a manufacturing method provided in some other embodiments of this disclosure;

[0045] Figure 16 is a schematic block diagram of the structure of an electronic device provided in some embodiments of this disclosure. 5. Detailed Implementation

[0046] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0047] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0048] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0049] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0050] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0051] In embodiments of this disclosure, the term "coupling" refers to the operative connection of two (or more) conductive structures to each other. Depending on actual needs, this may include, but is not limited to, the following: 1) two conductive structures are directly electrically connected; 2) two conductive structures are indirectly electrically connected (through other conductive structures); 3) although two conductive structures are not electrically connected (e.g., an insulating layer is provided between them), one of the two conductive structures can control the electrical performance of the other two conductive structures in response to an electrical signal, for example, a gate (or word line) is coupled to an active region (or channel region).

[0052] It should be noted that the technical solutions and technical features described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0053] Figure 1A is a partial planar structural schematic diagram of a three-dimensional memory, Figure 1B is a cross-sectional schematic diagram taken along line A1-A2 in Figure 1A, and Figure 1C is a cross-sectional schematic diagram taken along line B1-B2 in Figure 1A. As shown in Figures 1A-1C, the three-dimensional memory includes multiple bit lines 210', multiple word lines 230', and multiple memory cells MC' located on a substrate 100'. Each memory cell MC' includes a transistor T' and a capacitor C' coupled to the transistor T'. The transistor T' is coupled to the corresponding bit line 210' and the corresponding word line 230'. The transistor T' includes a semiconductor pattern 220', a gate 230' coupled to the semiconductor pattern 220' (a portion of the word line 230' can serve as the gate), and a gate dielectric layer 225' disposed between the semiconductor pattern 220' and the gate 230'. The word line 230' extends along the vertical direction Z on the substrate 100', and the semiconductor pattern 220' surrounds the word line 230'. The capacitor C' includes a first electrode 240', a second electrode 250', and a capacitor dielectric layer 245' disposed between the first electrode 240' and the second electrode 250'.

[0054] As shown in Figures 1A-1C, the three-dimensional memory also includes an etch stop layer 105' on a substrate 100', and alternating silicon oxide layers 120' and silicon nitride layers 110' on the etch stop layer 105'. Semiconductor pattern 220' and first electrode 240' are typically disposed in the same layer as silicon nitride layer 110'. It is understood that Figure 1A is a schematic planar structure diagram taken along one of the silicon nitride layers 110' in Figures 1B and 1C. Additionally, a fill pattern 215' is also shown in Figures 1A-1C, which can be referred to in the following description of the fill pattern 215.

[0055] In their research, the inventors of this application noted that in the aforementioned three-dimensional memory, metal oxides (e.g., indium gallium zinc oxide, IGZO) can be used as the channel material (i.e., the material of semiconductor pattern 220') of the transistor T' in the memory cell MC'. However, the bond energy of the MO bonds (M represents a metal atom, and the MO bond can be, for example, an In-O bond or a Zn-O bond) in the metal oxide is relatively weak, making it easy to break in subsequent manufacturing processes. This leads to the diffusion of metal elements and the generation of a large number of oxygen vacancy defects, resulting in increased leakage current in the transistor and thus affecting device performance. Specifically, in current semiconductor chip manufacturing processes, hydrogen (H2) and hydrogen-containing compounds are widely used, and hydrogen atoms have strong migration capabilities. Therefore, the MO bonds in the metal oxide are easily broken by hydrogen atoms, thereby damaging the channel material.

[0056] In principle, the semiconductor pattern 220' in the aforementioned three-dimensional memory can be annealed in an oxygen atmosphere to repair damage to the channel material and reduce oxygen vacancy defects. However, on the one hand, considering the small thickness of the gate dielectric layer 225' and the limitations of material selection, using it as an oxygen channel structure for oxygen atom migration is not very effective in repairing damage to the channel material; on the other hand, due to the high density of the silicon nitride layer 110', it will block the migration of oxygen atoms, thus making it impossible to use the silicon oxide layer 120' and the silicon nitride layer 110' together to form an oxygen channel structure for oxygen atom migration (the dashed arrow with an "X" in Figure 1C indicates that oxygen atoms cannot migrate downward through the silicon nitride layer). Therefore, even when the semiconductor pattern 220' in the above-mentioned three-dimensional memory is annealed in an oxygen atmosphere, it is often only possible to repair the semiconductor pattern 220' located in the upper layer (such as the top layer and a few layers near the top layer) and achieve a good repair effect (as shown by the dashed arrow in Figure 1C), while it is difficult to repair the semiconductor pattern 220' located in the lower layer (especially the bottom layer and several layers near the bottom layer) and achieve a good repair effect.

[0057] This disclosure provides a memory in at least some embodiments. The memory includes a first conductive line, a semiconductor pattern, a second conductive line, a conductive component, and an oxygen channel structure. The first conductive line extends vertically on a substrate. The semiconductor pattern is coupled to the first conductive line, and the semiconductor pattern is made of a metal oxide semiconductor material. The second conductive line extends horizontally and is coupled to a first end of the semiconductor pattern. The conductive component is coupled to a second end of the semiconductor pattern, and the second end of the semiconductor pattern is opposite to the first end. The oxygen channel structure includes a first insulating pattern and a second insulating pattern alternately arranged vertically. The first insulating pattern is disposed in the same layer as the semiconductor pattern and is in contact with the semiconductor pattern. The materials of both the first insulating pattern and the second insulating pattern include oxides.

[0058] In the memory provided in the embodiments of this disclosure, the oxygen channel structure can be used to anneal the metal oxide semiconductor material in the semiconductor pattern at each level under an oxygen atmosphere, thereby helping to reduce oxygen vacancy defects in the metal oxide semiconductor material, reduce the leakage current of the transistor, and improve the performance of the memory.

[0059] Figure 2A is a partial planar structure schematic diagram of a memory provided in some embodiments of this disclosure; Figure 2B is a cross-sectional schematic diagram taken along lines A1-A2 (corresponding to the left sub-figure) and B1-B2 (corresponding to the right sub-figure) in Figure 2A;

[0060] Figure 2C is a schematic cross-sectional view taken along lines C1-C2 (corresponding to the left sub-figure) and D1-D2 (corresponding to the right sub-figure) in Figure 2A. As shown in Figures 2A-2C, the memory includes multiple first conductive lines 230, multiple semiconductor patterns 220, and multiple second conductive lines 210 disposed on a substrate 100. The semiconductor patterns 220 are made of metal oxide semiconductor materials, such as at least one of indium gallium oxide (IGO), indium zinc oxide (IZO), or indium gallium zinc oxide (IGZO). For example, the material of the semiconductor patterns 220 may include amorphous metal oxides, polycrystalline metal oxides, or a combination of amorphous metal oxides and polycrystalline metal oxides.

[0061] As shown in Figures 2A-2C, a first conductive line 230 extends along the vertical direction Z on the substrate 100. A semiconductor pattern 220 is coupled to the corresponding first conductive line 230 to form a transistor T. For example, as shown in Figures 2A-2C, a gate dielectric layer 225 may be disposed between the semiconductor pattern 220 and the first conductive line 230. The material of the gate dielectric layer 225 may include, but is not limited to, silicon oxide and / or a high-k dielectric.

[0062] As shown in Figures 2A-2C, the second conductive line 210 extends along the first horizontal direction Y, is located at the first end of the semiconductor pattern 220, and is coupled to the first end of the semiconductor pattern 220. For example, as shown in Figure 2A, the second conductive line 210 has a recess facing the semiconductor pattern 220. For example, as shown in Figures 2A-2C, multiple second conductive lines 210 are spaced apart in the vertical direction Z. For example, as shown in Figures 2A-2C, the memory may further include a fill pattern 215, around which the second conductive lines 210 surround; that is, the planar shape of the second conductive lines 210 may be annular. For example, the material of the fill pattern 215 is an insulating material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide.

[0063] As shown in Figures 2A-2C, the memory also includes an oxygen channel structure OC disposed on the substrate 100. The oxygen channel structure OC includes a first insulating pattern 310 and a second insulating pattern 320 arranged alternately along the vertical direction Z. The first insulating pattern 310 is disposed in the same layer as the semiconductor pattern 220 and is in contact with the semiconductor pattern 220. The materials of the first insulating pattern 220 and the second insulating pattern 320 both include oxides (allowing oxygen atoms to diffuse and migrate therein). Therefore, if the semiconductor pattern 220 is annealed in an oxygen atmosphere, oxygen atoms can diffuse and migrate downward through the oxygen channel structure OC (as shown by the dashed arrows in Figures 2B and 2C) and reach the semiconductor patterns of each layer, thereby repairing the semiconductor patterns 220 of each layer and achieving a good repair effect.

[0064] For example, as shown in Figures 2A-2C, the first insulating pattern 310 contacts the side surface (e.g., the outer surface) of the semiconductor pattern 220, and the second insulating pattern 320 contacts the top or bottom surface of the semiconductor pattern 220. In this disclosure, unless otherwise stated, "contact" means "physical contact" (i.e., "direct connection").

[0065] For example, in some examples, as shown in Figures 2A and 2B, the memory may further include a capacitor C located at and coupled to a second end of the semiconductor pattern 220 opposite to the first end. For example, as shown in Figures 2A and 2B, the capacitor C includes a first electrode 240 electrically connected to the second end of the semiconductor pattern 220, a second electrode 250 disposed opposite to the first electrode 240, and a capacitor dielectric layer 245 disposed between the first electrode 240 and the second electrode 250. For example, as shown in Figure 2A, the first electrode 210 has a recess facing the semiconductor pattern 220. It is understood that in this example, the first electrode 240 of the capacitor C can serve as a conductive component coupled to the second end of the semiconductor pattern 220; the capacitor C and the transistor T (which may be referred to as an access transistor) coupled thereto together form a memory cell C, the first conductive line 230 coupled to the access transistor T can serve as a word line, and the second conductive line 210 coupled to the access transistor T can serve as a bit line. In this example, the semiconductor pattern 220, bit line 210, first electrode 240, and first insulating pattern 310 can be disposed in the same layer as the first dielectric layer 110 described below.

[0066] For example, in other examples, as shown in Figures 2A and 2C, the memory may further include a third conductive line 260 extending along a second horizontal direction X, the third conductive line 260 being located at and coupled to a second end of the semiconductor pattern 220 opposite to the first end. For example, as shown in Figure 2A, the third conductive line 260 has a recess facing the semiconductor pattern 220. For example, as shown in Figures 2A and 2C, multiple third conductive lines 260 are spaced apart in the vertical direction Z. It is understood that in this example, the third conductive line 260 can serve as a conductive component coupled to the second end of the semiconductor pattern 220; the third conductive line 260 can serve as a common bit line, the transistor T coupled to the common bit line 260 can be called a gate transistor, the first conductive line 230 coupled to the gate transistor T can serve as a gate line, and the second conductive line 210 coupled to the gate transistor T can serve as a bit line. In this example, the semiconductor pattern 220, bit line 210, common bit line 260, and first insulating pattern 310 can be disposed in the same layer as the first dielectric layer 110 described below. For example, as shown in Figures 2A and 2C, the memory may further include a fill pattern 265, and the third conductive line 260 may surround the fill pattern 265, that is, similar to the second conductive line 210, the planar shape of the third conductive line 260 may also be ring-shaped. For example, the material of the fill pattern 265 may be the same as the material of the fill pattern 215, but is not limited thereto. For example, the first horizontal direction Y and the second horizontal direction X are both perpendicular to the vertical direction Z, and the first horizontal direction Y intersects the second horizontal direction X. For example, the first horizontal direction Y and the second horizontal direction X are perpendicular to each other.

[0067] For example, in some other examples, as shown in Figures 2A-2C, the memory may simultaneously include the first electrode 240 and the third conductive line 260 described above. That is, the conductive component coupled to the second end of the semiconductor pattern 220 may include the first electrode 240 and the third conductive line 260 of the capacitor C.

[0068] In summary, in the embodiments of this disclosure, the conductive component may include at least one of an electrode of a capacitor C and a third conductive line 260 extending along a second horizontal direction X.

[0069] It should be noted that in this disclosure, "first end" and "second end" are used only to refer to the two opposite ends, and the two can be interchanged.

[0070] For example, in the embodiments shown in Figures 2A-2C, the material of the first insulating pattern 310 and the material of the second insulating pattern 320 can be the same. For example, the material of the first insulating pattern 310 and the material of the second insulating pattern 320 are both silicon oxide. It is understood that in the embodiments of this disclosure, there is an interface between the first insulating pattern 310 and the second insulating pattern 320 that are adjacent in the vertical direction Z (even if the material of the first insulating pattern 310 and the material of the second insulating pattern 320 are the same).

[0071] For example, as shown in Figures 2A-2C, the memory may include a first dielectric layer 110 and a second dielectric layer 120 arranged alternately along the vertical direction Z, wherein a first insulating pattern 310 is disposed in the same layer as the first dielectric layer 110, and a second insulating pattern 320 is disposed in the same layer as the second dielectric layer 120. For example, the materials of the first dielectric layer 110 and the second dielectric layer 120 are etch-selective relative to each other. For example, the material of the first dielectric layer 110 includes nitrides; for example, the material of the first dielectric layer 110 includes, but is not limited to, silicon nitride. For example, the material of the second dielectric layer 120 includes oxides; for example, the material of the second dielectric layer 120 includes, but is not limited to, silicon oxide. It is understood that Figure 2A is a schematic planar structure diagram taken along one of the first dielectric layers 110 in Figures 2B and 2C.

[0072] For example, in some examples, the materials of the first insulating pattern 310 and the second insulating pattern 320 are the same as the material of the second dielectric layer 120. For example, the materials of the first insulating pattern 310, the second insulating pattern 320, and the second dielectric layer 120 are all silicon oxide. It is understood that in this example, there is an interface between adjacent second insulating patterns 320 and second dielectric layers 120 (even if they are made of the same material).

[0073] It should be noted that the oxygen channel structure OC can include other configurations, and is not limited to those shown in Figures 2B and 2C. Figure 2D is a partial planar structure schematic diagram of a memory provided by some other embodiments of this disclosure, Figure 2E is a cross-sectional schematic diagram taken along lines A1-A2 and B1-B2 in Figure 2D, and Figure 2F is another cross-sectional schematic diagram taken along lines C1-C2 and D1-D2 in Figure 2D. The differences between the oxygen channel structure OC in the memory shown in Figures 2D-2F and the oxygen channel structure OC in the memory shown in Figures 2A-2C will be briefly described below; the remaining structures in Figures 2D-2F can be referred to the relevant descriptions of the embodiments shown in Figures 2A-2C, and will not be repeated here.

[0074] For example, as shown in Figures 2D-2F, the memory may include a first dielectric layer 110 and a second dielectric layer 120 arranged alternately along the vertical direction Z. A first insulating pattern 310 is disposed on the same layer as the first dielectric layer 110, and a second insulating pattern 320 is the portion of the second dielectric layer 120 opposite to the first insulating pattern 310 and the semiconductor pattern 220. The material of the first dielectric layer 110 includes a nitride. For example, the portion of the second dielectric layer 120 overlapping with the first insulating pattern 310 or the semiconductor pattern 220 can serve as the second insulating pattern 320. It is understood that the material of the second dielectric layer 120 is the same as the material of the second insulating pattern 320, i.e., it is also an oxide.

[0075] For example, in the embodiments shown in Figures 2D-2F, the materials of the first insulating pattern 310 and the second insulating pattern 320 may be different. For example, the material of the first insulating pattern 310 is aluminum oxide, and the material of the second insulating pattern 320 is silicon oxide; it is understood that embodiments of this disclosure include, but are not limited to, these.

[0076] For example, in embodiments of this disclosure, substrate 100 may include a substrate. For example, the substrate material may be silicon, germanium, or silicon-germanium (SiGe). For example, the substrate may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate. In some examples, substrate 100 may also include circuit structures (not shown), wiring layers (not shown), etc., disposed on the substrate; for example, the circuit structures may include some or all of the peripheral circuitry.

[0077] For example, as shown in Figures 2A-2F, the memory may further include an etch stop layer 105 disposed on the substrate 100. The material of the etch stop layer 105 may include, but is not limited to, silicon carbide, silicon carbon oxide (SiCO), or silicon carbon nitride (SiCN).

[0078] For example, as shown in Figures 2A-2F, the semiconductor pattern 220 surrounds the first conductive line 230. The first insulating pattern 310 may include two sub-insulating patterns 310a and 310b located on opposite sides of the semiconductor pattern 220. The first ends of the two sub-insulating patterns 310a and 310b are in contact with the second conductive line 210, and the second ends of the two sub-insulating patterns 310a and 310b are in contact with the first electrode 240 (or the third conductive line 260). It is understood that both sub-insulating patterns 310a and 310b are located outside the semiconductor pattern 220.

[0079] For example, as shown in Figures 2A-2F, the second insulating pattern 320 may include a closed loop pattern surrounding the first conductive line 230.

[0080] For example, in embodiments of this disclosure, the first conductive line 230, the second conductive line 210, the third conductive line 260, the first electrode 240, and the second electrode 250 may include any suitable conductive material, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten, molybdenum, metal silicides, or any combination thereof.

[0081] For example, the materials of the gate dielectric layer 225 and the capacitor dielectric layer 245 include any suitable dielectric material, such as silicon oxide, silicon nitride, high-K dielectric material or any combination thereof; for example, high-K dielectric materials may include, but are not limited to, hafnium oxide (HfO2), zirconium oxide (ZrO2), etc.

[0082] In the memory provided by the above embodiments of this disclosure, the oxygen channel structure OC can be used to anneal the metal oxide semiconductor material in the semiconductor pattern 220 at each level under an oxygen atmosphere, thereby helping to reduce oxygen vacancy defects in the metal oxide semiconductor material, reduce the leakage current of the transistor T, and improve the performance of the memory.

[0083] At least some embodiments of this disclosure also provide a method for manufacturing a memory, which can be used to manufacture the memory shown in the embodiments of FIG2A-2C. For example, the manufacturing method may include the steps S101 to S110.

[0084] S101: A laminated structure is formed on a substrate, wherein the laminated structure includes a first dielectric layer and a second dielectric layer arranged alternately in a vertical direction, the material of the first dielectric layer includes a nitride, and the material of the second dielectric layer includes an oxide;

[0085] S102: Etch the stacked structure to form a first opening, and form a second conductive line disposed in the same layer as the first dielectric layer through the first opening, wherein the second conductive line extends along a first horizontal direction;

[0086] S103: Etch the stacked structure to form a second opening, and form a conductive component disposed in the same layer as the first dielectric layer through the second opening;

[0087] S104: Etch the stacked structure to form a third opening, wherein the third opening is located between the first opening and the second opening, and exposes a portion of the sidewall of the second conductive line and a portion of the sidewall of the conductive component.

[0088] S105: A first sacrificial pattern and a second sacrificial pattern are alternately arranged in a vertical direction through the third opening, wherein the first sacrificial pattern is disposed in the same layer as the first dielectric layer, the second sacrificial pattern is disposed in the same layer as the second dielectric layer, the space occupied by the second sacrificial pattern is connected to the first opening and the second opening, and the material of the second sacrificial pattern is different from the material of the first sacrificial pattern.

[0089] S106: Replace the first sacrificial pattern with the first insulating pattern, wherein the material of the first insulating pattern is an oxide;

[0090] S107: A semiconductor layer covering the second conductive line, the conductive component, the first insulating pattern and the second sacrificial pattern, and an exposed sidewall of the third opening are formed, as well as a gate dielectric layer covering the semiconductor layer and a first conductive line covering the gate dielectric layer, wherein the first conductive line extends in a vertical direction on the substrate, and the material of the semiconductor layer includes a metal oxide semiconductor material.

[0091] S108: Remove the second sacrificial pattern through the first opening and the second opening, and laterally etch away the exposed portion of the semiconductor layer to form a lateral receiving trench, wherein the remaining portion of the semiconductor layer serves as a semiconductor pattern, and the semiconductor pattern is disposed in the same layer as the first insulating pattern.

[0092] S109: A second insulating pattern is formed in a transverse receiving groove, wherein the material of the second insulating pattern includes oxides, and the second insulating pattern and the first insulating pattern are arranged alternately in the vertical direction to form an oxygen channel structure;

[0093] S110: Annealing of semiconductor patterns in an oxygen atmosphere through an oxygen channel structure.

[0094] Figures 3A-9C show schematic diagrams of some stages of the above manufacturing method. The manufacturing method is briefly described below with reference to Figures 3A-9C. Figures 3A, 4A, 5A, 6A, 7A, 8A, and 9A are schematic diagrams of the planar structure of some stages corresponding to Figure 2A. Figures 3B, 4B, 5B, 6B, 7B, 8B, and 9B are schematic diagrams of cross-sections taken along lines A1-A2 (corresponding to the left sub-figure) and B1-B2 (corresponding to the right sub-figure) in Figures 3A, 4A, 5A, 6A, 7A, 8A, and 9A, respectively. Figures 3C, 4C, 5C, 6C, 7C, 8C, and 9C are schematic diagrams of cross-sections taken along lines C1-C2 (corresponding to the left sub-figure) and D1-D2 (corresponding to the right sub-figure) in Figures 3A, 4A, 5A, 6A, 7A, 8A, and 9A, respectively.

[0095] Referring to Figures 3A-3C, an etch stop layer 105 and a stacked structure located on the etch stop layer 105 can be formed on the substrate 100. The stacked structure includes a first dielectric layer 110 and a second dielectric layer 120 arranged alternately in a vertical direction. For example, the etch stop layer 105, the first dielectric layer 110, and the second dielectric layer 120 can each be formed by a deposition process.

[0096] Then, a mask pattern 200 can be formed on the stacked structure, and using the mask pattern 200 as a mask, the stacked structure can be etched to obtain openings O1, O2, and / or openings O4 and O3. For example, opening O1 can serve as a first opening and be used to form a second conductive line; openings O2 and / or O4 can serve as second openings and be used to form conductive components (the conductive components can be an electrode of a capacitor and / or a third conductive line); opening O3 can serve as a third opening and be used to form a transistor and a first conductive line; the third opening O3 is located between the first opening O1 and the second openings O2 / O4. At this time, the first opening O1, the second opening O2 / O4, and the third opening O3 are not interconnected. For example, the etch stop layer 105 is exposed by openings O1, O2, and / or openings O4 and O3, respectively.

[0097] Referring to Figures 4A-4C, a sacrificial fill pattern 125 can first be formed in openings O1, O2, and / or openings O4 and O3. Then, the sacrificial fill pattern 125 in opening O1 can be removed, and a second conductive line 210 disposed in the same layer as the first dielectric layer 110 can be formed through opening O1; the sacrificial fill pattern 125 in opening O2 can be removed, and a first electrode 240 disposed in the same layer as the first dielectric layer 110 can be formed through opening O2; and / or, the sacrificial fill pattern 125 in opening O4 can be removed, and a third conductive line 260 disposed in the same layer as the first dielectric layer 110 can be formed through opening O4. For example, the second conductive line 210 extends along a first horizontal direction Y. For example, the third conductive line 260 extends along a second horizontal direction X. For example, the second horizontal direction X intersects the first horizontal direction Y, for example, they are perpendicular to each other. For example, the sacrificial fill pattern 125 may include a material with etching selectivity relative to the first dielectric layer 110 and the second dielectric layer 120; for example, the material of the sacrificial fill pattern 125 may include polysilicon or a carbon-containing material.

[0098] For example, forming a second conductive line 210 disposed in the same layer as the first dielectric layer 110 through opening O1 may include: laterally etching away portions of the first dielectric layer 110 at each level through opening O1 to form a lateral receiving trench, wherein the lateral receiving trench exposes a portion of the sidewall of the sacrificial fill pattern 125 located in opening O3; conformally depositing a conductive material layer; and back etching the conductive material layer to remove the portion of the conductive material layer outside the lateral receiving trench, the portion of the conductive material layer remaining in the lateral receiving trench serving as the second conductive line 210. For example, as shown in FIG4A, the second conductive line 210 has a recess facing the sacrificial fill pattern 125.

[0099] For example, the formation of the first electrode 240 is similar to that of the second conductive line 210, and will not be described again here. For example, as shown in FIG4A, the first electrode 240 has a recess facing the sacrificial fill pattern 125. For example, the formation of the third conductive line 260 is similar to that of the second conductive line 210, and will not be described again here. For example, as shown in FIG4A, the third conductive line 260 has a recess facing the sacrificial fill pattern 125. For example, the first electrode 240 and / or the third conductive line 260 may be formed simultaneously with the second conductive line 210, but are not limited thereto.

[0100] Referring to Figures 5A-5C, a sacrificial fill pattern 135 can be formed in openings O1, O2, and / or O4, and the sacrificial fill pattern 125 in opening O3 can be removed. At this time, opening O3 exposes a portion of the sidewalls of the second conductive line 210 and a portion of the sidewalls of the conductive components (i.e., the first electrode 240 and / or the third conductive line 260). Then, a portion of the first dielectric layer 110 at each level can be removed by lateral etching through opening O3 to form a lateral receiving trench, and a first sacrificial pattern 301 disposed in the same layer as the first dielectric layer 110 is formed in the lateral receiving trench. For example, the sacrificial fill pattern 135 may include a material with etching selectivity relative to the first dielectric layer 110 and the second dielectric layer 120; for example, the material of the sacrificial fill pattern 135 may include polysilicon or a carbon-containing material. For example, the first sacrificial pattern 301 may include a material with etching selectivity relative to the first dielectric layer 110 and the second dielectric layer 120; for example, the material of the first sacrificial pattern 301 may include aluminum oxide.

[0101] For example, as shown in Figures 5A-5C, the first sacrificial pattern 301 may include two sub-sacrificial patterns 301a and 301b arranged opposite each other. The first ends of the two sub-sacrificial patterns 301a and 301b are in contact with the second conductive line 210, and the second ends of the two sub-sacrificial patterns 301a and 301b are in contact with the first electrode 240 (or the third conductive line 260). It is understood that the formation method of the first sacrificial pattern 301 may be similar to the formation method of the second conductive line 210, and will not be described in detail here.

[0102] Referring to 6A-6C, portions of the second dielectric layer 120 at each level can be removed by lateral etching through opening O3 to form a lateral receiving trench, wherein the lateral receiving trench exposes portions of the sidewalls of the sacrificial fill pattern 135 located in openings O1, O2, and / or O4; then, a second sacrificial pattern 302 disposed in the same layer as the second dielectric layer 120 is formed in the lateral receiving trench. Thus, the formation of the first sacrificial pattern 301 and the second sacrificial pattern 302 alternately arranged in the vertical direction Z through the third opening O3 is achieved. It is understood that the space occupied by the second sacrificial pattern 302 is in communication with openings O1, O2, and / or O4. For example, the second sacrificial pattern 302 can be a closed annular pattern. For example, the second sacrificial pattern 302 can include a material with etching selectivity relative to the first dielectric layer 110, the second dielectric layer 120, and the first sacrificial pattern 301; for example, the material of the second sacrificial pattern 302 can include polysilicon or a carbon-containing material. For example, the material of the second sacrificial pattern 302 can be the same as the material of the sacrificial fill pattern 135. It is understandable that the formation of the second sacrificial pattern 302 can be similar to the formation of the second conductive line 210, and will not be described in detail here.

[0103] Referring to Figures 7A-7C, the first sacrificial pattern 301 can be replaced with the first insulating pattern 310. For example, the first sacrificial pattern 301 can be removed by lateral etching through the opening O3 to form a lateral receiving trench; then, the first insulating pattern 310, which is disposed in the same layer as the first dielectric layer 110, is formed in the lateral receiving trench. For example, the material of the first insulating pattern 310 is an oxide, including but not limited to silicon oxide. For example, as shown in Figures 7A-7C, the first insulating pattern 310 may include two sub-insulating patterns 310a and 310b disposed opposite to each other, with the first ends of the two sub-insulating patterns 310a and 310b contacting the second conductive line 210, and the second ends of the two sub-insulating patterns 310a and 310b contacting the first electrode 240 (or the third conductive line 260). For example, the formation method of the first insulating pattern 310 can be similar to the formation method of the second conductive line 210, and will not be described again here.

[0104] Then, a semiconductor layer 220i covering the second conductive line 210, the conductive component (first electrode 240 or third conductive line 260), the first insulating pattern 310 and the exposed sidewalls of the second sacrificial pattern 302, as well as a gate dielectric layer 225 covering the semiconductor layer 220i and a first conductive line 230 covering the gate dielectric layer 225 can be formed in the opening O3. The first conductive line 230 extends in the vertical direction Z on the substrate 100, and the material of the semiconductor layer 220i includes a metal oxide semiconductor material. For example, a semiconductor material layer can be conformally deposited, and the semiconductor material layer can be etched back to retain the portion of the semiconductor material layer located on the sidewall of the opening O3 as the semiconductor layer 220i. Then, a gate dielectric material layer can be conformally deposited and a conductive material layer can be deposited. The gate dielectric material layer and the conductive material layer located outside the opening O3 can be removed by etch-back and / or chemical mechanical polishing processes, and the gate dielectric material layer and the conductive material layer retained in the opening O3 can serve as the gate dielectric layer 225 and the first conductive line 230, respectively.

[0105] Referring to Figures 8A-8C, the sacrificial fill pattern 135 in openings O1, O2, and / or O4 can be removed. The second sacrificial pattern 302 is removed by lateral etching through openings O1, O2, and / or O4, and the exposed portion of the semiconductor layer 220i is also removed by lateral etching to form a lateral receiving trench HG. The remaining portion of the semiconductor layer 220i serves as the semiconductor pattern 220, which is disposed on the same layer as the first insulating pattern 310. For example, if the material of the second sacrificial pattern 302 is the same as the material of the sacrificial fill pattern 135, the sacrificial fill pattern 135 and the second sacrificial pattern 302 can be removed using the same etching process. It is understandable that during the lateral etching process to remove the exposed portion of the semiconductor layer 220i, the top of the semiconductor layer 220i (i.e., the portion in contact with the mask pattern 200) will be partially or completely etched, and the resulting space will be filled during the subsequent formation of the second insulating pattern. Since the mask pattern 200 and the materials and structures co-layered with it will be removed subsequently by chemical mechanical polishing, even if the top of the semiconductor layer 220i is partially or completely etched, it will not affect the final semiconductor structure. Therefore, the effect of partial or complete etching of the top of the semiconductor layer 220i is ignored in the accompanying drawings.

[0106] Referring to Figures 9A-9C, a second insulating pattern 320 can be formed in the transverse receiving groove HG. For example, the material of the second insulating pattern is an oxide, including but not limited to silicon oxide. For example, the material of the second insulating pattern 320 is the same as the material of the first insulating pattern 310. For example, the second insulating pattern 320 includes a closed loop pattern surrounding the first conductive line 230. For example, the formation method of the second insulating pattern 320 can be similar to the formation method of the second conductive line 210, and will not be described again here.

[0107] Then, a filling pattern 215 can be formed in opening O1; a capacitor dielectric layer 245 and a second electrode 250 can be formed in opening O2; and / or, a filling pattern 265 can be formed in opening O4. The first electrode 240, the capacitor dielectric layer 245, and the second electrode 250 together form the capacitor C. For example, the capacitor dielectric layer 245 and the second electrode 250 can be formed in a similar manner to the gate dielectric layer 225 and the first conductive line 230, and will not be described in detail here. For example, the filling pattern 265 can be formed simultaneously with the filling pattern 215.

[0108] Next, the mask pattern 200 and the materials and structures disposed in the same layer as the mask pattern 200 can be removed by chemical mechanical polishing process to obtain the semiconductor structure shown in Figures 2A-2C, wherein the second insulating pattern 320 and the first insulating pattern 310 are arranged alternately along the vertical direction Z to form an oxygen channel structure OC.

[0109] Finally, the semiconductor patterns 220 at each level can be annealed in an oxygen atmosphere using an oxygen channel structure OC to reduce oxygen vacancy defects, reduce the leakage current of transistor T, and improve memory performance.

[0110] This disclosure also provides, at least some other embodiments, another method for manufacturing a memory, which can be used to manufacture the memory shown in the embodiments of FIG2A, 2D, and 2E. For example, the manufacturing method may include the steps S201 to S210.

[0111] S201: A laminated structure is formed on a substrate, wherein the laminated structure includes a first dielectric layer and a second dielectric layer arranged alternately in a vertical direction, the material of the first dielectric layer includes a nitride, and the material of the second dielectric layer includes an oxide;

[0112] S202: Etch the stacked structure to form a first opening, and form a second conductive line disposed in the same layer as the first dielectric layer through the first opening, wherein the second conductive line extends along a first horizontal direction;

[0113] S203: Etch the stacked structure to form a second opening, and form a conductive component disposed in the same layer as the first dielectric layer through the second opening;

[0114] S204: Etch the stacked structure to form a third opening, wherein the third opening is located between the first opening and the second opening;

[0115] S205: The first dielectric layer is laterally etched through the third opening to form a first receiving groove, wherein the first receiving groove exposes a portion of the sidewall of the second conductive line and a portion of the sidewall of the conductive component;

[0116] S206: An initial insulating pattern is formed in the first receiving groove, wherein the material of the initial insulating pattern is an oxide, and the material of the initial insulating pattern is different from the material of the second dielectric layer;

[0117] S207: The initial insulating pattern is laterally etched through the third opening to form a second receiving groove, wherein the second receiving groove exposes part of the sidewall of the second conductive line and part of the sidewall of the conductive component, and the remaining initial insulating pattern serves as the first insulating pattern.

[0118] S208: A semiconductor pattern is formed in the second receiving trench, wherein the material of the semiconductor pattern includes a metal oxide semiconductor material, the portion of the second dielectric layer opposite to the first insulating pattern and the semiconductor pattern serves as the second insulating pattern, and the second insulating pattern and the first insulating pattern are alternately arranged in the vertical direction to form an oxygen channel structure.

[0119] S209: A gate dielectric layer covering the semiconductor pattern and a first conductive line covering the gate dielectric layer are formed in the third opening, wherein the first conductive line extends in a vertical direction on the substrate;

[0120] S210: Annealing of semiconductor patterns in an oxygen atmosphere through an oxygen channel structure.

[0121] Figures 10A-15C show schematic diagrams of some stages of the above manufacturing method. The manufacturing method is briefly described below with reference to Figures 10A-15C. Figures 10A, 11A, 12A, 13A, 14A, and 15A are schematic diagrams of some stages corresponding to the planar structure of Figure 2D. Figures 10B, 11B, 12B, 13B, 14B, and 15B are schematic diagrams of cross-sections taken along lines A1-A2 (corresponding to the left sub-figure) and B1-B2 (corresponding to the right sub-figure) in Figures 10A, 11A, 12A, 13A, 14A, and 15A, respectively. Figures 10C, 11C, 12C, 13C, 14C, and 15C are schematic diagrams of cross-sections taken along lines C1-C2 (corresponding to the left sub-figure) and D1-D2 (corresponding to the right sub-figure) in Figures 10A, 11A, 12A, 13A, 14A, and 15A, respectively.

[0122] Referring to Figures 10A-10C, an etch stop layer 105 and a stacked structure located on the etch stop layer 105 can be formed on the substrate 100. The stacked structure includes a first dielectric layer 110 and a second dielectric layer 120 arranged alternately in a vertical direction. For example, the etch stop layer 105, the first dielectric layer 110, and the second dielectric layer 120 can each be formed by a deposition process.

[0123] Then, a mask pattern 200 can be formed on the stacked structure, and using the mask pattern 200 as a mask, the stacked structure can be etched to obtain openings O1, O2, and / or openings O4 and O3. For example, opening O1 can serve as a first opening and be used to form a second conductive line; openings O2 and / or O4 can serve as second openings and be used to form conductive components (the conductive components can be an electrode of a capacitor and / or a third conductive line); opening O3 can serve as a third opening and be used to form a transistor and a first conductive line; the third opening O3 is located between the first opening O1 and the second openings O2 / O4. At this time, the first opening O1, the second opening O2 / O4, and the third opening O3 are not interconnected. For example, the etch stop layer 105 is exposed by openings O1, O2, and / or openings O4 and O3, respectively.

[0124] Referring to Figures 11A-11C, a sacrificial fill pattern 125 can first be formed in openings O1, O2, and / or openings O4 and O3. Then, the sacrificial fill pattern 125 in opening O1 can be removed, and a second conductive line 210 disposed in the same layer as the first dielectric layer 110 can be formed through opening O1; the sacrificial fill pattern 125 in opening O2 can be removed, and a first electrode 240 disposed in the same layer as the first dielectric layer 110 can be formed through opening O2; and / or, the sacrificial fill pattern 125 in opening O4 can be removed, and a third conductive line 260 disposed in the same layer as the first dielectric layer 110 can be formed through opening O4. For example, the second conductive line 210 extends along a first horizontal direction Y. For example, the third conductive line 260 extends along a second horizontal direction X. For example, the second horizontal direction X intersects the first horizontal direction Y, for example, they are perpendicular to each other. For example, the sacrificial fill pattern 125 may include a material that has etching selectivity relative to the first dielectric layer 110 and the second dielectric layer 120; for example, the material of the sacrificial fill pattern 125 may include polysilicon or a carbon-containing material.

[0125] For example, the formation methods of the second conductive line 210, the first electrode 240, and the third conductive line 260 in the embodiments shown in Figures 11A-11C can refer to the relevant descriptions of the second conductive line 210, the first electrode 240, and the third conductive line 260 in the embodiments shown in Figures 4A-4C above, and will not be repeated here.

[0126] Referring to Figures 12A-12C, a sacrificial fill pattern 135 can be formed in openings O1, O2, and / or O4, and the sacrificial fill pattern 125 in opening O3 can be removed. Then, the first dielectric layer 110 is laterally etched through opening O3 to form a first receiving trench HG1, wherein the first receiving trench HG1 exposes a portion of the sidewalls of the second conductive line 210 and a portion of the sidewalls of the conductive components (i.e., the first electrode 240 and / or the third conductive line 260). It should be noted that the first dielectric layer 110 can be laterally etched through opening O3 to expose a portion of the sidewalls of the second conductive line 210 and a portion of the sidewalls of the conductive components (i.e., the first electrode 240 and / or the third conductive line 260), and the first dielectric layer 110 can continue to be laterally etched (i.e., over-etched) to obtain the first receiving trench HG1, so that the first receiving trench HG1 can simultaneously accommodate the subsequently formed first insulating pattern and semiconductor pattern. For example, the sacrificial fill pattern 135 may include a material that has etching selectivity relative to the first dielectric layer 110 and the second dielectric layer 120; for example, the material of the sacrificial fill pattern 135 may include polysilicon or a carbon-containing material.

[0127] Referring to Figures 13A-13C, an initial insulating pattern can be formed first in the first receiving tank HG1. The material of the initial insulating pattern is an oxide, and the material of the initial insulating pattern is different from the material of the second dielectric layer. For example, the material of the initial insulating pattern may include aluminum oxide, but is not limited to this. For example, the formation method of the initial insulating pattern may be similar to the formation method of the second conductive line 210 described above, and will not be repeated here.

[0128] Then, the initial insulating pattern can be laterally etched through the third opening O3 to form a second receiving groove HG2, wherein the second receiving groove HG2 exposes part of the sidewall of the second conductive line 210 and part of the sidewall of the conductive component (i.e., the first electrode 240 and / or the third conductive line 260), and the remaining initial insulating pattern serves as the first insulating pattern 310. For example, as shown in Figures 13A-13C, the first insulating pattern 310 may include two sub-insulating patterns 310a and 310b disposed opposite to each other, the first ends of the two sub-insulating patterns 310a and 310b contacting the second conductive line 210, and the second ends of the two sub-insulating patterns 310a and 310b contacting the first electrode 240 (or the third conductive line 260).

[0129] Referring to Figures 14A-14C, a semiconductor pattern 220 can be formed in the second receiving trench. The material of the semiconductor pattern 220 includes a metal oxide semiconductor material. The portion of the second dielectric layer 120 opposite to the first insulating pattern 310 and the semiconductor pattern 220 serves as the second insulating pattern 320. The second insulating pattern 320 and the first insulating pattern 310 are alternately arranged along the vertical direction Z to form an oxygen channel structure (see the oxygen channel structure OC in Figures 2E-2F). For example, the semiconductor pattern 220 can be formed in a similar manner to the formation of the second conductive line 210 described above, and will not be repeated here.

[0130] Then, a gate dielectric layer 225 covering the semiconductor pattern 220 and a first conductive line 230 covering the gate dielectric layer 225 can be formed in the opening O3, wherein the first conductive line 230 extends in the vertical direction Z on the substrate 100. For example, the formation method of the gate dielectric layer 225 and the first conductive line 230 in the embodiments shown in FIG14A-14C can refer to the relevant description of the gate dielectric layer 225 and the first conductive line 230 in the embodiments shown in FIG7A-7C above, and will not be repeated here.

[0131] Referring to Figures 15A-15C, the sacrificial fill pattern 135 in opening O1 can be removed to form a fill pattern 215 in opening O1; the sacrificial fill pattern 135 in opening O2 can be removed to form a capacitor dielectric layer 245 and a second electrode 250 in opening O2; and / or, the sacrificial fill pattern 135 in opening O4 can be removed to form a fill pattern 265 in opening O4. The first electrode 240, the capacitor dielectric layer 245, and the second electrode 250 together form the capacitor C. For example, the formation of the capacitor dielectric layer 245 and the second electrode 250 can be similar to the formation of the gate dielectric layer 225 and the first conductive line 230, and will not be described again here. For example, the fill pattern 265 can be formed simultaneously with the fill pattern 215.

[0132] Next, the mask pattern 200 and the materials and structures disposed in the same layer as the mask pattern 200 can be removed by chemical mechanical polishing process to obtain the semiconductor structure shown in Figures 2D-2F, wherein the second insulating pattern 320 and the first insulating pattern 310 are arranged alternately along the vertical direction Z to form an oxygen channel structure OC.

[0133] Finally, the semiconductor patterns 220 at each level can be annealed in an oxygen atmosphere using an oxygen channel structure OC to reduce oxygen vacancy defects, reduce the leakage current of transistor T, and improve memory performance.

[0134] It is understood that in the embodiments shown in Figures 10A-15C, the semiconductor pattern 220 is disposed outside the opening O3, while in the embodiments shown in Figures 3A-9C, the semiconductor pattern 220 is disposed inside the opening O3. Therefore, the opening area of ​​the opening O3 in the embodiments shown in Figures 10A-15C can be smaller than the opening area of ​​the opening O3 in the embodiments shown in Figures 3A-9C.

[0135] It is worth noting that, in this disclosure, details not described in the manufacturing method embodiments can be referred to the relevant descriptions in the memory embodiments, and details not described in the memory embodiments can be referred to the relevant descriptions in the manufacturing method embodiments.

[0136] At least some embodiments of this disclosure also provide an electronic device. FIG16 is a schematic block diagram of an electronic device provided in some embodiments of this disclosure. As shown in FIG16, the electronic device 1 includes a processor 20 and a memory 10 coupled to each other, wherein the memory 10 is the memory provided in any of the foregoing embodiments.

[0137] For example, processor 20 may include, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), etc. Memory 10 may be configured to store data to be processed by processor 20 and / or data already processed by the processor.

[0138] For example, electronic device 1 includes, but is not limited to, mobile phones, tablets, smart bracelets, wearable electronic devices, virtual reality devices, augmented reality devices, in-vehicle devices, servers, workstations, etc.

[0139] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A memory, comprising: The first conductive line (230) extends in the vertical direction (Z) on the substrate (100); A semiconductor pattern (200) is coupled to the first conductive line, wherein the material of the semiconductor pattern includes a metal oxide semiconductor material; The second conductive line (210) extends along the first horizontal direction (Y) and is coupled to the first end of the semiconductor pattern; Conductive components (240, 260) are coupled to a second end of the semiconductor pattern, the second end of the semiconductor pattern being opposite to the first end; The oxygen channel structure (OC) includes a first insulating pattern (310) and a second insulating pattern (320) arranged alternately along the vertical direction, wherein the first insulating pattern is disposed in the same layer as the semiconductor pattern and is in contact with the semiconductor pattern, and the materials of the first insulating pattern and the second insulating pattern respectively include oxides.

2. The memory according to claim 1, further comprising: A first dielectric layer (110) and a second dielectric layer (120) are alternately arranged along the vertical direction, wherein the first insulating pattern is disposed in the same layer as the first dielectric layer, the second insulating pattern is disposed in the same layer as the second dielectric layer, the material of the first dielectric layer includes nitride, and the material of the second dielectric layer includes oxide.

3. The memory according to claim 2, wherein, The material of the second insulating pattern is the same as that of the first insulating pattern.

4. The memory according to claim 3, wherein, The materials of the first insulating pattern and the second insulating pattern are the same as the material of the second dielectric layer.

5. The memory according to claim 1, further comprising: A first dielectric layer (110) and a second dielectric layer (120) are alternately arranged along the vertical direction, wherein the first insulating pattern is disposed in the same layer as the first dielectric layer, the second insulating pattern is the portion of the second dielectric layer opposite to the first insulating pattern and the semiconductor pattern, and the material of the first dielectric layer includes nitride.

6. The memory according to claim 5, wherein, The material of the second insulating pattern is different from that of the first insulating pattern.

7. The memory according to any one of claims 1-6, wherein, The conductive component includes at least one of an electrode (240) of a capacitor (C) and a third conductive line (260) extending along a second horizontal direction (X), the second horizontal direction intersecting the first horizontal direction.

8. The memory according to claim 7, wherein, The semiconductor pattern surrounds the first conductive line, and the first insulating pattern includes two sub-insulating patterns (310a, 310b) located on opposite sides of the semiconductor pattern. The first ends of the two sub-insulating patterns are in contact with the second conductive line, and the second ends of the two sub-insulating patterns are in contact with the conductive component.

9. The memory according to claim 8, wherein, The second insulating pattern includes a closed loop pattern surrounding the first conductive wire.

10. A method for manufacturing a memory, comprising: A stacked structure is formed on a substrate (100), wherein the stacked structure includes a first dielectric layer (110) and a second dielectric layer (120) arranged alternately along a vertical direction (Z), the material of the first dielectric layer includes a nitride, and the material of the second dielectric layer includes an oxide; The stacked structure is etched to form a first opening (O1), and a second conductive line (210) is formed through the first opening and disposed in the same layer as the first dielectric layer, wherein the second conductive line extends along a first horizontal direction (Y); The stacked structure is etched to form a second opening (O2, O4), and conductive components (240, 260) are formed through the second opening and disposed in the same layer as the first dielectric layer. The stacked structure is etched to form a third opening (O3), wherein the third opening is located between the first opening and the second opening and exposes a portion of the sidewall of the second conductive line and a portion of the sidewall of the conductive component; A first sacrificial pattern (301) and a second sacrificial pattern (302) are alternately arranged along the vertical direction through the third opening, wherein the first sacrificial pattern is disposed in the same layer as the first dielectric layer, the second sacrificial pattern is disposed in the same layer as the second dielectric layer, the space occupied by the second sacrificial pattern is connected to the first opening and the second opening, and the material of the second sacrificial pattern is different from that of the first sacrificial pattern. The first sacrificial pattern is replaced with a first insulating pattern (310), wherein the material of the first insulating pattern is an oxide; A semiconductor layer (220i) covering the exposed sidewalls of the second conductive line, the conductive component, the first insulating pattern and the second sacrificial pattern, a gate dielectric layer (225) covering the semiconductor layer and a first conductive line (230) covering the gate dielectric layer are formed in the third opening, wherein the first conductive line extends in a vertical direction (Z) on the substrate, and the material of the semiconductor layer includes a metal oxide semiconductor material; The second sacrificial pattern is removed through the first opening and the second opening, and the exposed portion of the semiconductor layer is removed by lateral etching to form a lateral receiving trench (HG), wherein the remaining portion of the semiconductor layer serves as a semiconductor pattern (220), and the semiconductor pattern is disposed in the same layer as the first insulating pattern; A second insulating pattern (320) is formed in the transverse receiving groove, wherein the material of the second insulating pattern includes oxides, and the second insulating pattern and the first insulating pattern are alternately arranged along the vertical direction to form an oxygen channel structure (OC); The semiconductor pattern is annealed through the oxygen channel structure in an oxygen atmosphere.

11. The manufacturing method according to claim 10, wherein, The conductive component includes a first electrode (240) of a capacitor (C), and the manufacturing method further includes: A capacitor dielectric layer (245) and a second electrode (250) are formed in the second opening, wherein the first electrode, the capacitor dielectric layer and the second electrode together form the capacitor.

12. The manufacturing method according to claim 10, wherein, The conductive component includes a third conductive line (260) extending along a second horizontal direction (X), which intersects with the first horizontal direction.

13. The manufacturing method according to any one of claims 10-12, wherein, The material of the second insulating pattern is the same as that of the first insulating pattern.

14. A method for manufacturing a memory, comprising: A stacked structure is formed on a substrate (100), wherein the stacked structure includes a first dielectric layer (110) and a second dielectric layer (120) arranged alternately along a vertical direction (Z), the material of the first dielectric layer includes a nitride, and the material of the second dielectric layer includes an oxide; The stacked structure is etched to form a first opening (O1), and a second conductive line (210) is formed through the first opening and disposed in the same layer as the first dielectric layer, wherein the second conductive line extends along a first horizontal direction (Y); The stacked structure is etched to form a second opening (O2, O4), and conductive components (240, 260) are formed through the second opening and disposed in the same layer as the first dielectric layer. The stacked structure is etched to form a third opening (O3), wherein the third opening is located between the first opening and the second opening; The first dielectric layer is laterally etched through the third opening to form a first receiving groove (HG1), wherein the first receiving groove exposes a portion of the sidewall of the second conductive line and a portion of the sidewall of the conductive component; An initial insulating pattern is formed in the first receiving groove, wherein the material of the initial insulating pattern is an oxide, and the material of the initial insulating pattern is different from the material of the second dielectric layer; The initial insulating pattern is laterally etched through the third opening to form a second receiving groove (HG2), wherein the second receiving groove exposes a portion of the sidewall of the second conductive wire and a portion of the sidewall of the conductive component, and the remaining initial insulating pattern serves as the first insulating pattern (310). A semiconductor pattern (220) is formed in the second receiving trench, wherein the material of the semiconductor pattern includes a metal oxide semiconductor material, and the portion of the second dielectric layer opposite to the first insulating pattern and the semiconductor pattern serves as a second insulating pattern (320). The second insulating pattern and the first insulating pattern are alternately arranged along the vertical direction to form an oxygen channel structure (OC). A gate dielectric layer covering the semiconductor pattern and a first conductive line (230) covering the gate dielectric layer are formed in the third opening, wherein the first conductive line extends on the substrate along the vertical direction; The semiconductor pattern is annealed through the oxygen channel structure in an oxygen atmosphere.

15. The manufacturing method according to claim 14, wherein, The conductive component includes a first electrode (240) of a capacitor (C), and the manufacturing method further includes: A capacitor dielectric layer (245) and a second electrode (250) are formed in the second opening, wherein the first electrode, the capacitor dielectric layer and the second electrode together form the capacitor.

16. The manufacturing method according to claim 14, wherein, The conductive component includes a third conductive line (260) extending along a second horizontal direction (X), which intersects with the first horizontal direction.

17. The manufacturing method according to any one of claims 14-16, wherein, The material of the second insulating pattern is different from that of the first insulating pattern.

18. An electronic device (1), comprising: Processor (20); as well as The memory (10) according to any one of claims 1-9, wherein the memory is coupled to the processor.

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