Solar cell, photovoltaic module, and solar cell manufacturing method

Abstract

The present application relates to the technical field of solar cells, and discloses a solar cell, a photovoltaic module, and a solar cell manufacturing method, used to solve the problem of poor film quality after patterning in the prior art. The solar cell comprises: a semiconductor substrate and a first doped semiconductor layer. The semiconductor substrate comprises a first surface and a second surface opposite to each other, and the first surface has first regions and second regions alternately distributed along a first direction. The first doped semiconductor layer is disposed in the first regions, and is absent from the second regions. Side surfaces of the first doped semiconductor layer adjacent to the respective second regions have a wavy shape along a second direction, the first direction being different from the second direction. Along the first direction, a distance between a protrusion and a depression of the wavy shape is less than or equal to 4 μm; and / or, an average roughness of the wavy shape extending along the second direction is less than or equal to 2.4 μm.

Description

A solar cell, a photovoltaic module, and a method for manufacturing a solar cell.

[0001] This application claims priority to Chinese Patent Application No. 202510074466.4, filed on January 16, 2025, entitled "A Solar Cell, a Photovoltaic Module and a Method for Manufacturing a Solar Cell", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of solar cell technology, and more particularly to a solar cell, a photovoltaic module, and a method for manufacturing a solar cell. Background Technology

[0003] A solar cell is a device that utilizes solar energy, directly converting light energy into electrical energy through the photoelectric effect.

[0004] Current solar cells include BC cells (Back Contact cells), and patterning BC cells is a crucial step in the solar cell fabrication process. Specifically, precise patterning is required during BC cell fabrication, after which the necessary film layers are formed.

[0005] However, the quality of the patterned film layer in existing technologies is poor. Therefore, how to improve the film quality of at least some layers in solar cells is a technical problem that the industry urgently needs to solve.

[0006] Application content

[0007] The purpose of this application is to provide a solar cell, a photovoltaic module, and a method for manufacturing a solar cell, for improving the film quality of at least some of the film layers in a solar cell.

[0008] To achieve the above objectives, in a first aspect, this application provides a solar cell. The solar cell includes a semiconductor substrate and a first doped semiconductor layer. The semiconductor substrate includes a first surface and a second surface opposite to each other. The first surface has a first region and a second region alternately distributed along a first direction. The first doped semiconductor layer is disposed in the first region, and no first doped semiconductor layer is disposed in the second region. The side of the first doped semiconductor layer near the second region has a wavy shape along a second direction, where the first direction is different from the second direction. Along the first direction, the distance between the protrusions and depressions of the wavy shape is less than or equal to 4 μm; and / or, the undulation of the wavy shape extending along the second direction is less than or equal to 2.4 μm.

[0009] Compared with the prior art, in the solar cell provided in this application, the side of the first doped semiconductor layer near the second region has a wavy shape along the second direction, where the first direction differs from the second direction. Along the first direction, the distance between the protrusions and depressions of the wavy shape is less than or equal to 4 μm; and / or, the undulation of the wavy shape extending along the second direction is less than or equal to 2.4 μm. Therefore, the wavy shape of the side of the first doped semiconductor layer is relatively flat, resulting in better film formation quality and a more uniform and neat film layer at the junction of the first and second regions. For example, the passivation film layer subsequently formed at the junction of the first and second regions has better film formation quality, improving the passivation effect. Furthermore, a preset region is selected, and the junction of the first and second regions is located within this preset region. When a film layer needs to be formed within the preset region, and film layers formed at the junction are excluded (in other words, film layers formed at the junction in the preset region have poorer quality and less practical effect), the area on the surface where the film layer is actually formed is the effective region. Because the wavy shape on the side of the first doped semiconductor layer is relatively flat, the area of ​​the aforementioned effective region is larger than that when the wavy shape on the side of the first doped semiconductor layer is uneven. Based on this, a larger error margin can be provided for subsequent processing (such as patterning processes, patterning other films on the first doped semiconductor layer), improving process accuracy and thus enhancing the quality of the solar cell.

[0010] From a process and structural perspective, the first doped semiconductor layer is fabricated, followed by the first patterning to expose the second region. Subsequent operations then proceed. This is because the first patterning requires the complete removal of the mask layer and the first doped semiconductor layer from the second region, leaving no residue. Any residue would affect the film quality in the second region, consequently impacting passivation and ultimately the solar cell's power generation performance. Furthermore, the wavy shape represents the interface between the first doped semiconductor layer and the second region. The unevenness of this interface affects the film quality in the second region, resulting in thinner films in certain areas and reducing the solar cell's power generation efficiency. Since the mask layer and the first doped semiconductor layer are relatively thick, to create a smaller unevenness at this interface (i.e., less undulation in the wavy shape and a smaller distance between protrusions and depressions), considering engineering efficiency and semiconductor substrate damage, if a laser removal process for the first doped semiconductor layer is used, a low-energy spot with a high overlap rate is preferred. This results in a smaller unevenness, minimizing semiconductor substrate damage while ensuring cleaner removal of the mask layer and the first doped semiconductor layer. It should be noted that the laser spot with high overlap is only one example. There may be other process methods with different characteristics (such as photolithography and etchant etching; in the etchant etching process, the wave shape after etching can be controlled by controlling process details such as the viscosity, leveling, and roughness of the stencil opening) to achieve the corresponding requirements.

[0011] In one implementation, along the first direction, the distance between the protrusions and depressions of the wave shape is greater than or equal to 1 μm and less than or equal to 4 μm.

[0012] In one implementation, along a first direction, the distance between the protrusions of the wave shape and the depressions adjacent to the protrusions is greater than or equal to 1 μm and less than or equal to 4 μm.

[0013] At the edge of the first region (near the boundary between the first and second regions), carrier recombination occurs, and the magnitude of the recombination current is directly related to the edge length. A smooth edge with minimal undulation can reduce the edge region length, decrease carrier recombination, and improve battery performance. Therefore, when the distance between the protrusions and adjacent depressions in the wavy shape meets the aforementioned range, the edge region length can be reduced, carrier recombination decreased, and battery performance improved. Furthermore, a smoother edge allows for a more uniform gas atmosphere during subsequent chemical vapor deposition, facilitating the formation of a more uniform film at the boundary between the first and second regions.

[0014] In one implementation, along the second direction, the distance between two adjacent protrusions of the wave shape is greater than or equal to 5 μm and less than or equal to 20 μm.

[0015] With the above technical solution, the edge of the first doped semiconductor layer near the second region is smoother. This not only further improves the film formation quality of the film layer formed at the junction of the first and second regions, but also reduces the length of the edge region, reduces carrier recombination, and improves battery performance.

[0016] In one implementation, the root mean square roughness of the wave shape extending along the second direction is less than or equal to 2.7 μm.

[0017] At the edge of the first region (near the boundary between the first and second regions), carrier recombination occurs, and the magnitude of the recombination current is directly related to the edge length. Smooth edges and low roughness can reduce the length of the edge region, decrease carrier recombination, and improve battery performance. Therefore, when the root mean square roughness of the wavy shape extending along the second direction is less than or equal to 2.7 μm, the length of the edge region can be reduced, carrier recombination can be decreased, and battery performance can be improved. Furthermore, smoother edges allow for a more uniform gas atmosphere during subsequent chemical vapor deposition, facilitating the formation of a more uniform film at the boundary between the first and second regions.

[0018] In one implementation, along a first direction, the second region includes a third region adjacent to the first region and a fourth region distant from the first region, with the third region located between the fourth region and the first region. Both the surfaces of the third and fourth regions have pyramidal texture structures, and the dimensional uniformity of the pyramidal texture structures on the surfaces of the third and fourth regions is approximately equal; and / or, along the direction from the first surface to the second surface, the height difference between the surface of the semiconductor substrate in the third region and the surface of the semiconductor substrate in the first region is greater than the height difference between the surface of the semiconductor substrate in the fourth region and the surface of the semiconductor substrate in the first region.

[0019] With the above technical solution, since both the surfaces of the third and fourth regions have pyramidal texture structures, the contact area between the film layer and the semiconductor substrate can be increased when subsequent film layers are formed on the third and fourth regions. In particular, when the film layer is a passivation layer, the passivation effect on the third and fourth regions can be improved, reducing the carrier recombination rate on the surfaces of the third and fourth regions, thereby improving the photoelectric conversion efficiency of the solar cell. Furthermore, the pyramidal texture structures on the surfaces of the third and fourth regions have approximately equal dimensional uniformity. In this case, the film layers subsequently formed on the surfaces of the third and fourth regions are more uniform, have better film formation quality, and better film density, which is beneficial to improving the quality and performance of the solar cell.

[0020] In one implementation, along the direction from the first surface to the second surface, the height difference between the surface of the semiconductor substrate in the second region and the surface of the semiconductor substrate in the first region is greater than or equal to 1 μm and less than or equal to 10 μm.

[0021] With the above technical solution, the first doped semiconductor layer and the film layer subsequently formed on at least a portion of the surface of the second region can be staggered along the thickness direction of the semiconductor substrate to avoid mutual influence between the first doped semiconductor layer and the subsequently formed film layer, or relative influence between the structures corresponding to the first doped semiconductor layer and the subsequently formed film layer. For example, when the film layer is a second doped semiconductor layer with a conductivity type opposite to that of the first doped semiconductor layer, the height difference between the surface of the semiconductor substrate in the second region and the surface of the semiconductor substrate in the first region is within the above-mentioned range. This can prevent the electrode structure of the first doped semiconductor layer and the second doped semiconductor layer with opposite conductivity types from being staggered along the thickness direction of the semiconductor substrate due to the small height difference, thereby reducing the risk of leakage. Furthermore, compared to the differences in the recess depth after subsequent wet etching caused by the large and uneven thermal damage to the semiconductor substrate during laser patterning; and the need to subsequently wet-etch away a portion of the semiconductor substrate thickness (the thermal damage layer is generally 10-20 μm) due to the large damage to the semiconductor substrate, which leads to the need for a thicker silicon wafer for battery fabrication. This application employs a non-destructive laser patterning method, which minimizes thermal damage to the semiconductor substrate and eliminates the need for subsequent wet polishing steps to remove the damaged layer. Therefore, it achieves thinning of the semiconductor substrate while reducing process time.

[0022] In one implementation, the solar cell further includes a second doped semiconductor layer. The second doped semiconductor layer is disposed on a second region and extends over a portion of the first doped semiconductor layer; the second doped semiconductor layer and the first doped semiconductor layer have opposite conductivity types. In this case, the solar cell is a hybrid back-contact cell.

[0023] In one implementation, the first doped semiconductor layer includes a first doped polycrystalline silicon layer; the second doped semiconductor layer includes a doped amorphous silicon layer and / or a doped microcrystalline silicon layer.

[0024] When the above technical solution is adopted, the first doped semiconductor layer includes a first doped polycrystalline silicon layer. In this case, compared with the doped amorphous silicon layer, the doped polycrystalline silicon layer has higher carrier transport characteristics. Therefore, when the first doped semiconductor layer is a doped polycrystalline silicon layer, the carrier recombination rate can be further reduced, which is beneficial to improving the photoelectric conversion efficiency of the hybrid back contact cell.

[0025] In one implementation, in the first region: the second doped semiconductor layer is disposed at a location of a portion of the first doped semiconductor layer as a stacked region, and in the stacked region: the second doped semiconductor layer has an undulating morphology along the first direction at a location close to the first region.

[0026] In one implementation, in the first region: the second doped semiconductor layer is disposed at a location of a portion of the first doped semiconductor layer as a stacked region; in the thickness direction of the solar cell, the second region also has a tilted region near the first region; the thickness of the second doped semiconductor layer in the stacked region is greater than the thickness in the tilted region; and / or, the thickness of the second doped semiconductor layer in the stacked region is greater than the thickness outside the tilted region of the second region.

[0027] In one implementation, the second region includes a doped region and two spacer regions. Along a first direction, the doped region is located between the two spacer regions; along the first direction, the spacer regions are located between the first region and the doped region; the side of the first doped semiconductor layer near the spacer regions is wavy along a second direction. The solar cell further includes a second doped semiconductor layer and a surface passivation layer. The second doped semiconductor layer is disposed in the doped region, and the second doped semiconductor layer has an opposite conductivity type to the first doped semiconductor layer. The surface passivation layer is disposed on the first doped semiconductor layer, the second doped semiconductor layer, and the spacer regions.

[0028] At this point, the aforementioned solar cell is a tunneling oxide passivated back contact solar cell (TOPCon Back Contact, abbreviated as TBC). Furthermore, the spacer region can isolate the first doped semiconductor layer and the second doped semiconductor layer, reducing the carrier recombination rate at the lateral boundary between the two layers, which is beneficial for improving the photoelectric conversion efficiency of the solar cell. Even further, the surface passivation layer can passivate one side of the TBC, reducing the carrier recombination rate on that side.

[0029] In one implementation, the first doped semiconductor layer includes a second doped polysilicon layer; the second doped semiconductor layer includes a third doped polysilicon layer.

[0030] In one implementation, the solar cell further includes a surface passivation layer. The surface passivation layer is disposed on the second region and extends onto the first doped semiconductor layer. In conjunction with the foregoing description, this solar cell is a tunnel oxide passivated contact (TOPCon) cell. Furthermore, the surface passivation layer can passivate one side of the first surface of the TOPCon, reducing the carrier recombination rate on that side.

[0031] In one implementation, along the first direction, the distance between the protrusions of the wave shape and the depressions adjacent to the protrusions is L1;

[0032] Along the second direction, the distance between adjacent protrusions or adjacent depressions in the wave shape is L2;

[0033] (L1 / L2) ranges from 0.03 to 0.9.

[0034] In one implementation, in the thickness direction of the solar cell, the second region near the first region further has an inclined region, and the semiconductor substrate surface on the inclined region has an inclined angle α between it and the surface defined by the first direction and the second direction, where α is 20° to 75°, preferably 30° to 70°, and more preferably 35° to 65°.

[0035] Secondly, this application also provides a photovoltaic module. The photovoltaic module includes a cell string and an encapsulation layer. The cell string is formed by connecting multiple solar cells as described in the above-mentioned technical solutions, and the encapsulation layer is used to cover the surface of the cell string.

[0036] The beneficial effects of the second aspect and its various implementations in this application can be found in the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0037] Thirdly, this application also provides a method for manufacturing a solar cell. The method for manufacturing the solar cell includes:

[0038] First, a semiconductor substrate is provided; the semiconductor substrate includes opposing first and second surfaces; the first surface has first and second regions alternately distributed along a first direction;

[0039] Next, a first doped semiconductor layer is formed on the entire first surface;

[0040] Next, a mask layer is formed over the entire first doped semiconductor layer;

[0041] Next, the mask layer and the first doped semiconductor layer located in the second region are processed to obtain the first doped semiconductor layer located in the first region, and no first doped semiconductor layer is formed on the second region;

[0042] The side of the first doped semiconductor layer near the second region is wavy along the second direction; the first direction is different from the second direction; along the first direction, the distance between the protrusions and depressions of the wavy shape is less than or equal to 4 μm; and / or, the undulation of the wavy shape extending along the second direction is less than or equal to 2.4 μm.

[0043] The beneficial effects of the third aspect and its various implementations in this application can be found in the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 is a schematic diagram of the structure of the first type of solar cell in the embodiment of this application;

[0046] Figure 2 is a schematic diagram of the structure of the second type of solar cell in the embodiment of this application;

[0047] Figure 3 is a schematic diagram of the structure of the third type of solar cell in the embodiments of this application;

[0048] Figure 4 is a top-view SEM image of the solar cell portion structure in an embodiment of this application;

[0049] Figure 5 is a top-view SEM image of a portion of the structure of a solar cell in the prior art;

[0050] Figures 6 and 7 are top-view SEM images of a portion of the solar cell structure in an embodiment of this application;

[0051] Figure 8 is a partially enlarged top view of the solar cell structure in an embodiment of this application;

[0052] Figure 9 shows a partial structural schematic diagram of the first surface of a semiconductor substrate of a solar cell according to an embodiment of this application.

[0053] Reference numerals: 1-Semiconductor substrate, 10-First region, 11-Second region, 110-Doped region, 111-Spacer region, 12-Preset region; 2-First doped semiconductor layer, 3-Second doped semiconductor layer, 4-First passivation layer, 5-Second passivation layer, 6-Transparent conductive layer, 7-Surface passivation layer, 8-First electrode, 9-Second electrode, 13-Tilted region. Specific Implementation

[0054] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0055] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0056] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise expressly specified. "Several" means one or more, unless otherwise expressly specified.

[0057] In the description of this application, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0058] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0059] To address the aforementioned technical problems, in a first aspect, this application provides a solar cell. Referring to Figures 1 to 4, the solar cell includes a semiconductor substrate 1 and a first doped semiconductor layer 2. The semiconductor substrate 1 includes a first surface and a second surface opposite to each other. The first surface has a first region 10 and a second region 11 alternately distributed along a first direction A. The first doped semiconductor layer 2 is disposed in the first region 10, and no first doped semiconductor layer 2 is formed on the second region 11. The side of the first doped semiconductor layer 2 near the second region 11 has a wavy shape along a second direction B, where the first direction A is different from the second direction B. It should be noted that Figures 1 to 3 are merely schematic diagrams of the solar cell structure, used to aid in understanding this application. The wavy shape refers to a shape with undulations along the second direction B; that is, any undulation is the wavy shape referred to in this application.

[0060] In this case, along the first direction, the distance between the crests (protrusions) and troughs (depressions) of the wave shape is less than or equal to 4 μm. Therefore, the wave shape has a smaller amplitude of undulation in the first direction, resulting in a relatively flat wave shape. Firstly, at the edge of the first region (near the boundary between the first and second regions), there is a problem of edge recombination of charge carriers. The magnitude of the recombination current is directly related to the edge length. A flat edge with less undulation can reduce the length of the edge region, reduce charge carrier recombination, and improve battery performance. Secondly, the relatively flat wave shape in the first direction results in better film quality and a more uniform and neat film layer formed subsequently at the boundary between the first region 10 and the second region 11 (e.g., a second doped semiconductor layer 3 with a conductivity type opposite to the first doped semiconductor layer 2, or a passivation layer, or a transparent conductive layer 6, etc.). For example, when a film is formed at the boundary between the first region 10 and the second region 11 using Chemical Vapor Deposition (CVD), the relatively flat wave shape has less impact on the CVD atmosphere, resulting in a more uniform distribution of the atmosphere in the space at the boundary between the first region 10 and the second region 11. This prevents the atmosphere from being disrupted by excessive undulations, thus facilitating film deposition at the boundary and leading to better film quality. Furthermore, a predetermined region 12 is selected, with the boundary between the first region 10 and the second region 11 located within this region. When a film needs to be formed within the predetermined region, and films formed at the boundary are excluded (in other words, films formed at the boundary within the predetermined region are of poor quality and have less practical effect), the area on the surface where the film is actually formed is the effective region. Referring to Figures 4 and 5, because the wave shape on the side of the first doped semiconductor layer 2 is relatively flat, the area of ​​the effective region is larger than the area when the wave shape on the side of the first doped semiconductor layer 2 is uneven (see Figure 5). Based on this, a larger error margin can be provided for subsequent processing (such as patterning processes, patterning other film layers on the first doped semiconductor layer), improving process accuracy and thus improving the quality of solar cells.

[0061] In some embodiments, along the first direction, the distance between the crests and troughs of the wave shape is greater than or equal to 1 μm and less than or equal to 4 μm. For example, the distance between the crests and troughs of the wave shape can be 1 μm, 1.2 μm, 1.5 μm, 1.8 μm, 2 μm, 2.3 μm, 2.5 μm, 2.8 μm, 3 μm, 3.3 μm, 3.5 μm, 3.8 μm, or 4 μm, etc. It should be noted that the aforementioned "distance between the crests and troughs of the wave shape" can refer to the distance between a wave crest and the trough adjacent to that crest.

[0062] It should be noted that the wave crests in the wave shape of this application can be understood as convexities, and the wave troughs can be understood as depressions. All wave crests appearing in this application are convexities, and all wave troughs appearing in this application are depressions. The wave crests and troughs in the wave shape of this application are not regular sine or cosine waves. In actual product measurement, the edge morphology contours at a certain magnification (e.g., between 200x and 10000x magnification under SEM, such as 200x, 300x, 500x, 1000x, 1500x, 2000x, 3000x, 5000x, 10000x, any magnification) are used for calculation, or the contours are drawn to form a relatively regular trend for comparison. This method can ignore extremely subtle fluctuations and compare the main contours.

[0063] Figure 8 is an enlarged schematic diagram of a partial wavy shape of the solar cell structure. For example, referring to Figures 7 and 8, a reference line C is selected along the first direction A at the boundary line (i.e., the wavy line M) between the first region 10 and the second region 11. This reference line C is parallel to the second direction B and intersects the wavy shape near the side of the first doped semiconductor layer 2 of the second region 11. On one side of the reference line C along the first direction A, the wavy shape has several protrusions (bumps or crests), and on the other side of the reference line C, the wavy shape has several depressions (dents or troughs).

[0064] For example, in Figure 8, the wave shape to the left of reference line C is defined as a convex shape, and the wave shape to the right of reference line C is defined as a concave shape. Then the wave shape in Figure 8 has 6 convex shapes and 5 concave shapes.

[0065] Preferably, referring to Figure 4, along the first direction A, the distance L1 between the crest of the wave shape and the trough adjacent to the crest is greater than or equal to 1 μm and less than or equal to 4 μm. For example, the distance L1 between the crest of the wave shape and the trough adjacent to the crest can be 1 μm, 1.2 μm, 1.5 μm, 1.8 μm, 2 μm, 2.06 μm, 2.3 μm, 2.5 μm, 2.75 μm, 2.8 μm, 3 μm, 3.3 μm, 3.5 μm, 3.8 μm, or 4 μm, etc. As shown in Figure 4, L1 is 2.06 μm and 2.75 μm respectively. At the edge of the first region (near the boundary between the first and second regions), there is an edge recombination problem of charge carriers, and the magnitude of the recombination current is directly related to the edge length. A smooth edge with minimal undulation can reduce the length of the edge region, reduce charge carrier recombination, and improve battery performance. Therefore, when the distance between the crests and adjacent troughs of the wave shape meets the above-mentioned range, the length of the edge region can be reduced, carrier recombination can be decreased, and battery performance can be improved. On the other hand, a smoother edge allows for a more uniform gas atmosphere during subsequent chemical vapor deposition of the film, which is beneficial for forming a more uniform film at the boundary between the first and second regions.

[0066] And / or, the average roughness Ra of the wavy shape extending along the second direction is less than or equal to 2.4 μm. For example, the average roughness Ra of the wavy shape extending along the second direction may be 2.4 μm, 2.3 μm, 2.2 μm, 2.1 μm, 2.0 μm, 1.9 μm, 1.8 μm, 1.7 μm, 1.6 μm, 1.5 μm, or 1.4 μm, etc.

[0067] It should be noted that, in this application, the average roughness of the wave shape extending along the second direction can be understood as the degree of undulation. All the average roughness appearing in this application is the degree of undulation.

[0068] Optionally, one example of determining the average roughness or undulation of the wave shape extending along the second direction could be: for example, selecting a reference line in the second direction that intersects the wave shape on the side of the first doped semiconductor layer near the second region. The distances from the concave points of the wave shape to the reference line and the distances from the convex points of the wave shape to the reference line are then averaged. A larger average indicates greater undulation, and a smaller average indicates less undulation. The locations of the concave and convex points can be roughly determined based on the distribution trend of the wave shape in the figure; once the approximate range of the locations is determined, the trend of their undulation will be similar. A convex point refers to the point along the second direction B furthest from the reference line for a given convexity, or the point along the second direction B closest to the point furthest from the reference line. The definition of the concave point is similar and will not be repeated here.

[0069] More specifically, referring to Figure 8, select multiple concave and convex points adjacent to each other along the second direction B, and measure the distances from each concave and convex point to the reference line C. The directions of these distances are all parallel to the first direction A. Then, calculate the arithmetic or geometric mean of the distances from these multiple concave and convex points to the reference line C, which serves as the degree of undulation of the wave shape. Here, "multiple concave and convex points" refers to two or more points; the specific values ​​are not limited.

[0070] For example, in Figure 8, ten concave and convex points adjacent to each other along the second direction B are selected. The distances from these ten concave and convex points to the reference line C are measured as R10, R11, R12, R13, R14, R15, R16, R17, R18, and R19, respectively. The directions of these distances are all parallel to the first direction A. Then, the arithmetic mean of the distances from these ten concave and convex points to the reference line C is calculated as (R10 + R11 + R13 + ... + R18 + R19) / 10, which is used as the degree of undulation of the wave shape or the average roughness of the wave shape. It should be noted that in this application, in the process of determining the crests (convexities) and troughs (concaveities) of the wave shape, the two are only determined as crests (convexities) and troughs (concaveities) if the distance between them along the first direction A is greater than or equal to 1 μm.

[0071] Referring to Figures 1 to 5, in the solar cell provided in this embodiment, the side of the first doped semiconductor layer 2 near the second region 11 has a wavy shape along the second direction B, where the first direction A is different from the second direction B. Along the first direction A, the distance between the peaks and troughs of the wavy shape is greater than or equal to 1 μm and less than or equal to 4 μm; and / or, the average roughness of the wavy shape extending along the second direction B is less than or equal to 2.4 μm. Therefore, the wavy shape on the side of the first doped semiconductor layer 2 is relatively flat, resulting in better film quality and a more uniform and neat film layer in the subsequent film layer formed at the junction of the first region 10 and the second region 11 (e.g., a second doped semiconductor layer 3 with a conductivity type opposite to that of the first doped semiconductor layer 2, or a passivation layer, or a transparent conductive layer 6, etc.). For example, when a film is formed at the boundary between the first region 10 and the second region 11 using Chemical Vapor Deposition (CVD), the relatively flat wave shape has less impact on the CVD atmosphere, resulting in a more uniform distribution of the atmosphere in the space at the boundary between the first region 10 and the second region 11. This prevents the atmosphere from being disrupted by excessive undulations, thus facilitating film deposition at the boundary and leading to better film quality. Furthermore, a predetermined region 12 is selected, with the boundary between the first region 10 and the second region 11 located within this region. When a film needs to be formed within the predetermined region, and films formed at the boundary are excluded (in other words, films formed at the boundary within the predetermined region are of poor quality and have less practical effect), the area on the surface where the film is actually formed is the effective region. Referring to Figures 4 and 5, because the wave shape on the side of the first doped semiconductor layer 2 is relatively flat, the area of ​​the effective region is larger than the area when the wave shape on the side of the first doped semiconductor layer 2 is uneven (see Figure 5). Based on this, a larger error margin can be provided for subsequent processing (such as patterning processes, patterning other film layers on the first doped semiconductor layer), improving process accuracy and thus improving the quality of solar cells.

[0072] From a process and structural perspective, the first doped semiconductor layer is fabricated, followed by the first patterning to expose the second region. Subsequent operations then proceed. This is because the first patterning requires the complete removal of the mask layer and the first doped semiconductor layer from the second region, leaving no residue. Any residue would affect the film quality in the second region, consequently impacting passivation and ultimately the solar cell's power generation performance. Furthermore, the wavy shape represents the interface between the first doped semiconductor layer and the second region. The unevenness of this interface affects the film quality in the second region, resulting in thinner films in certain areas and reducing the solar cell's power generation efficiency. Since the mask layer and the first doped semiconductor layer are relatively thick, to create a smaller unevenness at this interface (i.e., less undulation in the wavy shape and a smaller distance between protrusions and depressions), considering engineering efficiency and semiconductor substrate damage, if a laser removal process for the first doped semiconductor layer is used, a low-energy spot with a high overlap rate is preferred. This results in a smaller unevenness, minimizing semiconductor substrate damage while ensuring cleaner removal of the mask layer and the first doped semiconductor layer. It should be noted that the laser spot with high overlap is only one example. There may be other process methods with different characteristics (such as photolithography and etchant etching; in the etchant etching process, the wave shape after etching can be controlled by controlling process details such as the viscosity, leveling, and roughness of the stencil opening) to achieve the corresponding requirements.

[0073] In practical applications, the materials of the semiconductor substrates in this application are not specifically limited, as long as they can be used in the solar cells provided in this application. For example, the semiconductor substrate can be any semiconductor material such as silicon, germanium-silicon, germanium, or gallium arsenide.

[0074] In some embodiments, the semiconductor substrate can be an N-type semiconductor substrate, a P-type semiconductor substrate, or a semiconductor substrate of a similar intrinsic conductivity type. The N-type semiconductor substrate is doped with an N-type dopant element, which can be any one of group V elements such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As). The P-type semiconductor substrate is doped with a P-type dopant element, which can be any one of group III elements such as boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0075] In some embodiments, the crystal type of the semiconductor substrate may be single crystal or polycrystalline, etc.

[0076] It should be understood that the first surface mentioned above is the backlight surface, and the second surface is the light-facing surface. The light-facing surface (i.e., the second surface) of the semiconductor substrate can be a plane, or, as shown in Figures 1 to 3, the light-facing surface of the semiconductor substrate 1 can also be a textured surface. Since a textured surface has a light-trapping effect, when the light-facing surface of the semiconductor substrate 1 is textured, the reflectivity of the light-facing surface can be reduced, allowing more light to be refracted from the light-facing surface into the semiconductor substrate 1 and absorbed and utilized by the semiconductor substrate 1, thereby improving the photoelectric conversion efficiency of the solar cell.

[0077] The first surface described above has alternating first and second regions, wherein the direction of the alternation is the first direction. Further, the first and second directions can be any two directions parallel to the semiconductor substrate surface and not identical to each other. Preferably, referring to Figure 1, the first direction A and the second direction B are orthogonal.

[0078] In terms of scope, the boundary between the first region and the second region on the first surface of the aforementioned semiconductor substrate is a virtual boundary. As shown in Figures 1 to 3, the first doped semiconductor layer 2 is formed on the first region 10. Therefore, the scope of the first region 10 on the first surface of the semiconductor substrate 1 can be determined according to the requirements of the formation scope of the first doped semiconductor layer 2 in the actual application scenario. It can be understood that after the scope of the first region 10 is determined, the scope of the second region 11 on one side of the first surface can be determined.

[0079] As one possible implementation, referring to Figure 4, along the second direction B, the distance L2 between two adjacent protrusions of the wave shape is greater than or equal to 5 μm and less than or equal to 20 μm. For example, the distance L2 between two adjacent protrusions of the wave shape can be 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 11 μm, 12 μm, 13 μm, 14 μm, 15 μm, 16 μm, 17 μm, 18 μm, 19 μm, or 20 μm, etc. At this point, compared to the prior art (see Figure 5), in this application, the distance L2 between two adjacent protrusions of the wave shape along the second direction B is relatively small. Therefore, along the second direction B, within the same size, the wave shape in this application has more troughs or peaks, the wave shape is more evenly distributed, and the edge of the first doped semiconductor layer 2 near the second region 11 is more even. This not only further improves the film formation quality of the film layer formed at the junction of the first and second regions, but also reduces the length of the edge region, reduces carrier recombination, and improves battery performance.

[0080] As one possible implementation, the root mean square roughness Rq of the wavy shape extending along the second direction is less than or equal to 2.7 μm. For example, the root mean square roughness Rq of the wavy shape extending along the second direction can be 2.7 μm, 2.6 μm, 2.5 μm, 2.4 μm, 2.3 μm, 2.2 μm, 2.1 μm, 2.0 μm, 1.9 μm, 1.8 μm, 1.7 μm, 1.6 μm, 1.5 μm, or 1.4 μm, etc. At the edge of the first region (near the boundary between the first and second regions), there is an edge recombination problem of charge carriers, and the magnitude of the recombination current is directly related to the edge length. Smooth edges and low roughness can reduce the length of the edge region, reduce charge carrier recombination, and improve battery performance. Therefore, when the root mean square roughness of the wavy shape extending along the second direction is less than or equal to 2.7 μm, the length of the edge region can be reduced, charge carrier recombination can be reduced, and battery performance can be improved. On the other hand, a smoother edge allows for a more uniform gas atmosphere during subsequent chemical vapor deposition of the film, facilitating the formation of a more uniform film at the boundary between the first and second regions. For example, referring to Figure 6, a straight line N is selected as a reference line along the first direction A, on one side of the boundary line (i.e., the wavy line M) between the first region 10 and the second region 11. This reference line N is located within the first region 10, and its extension direction is consistent with the second direction B. I points are sampled at equal intervals on the wavy line M, where i is greater than or equal to 10. For example, 10 points are sampled at approximately equal intervals along the second direction B on the wavy line M. Then, along the first direction A, the minimum distance between these 10 points and the reference line N is calculated, thus obtaining 10 data points from H1 to H10. Next, the average value is calculated based on these 10 data points. Next, based on this average value In Figure 6, an average value line P extending along the second direction B is obtained. Next, the minimum distance (i.e., deviation height) between the 10 points on the previously mentioned wavy line M and the average value line P is calculated, thus obtaining 10 data points h1 to h10. Then, these 10 data points h1 to h10 are substituted into the h value in Formula 1. i In this process, the average roughness Ra is obtained. Substituting the 10 data points h1 to h10 into formula two, we obtain... i In this way, the root mean square roughness Rq is obtained.

[0081] Formula 1 is:

[0082] Formula 2 is:

[0083] Where Ra represents the average roughness, n represents the number of measurements, and h i Rq represents the deviation height of the i-th sampling point, and Rq represents the root mean square roughness.

[0084] It should be noted that Figures 4, 6, and 7 are essentially the same SEM image. In this application, the method for determining the average roughness or undulation of the wave shape extending along the second direction can be the method shown in Figure 8 above, or the method corresponding to Formula 1, or other methods in the field, not limited to the two example methods mentioned above.

[0085] As one possible implementation, at least a portion of the surface of the second region described above can be a polished surface or have a pyramidal texture structure.

[0086] In one example, when at least a portion of the surface of the second region is polished, it facilitates the refraction of more light through this surface into the semiconductor substrate and its utilization by the semiconductor substrate, thereby improving light reabsorption. Specifically, as shown in Figure 2, the surface of the doped region 110 included in the second region 11 is polished.

[0087] In another example, when at least a portion of the surface of the second region has a pyramidal texture structure, the contact area between the film layer and the semiconductor substrate can be increased when a film layer is subsequently formed on the second region. In particular, when the film layer is a passivation layer, the passivation effect of the passivation layer on the second region can be improved, reducing the carrier recombination rate on the surface of the second region, thereby improving the photoelectric conversion efficiency of the solar cell. Specifically, as shown in Figure 1, the surface of the portion of the second region 11 that is recessed downwards relative to the first region has a pyramidal texture structure. As shown in Figure 2, the surface of the spacer regions 111 included in the second region 11 has a pyramidal texture structure. As shown in Figure 3, the surface of the second region 11 has a pyramidal texture structure.

[0088] For example, along the first direction, the second region includes a third region adjacent to the first region and a fourth region distant from the first region, with the third region located between the fourth region and the first region. For example, along the first direction, a range extending 5 μm from the boundary between the first and second regions into the interior of the second region is defined as the third region. The regions within the second region other than the adjacent third region are defined as the fourth region distant from the first region. Both the surfaces of the third and fourth regions have pyramidal texture structures, and the dimensional uniformity of the pyramidal texture structures on the surfaces of the third and fourth regions is approximately equal. In this case, the film layer subsequently formed on the surface of the second region using the solar cell provided in this application is more uniform, has better film formation quality, and better film density, which is beneficial for improving the quality and performance of the solar cell. Further, along the direction from the first surface to the second surface, the height difference between the surface of the semiconductor substrate in the third region and the surface of the semiconductor substrate in the first region is greater than the height difference between the surface of the semiconductor substrate in the fourth region and the surface of the semiconductor substrate in the first region.

[0089] As one possible implementation, referring to Figures 1 to 3, at least a portion of the surface of the second region 11 is recessed into the semiconductor substrate 1 to a depth greater than or equal to 1 μm and less than or equal to 10 μm. In other words, along the direction from the first surface to the second surface, the height difference between the surface of the semiconductor substrate in the second region and the surface of the semiconductor substrate in the first region is greater than or equal to 1 μm and less than or equal to 10 μm. Exemplarily, the height difference can be 1 μm, 1.2 μm, 1.5 μm, 1.61 μm, 1.8 μm, 1.94 μm, 2 μm, 2.02 μm, 2.3 μm, 2.5 μm, 2.8 μm, 3 μm, 3.3 μm, 3.5 μm, 3.8 μm, 3.89 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, or 10 μm, etc. Preferably, along the direction from the first surface to the second surface, the height difference between the surface of the semiconductor substrate in the second region and the surface of the semiconductor substrate in the first region is greater than or equal to 1 μm and less than or equal to 4 μm. More preferably, along the direction from the first surface to the second surface, the height difference between the surface of the semiconductor substrate in the second region and the surface of the semiconductor substrate in the first region is greater than or equal to 1 μm and less than or equal to 3 μm.

[0090] With the above technical solution, the first doped semiconductor layer 2 and the film layer subsequently formed on at least a portion of the surface of the second region 11 can be staggered along the thickness direction of the semiconductor substrate 1 to avoid mutual influence between the first doped semiconductor layer 2 and the subsequently formed film layer, or relative influence between the structures corresponding to the first doped semiconductor layer 2 and the subsequently formed film layer. For example, when the film layer is a second doped semiconductor layer 3 with a conductivity type opposite to that of the first doped semiconductor layer 2, the height difference between the surface of the semiconductor substrate in the second region and the surface of the semiconductor substrate in the first region is within the above-mentioned range. This can prevent the electrode structure of the first doped semiconductor layer 2 and the second doped semiconductor layer 3 with opposite conductivity types from being staggered along the thickness direction of the semiconductor substrate 1 due to the small height difference, thereby reducing the risk of leakage. Furthermore, compared to the differences in the recess depth after subsequent wet etching caused by the large and uneven thermal damage to the semiconductor substrate during laser patterning, and the need to subsequently wet-etch away a portion of the semiconductor substrate thickness (the thermal damage layer is generally 10-20 μm) due to the large damage to the semiconductor substrate, which results in the need for a thicker silicon wafer for battery fabrication. This application employs a non-destructive laser patterning method, which minimizes thermal damage to the semiconductor substrate and eliminates the need for subsequent wet polishing steps to remove the damaged layer. Therefore, it achieves thinning of the semiconductor substrate while reducing process time.

[0091] When the specific structure of the solar cells provided in the embodiments of this application is different, they correspond to different types of solar cells. The following description uses three types of solar cells as examples. It should be understood that the following description is for understanding only and is not intended to limit the specific application.

[0092] The first type: Referring to Figures 1 and 4, the solar cell includes: a semiconductor substrate 1, a first doped semiconductor layer 2, and a second doped semiconductor layer 3. The semiconductor substrate 1 includes a first surface and a second surface opposite to each other. The first surface has a first region 10 and a second region 11 alternately distributed along a first direction A. The first doped semiconductor layer 2 is disposed in the first region 10; the second doped semiconductor layer 3 is disposed on the second region 11 and extends onto a portion of the first doped semiconductor layer 2; the second doped semiconductor layer 3 and the first doped semiconductor layer 2 have opposite conductivity types. The side of the first doped semiconductor layer 2 near the second region 11 has a wavy shape along a second direction B, where the first direction A is different from the second direction B. Along the first direction A, the distance between the crests and troughs of the wavy shape is less than or equal to 4 μm, and may be greater than or equal to 1 μm and less than or equal to 4 μm; and / or, the average roughness or undulation of the wavy shape extending along the second direction B is less than or equal to 2.4 μm. In this case, the above-mentioned solar cell is a hybrid back-contact cell (high and low temperature hybrid back-contact solar cell).

[0093] Regarding the first and second doped semiconductor layers mentioned above, in terms of doping type, the first doped semiconductor layer can be N-type, in which case the second doped semiconductor layer is P-type; alternatively, the first doped semiconductor layer can also be P-type, in which case the second doped semiconductor layer is N-type. This application does not specifically limit the doping type of the first and second doped semiconductor layers, as long as their doping types are opposite. When the doping type is P-type, it is generally doped with Group III elements. When the doping type is N-type, it is generally doped with Group V or Group VI elements.

[0094] From a material perspective, the materials of the first doped semiconductor layer and / or the second doped semiconductor layer can include any semiconductor material such as silicon, germanium-silicon, or germanium. From the perspective of the arrangement of matter, the crystal phase of the first doped semiconductor layer and / or the second doped semiconductor layer can be amorphous, microcrystalline, nanocrystalline, single-crystal, or polycrystalline. For example, the first doped semiconductor layer and / or the second doped semiconductor layer can be composed of one or more of polycrystalline silicon, amorphous silicon, and microcrystalline silicon. Preferably, the first doped semiconductor layer includes a first doped polycrystalline silicon layer. In this case, compared with a doped amorphous silicon layer, the doped polycrystalline silicon layer has higher carrier transport characteristics. Therefore, when the first doped semiconductor layer is a doped polycrystalline silicon layer, the carrier recombination rate can be further reduced, which is beneficial to improving the photoelectric conversion efficiency of the hybrid back contact cell. The second doped semiconductor layer includes a doped amorphous silicon layer and / or a doped microcrystalline silicon layer. It should be noted that the term "microcrystalline" in the above-mentioned doped microcrystalline silicon layer refers to a limitation on the grain size of the silicon material. Specifically, microcrystalline silicon material refers to silicon material with a grain size at the nanometer scale.

[0095] In terms of formation location, the first doped semiconductor layer can be directly formed on the first region of the first surface. Alternatively, as shown in Figure 1, the hybrid back contact cell further includes a first passivation layer 4, which is located between the first doped semiconductor layer 2 and the semiconductor substrate 1 corresponding to the first region 10. In this case, the first passivation layer 4 and the first doped semiconductor layer 2 can form a passivated contact structure, which has excellent interface passivation effect and can achieve selective collection of charge carriers, reduce the carrier recombination rate of the first region 10 on the first surface of the semiconductor substrate 1, and further improve the photoelectric conversion efficiency of the hybrid back contact cell. The material of the first passivation layer 4 can be determined according to the material of the first doped semiconductor layer 2. For example, when the first doped semiconductor layer 2 includes a first doped polysilicon layer, the first passivation layer 4 is a tunneling passivation layer. Preferably, the material of the first passivation layer 4 can be silicon oxide, aluminum oxide, or titanium oxide, etc. The thickness of the first passivation layer 4 is greater than or equal to 1 nm and less than or equal to 2 nm. For example, the thickness of the first passivation layer 4 can be 1 nm, 1.3 nm, 1.5 nm, 1.8 nm, or 2 nm. The first passivation layer 4 can be a single-layer structure or a stacked structure composed of multiple film layers. For example, the first passivation layer 4 can be a stacked structure of silicon oxide and aluminum oxide; or a stacked structure of aluminum oxide and titanium oxide; or a stacked structure of silicon oxide and titanium oxide.

[0096] The aforementioned second doped semiconductor layer can be directly formed on the second region of the first surface and extend to a portion of the first doped semiconductor layer. Alternatively, as shown in FIG1, the aforementioned hybrid back contact cell further includes a second passivation layer 5. The second passivation layer 5 is located between the second doped semiconductor layer 3 and the semiconductor substrate 1 corresponding to the second region 11, and extends to a portion of the first doped semiconductor layer 2. The portion of the second doped semiconductor layer 3 corresponding to the first region 10 is located on the portion of the second passivation layer 5 corresponding to the first region 10. In this case, the second passivation layer 5 and the second doped semiconductor layer 3 can constitute a passivated contact structure, which has excellent interface passivation effect and can achieve selective collection of charge carriers, reduce the carrier recombination rate of the second region 11 of the first surface of the semiconductor substrate 1, and further improve the photoelectric conversion efficiency of the hybrid back contact cell. The material of the aforementioned second passivation layer 5 can be determined according to the material of the second doped semiconductor layer 3. For example, when the second doped semiconductor layer 3 includes a doped amorphous silicon layer and / or a doped microcrystalline silicon layer, the second passivation layer 5 includes an intrinsic amorphous silicon layer and / or an intrinsic microcrystalline silicon layer. The thickness of the second passivation layer 5 is greater than or equal to 1 nm and less than or equal to 50 nm. For example, the thickness of the second passivation layer 5 can be 1 nm, 5 nm, 10 nm, 12 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, or 50 nm, etc. Furthermore, the above-mentioned second passivation layer 5 can be a single-layer structure or a stacked structure composed of multiple film layers.

[0097] As one possible implementation, referring to Figure 1, the solar cell further includes a transparent conductive layer 6 disposed on the first doped semiconductor layer 2 and the second doped semiconductor layer 3. The transparent conductive layer 6 has insulating grooves to physically insulate the portion of the transparent conductive layer 6 corresponding to the first region 10 from the portion of the transparent conductive layer 6 corresponding to the second region 11.

[0098] The aforementioned transparent conductive layer can be composed of one or more stacked layers selected from ITO (indium tin oxide), ITiO (titanium-doped indium oxide), IWO (indium tungsten oxide), and ICO (indium zirconium oxide). The thickness of the transparent conductive layer is greater than or equal to 10 nm and less than or equal to 500 nm. For example, the thickness of the transparent conductive layer can be 10 nm, 30 nm, 40 nm, 60 nm, 80 nm, 100 nm, 180 nm, 200 nm, 230 nm, 300 nm, 400 nm, or 500 nm. Preferably, the thickness of the transparent conductive layer is greater than or equal to 50 nm and less than or equal to 200 nm. The thickness direction of the aforementioned transparent conductive layer is consistent with the direction from the first surface to the second surface.

[0099] Using the above technical solution, the transparent conductive layer 6 covering the first doped semiconductor layer 2 and the second doped semiconductor layer 3 has high conductivity, which can promptly export the charge carriers collected by the first doped semiconductor layer 2 and the second doped semiconductor layer 3, reducing the carrier recombination rate. Furthermore, the transparent conductive layer 6 not only improves the current collection capability of the hybrid back contact cell, but also acts as an anti-reflection film to improve the light absorption rate of the hybrid back contact cell. In addition, the transparent conductive layer 6 also has passivation properties. Regarding the insulating groove provided within the transparent conductive layer 6, this insulating groove is used to physically insulate the portion of the transparent conductive layer 6 corresponding to the first region 10 from the portion of the transparent conductive layer 6 corresponding to the second region 11. Specifically, since the portion of the transparent conductive layer 6 corresponding to the first region 10 is used for ohmic connection with the first electrode 8, and the portion of the transparent conductive layer 6 corresponding to the second region 11 is used for ohmic connection with the second electrode 9, these two portions of the transparent conductive layer 6 cannot be directly electrically connected; that is, these two portions of the transparent conductive layer 6 must be physically insulated, i.e., not in contact. Based on this, it is understandable that, in order to prevent short circuits, the positions of the two ends of the insulating groove are not restricted, as long as they can insulate against the transparent conductive layer 6 of the first electrode 8 and the second electrode 9.

[0100] Furthermore, as described above, since the wave shape on the side of the first doped semiconductor layer 2 is relatively flat, it provides a larger error margin for subsequent processing (such as patterning processes, patterning other film layers on the first doped semiconductor layer), improving process accuracy and thus enhancing the quality of the solar cell. For the first type of solar cell, the aforementioned patterning process can be understood as a patterning process that partially opens the second doped semiconductor layer 3 in the first region 10, exposing the first doped semiconductor layer 2 and allowing the charge carriers of the first doped semiconductor layer 2 to be discharged. Alternatively, an insulating trench can be provided in the transparent conductive layer 6 to isolate the first electrode 8 and the second electrode 9 of different polarities to prevent leakage.

[0101] In some embodiments, referring to FIG1, the second doped semiconductor layer 3 in the first region 10 is disposed at a position of part of the first doped semiconductor layer 2 as a stacked region (the position between the dashed line Q in the first region 10 and the boundary between the first region 10 and the second region 11). That is, the stacked region is the position in the first region 10 where the second doped semiconductor layer 3 covers the first doped semiconductor layer 2. In the stacked region: the second doped semiconductor layer, near the first region (approximately the position of the dashed line Q in FIG1), has an undulating morphology along the first direction A, which is beneficial to further increase the light trapping effect at the stacked region, improve the utilization rate of light by the semiconductor substrate, and also improve the power generation efficiency of the solar cell.

[0102] In the stacked region (the position between the dashed line Q in the first region 10 and the boundary between the first region 10 and the second region 11): the second doped semiconductor layer has an undulating morphology along the first direction A near the first region (approximately the position of the dashed line Q in Figure 1). Specifically, in the stacked region: the thickness of the second doped semiconductor layer varies at various positions along the first direction A near the first region (approximately the position of the dashed line Q).

[0103] It should be noted that the dashed line Q in this application is only for illustrating different areas; in actual solar cells, there is no such clear division. Other dashed lines mentioned in this application are similar, merely for distinguishing different areas; in actual solar cells, there is no such clear distinction.

[0104] More specifically, for the back-contact solar cells shown in Figures 1 and 4, the second doped semiconductor layer 3 is superimposed on the first doped semiconductor layer 2, meaning that the second doped semiconductor layer 3 is fabricated after the first doped semiconductor layer 2 is prepared. Firstly, the undulation of the wave shape on the side of the first doped semiconductor layer 2 near the second region is smaller, and the distance between protrusions and depressions is smaller (i.e., the amplitude of the wave shape is smaller). The side of the first doped semiconductor layer 2 near the second region is relatively flat, resulting in better film quality for the second doped semiconductor layer 3 formed on it. Consequently, the passivation effect is better at the boundary between the first doped semiconductor layer 2 and the second region, or in the stacked region where the second doped semiconductor layer 3 extends and covers the first doped semiconductor layer 2, thus improving the passivation effect at the boundary between the first doped semiconductor layer 2 and the second region in the solar cell, which can improve the power generation efficiency of the solar cell. Secondly, when viewed from above and extending along the second direction, the wave shape on the side of the first doped semiconductor layer 2 near the second region is relatively flat. When a passivation layer, a second doped semiconductor layer, or a transparent conductive layer is deposited on the side of the first doped semiconductor layer 2 near the second region, the quality of these film layers is good, and they are relatively uniform and neat. In particular, when using vapor deposition such as CVD (chemical vapor deposition), the relatively flat wave shape has a regular effect on the atmosphere in vapor deposition, making the distribution of the atmosphere in the space of this region more uniform. The atmosphere environment will not be disrupted by unevenness, thus making it better to deposit the above-mentioned film layers in this region. Thirdly, when viewed from above and extended along the second direction, the wave shape of the side of the first doped semiconductor layer 2 near the second region has a relatively flat shape. The relatively flat shape at the edge can also provide a larger error margin for subsequent patterning accuracy, improving the process yield.

[0105] For the back-contact solar cells shown in Figures 1 and 4, considering the process and structure, the first doped semiconductor layer 2 is fabricated first, followed by the first patterning, and then the second doped semiconductor layer 3 is fabricated and patterned. This is because the first patterning requires the complete removal of the mask layer and the first doped semiconductor layer 2 on the second region, leaving no residue. Any residue would affect the film quality of the second doped semiconductor layer 3 on the second region. More specifically, the second doped semiconductor layer 3 is directly deposited on the semiconductor substrate; any residue would affect the passivation effect of the second doped semiconductor layer 3 on the semiconductor substrate, thus impacting the power generation performance of the solar cell. Simultaneously, the wavy shape represents the interface between the first doped semiconductor layer 2 and the second doped semiconductor layer 3. The unevenness of this interface affects the film quality of the second doped semiconductor layer 3, resulting in thinner second doped semiconductor layer 3 in some areas. This, in turn, leads to leakage between the first and second doped semiconductor layers 2 and 3, affecting the power generation efficiency of the solar cell. Furthermore, because the mask layer and the first doped semiconductor layer 2 are relatively thick, in order to form a smaller unevenness at the interface (i.e., less undulation in the wave shape and a smaller distance between protrusions and depressions), considering engineering efficiency and semiconductor substrate damage, if a laser removal process for the first doped semiconductor layer is used, a low-energy laser spot with a high overlap rate should be preferred. This will result in a smaller unevenness, while also minimizing damage to the semiconductor substrate and achieving cleaner removal of the mask layer and the first doped semiconductor layer. It should be noted that a laser spot with a high overlap rate is only one example; other process methods with different characteristics may exist (such as photolithography and etchant etching; in etchant etching, the wave shape after etching can be controlled by adjusting the viscosity, leveling, and roughness of the stencil openings, etc.) to achieve the corresponding requirements. In summary, a relatively flat wave shape is formed to ensure the deposition quality of the second doped semiconductor layer 3, prevent leakage between the first doped semiconductor layer 2 and the second doped semiconductor layer 3, reduce damage to the first doped semiconductor layer 2 during the patterning process, and also facilitate the deposition of the transparent conductive layer, thereby realizing the fabrication of high-efficiency solar cells.

[0106] As one possible implementation, the aforementioned solar cell is a high-low temperature hybrid back-contact solar cell. The semiconductor substrate is N-type monocrystalline silicon, the first doped semiconductor layer is an N-type doped polycrystalline silicon layer, and the second doped semiconductor layer is a P-type doped hybrid layer of P-type doped amorphous silicon and P-type doped nanocrystalline silicon. On the first surface of the N-type monocrystalline silicon, a tunneling silicon oxide layer, an N-type doped polycrystalline silicon layer, a TCO layer (transparent conductive layer), and an N-electrode are sequentially disposed in a first region. On the second surface of the N-type monocrystalline silicon, an intrinsic amorphous silicon layer, a P-type doped hybrid layer, a TCO layer, and a P-electrode are sequentially disposed in a second region. The N-electrode is used to extract charge carriers from the N-type doped polycrystalline silicon layer, and the P-electrode is used to extract charge carriers from the P-type doped hybrid layer. In the first region near the second region, there is a stacked region. On this stacked region, a tunneling silicon oxide layer, an N-type doped polycrystalline silicon layer, an intrinsic amorphous silicon layer, (a P-type doped mixed layer or a P-type doped amorphous silicon layer), and a partial TCO layer are sequentially stacked from the surface of the N-type monocrystalline silicon. The TCO layer is disconnected in this region, achieving insulation between the PN regions. The surface of the first region of the N-type monocrystalline silicon has a polished structure, while the surface of the second region of the N-type monocrystalline silicon has a pyramidal textured structure.

[0107] On the second surface of the N-type monocrystalline silicon, which is positioned opposite to the first surface, a passivation antireflection layer is disposed. This passivation antireflection layer consists of an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, sequentially disposed from the surface of the N-type monocrystalline silicon. The surface of the second surface of the N-type monocrystalline silicon has a pyramidal textured surface structure.

[0108] The second type: Referring to Figures 2 and 4, the solar cell includes: a semiconductor substrate 1, a first doped semiconductor layer 2, and a second doped semiconductor layer 3. The semiconductor substrate 1 includes a first surface and a second surface opposite to each other. The first surface has a first region 10 and a second region 11 alternately distributed along a first direction A. The first doped semiconductor layer 2 is disposed in the first region 10, and no first doped semiconductor layer 2 is formed on the second region 11. The second region 11 includes a doped region 110 and two spacer regions 111. Along the first direction A, the doped region 110 is located between the two spacer regions 111; along the first direction A, the spacer regions 111 are located between the first region 10 and the doped region 110; the side of the first doped semiconductor layer 2 near the spacer region 111 has a wavy shape along a second direction B. The second doped semiconductor layer 3 is disposed in the doped region 110, and the second doped semiconductor layer 3 has an opposite conductivity type to the first doped semiconductor layer 2. The side of the first doped semiconductor layer 2 near the second region 11 has a wavy shape along the second direction B, and the first direction A is different from the second direction B. Along the first direction A, the distance between the crests and troughs of the wave shape is less than or equal to 4 μm, and further greater than or equal to 1 μm and less than or equal to 4 μm; and / or, the average roughness or undulation of the wave shape extending along the second direction B is less than or equal to 2.4 μm. In this case, the above-mentioned solar cell is a hybrid back-contact cell.

[0109] At this point, the aforementioned solar cell is a tunnel oxide passivated back contact solar cell (TOPCon Back Contact, abbreviated as TBC). Furthermore, the spacer region 111 can isolate the first doped semiconductor layer 2 and the second doped semiconductor layer 3, reducing the carrier recombination rate at the lateral boundary between the first doped semiconductor layer 2 and the second doped semiconductor layer 3, which is beneficial to improving the photoelectric conversion efficiency of the solar cell.

[0110] For information on doping types, please refer to the first type of solar cell; it will not be elaborated upon here.

[0111] From a material perspective, the first doped semiconductor layer and / or the second doped semiconductor layer can be made of any semiconductor material such as silicon, germanium-silicon, or germanium. From a material arrangement perspective, the crystal phase of the first doped semiconductor layer and / or the second doped semiconductor layer can be amorphous, microcrystalline, nanocrystalline, single-crystal, or polycrystalline. For example, the first doped semiconductor layer and / or the second doped semiconductor layer can be composed of one or more of polycrystalline silicon, amorphous silicon, and microcrystalline silicon. Preferably, the first doped semiconductor layer includes a second doped polycrystalline silicon layer, and the second doped semiconductor layer includes a third doped polycrystalline silicon layer.

[0112] In terms of formation location, the first doped semiconductor layer can be directly formed on the first region of the first surface. Alternatively, as shown in Figure 2, the solar cell further includes a first passivation layer 4, which is located between the first doped semiconductor layer 2 and the semiconductor substrate 1 corresponding to the first region 10. In this case, the first passivation layer 4 and the first doped semiconductor layer 2 can form a passivation contact structure, which has excellent interface passivation effect and can achieve selective collection of charge carriers, reduce the carrier recombination rate of the first region 10 on the first surface of the semiconductor substrate 1, and further improve the photoelectric conversion efficiency of the solar cell. The material of the first passivation layer 4 can be determined according to the material of the first doped semiconductor layer 2. For example, when the first doped semiconductor layer 2 includes a second doped polycrystalline silicon layer, the first passivation layer 4 is a tunneling passivation layer. Preferably, the material of the first passivation layer 4 can be alumina, silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide, etc., and the thickness of the first passivation layer 4 is greater than or equal to 1 nm and less than or equal to 2 nm. For example, the thickness of the first passivation layer 4 can be 1 nm, 1.3 nm, 1.5 nm, 1.8 nm, or 2 nm. The first passivation layer 4 can be a single-layer structure or a stacked structure composed of multiple film layers. For example, the first passivation layer 4 can be a stacked structure of aluminum oxide and silicon nitride; or a stacked structure of aluminum oxide and silicon oxide; or a stacked structure of silicon oxide and silicon nitride.

[0113] The second doped semiconductor layer can be directly formed on the doped region of the first surface. Alternatively, as shown in Figure 2, the solar cell further includes a second passivation layer 5 located between the semiconductor substrate 1 and the second doped semiconductor layer 3 corresponding to the doped region 110. In this case, the second passivation layer 5 and the second doped semiconductor layer 3 can form a selective contact structure to achieve chemical passivation of the doped region 110 on the first surface of the semiconductor substrate 1 and selective collection of carriers of the corresponding conductivity type, reducing the carrier recombination rate on the first surface and improving the photoelectric conversion efficiency of the solar cell. The material of the second passivation layer 5 can be determined based on the material of the second doped semiconductor layer 3. For example, if the second doped semiconductor layer 3 includes a third doped polycrystalline silicon layer, the second passivation layer 5 is a tunneling passivation layer. Preferably, the material of the second passivation layer 5 can be silicon oxide, aluminum oxide, or titanium oxide, etc. The thickness of the second passivation layer 5 is greater than or equal to 1 nm and less than or equal to 50 nm. For example, the thickness of the second passivation layer 5 can be 1 nm, 5 nm, 10 nm, 12 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, or 50 nm. Furthermore, the second passivation layer 5 can be a single-layer structure or a stacked structure composed of multiple film layers.

[0114] As one possible implementation, referring to Figure 2, the second type of solar cell described above may further include a surface passivation layer 7, which is disposed on the first doped semiconductor layer 2, the second doped semiconductor layer 3, and the spacer region 111. The surface passivation layer 7 can passivate one side of the TBC, reducing the carrier recombination rate on that side.

[0115] Specifically, the material of the aforementioned surface passivation layer can be any insulating material with passivation properties, such as silicon oxide, aluminum oxide, or silicon nitride. The thickness of the surface passivation layer can be determined based on the actual application scenario and is not specifically limited here. Furthermore, the aforementioned surface passivation layer can be a single-layer structure or a stacked structure composed of multiple film layers. As shown in Figure 2, the aforementioned surface passivation layer 7 is a stacked structure.

[0116] As one possible implementation, the aforementioned solar cell is a TBC (Transient Carbon-Based Cell), with an N-type monocrystalline silicon semiconductor substrate, a first doped semiconductor layer being an N-type doped polycrystalline silicon layer, and a second doped semiconductor layer being a P-type doped polycrystalline silicon layer. On the first surface of the N-type monocrystalline silicon, a tunneling silicon oxide layer, an N-type doped polycrystalline silicon layer, an aluminum oxide layer, a silicon nitride layer, and an N-electrode are sequentially stacked in a first region. On the first surface of the N-type monocrystalline silicon, a tunneling silicon oxide layer, a P-type doped polycrystalline silicon layer, an aluminum oxide layer, a silicon nitride layer, and a P-electrode are sequentially disposed in a doped region of the second region. On the first surface of the N-type monocrystalline silicon, an aluminum oxide layer and a silicon nitride layer are sequentially disposed in a spacer region of the second region. A portion of the N-electrode penetrates the aluminum oxide and silicon nitride layers to contact the N-type doped polycrystalline silicon layer, achieving carrier extraction in the N-region; a portion of the P-electrode penetrates the aluminum oxide and silicon nitride layers to contact the P-type doped polycrystalline silicon layer, achieving carrier extraction in the P-region. The surface of the first region of N-type monocrystalline silicon is a polished surface structure, the surface of the spacer region of N-type monocrystalline silicon is a polished surface structure or a pyramid structure, and the surface of the doped region of N-type monocrystalline silicon is a polished surface structure.

[0117] On the second surface of the N-type monocrystalline silicon, which is positioned opposite to the first surface, a passivation antireflection layer is disposed. This passivation antireflection layer consists of an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, sequentially disposed from the surface of the N-type monocrystalline silicon. The surface of the second surface of the N-type monocrystalline silicon has a pyramidal textured surface structure.

[0118] The third type: Referring to Figure 3, the solar cell includes a semiconductor substrate 1, a first doped semiconductor layer 2, and a surface passivation layer 7. The semiconductor substrate 1 includes a first surface and a second surface opposite to each other. The first surface has a first region 10 and a second region 11 alternately distributed along a first direction A. The first doped semiconductor layer 2 is disposed in the first region 10, and no first doped semiconductor layer 2 is formed on the second region 11. The surface passivation layer 7 is disposed on the second region 11 and extends onto the first doped semiconductor layer 2. The side of the first doped semiconductor layer 2 near the second region 11 has a wavy shape along a second direction B, where the first direction A is different from the second direction B. Along the first direction A, the distance between the peaks (protrusions) and troughs (recesses) of the wavy shape is less than or equal to 4 μm, and further, greater than or equal to 1 μm and less than or equal to 4 μm; and / or, the average roughness or undulation of the wavy shape extending along the second direction B is less than or equal to 2.4 μm. In this case, the solar cell is a tunnel oxide passivated contact (TOPCon) cell. Specifically, the third type of solar cell corresponds to the local polyfinger structure in TOPCon. Furthermore, the aforementioned surface passivation layer 7 can passivate one side of the first surface of TOPCon, reducing the carrier recombination rate on that side.

[0119] For details regarding the doping type, materials, and surface passivation layer of the first doped semiconductor layer, please refer to the description of the second type of solar cell; these will not be repeated here.

[0120] In terms of formation location, the first doped semiconductor layer can be directly formed on the first region of the first surface. Alternatively, as shown in Figure 3, the solar cell further includes a first passivation layer 4, which is located between the first doped semiconductor layer 2 and the semiconductor substrate 1 corresponding to the first region 10. In this case, the first passivation layer 4 and the first doped semiconductor layer 2 can form a passivation contact structure, which has excellent interface passivation effect and can achieve selective collection of charge carriers, reduce the carrier recombination rate of the first region 10 on the first surface of the semiconductor substrate 1, and further improve the photoelectric conversion efficiency of the solar cell. The material of the first passivation layer 4 can be determined according to the material of the first doped semiconductor layer 2. For example, when the first doped semiconductor layer 2 includes a second doped polycrystalline silicon layer, the first passivation layer 4 is a tunneling passivation layer. Preferably, the material of the first passivation layer 4 can be alumina, silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide, etc., and the thickness of the first passivation layer 4 is greater than or equal to 1 nm and less than or equal to 2 nm. For example, the thickness of the first passivation layer 4 can be 1 nm, 1.3 nm, 1.5 nm, 1.8 nm, or 2 nm. The first passivation layer 4 can be a single-layer structure or a stacked structure composed of multiple film layers. For example, the first passivation layer 4 can be a stacked structure of aluminum oxide and silicon nitride; or a stacked structure of aluminum oxide and silicon oxide; or a stacked structure of silicon oxide and silicon nitride.

[0121] Furthermore, the aforementioned surface passivation layer can be a single-layer structure or a stacked structure composed of multiple film layers. As shown in Figure 3, the aforementioned surface passivation layer 7 is a stacked structure.

[0122] As one possible implementation, the aforementioned solar cell is a TOPcon cell. The semiconductor substrate is N-type monocrystalline silicon, the first doped semiconductor layer is an N-type doped polycrystalline silicon layer, and the surface passivation layers include a back passivation layer on the first surface and a front passivation layer on the second surface. On the first surface of the N-type monocrystalline silicon, a tunneling oxide layer, an N-type doped polycrystalline silicon layer, an aluminum oxide layer, a silicon nitride layer, and an N-electrode are sequentially stacked on a first region. On the first surface of the N-type monocrystalline silicon, an aluminum oxide layer and a silicon nitride layer are sequentially stacked on a second region. A portion of the N-electrode penetrates the aluminum oxide layer and the silicon nitride layer to contact the N-type doped polycrystalline silicon layer, achieving carrier extraction in the N-region. The back passivation layer can be understood as a stack of an aluminum oxide layer and a silicon nitride layer. In the second region on the first surface of the N-type monocrystalline silicon, the surface of the N-type monocrystalline silicon has a pyramidal textured structure or a polished structure.

[0123] On the second surface of the N-type single-crystal silicon, which is positioned opposite the first surface, a P-type doped diffusion layer is disposed. On the P-type doped diffusion layer, an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, and a P-electrode are sequentially disposed. A portion of the P-electrode penetrates the aluminum oxide and silicon nitride layers to contact the P-type doped diffusion layer, enabling carrier extraction from the P-region. The surface of the second surface of the N-type single-crystal silicon has a pyramidal textured structure.

[0124] More specifically, for the solar cells shown in Figures 2 and 3, the surface passivation layer 7 is applied over the first doped semiconductor layer 2, meaning it is prepared after the first doped semiconductor layer 2 is completed. Firstly, the undulation of the wave shape on the side of the first doped semiconductor layer 2 near the second region is smaller, and the distance between protrusions and depressions is smaller (i.e., the amplitude of the wave shape is smaller, the undulation of the wave shape is smaller, and the distance between protrusions and depressions is smaller). The side of the first doped semiconductor layer 2 near the second region is relatively flat, resulting in a better quality surface passivation layer 7. Consequently, the passivation effect at the boundary between the first doped semiconductor layer 2 and the second region is better, improving the passivation effect at this boundary and thus increasing the power generation efficiency of the solar cell. Secondly, when viewed from above along the second direction, the wave shape on the side of the first doped semiconductor layer 2 near the second region is relatively flat. When the surface passivation layer 7 is deposited on the side of the first doped semiconductor layer 2 near the second region, the film quality is better, more uniform and neat. In particular, when using vapor deposition such as CVD (chemical vapor deposition), the relatively flat wave shape has a regular effect on the atmosphere in the vapor deposition, making the distribution of the atmosphere in the space of the region more uniform. The atmosphere environment will not be disrupted by unevenness, thus making the surface passivation layer 7 better deposited in the region. Thirdly, when viewed from above and extended along the second direction, the wave shape of the side of the first doped semiconductor layer 2 near the second region has a relatively flat shape. The relatively flat shape at the edge can also provide a larger error margin for subsequent patterning accuracy, improving the process yield.

[0125] For the solar cells shown in Figures 2 and 3, considering the process and structure, the first doped semiconductor layer 2 is fabricated first, followed by the first patterning, and then the surface passivation layer 7 is fabricated. This is because the first patterning requires the complete removal of the mask layer and the first doped semiconductor layer 2 in the second region, leaving no residue. Any residue would affect the film quality of the surface passivation layer 7 in the second region, impacting its passivation effect on the semiconductor substrate and consequently affecting the power generation performance of the solar cell. Furthermore, since the mask layer and the first doped semiconductor layer 2 are relatively thick, considering engineering efficiency and semiconductor substrate damage, if a laser removal process for the first doped semiconductor layer 2 is used, a low-energy laser spot with a high overlap rate is preferred. This results in less damage to the semiconductor substrate while removing the mask layer and the first doped semiconductor layer 2 more cleanly, and also creates a smaller interface (i.e., smaller wave-shaped amplitude, less undulation, and smaller distance between protrusions and depressions). Similarly, it should be noted that the high laser overlap rate spot is only one example. Other process methods with different characteristics (such as photolithography and etchant etching; in etchant etching, the wave shape after etching can be controlled by adjusting the viscosity, leveling, and roughness of the stencil openings) to achieve the desired result. In summary, forming a relatively smooth wave shape ensures the deposition quality of the surface passivation layer 7, reduces damage to the first doped semiconductor layer 2 during patterning, and facilitates the deposition of the surface passivation layer 7, thereby enabling the fabrication of high-efficiency solar cells.

[0126] In some embodiments, referring to FIG4, along the first direction A, the distance between the protrusions and the adjacent recesses of the aforementioned wave shape is L1; along the second direction B, the distance between adjacent protrusions or adjacent recesses of the aforementioned wave shape is L2, and (L1 / L2) is 0.03 to 0.9. The process of forming the aforementioned wave shape is simple, and the film formation quality of the passivation layer, the second doped semiconductor layer, or the transparent conductive layer deposited on the side of the first doped semiconductor layer near the second region is good. For example, (L1 / L2) can be 0.03, 0.04, 0.05, 0.06, 0.09, 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, or 0.9.

[0127] In some embodiments, referring to FIG9, in the thickness direction Z of the solar cell, the second region 11 near the first region also has an inclined region 13. The surface of the semiconductor substrate 1 on the inclined region 13 has an inclined angle α with the surface defined by the first and second directions (shown by the dashed line adjacent to angle α in FIG9). α is 20° to 75°, further α is 30° to 70°, and even further α is 35° to 65°. Therefore, at the boundary between the first doped semiconductor layer and the second region, there is a smooth transition without sharp corners. The film structure at the inclined boundary location is unlikely to have defects such as discontinuity, resulting in good film quality and improved passivation effect at the boundary location. In addition, the inclined boundary can better release the stress of the interconnects, reducing the damage of the interconnects to the solar cell film layer, thus improving the reliability and lifespan of the photovoltaic module. For example, the inclined angle α can be 20°, 25°, 30°, 35°, 40°, 45°, 50°, 55°, 60°, 65°, 70°, or 75°. Interconnect components refer to structures such as solder strips.

[0128] In some embodiments, referring to FIG1, in the aforementioned stacked region, the thickness of the second doped semiconductor layer in the thickness direction Z of the solar cell is greater in the stacked region than in the tilted region 13. By varying the thickness of the second doped semiconductor layer at different locations, the light trapping effect can be improved.

[0129] In some embodiments, referring to FIG1, in the aforementioned stacked region, in the thickness direction Z of the solar cell, the thickness of the second doped semiconductor layer in the stacked region is greater than the thickness outside the tilted region 13 in the second region. By varying the thickness at different positions of the second doped semiconductor layer, the light trapping effect can be improved.

[0130] It should be noted that all the features described above, unless otherwise specified, apply to all types of solar cells.

[0131] Secondly, embodiments of this application also provide a photovoltaic module. The photovoltaic module includes a cell string and an encapsulation layer. The cell string is formed by connecting multiple solar cells as described in the above-described technical solutions, and the encapsulation layer is used to cover the surface of the cell string.

[0132] The beneficial effects of the second aspect and its various implementations in the embodiments of this application can be found by referring to the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0133] Specifically, the aforementioned battery string can be directly formed by connecting multiple solar cells as described in the first aspect, or the battery string can include multiple segmented solar cells formed by dividing the solar cells as described in the first aspect. In other words, the aforementioned solar cell can be a whole solar cell or a half solar cell. When the aforementioned solar cell is a half solar cell, the whole solar cell can be cut along the cutting line located within the dividing area. The "dividing area" will not be described in detail here, as long as it meets the actual needs.

[0134] Thirdly, this application also provides a method for manufacturing a solar cell. The method for manufacturing the solar cell includes:

[0135] First, a semiconductor substrate is provided; the semiconductor substrate includes opposing first and second surfaces; the first surface has first and second regions alternately distributed along a first direction;

[0136] For example, the first surface mentioned above is the backlight surface. As for the relevant description of the semiconductor substrate, please refer to the first aspect, which will not be repeated here. It should be noted that the first surface here can also be the light-facing surface. For the light-facing surface, the step of forming the first semiconductor layer located in the first region is similar to or the same as the step of forming the first semiconductor layer located in the first region on the backlight surface. To avoid repetition, it will not be repeated here.

[0137] Before actual use, the semiconductor substrate is polished and cleaned. Specifically, the semiconductor substrate is placed in a tank polishing machine for pre-cleaning to remove cutting damage and organic matter and other contaminants generated during transportation. The polishing and cleaning steps for the semiconductor substrate include: cleaning with SC-1 from the RCA (Resist Cleaning) process. SC-1 consists of NH4OH / KOH-H2O2-H2O in a ratio of (1:1:5), and the cleaning temperature is 65°C. Next, the residual chemicals from the SC-1 cleaning are neutralized by rinsing with deionized water. Then, alkaline polishing is performed. The alkaline polishing formula is: 5.00% wt KOH, with a KOH stock concentration of (45%), at a temperature of 80°C for 300 seconds. This removes the surface damage layer caused by cutting, and the silicon wafer surface is polished. Next, a high-efficiency SC-1 cleaning was performed, with the ratio of NH4OH / KOH-H2O2-H2O being (1:1:5), at a temperature of 65℃ for 300 seconds. Following this, SC-2 was used to remove residual metal ions. SC-2 was a solution of HCl:H2O2:H2O in a ratio of 1:1:5, at a temperature of 65℃ for 200 seconds. Finally, the substrate was cleaned with 5% wt hydrofluoric acid, dried, and then polished. The polishing thickness of the first and second surfaces of the semiconductor substrate was 5μm to 10μm, resulting in semiconductor substrates with different crystal orientations on the polished silicon wafer surface.

[0138] Next, a first doped semiconductor layer is formed on the entire first surface;

[0139] For example, a semiconductor material layer can be formed integrally on the first surface using processes such as chemical vapor deposition. Next, the semiconductor material layer is doped to form a first doped semiconductor layer integrally on the first surface, and a first doped silicon glass layer integrally formed on the first doped semiconductor layer. The material and thickness of the first doped semiconductor layer can be referred to the description above. It should be noted that the first doped silicon glass layer may or may not be removed before forming the mask layer.

[0140] For example, the aforementioned semiconductor material layer can be a polycrystalline silicon layer, formed using a phosphorus diffusion apparatus to create a doped polycrystalline silicon layer and a phosphorus silicate glass layer on its surface. If the phosphorus silicate glass layer is removed: it can be removed via an acid etching process before forming the mask layer, which improves the passivation effect of the mask layer on the first doped semiconductor layer. If the phosphorus silicate glass layer is not removed and the mask layer is formed directly on the phosphorus silicate glass layer, the number of fabrication steps for the solar cell can be reduced.

[0141] Next, a mask layer is formed over the entire first doped semiconductor layer;

[0142] The mask layer can be made of one or more of silicon nitride, silicon oxynitride, silicon oxide, silicon carbide, or intrinsic silicon. The mask layer can be a single-layer structure formed from one of the aforementioned materials, or a stacked structure formed from a first doped silicon glass layer and silicon nitride. Further, the thickness of the mask layer is greater than or equal to 2 nm and less than or equal to 100 nm. For example, the thickness of the mask layer can be 2 nm, 5 nm, 8 nm, 10 nm, 30 nm, 40 nm, 60 nm, 80 nm, 90 nm, or 100 nm. The methods for forming the mask layer include one or more of plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, catalytic chemical vapor deposition (Cat-CVD), or atomic layer deposition (ALD).

[0143] When patterning using etch paste or photolithography, the first doped silicon glass layer generated in the above steps can be retained, or the thickness of the first doped silicon glass layer can be increased to use it as a mask.

[0144] Next, the mask layer and the first doped semiconductor layer located in the second region are processed to obtain the first doped semiconductor layer located in the first region; it should be noted that the first doped semiconductor layer is not formed on the second region.

[0145] For example, when the mask layer material is silicon nitride, a laser with a relatively long pulse and relatively low power density is used to treat the mask layer located in the second region. The treated mask layer is porous and has a reduced N content and an increased Si content (specifically, some nitrogen evaporates in gaseous form, thus reducing the N content and increasing the Si content). This makes the treated silicon nitride mask layer less alkali-resistant than the untreated silicon nitride mask layer. Therefore, during polishing / texturing with an alkaline solution, the treated silicon nitride mask layer can be removed, while the untreated silicon nitride mask layer, being more alkali-resistant, can be used to protect the corresponding first doped semiconductor layer and semiconductor substrate from etching by the alkaline wet solution. After polishing and / or texturing, an acid pickling step is added to remove the untreated silicon nitride mask layer, thus achieving non-destructive patterning. In other words, when irradiated with a relatively long pulse and relatively low power density laser, the silicon nitride near the first doped semiconductor layer decomposes under the thermal effect of the first doped semiconductor layer, and some nitrogen evaporates in gaseous form, thus reducing the proportion of N and increasing the proportion of Si. The silicon nitride relatively far from the first doped semiconductor layer is oxidized by air to form silicon oxide and silicon oxynitride. After laser treatment, the silicon nitride becomes loose, porous, and layered, allowing alkaline solution to easily penetrate through the pores to the underlying silicon-rich silicon nitride layer, thereby corroding the underlying silicon nitride and the corresponding semiconductor substrate below. Compared to the prior art method of using high-power lasers to blast open and remove the silicon nitride mask layer, the laser power used in this embodiment is lower. Therefore, the processing method provided in this embodiment causes less or virtually no damage to the semiconductor substrate, enabling thinning of the semiconductor substrate and reducing the manufacturing cost of solar cells. Furthermore, when the semiconductor substrate is essentially undamaged, after polishing and / or texturing, it is not necessary to remove the damaged layer on the semiconductor substrate, saving fabrication steps.

[0146] When the mask layer is a stacked structure of a first-doped silicon glass layer and silicon nitride, the processing method for the mask layer remains unchanged, as described earlier regarding "the material of the mask layer is silicon nitride". Because the first-doped silicon glass layer has thermal insulation capabilities, the thermal effect generated by laser absorption in the first-doped semiconductor layer is more pronounced. Under the same laser conditions, the processing effect on silicon nitride is more significant, meaning that the processed silicon nitride produces more pores and is more easily etched with alkaline solutions.

[0147] When the mask layer is a first-doped silicon glass layer, patterned etching paste can be printed or sprayed onto the first surface of the semiconductor substrate using methods such as screen printing, stencil printing, or spraying. The purpose is to use the etching paste to etch away the first-doped silicon glass layer in the second region. Then, wet etching or other processes are used to remove the exposed first-doped semiconductor layer. The remaining first-doped silicon glass layer in the first region can serve as a barrier layer or mask layer for wet etching processes, preventing chemical agents from damaging the first-doped semiconductor layer in the first region, thus achieving a patterned first-doped semiconductor layer. The first-doped semiconductor layer near the second region exhibits a wavy shape along the second direction, mainly because the etching paste flows after printing or spraying, forming undulating wavy lines after etching. This solution can directly use the first-doped silicon glass layer as the mask layer, eliminating the need for a separate special mask layer, saving process steps, improving production efficiency, and reducing production costs.

[0148] When the mask layer is a structure of a first doped silicon glass layer, photoresist can be printed or sprayed onto the first surface of the semiconductor substrate using screen printing, stencil printing, or photoresist spraying. Then, photoresist is exposed to a second region, causing it to denature and be removed. The denatured photoresist in this region is then removed. Next, a wet etching solution is used to etch away the first doped silicon glass layer and the first doped semiconductor layer in the second region. The purpose is to utilize the photoresist denaturation principle combined with wet etching to remove the first doped silicon glass layer in the second region. After further wet etching, the exposed first doped semiconductor layer is removed. The undenatured photoresist remaining in the first region can act as a barrier layer or mask layer for wet etching of the first doped silicon glass layer, preventing chemical agents from damaging it and achieving a patterned first doped semiconductor layer. The first doped semiconductor layer near the second region exhibits a wavy shape along the second direction, primarily because the exposure and development of the photoresist, combined with the wet etching process, creates undulating wavy lines. This solution can directly use the first doped silicon glass layer as a mask layer, eliminating the need to fabricate a separate special mask layer. This can save process steps, improve production efficiency, and reduce production costs.

[0149] After the above processing, the side of the first doped semiconductor layer near the second region has a wavy shape along the second direction; the first direction is different from the second direction; along the first direction, the distance between the crests (protrusions) and troughs (recesses) of the wavy shape is less than or equal to 4 μm, and further greater than or equal to 1 μm and less than or equal to 4 μm; and / or, the average roughness or undulation of the wavy shape extending along the second direction is less than or equal to 2.4 μm. For example, along the first direction, the distance between the crests and troughs of the wavy shape can be 1 μm, 1.2 μm, 1.5 μm, 1.8 μm, 2 μm, 2.3 μm, 2.5 μm, 2.8 μm, 3 μm, 3.3 μm, 3.5 μm, 3.8 μm, or 4 μm, etc. The average roughness or undulation of the wave shape extending along the second direction can be 2.4 μm, 2.3 μm, 2.2 μm, 2.1 μm, 2.0 μm, 1.9 μm, 1.8 μm, 1.7 μm, 1.6 μm, 1.5 μm, or 1.4 μm, etc. The calculation method for the average roughness or undulation of the wave shape extending along the second direction can refer to the calculation method for average roughness or undulation in the first aspect. The beneficial effects of the third aspect and its various implementations in this application can be referred to the beneficial effect analysis in the first aspect and its various implementations, and will not be repeated here.

[0150] Next, a second doped semiconductor layer is deposited according to the type of solar cell.

[0151] For example, the second doped semiconductor layer is prepared by a low-temperature method such as plasma enhanced chemical vapor deposition (PECVD). The formation location, material and thickness of the second doped semiconductor layer can be referred to the previous description.

[0152] It should be noted that, depending on actual needs, structures such as the first passivation layer, the second passivation layer, the surface passivation layer, and the transparent conductive layer can be selectively formed. The specific formation process will not be described in detail here.

[0153] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0154] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A solar cell, wherein, include: A semiconductor substrate, the semiconductor substrate including opposing first and second surfaces; The first surface has a first region and a second region that are alternately distributed along a first direction; A first doped semiconductor layer is disposed in the first region; The second region does not have the first doped semiconductor layer; The side of the first doped semiconductor layer near the second region is wavy along the second direction; the first direction is different from the second direction. Along the first direction, the distance between the protrusions and depressions of the wave shape is less than or equal to 4 μm; And / or, the undulation of the wave shape extending along the second direction is less than or equal to 2.4 μm.

2. The solar cell according to claim 1, wherein, Along the first direction, the distance between the protrusions and depressions of the wave shape is greater than or equal to 1 μm and less than or equal to 4 μm.

3. The solar cell according to claim 1, wherein, Along the first direction, the distance L1 between the protrusions of the wave shape and the depressions adjacent to the protrusions is greater than or equal to 1 μm and less than or equal to 4 μm.

4. The solar cell according to claim 1, wherein, Along the second direction, the distance L2 between two adjacent protrusions of the wave shape is greater than or equal to 5 μm and less than or equal to 20 μm.

5. The solar cell according to claim 1, wherein, The root mean square roughness of the wave shape extending along the second direction is less than or equal to 2.7 μm.

6. The solar cell according to claim 1, wherein, Along the first direction, the second region includes a third region adjacent to the first region and a fourth region away from the first region, the third region being located between the fourth region and the first region; The surfaces of the third region and the fourth region both have a pyramidal texture structure, and the size uniformity of the pyramidal texture structures on the surfaces of the third region and the fourth region is approximately equal; and / or, along the direction from the first surface to the second surface, the height difference between the surface of the semiconductor substrate in the third region and the surface of the semiconductor substrate in the first region is greater than the height difference between the surface of the semiconductor substrate in the fourth region and the surface of the semiconductor substrate in the first region.

7. The solar cell according to claim 1, wherein, Along the direction from the first surface to the second surface, the height difference between the surface of the semiconductor substrate in the second region and the surface of the semiconductor substrate in the first region is greater than or equal to 1 μm and less than or equal to 10 μm.

8. The solar cell according to claim 1, wherein, The solar cell also includes: A second doped semiconductor layer is disposed on the second region and extends onto a portion of the first doped semiconductor layer; the second doped semiconductor layer and the first doped semiconductor layer have opposite conductivity types.

9. The solar cell according to claim 8, wherein, The first doped semiconductor layer includes a first doped polycrystalline silicon layer; the second doped semiconductor layer includes a doped amorphous silicon layer and / or a doped microcrystalline silicon layer.

10. The solar cell according to claim 8, wherein, In the first region: the second doped semiconductor layer is disposed in a stacked region at a portion of the first doped semiconductor layer, and in the stacked region: the second doped semiconductor layer has an undulating morphology along the first direction at a position close to the first region.

11. The solar cell according to claim 8, wherein, In the first region: the second doped semiconductor layer is disposed at a position of part of the first doped semiconductor layer as a stacked region. In the thickness direction of the solar cell, the second region near the first region also has a tilted region. The thickness of the second doped semiconductor layer in the stacked region is greater than the thickness in the tilted region, and / or the thickness of the second doped semiconductor layer in the stacked region is greater than the thickness outside the tilted region of the second region.

12. The solar cell according to claim 1, wherein, The second region includes a doped region and two spacer regions; along the first direction, the doped region is located between the two spacer regions; along the first direction, the spacer regions are located between the first region and the doped region; the side of the first doped semiconductor layer near the spacer regions is wavy along the second direction; The solar cell also includes: A second doped semiconductor layer is disposed in the doped region; the second doped semiconductor layer and the first doped semiconductor layer have opposite conductivity types. A surface passivation layer is disposed on the first doped semiconductor layer, the second doped semiconductor layer, and the spacer region.

13. The solar cell according to claim 12, wherein, The first doped semiconductor layer includes a second doped polysilicon layer; the second doped semiconductor layer includes a third doped polysilicon layer.

14. The solar cell according to claim 1, wherein, The solar cell further includes a surface passivation layer disposed on the second region and extending onto the first doped semiconductor layer.

15. The solar cell according to any one of claims 1 to 14, wherein, Along the first direction, the distance between the protrusions of the wave shape and the depressions adjacent to the protrusions is L1; Along the second direction, the distance between adjacent protrusions or adjacent depressions in the wave shape is L2; (L1 / L2) ranges from 0.03 to 0.

9.

16. The solar cell according to any one of claims 1 to 14, wherein, In the thickness direction of the solar cell, the second region near the first region also has an inclined region, and the semiconductor substrate surface on the inclined region has an inclined angle α between itself and the surface defined by the first direction and the second direction, where α is 20° to 75°, preferably 30° to 70°, and more preferably 35° to 65°.

17. A photovoltaic module, wherein, The photovoltaic module includes: A battery string, wherein the battery string is formed by connecting a plurality of solar cells as described in any one of claims 1 to 16; An encapsulation layer is used to cover the surface of the battery string.

18. A method for manufacturing a solar cell, wherein, include: Provide a semiconductor substrate; The semiconductor substrate includes opposing first and second surfaces; The first surface has a first region and a second region that are alternately distributed along a first direction; A first doped semiconductor layer is formed on the entire surface of the first surface; A mask layer is formed entirely on the first doped semiconductor layer; The mask layer and the first doped semiconductor layer located in the second region are processed to obtain the first doped semiconductor layer located in the first region, and the first doped semiconductor layer is not formed on the second region; The side of the first doped semiconductor layer near the second region is wavy along the second direction; the first direction is different from the second direction. Along the first direction, the distance between the protrusions and depressions of the wave shape is less than or equal to 4 μm; And / or, the undulation of the wave shape extending along the second direction is less than or equal to 2.4 μm.

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