Superconducting quantum circuit and preparation method therefor
By integrating the fabrication of Josephson junctions with the large-scale circuitry of superconducting quantum chips and air bridges, the problems of cumbersome fabrication processes and the influence of dielectric insulating materials in superconducting quantum circuits have been solved, achieving simplified processes and improved performance.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- YANGTZE DELTA IND INNOVATION CENT OF QUANTUM SCI & TECH
- Filing Date
- 2026-01-16
- Publication Date
- 2026-07-23
AI Technical Summary
The fabrication process of existing superconducting quantum circuits is cumbersome, and the introduction of dielectric insulating layer materials may reduce the performance of quantum bits.
The fabrication of Josephson junctions is integrated into the fabrication of large-scale circuits and air bridges in superconducting quantum chips, eliminating the need for separate fabrication. Direct connection between the Josephson junction and the large-scale circuit, as well as the independence of the electrodes, are achieved through isolation connectors, avoiding the introduction of dielectric insulating materials.
It simplifies the fabrication process of superconducting quantum circuits, improves the stability and uniformity of Josephson junctions, ensures superconducting properties and quantum tunneling effect, and avoids the negative impact of dielectric insulating materials on the performance of qubits.
Smart Images
Figure CN2026073114_23072026_PF_FP_ABST
Abstract
Description
A superconducting quantum circuit and its fabrication method Technical Field
[0001] This application relates to the field of quantum device technology, and in particular to a superconducting quantum circuit and its fabrication method. Background Technology
[0002] Superconducting quantum computing, a quantum computing approach with immense potential, relies on a core hardware component: the superconducting quantum circuit. This circuit primarily consists of six parts: a Josephson junction, a resonant cavity, qubit capacitors, control lines, readout lines, and an air bridge. These components collectively form the foundation of the superconducting quantum circuit, enabling efficient quantum information processing at extremely low temperatures.
[0003] In the fabrication process of superconducting quantum circuits, a superconducting-insulating-superconducting thin film layer is typically prepared on a substrate first. Then, the upper and lower electrode regions of the Josephson junction are defined by etching, and the Josephson junction regions are covered by an insulating layer. Finally, the upper and lower electrodes are brought out by filling with superconducting metal to connect with external circuits. Although this process can improve the uniformity and stability of the Josephson junction performance and is more compatible with traditional semiconductor process equipment, its overall process is relatively cumbersome. Summary of the Invention
[0004] The main objective of this application is to provide a superconducting quantum circuit and its fabrication method, which effectively simplifies the fabrication process of the superconducting quantum circuit.
[0005] To achieve the above objectives, this application provides a method for fabricating a superconducting quantum circuit, comprising the following steps:
[0006] A substrate is provided, and an initial structure of a large structure circuit is formed on one side surface of the substrate, wherein the initial structure is divided by a channel, the channel including a first channel, and the initial structure includes a first superconducting layer, a barrier layer and a second superconducting layer sequentially stacked from the side near the substrate.
[0007] A first photoresist pattern is defined on the surface of the initial structure, wherein the first photoresist pattern is adjacent to the first channel;
[0008] Based on the first photoresist pattern, the second superconducting layer and the barrier layer are etched, and the first photoresist pattern is removed to form a Josephson junction and a large structure circuit.
[0009] An isolation connector is fabricated to obtain a superconducting quantum circuit. The isolation connector includes a third superconducting layer and is used to connect the upper surface of the Josephson junction and the first superconducting layer, and to block the electrical connection between the first electrode and the second electrode of the Josephson junction.
[0010] In one embodiment, the step of forming the initial structure of a large-scale circuit on one side surface of the substrate includes:
[0011] The first superconducting layer, the barrier layer, and the second superconducting layer are sequentially formed on one side surface of the substrate;
[0012] A second photoresist pattern is defined on the surface of the second superconducting layer;
[0013] Based on the second photoresist pattern, the second superconducting layer, the barrier layer, and the first superconducting layer are etched until the substrate is fully exposed. The second photoresist pattern is then removed to form the initial structure.
[0014] In one embodiment, the step of forming the initial structure of a large-scale circuit on one side surface of the substrate includes:
[0015] A third photoresist pattern is defined on one side surface of the substrate;
[0016] The first superconducting layer, the barrier layer, and the second superconducting layer are prepared sequentially.
[0017] The initial structure is formed by peeling off the third photoresist pattern and the first superconducting layer, the barrier layer, and the second superconducting layer on its upper surface.
[0018] In one embodiment, the barrier layer is formed by partial oxidation of the first superconducting layer.
[0019] In one embodiment, the thickness of the first superconducting layer is 100–1000 nm;
[0020] And / or, the thickness of the second superconducting layer is 50–200 nm;
[0021] And / or, the thickness of the third superconducting layer is greater than the sum of the thicknesses of the first superconducting layer and the second superconducting layer, and the thickness of the third superconducting layer is 400-1500 nm;
[0022] The substrate material includes: sapphire and / or intrinsic silicon;
[0023] And / or, the material of the first superconducting layer includes at least one of Al-based superconducting materials, Nb-based superconducting materials, Ta-based superconducting materials, and TiN-based superconducting materials;
[0024] And / or, the material of the second superconducting layer includes at least one of Al-based superconducting materials, Nb-based superconducting materials, Ta-based superconducting materials, and TiN-based superconducting materials;
[0025] And / or, the material of the third superconducting layer includes at least one of Al-based superconducting materials, Nb-based superconducting materials, Ta-based superconducting materials, and TiN-based superconducting materials.
[0026] In one embodiment, the step of preparing the insulating connector includes:
[0027] Define the fourth photoresist pattern;
[0028] Prepare the third superconducting layer;
[0029] A fifth photoresist pattern is defined on the surface of the third superconducting layer;
[0030] The third superconducting layer is etched based on the fifth photoresist pattern until the fourth photoresist pattern is exposed, and the fourth and fifth photoresist patterns are removed to form the isolation connector.
[0031] In one embodiment, the isolation connector includes: a first air bridge and / or a superconducting lead;
[0032] The first air bridge spans the first channel and contacts the upper surface of the Josephson junction and the first superconducting layer, respectively.
[0033] The superconducting lead covers at least a portion of the upper surface of the Josephson junction and extends to contact the first superconducting layer adjacent to the Josephson junction, wherein the side surface of the Josephson junction in contact with the superconducting lead has a native oxide layer.
[0034] In one embodiment, the channel further includes: a second channel and a third channel, and after the step of etching the third superconducting layer based on the fifth photoresist pattern, the method further includes:
[0035] A second air bridge is obtained, which is spaced apart from the isolation connector, wherein the second air bridge spans the second channel and the third channel and contacts the first superconducting layer.
[0036] To achieve the above objectives, this application provides a superconducting quantum circuit, which is fabricated by the superconducting quantum circuit fabrication method described above, comprising: a substrate, a first superconducting layer, a barrier layer, a second superconducting layer, and a third superconducting layer stacked sequentially.
[0037] The first superconducting layer includes a large-structure circuit divided by a channel, the channel including a first channel;
[0038] The overlapping region between the first superconducting layer, the barrier layer and the second superconducting layer constitutes a Josephson junction, and the Josephson junction is adjacent to the first channel;
[0039] The third superconducting layer includes an isolation connector for connecting the upper surface of the Josephson junction and the first superconducting layer, and for blocking the electrical connection between the first electrode and the second electrode of the Josephson junction.
[0040] In one embodiment, the isolation connector includes: a first air bridge and / or a superconducting lead;
[0041] The first air bridge spans the first channel and contacts the upper surface of the Josephson junction and the first superconducting layer, respectively.
[0042] A superconducting lead covers at least a portion of the upper surface of the Josephson junction and extends to contact the first superconducting layer adjacent to the Josephson junction, wherein the side surface of the Josephson junction in contact with the superconducting lead has a native oxide layer.
[0043] In one embodiment, the channel further includes: a second channel and a third channel;
[0044] The second channel, the third channel, and the first superconducting layer located between the second channel and the third channel constitute a resonant cavity.
[0045] In one embodiment, the third superconducting layer further includes a second air bridge spaced apart from the isolation connector, wherein the second air bridge spans the second channel and the third channel and contacts the first superconducting layer.
[0046] This application provides a method for fabricating superconducting quantum circuits, integrating the fabrication of Josephson junctions entirely into the fabrication of the large-scale circuit and air bridge of the superconducting quantum chip. This eliminates the need for separate fabrication, enabling the simultaneous fabrication of the large-scale circuit, air bridge, and Josephson junction, simplifying the overall chip fabrication process. The Josephson junction is directly integrated with the large-scale circuit, eliminating the need for separate wire connections and effectively reducing additional steps required in traditional processes. Furthermore, isolation connectors ensure direct connectivity between the Josephson junction and the large-scale circuit within the superconducting quantum circuit, as well as the independence of the first and second electrodes of the Josephson junction. This ensures the superconducting properties and quantum tunneling effect of the Josephson junction, while avoiding the negative impact on qubit performance caused by the introduction and retention of insulating materials such as oxides and nitrides, thus improving the superconducting qubit performance of the superconducting quantum circuit. Attached Figure Description
[0047] Figure 1 is a flowchart of the superconducting quantum circuit fabrication method involved in the embodiment of this application;
[0048] Figure 2 is a process flow diagram of the superconducting quantum circuit fabrication method involved in the embodiment of this application;
[0049] Figure 3 is a process flow diagram of the superconducting quantum circuit fabrication method involved in the embodiment of this application.
[0050] Figure 4 is a process flow diagram of a more complete embodiment of the superconducting quantum circuit fabrication method involved in the present application.
[0051] Figure 5 is a process flow diagram of a more complete embodiment two of the superconducting quantum circuit fabrication method involved in the embodiments of this application;
[0052] Figure 6 is a schematic diagram of the structure of the superconducting quantum circuit involved in the embodiment of this application;
[0053] Figure 7 is a schematic diagram of the structure of the superconducting quantum circuit involved in the embodiment of this application.
[0054] Figure reference numerals: 100, Superconducting quantum circuit; 110, Substrate; 120, First superconducting layer; 121, First channel; 122, Second channel; 123, Third channel; 130, Barrier layer; 140, Second superconducting layer; 150, Third superconducting layer; 151, First air bridge; 152, Second air bridge; 153, Superconducting lead; 160, Josephson junction; 171, First photoresist pattern; 172, Fourth photoresist pattern; 173, Fifth photoresist pattern; 174, Second photoresist pattern; 175, Third photoresist pattern; 176, Native oxide layer; 180, Large-scale circuit.
[0055] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation
[0056] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below. Where specific conditions are not specified in the embodiments, conventional conditions or conditions recommended by the manufacturer shall apply. Reagents or instruments whose manufacturers are not specified are all conventional products that can be purchased commercially.
[0057] The following detailed description, with appropriate reference to the accompanying drawings, discloses embodiments of the superconducting quantum circuit and its fabrication method of this application. However, unnecessary detailed descriptions may be omitted. For example, detailed descriptions of well-known matters and repetitive descriptions of practically identical structures may be omitted. This is to avoid unnecessarily lengthy descriptions and to facilitate understanding by those skilled in the art. Furthermore, the accompanying drawings and the following description are provided for the purpose of enabling those skilled in the art to fully understand this application and are not intended to limit the subject matter of the claims.
[0058] The "range" disclosed in this application is defined by a lower limit and an upper limit. A given range is defined by selecting a lower limit and an upper limit, which define the boundaries of a particular range. Ranges defined in this way can include or exclude endpoints and can be arbitrarily combined; that is, any lower limit can be combined with any upper limit to form a range. For example, if ranges of 60–120 and 80–110 are listed for a specific parameter, it is understood that ranges of 60–110 and 80–120 are also expected. Furthermore, if minimum range values of 1 and 2 are listed, and if maximum range values of 3, 4, and 5 are listed, then the following ranges are all expected: 1–3, 1–4, 1–5, 2–3, 2–4, and 2–5. In this application, unless otherwise stated, the numerical range "a–b" represents a shortened representation of any combination of real numbers between a and b, where a and b are real numbers. For example, the numerical range "0~5" indicates that all real numbers between "0~5" have been listed in this article; "0~5" is simply a shortened representation of these numerical combinations. Furthermore, when a parameter is stated as an integer ≥2, it is equivalent to disclosing that the parameter is, for example, an integer such as 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, etc.
[0059] Unless otherwise specified, all embodiments and optional embodiments of this application can be combined to form new technical solutions.
[0060] Unless otherwise specified, all steps of this application may be performed sequentially or randomly, preferably sequentially. For example, if the method includes steps (a) and (b), it means that the method may include steps (a) and (b) performed sequentially, or it may include steps (b) and (a) performed sequentially. For example, if the method may also include step (c), it means that step (c) may be added to the method in any order. For example, the method may include steps (a), (b), and (c), or it may include steps (a), (c), and (b), or it may include steps (c), (a), and (b), etc.
[0061] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the technical solution of this application is further described below in conjunction with the accompanying drawings and embodiments. However, this application is not limited to the listed embodiments, but should also include any other well-known modifications within the scope of the claims made in this application.
[0062] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.
[0063] In conventional techniques, superconducting quantum circuits typically involve first fabricating a superconducting-insulator-superconducting thin film layer on a substrate, then defining the upper and lower electrode regions of the Josephson junction using an etching process, and finally encapsulating the Josephson junction region with an insulating layer. Finally, the upper and lower electrodes are brought out by filling with superconducting metal to connect to external circuitry. While this process improves the uniformity and stability of the Josephson junction's performance and offers better compatibility with traditional semiconductor equipment, the need to fabricate and connect each component individually makes the overall process cumbersome. Furthermore, the introduced dielectric insulating layer, such as silicon oxide or silicon nitride, can significantly degrade the performance of superconducting quantum bits.
[0064] This application provides a method for fabricating superconducting quantum circuits, integrating the fabrication of Josephson junctions entirely into the fabrication of the large-scale circuit and air bridge of the superconducting quantum chip. This eliminates the need for separate fabrication, enabling simultaneous fabrication of the large-scale circuit, air bridge, and Josephson junction, simplifying the overall chip fabrication process. The Josephson junction is directly integrated with the large-scale circuit, eliminating the need for separate wire connections and effectively reducing additional steps required in traditional processes. Furthermore, isolation connectors ensure direct connectivity between the Josephson junction and the large-scale circuit within the superconducting quantum circuit, as well as independence between the first and second electrodes of the Josephson junction. This ensures the superconducting properties and quantum tunneling effect of the Josephson junction, while avoiding the negative impacts on qubit performance caused by the introduction and retention of insulating materials such as oxides and nitrides, thus improving the superconducting qubit performance of the superconducting quantum circuit.
[0065] The first embodiment of this application provides a method for fabricating a superconducting quantum circuit, referring to Figure 1, including the following steps:
[0066] Step S10: Provide a substrate and form an initial structure of a large structure circuit on one side surface of the substrate, wherein the initial structure is divided by a channel, the channel includes a first channel, and the initial structure includes a first superconducting layer, a barrier layer and a second superconducting layer stacked sequentially from the side near the substrate.
[0067] In one feasible embodiment, a clean substrate is provided, and an initial structure of a large-structure circuit, segmented by multiple channels, is formed on the substrate surface. The initial structure of the large-structure circuit includes a first superconducting layer, a barrier layer, and a second superconducting layer sequentially stacked from the side closest to the substrate, and the channels include a first channel. The large-structure circuit is a basic circuit structure, typically composed of four parts: a resonant cavity, a bit capacitor, control lines, and read lines. Therefore, an initial structure of the large-structure circuit, consisting of a resonant cavity, bit capacitor, control lines, and read lines, can be formed on the substrate first.
[0068] It is understandable that large-scale circuit structures include at least one first channel.
[0069] In one feasible embodiment, the substrate material includes sapphire and / or intrinsic silicon.
[0070] Sapphire is favored for its low dielectric loss, high mechanical strength, good thermal conductivity, relatively low price, good chemical stability, small coefficient of thermal expansion, and high transmittance of infrared light. These properties help improve the coherence, stability, and performance of superconducting quantum circuits.
[0071] Intrinsic silicon, with its high resistance and low leakage current characteristics, provides excellent insulation properties for superconducting quantum circuits, which helps to reduce circuit noise and improve the coherence time of qubits.
[0072] In one feasible embodiment, the material of the first superconducting layer includes at least one of Al-based superconducting materials, Nb-based superconducting materials, Ta-based superconducting materials, and TiN-based superconducting materials.
[0073] In one feasible embodiment, the material of the second superconducting layer includes at least one of Al-based superconducting materials, Nb-based superconducting materials, Ta-based superconducting materials, and TiN-based superconducting materials.
[0074] Aluminum (Al) has a long coherence length, a low melting point, and its surface is easily oxidized to form an oxide barrier layer. It is also more compatible with silicon semiconductor processes. Therefore, it is a commonly used material for preparing Josephson junctions.
[0075] Niobium (Nb) has a high melting point and can be used to prepare large-area dense thin films by magnetron sputtering, making it suitable for the fabrication of large-sized devices such as capacitors, coplanar waveguides, and inductors on quantum chips.
[0076] Tantalum (Ta) has small grains and a relatively rough surface. Quantum bits made from tantalum films have a higher quality factor and a coherence time exceeding 0.5 ms. Therefore, it has potential application value in superconducting quantum circuits.
[0077] Titanium nitride (TiN) has low surface roughness and good surface smoothness, which is crucial for the fabrication of high-quality superconducting tunnel junctions.
[0078] In one feasible embodiment, the thickness of the first superconducting layer is 100 to 1000 nm. For example, the thickness of the first superconducting layer is 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1000 nm, etc.
[0079] In one feasible embodiment, the thickness of the second superconducting layer is 50–200 nm. For example, the thickness of the second superconducting layer is 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, 190 nm, 200 nm, etc.
[0080] Step S20: Define a first photoresist pattern on the surface of the initial structure, wherein the first photoresist pattern is adjacent to the first channel;
[0081] In one feasible embodiment, a photoresist layer is prepared on the surface of the second superconducting layer, and the photoresist layer is patterned to obtain a first photoresist pattern adjacent to the first channel.
[0082] For example, photoresist is uniformly coated on the surface of the second superconducting layer, exposed to the photoresist, and then developed to prepare the photoresist layer. The exposure can be performed using an ultraviolet contact lithography machine, a stepper lithography machine, or a laser direct writing device; the development can be performed using a solution corresponding to the type of photoresist and the lithography parameters.
[0083] Step S30: Etch the second superconducting layer and barrier layer based on the first photoresist pattern, and remove the first photoresist pattern to form a Josephson junction and a large structure circuit.
[0084] In one feasible embodiment, a first photoresist pattern is used as an etch-resistant layer to etch the second superconducting layer and the barrier layer until the first superconducting layer is completely exposed. After removing the remaining first photoresist pattern on the substrate surface, a large-structure circuit is formed, along with a Josephson junction consisting of the overlapping region between the first superconducting layer, the barrier layer, and the second superconducting layer. The first superconducting layer in the overlapping region constitutes the lower electrode of the Josephson junction and is directly integrated with the large-structure circuit. This eliminates the need to separately fabricate the lower electrode of the Josephson junction or separately connect the Josephson junction to the large-structure circuit via leads during the fabrication of the superconducting quantum circuit, effectively reducing the additional steps required in traditional processes and simplifying the entire fabrication process.
[0085] Step S40: Prepare an isolation connector to obtain a superconducting quantum circuit. The isolation connector includes a third superconducting layer. The isolation connector is used to connect the upper surface of the Josephson junction and the first superconducting layer, and to block the electrical connection between the first electrode and the second electrode of the Josephson junction.
[0086] In one feasible embodiment, the lower electrode of the Josephson junction is already connected to the large structure circuit. In order for the superconducting quantum circuit to function properly, the upper electrode of the Josephson junction also needs to be connected to the large structure circuit. Therefore, an isolation connector is further fabricated to connect the upper surface of the Josephson junction (i.e., the upper electrode of the Josephson junction) and the first superconducting layer to achieve the connection between the Josephson junction and the large structure circuit. At the same time, the isolation connector can block the electrical connection between the first electrode and the second electrode of the Josephson junction. The first electrode and the second electrode of the Josephson junction can be the upper electrode and the lower electrode of the Josephson junction, respectively.
[0087] For example, the upper surface of the Josephson junction forms the upper electrode (i.e., the first electrode) of the Josephson junction, and the upper surface of the Josephson junction forms the lower electrode (i.e., the second electrode) of the Josephson junction.
[0088] In one feasible embodiment, step S40, the step of preparing the isolation connector, includes:
[0089] S41 defines the fourth photoresist pattern;
[0090] In one feasible embodiment, a photoresist layer is prepared again and patterned to obtain a fourth photoresist pattern, which can be used to avoid the deposition of a third superconducting layer in certain areas, for example, to avoid the deposition of the third superconducting layer in the channel portion of a large structure circuit.
[0091] Step S42: Prepare the third superconducting layer;
[0092] In one feasible embodiment, a third superconducting layer is prepared, wherein the third superconducting layer can be prepared on the substrate surface by methods such as double tilt evaporation, magnetron sputtering, metal-organic deposition, electron beam co-evaporation, pulsed laser deposition, metal-organic chemical vapor deposition, and high-rate physical vapor deposition.
[0093] In one feasible embodiment, the thickness of the third superconducting layer is greater than the sum of the thicknesses of the first and second superconducting layers, and the thickness of the third superconducting layer is 400–1500 nm. For example, the thickness of the third superconducting layer is 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1000 nm, 1100 nm, 1200 nm, 1300 nm, 1400 nm, 1500 nm, etc.
[0094] In one feasible embodiment, the material of the third superconducting layer includes at least one of Al-based superconducting materials, Nb-based superconducting materials, Ta-based superconducting materials, and TiN-based superconducting materials.
[0095] For example, if the first superconducting layer is prone to oxidation, the oxide layers on the surfaces of the first and second superconducting layers can be pre-cleaned and removed before the third superconducting layer is formed on the substrate surface, and then the substrate can be placed in a multi-cavity electron beam evaporation device to deposit the third superconducting layer.
[0096] Step S43: Define a fifth photoresist pattern on the surface of the third superconducting layer;
[0097] In one feasible embodiment, a photoresist layer is prepared again on the surface of the third superconducting layer away from the substrate, and the photoresist layer is patterned to obtain a fifth photoresist pattern.
[0098] Step S44: Etch the third superconducting layer based on the fifth photoresist pattern until the fourth photoresist pattern is exposed, and remove the fourth and fifth photoresist patterns to form an isolation connector.
[0099] In one feasible embodiment, the third superconducting layer is etched using the fifth photoresist pattern as an etch-resistant layer until the exposed third superconducting layer is completely etched clean. The remaining fourth and fifth photoresist patterns are then removed to form an isolation connector connecting the upper surface of the Josephson junction and the first superconducting layer, thereby enabling the Josephson junction to communicate with the large-structure circuit. At the same time, the isolation connector can block the electrical communication between the first and second electrodes of the Josephson junction.
[0100] For example, the etching method can be dry etching or wet etching. Dry etching can be inductively coupled plasma etching or reactive ion etching, and the etching gas can be fluorine-based gas or chlorine-based gas. Wet etching can be performed using an etching solution.
[0101] In one feasible embodiment, the channel further includes a second channel and a third channel, wherein the second channel, the third channel, and the first superconducting layer located between the second channel and the third channel constitute a resonant cavity. After step S44, the step of etching the third superconducting layer based on the fifth photoresist pattern, the method further includes:
[0102] Step S45, a second air bridge is obtained, which is spaced apart from the isolation connector, wherein the second air bridge spans the second channel and the third channel and is in contact with the first superconducting layer.
[0103] In one feasible embodiment, the fourth photoresist pattern can simultaneously include the regions corresponding to the first region and the piers of the second air bridge, while the fifth photoresist pattern can also simultaneously include the regions corresponding to the second region and the bridge surfaces of the second air bridge, respectively. Thus, a single etching process can simultaneously obtain the spaced-apart isolation connectors and the second air bridge. The isolation connectors connect the upper electrode of the Josephson junction to the large-structure circuit, maintaining the independence of the upper and lower electrodes to ensure the superconducting properties and quantum tunneling effect of the Josephson junction. The second air bridge spans the second and third channels (i.e., the resonant cavity) and contacts the first superconducting layer located on both sides of the second and third channels, balancing the potential difference, reducing parasitic capacitance, and thereby optimizing the performance of the resonant cavity.
[0104] By using isolation connectors, the adverse effects of introducing dielectric insulating layer materials into superconducting quantum circuits can be avoided, effectively improving the performance of superconducting quantum bits in superconducting quantum circuits.
[0105] The second air bridge can balance the potential difference and reduce parasitic capacitance, thereby optimizing the performance of the resonant cavity.
[0106] It is understandable that large-scale circuits include at least one second channel and at least one third channel.
[0107] In this embodiment, the fabrication of the Josephson junction is fully integrated into the fabrication of the large-scale circuit and air bridge of the superconducting quantum chip, eliminating the need for separate fabrication. This allows for simultaneous fabrication of the large-scale circuit, air bridge, and Josephson junction, simplifying the overall chip fabrication process. Furthermore, the Josephson junction is directly integrated with the large-scale circuit, eliminating the need for separate wire connections and effectively reducing additional steps required in traditional processes. In addition, isolation connectors ensure direct connectivity between the Josephson junction and the large-scale circuit in the superconducting quantum circuit, as well as independence between the first and second electrodes of the Josephson junction. This ensures the superconducting properties and quantum tunneling effect of the Josephson junction and avoids the negative impact on qubit performance caused by the introduction and retention of insulating materials such as oxides and nitrides, thus improving the superconducting qubit performance of the superconducting quantum circuit. The superconducting quantum circuit fabrication method provided in this application is fully compatible with traditional semiconductor equipment and processes, enabling fabrication on large-size wafers and effectively improving the stability and uniformity of the Josephson junction.
[0108] Based on the first embodiment described above, a second embodiment of the superconducting quantum circuit fabrication method of this application is provided. In this embodiment, step S10, the step of forming the initial structure of a large-structure circuit on one side surface of the substrate, includes:
[0109] Step A11: A first superconducting layer, a barrier layer, and a second superconducting layer are sequentially formed on one side surface of the substrate;
[0110] In one feasible embodiment, a first superconducting layer, a barrier layer, and a second superconducting layer are sequentially formed on one side surface of a clean substrate.
[0111] For example, a first superconducting layer and / or a second superconducting layer can be formed on the surface of a clean substrate by methods such as double-tilt evaporation, magnetron sputtering, metal-organic deposition, electron beam co-evaporation, pulsed laser deposition, metal-organic chemical vapor deposition, and high-rate physical vapor deposition.
[0112] In one feasible embodiment, the barrier layer is formed by partial oxidation of the first superconducting layer. After the first superconducting layer is formed on the substrate surface, the first superconducting layer located on the surface can be oxidized to form the barrier layer. The barrier layer is located between the first and second superconducting layers and can be formed directly on the superconducting layer by oxidation. In this way, the barrier layer of the Josephson junction and the fabrication of the large-structure circuit can be completed in the same process flow without the need for additional insulating layer material.
[0113] For example, the substrate is placed in a multi-cavity electron beam evaporation apparatus to deposit a first superconducting layer; then it is transferred to an oxidation cavity to oxidize using oxygen to prepare a barrier layer; then it is transferred again to a multi-cavity electron beam evaporation apparatus to deposit a second superconducting layer.
[0114] For example, the oxidation pressure during the barrier layer formation process is 1 to 99 torr, such as 1 torr, 10 torr, 20 torr, 30 torr, 40 torr, 50 torr, 60 torr, 70 torr, 80 torr, 90 torr, 95 torr, 99 torr, etc.; the oxidation time is 1 to 100 min, such as 1 min, 10 min, 20 min, 30 min, 40 min, 50 min, 60 min, 70 min, 80 min, 90 min, 95 min, 100 min, etc.
[0115] For example, a clean sapphire substrate is placed in a multi-cavity electron beam evaporation apparatus, and the vacuum level is less than 1×e -9 In the case of torr, the first aluminum film (i.e., the first superconducting layer) is deposited by evaporation, and then transferred to the oxidation chamber to prepare the barrier layer by oxidation using oxygen; then transferred to the evaporation chamber again to deposit the second aluminum film (i.e., the second superconducting layer).
[0116] Step A12: Define a second photoresist pattern on the surface of the second superconducting layer;
[0117] In one feasible embodiment, a photoresist layer is prepared on the surface of the second superconducting layer, and the photoresist layer is patterned to form a second photoresist pattern.
[0118] For example, photoresist is uniformly coated on the surface of the second superconducting layer, exposed to the photoresist, and then developed to prepare the photoresist layer. The exposure can be performed using an ultraviolet contact lithography machine, a stepper lithography machine, or a laser direct writing device; the development can be performed using a solution corresponding to the type of photoresist and the lithography parameters.
[0119] Step A13: Etch the second superconducting layer, the barrier layer, and the first superconducting layer based on the second photoresist pattern until the substrate is fully exposed, and remove the second photoresist pattern to form the initial structure.
[0120] In one feasible embodiment, the second photoresist pattern is used as an etch-resistant layer to etch the second superconducting layer, the barrier layer and the first superconducting layer until the substrate is completely exposed. After removing the remaining second photoresist pattern, the initial structure of the large-structure circuit is formed.
[0121] For example, the etching method can be dry etching or wet etching. Dry etching can be inductively coupled plasma etching or reactive ion etching, and the etching gas can be fluorine-based gas or chlorine-based gas. Wet etching can be performed using an etching solution.
[0122] For example, refer to Figure 2. Referring to Figure 2(a), a clean substrate 110 is provided, and a first superconducting layer 120, a barrier layer 130, and a second superconducting layer 140 are sequentially formed on one side surface of the substrate 110. Referring to Figure 2(b), a photoresist layer (not shown) is prepared and patterned on the surface of the second superconducting layer 140 to obtain a second photoresist pattern 174. Referring to Figure 2(c), using the second photoresist pattern 174 as an etch resist layer, the second superconducting layer 140, the barrier layer 130, and the first superconducting layer 120 are etched until the substrate 110 is completely exposed, and the second photoresist pattern 174 is removed to form the initial structure 180 of the large-structure circuit.
[0123] In this embodiment, the initial pattern of a large-structure circuit is formed on the substrate through an etching process, achieving high-precision pattern transfer with stable process and strong repeatability.
[0124] In one feasible embodiment, step S10, the step of forming the initial structure of the large-structure circuit on one side surface of the substrate, includes:
[0125] Step B11: Define a third photoresist pattern on one side surface of the substrate;
[0126] In one feasible embodiment, a photoresist layer is pre-prepared on one side surface of the substrate and the photoresist layer is patterned, forming a third photoresist pattern.
[0127] For example, a photoresist is uniformly coated on the substrate surface, exposed to the photoresist, and then developed to prepare a photoresist layer. The exposure can be performed using an ultraviolet contact lithography machine, a stepper lithography machine, or a laser direct writing device; the development can be performed using a solution corresponding to the type of photoresist and the lithography parameters.
[0128] Step B12: The first superconducting layer, the barrier layer, and the second superconducting layer are prepared sequentially.
[0129] In one feasible embodiment, a first superconducting layer, a barrier layer, and a second superconducting layer are sequentially fabricated on the surface of a substrate having a third photoresist pattern.
[0130] For example, a first superconducting layer and / or a second superconducting layer can be formed on the surface of a clean substrate by methods such as double-tilt evaporation, magnetron sputtering, metal-organic deposition, electron beam co-evaporation, pulsed laser deposition, metal-organic chemical vapor deposition, and high-rate physical vapor deposition.
[0131] In one feasible embodiment, the barrier layer is formed by partially oxidizing the first superconducting layer. After the first superconducting layer is formed on the substrate surface, the first superconducting layer located on the surface can be oxidized to form the barrier layer.
[0132] For example, the substrate is placed in a multi-cavity electron beam evaporation apparatus to deposit a first superconducting layer; then it is transferred to an oxidation cavity to oxidize using oxygen to prepare a barrier layer; then it is transferred again to a multi-cavity electron beam evaporation apparatus to deposit a second superconducting layer.
[0133] For example, a clean sapphire substrate with a third photoresist pattern on its surface is placed in a multi-cavity electron beam evaporation apparatus, and the evaporation is carried out at a vacuum level of less than 1×e. -9 In the case of torr, the first aluminum film (i.e., the first superconducting layer) is deposited by evaporation, and then transferred to the oxidation chamber to prepare the barrier layer by oxidation using oxygen; then transferred to the evaporation chamber again to deposit the second aluminum film (i.e., the second superconducting layer).
[0134] Step B13: Remove the third photoresist pattern and the first superconducting layer, barrier layer and second superconducting layer on its upper surface to form the initial structure.
[0135] In one feasible embodiment, the third photoresist pattern, as well as the first superconducting layer, the barrier layer, and the second superconducting layer located on the upper surface of the third photoresist pattern, are stripped to obtain the initial structure of the large-structure circuit.
[0136] For example, the third photoresist pattern and its first superconducting layer, barrier layer and second superconducting layer on its surface can be removed by chemical dissolution, pyrolysis, wet removal, mechanical removal, dry stripping, wet stripping and other methods.
[0137] For example, the initial structure is formed by chemically dissolving the third photoresist pattern and the first superconducting layer, barrier layer and second superconducting layer on its upper surface.
[0138] For example, refer to Figure 3. Referring to Figure 3(a), a clean substrate 110 is provided, and a photoresist layer (not shown) is prepared and patterned on one side surface of the substrate 110 to obtain a third photoresist pattern 175. Referring to Figure 3(b), a first superconducting layer 120, a barrier layer 130, and a second superconducting layer 140 are sequentially formed on the surface of the substrate 110 on which the third photoresist pattern 175 is formed. Referring to Figure 3(c), the third photoresist pattern 175 and the first superconducting layer 120, the barrier layer 130, and the second superconducting layer 140 on its upper surface are stripped to form an initial structure 180.
[0139] In this embodiment, the initial structure of the large-scale circuit is obtained by vapor deposition and lift-off process; this method can realize the fabrication of large-area, highly stable and repeatable superconducting junctions, and can also avoid damage to the substrate during the etching process.
[0140] Based on the first and / or second embodiments described above, a third embodiment of the superconducting quantum circuit fabrication method of this application is provided. In this embodiment, the isolation connector includes: a first air bridge and / or a superconducting lead.
[0141] The first air bridge spans the first channel and contacts the upper surface of the Josephson junction and the first superconducting layer, respectively.
[0142] The superconducting lead covers at least a portion of the upper surface of the Josephson junction and extends to a first superconducting layer contact adjacent to the Josephson junction, the side surface of the Josephson junction in contact with the superconducting lead having a native oxide layer.
[0143] In one feasible embodiment, the isolation connector includes a first air bridge spanning a first channel and contacting the upper surface of the Josephson junction and the first superconducting layer, respectively, whereby the first channel can constitute a bit capacitor in a large-scale circuit. The first air bridge enables the connection between the Josephson junction and the large-scale circuit while preventing electrical connection between the first and second electrodes of the Josephson junction.
[0144] For example, a superconducting quantum circuit may include multiple Josephson junctions, each of which can be connected to a large-scale circuit via a first air bridge and a superconducting lead.
[0145] To aid in understanding the above technical solutions, a more complete embodiment of this application is provided, referring to Figure 4. Referring to Figure 4(a), a substrate 110 is provided, and an initial structure (not shown in the figure) of a large-structure circuit 180 divided by channels is formed on the surface of the substrate 110. The channels include a first channel 121, a second channel 122, and a third channel 123. The initial structure includes a first superconducting layer 120, a barrier layer 130, and a second superconducting layer 140 sequentially stacked from the side closest to the substrate. Referring to Figure 4(b), a photoresist layer is prepared and patterned on the surface of the second superconducting layer 140 to obtain a first photoresist pattern 171 adjacent to the first channel 121. Referring to Figure 4(c), using the first photoresist pattern 171 as an etch resist layer, the second superconducting layer 140 and the barrier layer 130 are etched until the first superconducting layer 120 is completely exposed. The first photoresist pattern 171 is then removed to form a Josephson junction 160 and the large-structure circuit 180. Referring to Figure 4(d), a photoresist layer is prepared and patterned to obtain a fourth photoresist pattern 172. Referring to Figure 4(e), after removing the native oxide layers on the exposed surfaces of the first superconducting layer 120 and the second superconducting layer 140, a third superconducting layer 150 is deposited. Referring to Figure 4(f), a photoresist layer is prepared and patterned on the surface of the third superconducting layer 150 to obtain a fifth photoresist pattern 173. Referring to Figure 4(g), using the fifth photoresist pattern 173 as an etch resist layer, the third superconducting layer 150 is etched until the exposed third superconducting layer 150 is completely etched clean, forming a first air bridge 151 that spans the first channel 121 and contacts the upper surface of the Josephson junction 160 and the first superconducting layer 120, respectively, as an isolation connector; and a second air bridge 152 that is spaced apart from the first air bridge 151 and spans the second channel 122 and the third channel 123. Referring to Figure 4(h), the fourth photoresist pattern 172 and the fifth photoresist pattern 173 are removed to obtain a superconducting quantum circuit 100. The superconducting quantum circuit 100 includes: a substrate 110, a first superconducting layer 120, a barrier layer 130, a second superconducting layer 140, and a third superconducting layer 150, sequentially stacked. The first superconducting layer 120 includes a large-structure circuit divided by channels, including a first channel 121, a second channel 122, and a third channel 123. The second channel 122, the third channel 123, and the third channel 123 are located at the first... The first superconducting layer 120 between the second channel 122 and the third channel 123 forms a resonant cavity (not shown in the attached diagram); the overlapping region between the first superconducting layer 120, the barrier layer 130, and the second superconducting layer 140 forms a Josephson junction 160, and the Josephson junction 160 is adjacent to the first channel 121; the third superconducting layer 150 includes: a first air bridge 151 and a second air bridge 152 spaced apart; the first air bridge 151 spans the first channel 121 and contacts the upper surface of the Josephson junction 160 and the first superconducting layer 120, respectively. The second air bridge 152 spans the second channel 122 and the third channel 123 and contacts the first superconducting layer 120.
[0146] In one feasible embodiment, if the first and second superconducting layers are made of easily oxidizable materials, a natural oxide layer can be formed on the surfaces of the first and second superconducting layers during the fabrication of the superconducting quantum circuit. Therefore, before fabricating the third superconducting layer, it is usually necessary to pre-clean and remove the oxide layer from the surfaces of the first and second superconducting layers. However, since the natural oxide layer is generally electrically insulating and cannot achieve electron tunneling, it cannot achieve the Josephson effect at ultra-low temperatures. Therefore, this natural oxide layer can be used to block the electrical connection between the first and second electrodes of the Josephson junction. Based on this, embodiments of this application can use superconducting leads as barrier connectors. Before fabricating the third superconducting layer, the natural oxide layer on the side surface where the Josephson junction contacts the superconducting lead is retained to prevent the superconducting lead from connecting the first and second electrodes of the Josephson junction. Simultaneously, the remaining portion of the natural oxide layer is removed. Then, the superconducting lead is fabricated by depositing the third superconducting layer to cover at least a portion of the upper surface of the Josephson junction and the width of the first channel adjacent to the Josephson junction, extending to the contact point of the first superconducting layer adjacent to the Josephson junction, thus achieving a direct connection between the Josephson junction and the large-structure circuit. At this time, because the side surface where the Josephson junction contacts the superconducting lead has a natural oxide layer, the independence of the first and second electrodes of the Josephson junction is ensured.
[0147] Understandably, the superconducting leads cover the width of the first channel adjacent to the Josephson junction, but not the entire length of the first channel.
[0148] To aid in understanding the above technical solutions, a more complete second embodiment of this application is provided, referring to Figure 5. Referring to Figure 5(a), a substrate 110 is provided, and an initial structure (not shown in the figure) of a large-structure circuit 180 divided by channels is formed on the surface of the substrate 110. The channels include a first channel 121, a second channel 122, and a third channel 123. The initial structure includes a first superconducting layer 120, a barrier layer 130, and a second superconducting layer 140 sequentially stacked from the side closest to the substrate. Referring to Figure 5(b), a photoresist layer is prepared and patterned on the surface of the second superconducting layer 140 to obtain a first photoresist pattern 171 adjacent to the first channel 121. Referring to Figure 5(c), using the first photoresist pattern 171 as an etch resist layer, the second superconducting layer 140 and the barrier layer 130 are etched until the first superconducting layer 120 is completely exposed. The first photoresist pattern 171 is then removed to form a Josephson junction 160 and the large-structure circuit 180. Referring to Figure 5(d), a photoresist layer is prepared and patterned to obtain a fourth photoresist pattern 172. Simultaneously, a native oxide layer 176 is formed on the side surface of the Josephson junction exposed to air. Referring to Figure 5(e), the native oxide layer 170 on the side surface where the Josephson junction 160 contacts the superconducting lead 153 is retained, while the remaining oxide layer is removed, and a third superconducting layer 150 is deposited. Referring to Figure 5(f), a photoresist layer is prepared and patterned on the surface of the third superconducting layer 150 to obtain a fifth photoresist pattern 173. Referring to Figure 5(g), the third superconducting layer 150 is etched using the fifth photoresist pattern 173 as an etch resist layer until the exposed third superconducting layer 150 is completely etched clean, forming a superconducting lead 153 that covers the upper surface of the Josephson junction 160 and the width of the first channel 121 adjacent to the Josephson junction 160, and extends to the first superconducting layer 120 adjacent to the Josephson junction 160 as an isolation connector; and a second air bridge 152 that is spaced apart from the superconducting lead 153 and spans the second channel 122 and the third channel 123.Referring to Figure 5(h), the fourth photoresist pattern 172 and the fifth photoresist pattern 173 are removed to obtain a superconducting quantum circuit 100. The superconducting quantum circuit 100 includes: a substrate 110, a first superconducting layer 120, a barrier layer 130, a second superconducting layer 140, and a third superconducting layer 150, sequentially stacked. The first superconducting layer 120 includes a large-structure circuit divided by channels, including a first channel 121, a second channel 122, and a third channel 123. The second channel 122, the third channel 123, and the channel located between the second channel 122 and the third channel 123 are described. The first superconducting layer 120 between the two layers forms a resonant cavity (not shown in the figure); the overlapping region between the first superconducting layer 120, the barrier layer 130, and the second superconducting layer 140 forms a Josephson junction 160, and the Josephson junction 160 is adjacent to the first channel 121; the third superconducting layer 150 includes: a superconducting lead 153 spaced apart and a second air bridge 152; the superconducting lead 153 covers the upper surface of the Josephson junction 160 and the width of the first channel 121 adjacent to the Josephson junction 160, and extends to contact the first superconducting layer 120 adjacent to the Josephson junction 160. The second air bridge 152 spans the second channel 122 and the third channel 123 and contacts the first superconducting layer 120.
[0149] This application provides a superconducting quantum circuit, comprising: a substrate, a first superconducting layer, a barrier layer, a second superconducting layer, and a third superconducting layer stacked sequentially;
[0150] The first superconducting layer includes a large-structure circuit divided by a channel, the channel including the first channel;
[0151] The overlapping region between the first superconducting layer, the barrier layer, and the second superconducting layer constitutes a Josephson junction, and the Josephson junction is adjacent to the first channel.
[0152] The third superconducting layer includes: an isolation connector;
[0153] The isolation connector spans the first channel and contacts the upper surface of the Josephson junction and the first superconducting layer, respectively, and the first channel can form a bit capacitor in a large-scale circuit.
[0154] In one feasible embodiment, the isolation connector includes: a first air bridge and / or a superconducting lead;
[0155] The first air bridge spans the first channel and contacts the upper surface of the Josephson junction and the first superconducting layer, respectively.
[0156] The superconducting lead covers at least a portion of the upper surface of the Josephson junction and extends to a first superconducting layer contact adjacent to the Josephson junction, the side surface of the Josephson junction in contact with the superconducting lead having a native oxide layer.
[0157] In one feasible embodiment, the channel for interrupting the large structure circuit further includes a second channel and a third channel, wherein the second channel, the third channel, and the first superconducting layer located between the second channel and the third channel constitute a resonant cavity.
[0158] In one feasible embodiment, the third superconducting layer further includes a second air bridge spaced apart from the isolation connector, wherein the second air bridge spans the second channel and the third channel and contacts the first superconducting layer to balance the potential difference, reduce parasitic capacitance, and thereby optimize the performance of the resonant cavity.
[0159] For example, referring to FIG6, the superconducting quantum circuit 100 includes: a substrate 110, a first superconducting layer 120, a barrier layer 130, a second superconducting layer 140 and a third superconducting layer 150 stacked sequentially;
[0160] The first superconducting layer 120 includes a large structure circuit divided by channels, including a first channel 121, a second channel 122 and a third channel 123, wherein the second channel 122, the third channel 123 and the first superconducting layer 120 located between the second channel 122 and the third channel 123 constitute a resonant cavity (not shown in the figure).
[0161] The overlapping region between the first superconducting layer 120, the barrier layer 130, and the second superconducting layer 140 constitutes a Josephson junction 160, and the Josephson junction 160 is adjacent to the first channel 121.
[0162] The third superconducting layer 150 includes: a first air bridge 151 and a second air bridge 152 arranged at intervals;
[0163] The first air bridge 151 spans the first channel 121 and contacts the upper surface of the Josephson junction 160 and the first superconducting layer 120, respectively.
[0164] The second air bridge 152 spans the second channel 122 and the third channel 123 and is in contact with the first superconducting layer 120.
[0165] For example, referring to FIG7, the superconducting quantum circuit 100 includes: a substrate 110, a first superconducting layer 120, a barrier layer 130, a second superconducting layer 140 and a third superconducting layer 150 stacked sequentially.
[0166] The first superconducting layer 120 includes a large structure circuit divided by channels, including a first channel 121, a second channel 122 and a third channel 123, wherein the second channel 122, the third channel 123 and the first superconducting layer 120 located between the second channel 122 and the third channel 123 constitute a resonant cavity (not shown in the figure).
[0167] The overlapping region between the first superconducting layer 120, the barrier layer 130, and the second superconducting layer 140 constitutes a Josephson junction 160, and the Josephson junction 160 is adjacent to the first channel 121.
[0168] The third superconducting layer 150 includes: superconducting leads 153 spaced apart and a second air bridge 152; the superconducting leads 153 cover the upper surface of the Josephson junction 160 and the width of the first channel 121 adjacent to the Josephson junction 160, and extend to contact the first superconducting layer 120 adjacent to the Josephson junction 160.
[0169] The second air bridge 152 spans the second channel 122 and the third channel 123 and is in contact with the first superconducting layer 120.
[0170] In this embodiment, the Josephson junction and the large-scale circuit in the superconducting quantum circuit are directly connected through an isolation connector, thereby avoiding the adverse effects of dielectric insulating layer materials on circuit performance and effectively improving the superconducting quantum bit performance of the superconducting quantum circuit. Meanwhile, the components of the superconducting quantum circuit provided in this embodiment consist of a substrate, multiple superconducting layers (a first superconducting layer, a second superconducting layer, and a third superconducting layer), and a barrier layer. This stacked structure allows for the simultaneous formation of the Josephson junction and other parts of the large-scale circuit in a single process flow, for example, by controlling the formation and patterning of each layer. Since the fabrication of the Josephson junction and the large-scale circuit can be completed in the same process flow, this effectively reduces the additional steps required in conventional processes, such as dual-angle evaporation and stripping processes, thereby simplifying the entire fabrication process.
[0171] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the patent protection scope of this application.
Claims
1. A method for fabricating a superconducting quantum circuit, characterized in that, The method for fabricating the superconducting quantum circuit includes the following steps: A substrate is provided, and an initial structure of a large structure circuit is formed on one side surface of the substrate, wherein the initial structure is divided by a channel, the channel including a first channel, and the initial structure includes a first superconducting layer, a barrier layer and a second superconducting layer sequentially stacked from the side near the substrate. A first photoresist pattern is defined on the surface of the initial structure, wherein the first photoresist pattern is adjacent to the first channel; Based on the first photoresist pattern, the second superconducting layer and the barrier layer are etched, and the first photoresist pattern is removed to form a Josephson junction and a large structure circuit. An isolation connector is fabricated to obtain a superconducting quantum circuit. The isolation connector includes a third superconducting layer and is used to connect the upper surface of the Josephson junction and the first superconducting layer, and to block the electrical connection between the first electrode and the second electrode of the Josephson junction.
2. The method for fabricating a superconducting quantum circuit as described in claim 1, characterized in that, The step of forming the initial structure of the large-structure circuit on one side surface of the substrate includes: The first superconducting layer, the barrier layer, and the second superconducting layer are sequentially formed on one side surface of the substrate; A second photoresist pattern is defined on the surface of the second superconducting layer; Based on the second photoresist pattern, the second superconducting layer, the barrier layer, and the first superconducting layer are etched until the substrate is fully exposed. The second photoresist pattern is then removed to form the initial structure.
3. The method for fabricating a superconducting quantum circuit as described in claim 1, characterized in that, The step of forming the initial structure of the large-structure circuit on one side surface of the substrate includes: A third photoresist pattern is defined on one side surface of the substrate; The first superconducting layer, the barrier layer, and the second superconducting layer are prepared sequentially. The initial structure is formed by peeling off the third photoresist pattern and the first superconducting layer, the barrier layer, and the second superconducting layer on its upper surface.
4. The method for fabricating a superconducting quantum circuit as described in any one of claims 1 to 3, characterized in that, The barrier layer is formed by partial oxidation of the first superconducting layer.
5. The method for fabricating a superconducting quantum circuit as described in any one of claims 1 to 3, characterized in that, The thickness of the first superconducting layer is 100–1000 nm; And / or, the thickness of the second superconducting layer is 50–200 nm; And / or, the thickness of the third superconducting layer is greater than the sum of the thicknesses of the first superconducting layer and the second superconducting layer, and the thickness of the third superconducting layer is 400-1500 nm; The substrate material includes: sapphire and / or intrinsic silicon; And / or, the material of the first superconducting layer includes at least one of Al-based superconducting materials, Nb-based superconducting materials, Ta-based superconducting materials, and TiN-based superconducting materials; And / or, the material of the second superconducting layer includes at least one of Al-based superconducting materials, Nb-based superconducting materials, Ta-based superconducting materials, and TiN-based superconducting materials; And / or, the material of the third superconducting layer includes at least one of Al-based superconducting materials, Nb-based superconducting materials, Ta-based superconducting materials, and TiN-based superconducting materials.
6. The method for fabricating a superconducting quantum circuit as described in claim 1, characterized in that, The steps for preparing the isolation connector include: Define the fourth photoresist pattern; Prepare the third superconducting layer; A fifth photoresist pattern is defined on the surface of the third superconducting layer; The third superconducting layer is etched based on the fifth photoresist pattern until the fourth photoresist pattern is exposed, and the fourth and fifth photoresist patterns are removed to form the isolation connector.
7. The method for fabricating a superconducting quantum circuit as described in claim 1 or 6, characterized in that, The isolation connector includes: a first air bridge and / or a superconducting lead; The first air bridge spans the first channel and contacts the upper surface of the Josephson junction and the first superconducting layer, respectively. The superconducting lead covers at least a portion of the upper surface of the Josephson junction and extends to contact the first superconducting layer adjacent to the Josephson junction, wherein the side surface of the Josephson junction in contact with the superconducting lead has a native oxide layer.
8. The method for fabricating a superconducting quantum circuit as described in claim 6, characterized in that, The channel further includes: a second channel and a third channel, and after the step of etching the third superconducting layer based on the fifth photoresist pattern, it further includes: A second air bridge is obtained, which is spaced apart from the isolation connector, wherein the second air bridge spans the second channel and the third channel and contacts the first superconducting layer.
9. A superconducting quantum circuit, characterized in that, The superconducting quantum circuit is fabricated by the method described in any one of claims 1 to 8, comprising: a substrate, a first superconducting layer, a barrier layer, a second superconducting layer, and a third superconducting layer stacked sequentially; The first superconducting layer includes a large-structure circuit divided by a channel, the channel including a first channel; The overlapping region between the first superconducting layer, the barrier layer and the second superconducting layer constitutes a Josephson junction, and the Josephson junction is adjacent to the first channel; The third superconducting layer includes an isolation connector for connecting the upper surface of the Josephson junction and the first superconducting layer, and for blocking the electrical connection between the first electrode and the second electrode of the Josephson junction.
10. The superconducting quantum circuit as described in claim 9, characterized in that, The isolation connector includes: a first air bridge and / or a superconducting lead; The first air bridge spans the first channel and contacts the upper surface of the Josephson junction and the first superconducting layer, respectively. A superconducting lead covers at least a portion of the upper surface of the Josephson junction and extends to contact the first superconducting layer adjacent to the Josephson junction, wherein the side surface of the Josephson junction in contact with the superconducting lead has a native oxide layer.
11. The superconducting quantum circuit as described in claim 9, characterized in that, The trench also includes: a second trench and a third trench; The second channel, the third channel, and the first superconducting layer located between the second channel and the third channel constitute a resonant cavity.
12. The superconducting quantum circuit as described in claim 11, characterized in that, The third superconducting layer further includes a second air bridge spaced apart from the isolation connector, wherein the second air bridge spans the second channel and the third channel and contacts the first superconducting layer.