Solar cell and photovoltaic module

Abstract

The present application relates to the technical field of photovoltaics, and provides a solar cell and a photovoltaic module. The solar cell comprises: a silicon substrate, wherein in the thickness direction of the silicon substrate, the silicon substrate has a first surface and a second surface that are opposite to each other; a texture structure arranged on the first surface; and a transport layer and a passivation anti-reflection layer stacked on the texture structure, wherein in the thickness direction of the silicon substrate, the transport layer is located between the silicon substrate and the passivation anti-reflection layer, the passivation anti-reflection layer is provided with a plurality of openings, and the ratio of the maximum size of each opening to the one-dimensional size of the texture structure is 0.5 to 5.

Description

Solar cell and photovoltaic module

[0001] The present application claims priority to Chinese Patent Application No. 202510120935.1, filed on January 24, 2025, entitled "Solar cell and photovoltaic module", Chinese Patent Application No. 202510122638.0, filed on January 24, 2025, entitled "Solar cell and photovoltaic module", and Chinese Patent Application No. 202510090615.6, filed on January 20, 2025, entitled "Solar cell and photovoltaic module", all of which are incorporated herein by reference in their entirety. TECHNICAL FIELD

[0002] The present application relates to the field of photovoltaic technology, and in particular, to a solar cell and a photovoltaic module. BACKGROUND

[0003] A solar cell is a device that directly converts light energy into electrical energy through the photoelectric effect. Since solar cells mainly use clean energy, they have broad application prospects. Specifically, solar cells use the photovoltaic principle to generate carriers, and then use electrodes to lead out the carriers, thereby facilitating the effective use of electrical energy.

[0004] A conventional high-temperature metallization process uses high-temperature silver paste to sinter on a passivation anti-reflection layer. The paste can penetrate the interface of the passivation anti-reflection layer and form good metal contact with the underlying transport layer. However, the cost of high-temperature silver paste is relatively high, so in recent years the industry has been actively researching other metallization processes. For example, an opening is made in the passivation anti-reflection layer to expose the underlying transport layer. A low-temperature metallization process is used to make electrodes on the exposed transport layer, such as using low-temperature paste instead of high-temperature silver paste, or using an electroplating process to form electrodes. The bonding force or contact effect of the electrode and the transport layer at the opening has a great influence on the current collection and conduction effect.

[0005] In existing solar cells, the bonding force or contact effect of the electrode and the transport layer is in conflict with the quality of the film layer, which affects the performance of the solar cell.

[0006] SUMMARY

[0007] The present application provides a solar cell and a photovoltaic module, which aims to solve the problem of conflict between the bonding force or contact effect of the electrode and the transport layer and the quality of the film layer in existing solar cells.

[0008] In a first aspect, the present application provides a solar cell, comprising:

[0009] A silicon substrate; the silicon substrate has opposing first and second surfaces in the direction of its thickness.

[0010] A textured structure is provided on the first surface; a transport layer and a passivation antireflection layer are stacked on the textured structure; in the direction of the thickness of the silicon substrate, the transport layer is located between the silicon substrate and the passivation antireflection layer; the passivation antireflection layer has a plurality of openings; the ratio of the maximum size of the openings to the one-dimensional size of the textured structure is 0.5 to 5.

[0011] In this application, the passivation antireflection layer typically suffers damage to the film layer below and around the opening during the opening process. The texture structure on the first surface exhibits regular unevenness, and the film layer deposited at the raised ridges is usually of poor quality and more susceptible to damage during the opening process. When the ratio of the maximum size of the opening to the one-dimensional size of the texture structure is greater than 5, the opening is too large, encompassing too much texture structure in the opening area, resulting in significant damage to the film layer below and around the opening during the opening process, affecting the film quality, especially the passivation quality. When the ratio of the maximum size of the opening to the one-dimensional size of the texture structure is less than 0.5, the opening is too small. When an electrode is placed above the opening, the contact area between the electrode and the exposed transport layer at the opening is too small, affecting the collection and conduction of current or charge carriers. Furthermore, the textured structure has a larger specific surface area and rougher raised ridges. If the opening is too small, the opening area will cover too little textured structure, resulting in insufficient roughness at the opening and poor adhesion or contact between the electrode and the transport layer. In this application, the ratio of the maximum size of the opening to the one-dimensional size of the textured structure is 0.5 to 5, which is at least a balance between the damage to the film layers below and around the opening during the opening process and the adhesion and contact performance between the electrode and the transport layer. On the one hand, it reduces damage to the film layers below and around the opening, resulting in better quality of the transport layer, passivation and antireflection layer, etc., ensuring good passivation effects. On the other hand, it enhances the adhesion between the electrode and the transport layer, avoiding the risk of pull-out in subsequent processes and improving reliability. At the same time, the contact performance between the electrode and the transport layer is improved, reducing contact resistance, thereby improving current collection and conduction effects, and thus improving the performance of the solar cell. In summary, this application achieves both good passivation effect and good contact performance.

[0012] In some embodiments, the transport layer includes: a first transport layer and a second transport layer, wherein the first transport layer and the second transport layer have different doping types;

[0013] The maximum size of the opening in the corresponding region of the first transport layer is 1 to 5 times the one-dimensional size of the texture structure;

[0014] The maximum size of the opening in the corresponding region of the second transport layer is 0.5 to 5 times the one-dimensional size of the texture structure.

[0015] In some embodiments, the transmission layer includes a plurality of transmission regions, and in one of the transmission regions, the openings are spaced apart to form at least one row of openings, the extension direction of the row of openings being parallel to the extension direction of the transmission region.

[0016] In some embodiments, the number of open rows in one transmission region is greater than or equal to 2; the spacing d2 between adjacent open rows is 0.5 to 5 times the one-dimensional dimension of the texture structure.

[0017] In some embodiments, the openings in adjacent rows of openings are staggered.

[0018] In some embodiments, within one of the opening rows, the spacing d1 between adjacent openings is 1 to 7 times the one-dimensional dimension of the texture structure.

[0019] In some embodiments, the texture structure includes: a base; the one-dimensional dimension of the base is 5µm to 40µm, and / or the side length of the base is 5µm to 40µm.

[0020] In some embodiments, the transmission layer includes a plurality of transmission zones, with each of the tower bases arranged in a row along the extension direction of the transmission zone; and / or, each of the openings is spaced apart and arranged in a row along the extension direction of the transmission zone.

[0021] In some embodiments, within one of the opening rows, the spacing d1 between adjacent openings is 10 μm to 100 μm; and / or, the spacing d2 between adjacent opening rows is 8 μm to 80 μm.

[0022] In some embodiments, the transport layer includes: a first transport layer and a second transport layer, wherein the first transport layer and the second transport layer have different doping types; the side length of the base in the second transport layer is greater than the side length of the base in the first transport layer; and / or, the depth of the base in the second transport layer is less than the depth of the base in the first transport layer.

[0023] In some embodiments, the maximum size of the opening is 10 μm to 45 μm.

[0024] In some embodiments, the region corresponding to the opening on the side of the transport layer opposite to the silicon substrate is a contact region; at least one of the contact regions has an edge line;

[0025] The solar cell also includes an electrode disposed on the side of the passivation antireflection layer away from the silicon substrate, the electrode passing through the opening and contacting the transport layer.

[0026] In some embodiments, at least one of the contact areas has a base, and the ridge line includes the side length of the base.

[0027] In some embodiments, at least one hole is provided at the location of the ridge line within the contact area.

[0028] In some embodiments, the edge of the hole has an annular protrusion.

[0029] In some embodiments, the density of holes at the ridge line is greater than the density of holes in other areas, and / or the density of protrusions at the ridge line is greater than the density of protrusions in other areas.

[0030] In some embodiments, at least some of the holes at the location of the ridge are interconnected, and / or the protrusions at the ridge extend along the ridge in a strip shape.

[0031] In some embodiments, the contact area has a plurality of holes; the contact area includes a central region and an edge region surrounding the central region; for a single contact area, the size of the hole in the central region is larger than the size of the hole in the edge region.

[0032] In some embodiments, the area outside the contact area on the side of the transport layer opposite to the silicon substrate is a non-contact area;

[0033] The roughness of the contact area is greater than that of the non-contact area.

[0034] In some embodiments, the transmission layer includes a plurality of transmission regions, and on one of the transmission regions, there is a gap between the contact area and the edge of the transmission region.

[0035] In some embodiments, the height and width of the protrusion are both less than or equal to 0.5 μm; the direction of the height is parallel to the direction of the thickness of the silicon substrate, and the width is the maximum dimension of the protrusion in a plane perpendicular to the direction of the height.

[0036] In some embodiments, the transport layer includes a polysilicon doped layer; the polysilicon doped layer has a polysilicon region and an amorphous silicon region, the amorphous silicon region being located on the side of the polysilicon doped layer opposite to the silicon substrate; the amorphous silicon region is located between the passivation antireflection layer and the polysilicon region, and is located at the opening.

[0037] In some embodiments, the thickness of the amorphous silicon at the ridge is greater than the thickness of the amorphous silicon in other regions.

[0038] In some embodiments, the electrode comprises a stacked seed layer and a non-burn-through slurry layer.

[0039] In some embodiments, the transport layer includes a first transport layer, and the solar cell further includes a first electrode disposed on the side of the passivation antireflection layer away from the silicon substrate, the first electrode passing through the opening and contacting the first transport layer;

[0040] Along the extension direction of the first electrode, the silicon substrate includes a first edge and a second edge disposed opposite to each other, and the plurality of openings includes a first opening closest to the first edge, the distance between the edge of the first opening and the first edge being b1, 1000μm≥b1≥150μm.

[0041] In some embodiments, the distance between the edge of the first opening and the edge of the first transmission layer along the extending direction of the first electrode is d3;

[0042] The first transport layer has the same doping type as the silicon substrate, b1-d3≤20μm; or, the first transport layer has the opposite doping type to the silicon substrate, 50μm≤d3≤550μm.

[0043] In some embodiments, along the extending direction of the first electrode, the distance between the edge of the first opening and the edge of the electrode is b2, where 50 μm ≤ b2 ≤ 500 μm.

[0044] In some embodiments, the opening closest to the edge of the first transmission layer along the second direction is the second opening, and the second direction intersects the extending direction of the first electrode;

[0045] Along the second direction, the distance between the edge of the second opening and the edge of the first transmission layer is S, where 50μm≤S≤550μm.

[0046] In some embodiments, the passivation antireflection layer has a heat-affected zone surrounding the opening, the width of which is W; 1μm≤W≤5μm, or S>W.

[0047] In some embodiments, the heat-affected zone includes a plurality of openings filled with a conductive material, the conductive material being electrically connected to the first transport layer.

[0048] In some embodiments, the first electrode includes a stacked seed layer and a slurry layer, the seed layer filling a plurality of the openings, and the slurry layer covering the seed layer and the conductive material on the side opposite to the silicon substrate.

[0049] In some embodiments, the orthographic projections of the heat-affected zones surrounding two adjacent openings onto the first surface do not overlap.

[0050] In some embodiments, the orthographic projection of the plurality of openings on the first surface is located inside the orthographic projection of the first electrode on the first surface; or, part or all of the orthographic projection of the first opening on the first surface is located outside the orthographic projection of the first electrode on the first surface.

[0051] In some embodiments, the first transmission layer is a strip extending along the extension direction of the first electrode, and a plurality of the first transmission layers are spaced apart along the second direction; or, the entire first transmission layer is disposed on the first surface.

[0052] In some embodiments, the transport layer further includes a second transport layer, the second transport layer having the opposite conductivity type to the first transport layer;

[0053] The second transport layer covers at least a portion of the second surface of the silicon substrate; or, the second transport layer covers at least a portion of the first surface of the silicon substrate, and the first transport layer and the second transport layer are spaced apart along a second direction.

[0054] In some embodiments, the first transport layer comprises one or more of polycrystalline silicon, amorphous silicon, nanocrystalline silicon, and microcrystalline silicon; the solar cell further comprises a first interface layer located on the side of the first transport layer near the silicon substrate;

[0055] The second transport layer includes one or more of polycrystalline silicon, amorphous silicon, nanocrystalline silicon, and microcrystalline silicon; the solar cell also includes a second interface layer located on the side of the second transport layer near the silicon substrate.

[0056] A second aspect of this application provides a photovoltaic module, wherein the photovoltaic module includes a plurality of battery strings, the battery strings including a plurality of solar cells and a plurality of interconnecting elements, the interconnecting elements being used to connect the plurality of solar cells in series; wherein the solar cells are any of the aforementioned solar cells.

[0057] The aforementioned solar cells and photovoltaic modules have the same or similar beneficial effects, and will not be repeated here to avoid repetition.

[0058] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0059] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0060] Figures 1 to 3, 7, 11 to 15 and 17 show partial structural schematic diagrams of ten solar cells in embodiments of this application;

[0061] Figures 4 to 6, 8 to 10, and 16 show partial SEM structural diagrams of seven types of solar cells in the embodiments of this application;

[0062] Figure numbering explanation: 1-Silicon substrate, 12-Tower base, 11-Ridge of tower base, 2-Polycrystalline silicon doped layer, 3-Tunneling oxide layer, 4-Passivation and antireflection layer, 5-Electrode, 51-Seed layer, 52-Slurry layer, 6-Opening, 71-Contact area, 72-Non-contact area, 73-Transmission area of ​​the first transport layer, 74-Transmission area of ​​the second transport layer, 8-Isolation area, 9-Void, 21-Amorphous silicon region, 22-Micron-crystal and / or nano-crystal, 23-Polycrystalline silicon region, 24-Protrusion, 1a-First edge, 70-First transport layer, 61-First opening, 50-First electrode, 13-Heat-affected zone, 14-First interface layer, 15-Conductive material. Specific Implementation

[0063] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0064] This application provides a solar cell. In terms of cell type, the solar cell provided in this application includes, but is not limited to, any of the following photovoltaic cells capable of converting light energy into electrical energy. For example, the solar cell provided in this application can be any of the following: a tunneling oxide passivated contact cell (Topcon), a doped polycrystalline silicon all-back contact cell (TBC), a composite passivated back contact cell (HPBC), a bifacial hybrid cell, etc. Referring to Figures 1, 7, and 15, the solar cell includes: a silicon substrate 1, a transport layer, and a passivation antireflection layer 4. In the thickness direction Q of the silicon substrate 1, the silicon substrate 1 has opposing first and second surfaces. During the operation of the solar cell, the surface of the silicon substrate 1 that mainly receives light is its light-facing surface. In the thickness direction Q of the silicon substrate 1, the back-light surface and the light-facing surface are opposite each other. Of the first and second surfaces, one surface can be the back-light surface of the silicon substrate 1, and the other surface can be the light-facing surface of the silicon substrate 1. For example, in Figures 1 and 7, the upper surface of the silicon substrate is the back-light surface of the silicon substrate. It should be noted that the polycrystalline silicon doped layer 2 in the accompanying drawings, as shown in Figures 1 and 7, may include both N-type and P-type polycrystalline silicon doped layers. It should also be noted that in solar cells, the silicon substrate can be replaced by materials such as germanium (Ge) or gallium arsenide (GaAs), and this application does not specifically limit this. The silicon substrate can be an intrinsically conductive substrate, an N-type silicon substrate, or a P-type silicon substrate. In some embodiments, the silicon substrate 1 is a P-type or N-type silicon substrate. Compared to an intrinsic silicon substrate, a P-type or N-type silicon substrate has better conductivity, resulting in a lower bulk resistivity in the final solar cell, thereby improving the efficiency of the solar cell.

[0065] For example, the silicon substrate 1 can be a P-type or N-type silicon substrate. The N-type silicon substrate has advantages such as high minority carrier lifetime, no light decay, and good performance in low light.

[0066] In solar cell technologies, to reduce the cost of high-temperature silver paste, openings are typically made at the interface of the passivation antireflection layer or passivation layer such as silicon nitride. Part of the passivation antireflection layer or passivation layer is removed to form exposed transport layer contact windows. Electrodes are then fabricated using low-temperature metallization processes, such as using low-temperature paste instead of high-temperature silver paste, or electroplating. However, the adhesion between electrodes formed by low-temperature metallization and the transport layer is currently lower than that provided by the fusion of the glass matrix within the silver paste and the silicon interface in high-temperature silver paste electrodes. Furthermore, to ensure the quality of the transport layer film, the film is usually quite uniform, resulting in poor adhesion between the electrode and the contact area within the transport layer. All these factors contribute to a higher risk of electrode detachment from the transport layer, reducing the structural reliability of the solar cell.

[0067] A transport layer and a passivation antireflection layer 4 are stacked on at least one surface of the first surface and the second surface of the silicon substrate 1. In the thickness direction Q of the silicon substrate 1, the transport layer is located between the silicon substrate 1 and the passivation antireflection layer 4. Referring to Figures 2 and 3, the passivation antireflection layer 4 has several openings 6 at local locations; the number of openings 6 in the passivation antireflection layer 4 is not specifically limited. The openings 6 in this application may be circular, square, elliptical, or other shapes. Because the passivation antireflection layer has insulating properties, opening regions are provided, and these openings expose at least a portion of the transport layer. This method allows electrodes to be formed at the openings using a low-temperature metallization process, reducing metallization costs. After the passivation antireflection layer 4 has an opening 6, the area corresponding to the opening 6 on the side of the transport layer facing away from the silicon substrate 1 will be exposed. Referring to Figures 4 to 6, the area corresponding to the opening 6 on the side of the transport layer facing away from the silicon substrate 1 is the contact area between the transport layer and the electrode. That is, the area corresponding to the opening 6 on the side of the transport layer facing away from the silicon substrate 1 is the contact area 71, and the area outside the contact area 71 on the side of the transport layer facing away from the silicon substrate 1 is the non-contact area 72. SEM image refers to scanning electron microscope image.

[0068] This application primarily studies the opening and its surrounding features in solar cells from three levels. The first level focuses on the surface of the silicon substrate where the transport layer and passivation / anti-reflection layer 4 are located, investigating the opening and its surrounding features to at least address the contradiction between the bonding strength or contact effect between the electrode and transport layer and the passivation quality in existing solar cells. The second level focuses on the contact area corresponding to the opening on the side of the transport layer away from the silicon substrate, investigating the opening and its surrounding features to at least address the problem of insufficient bonding strength and poor reliability in the contact area between the electrode and transport layer in existing solar cells. The third level focuses on the relative positional relationship between the opening and its surrounding structures, investigating the opening and its surrounding features to at least address the problem of poor passivation effect in the edge regions of solar cells.

[0069] The following sections will explain each of the three levels in detail, starting with the first level, then the second, and finally the third. It should be noted that content already covered in previous sections will not be repeated in subsequent sections to avoid repetition.

[0070] First, let's introduce the content of the first level:

[0071] A textured structure is formed on the first surface of the silicon substrate 1. This first surface can be either the light-facing or back-facing side of the silicon substrate, without specific limitations. For example, in Figures 1 and 7, the first surface of the silicon substrate refers to its back-facing side. The textured structure here can refer to the textured structure of the base 12 (the roughly square outline or structure within the frame in Figure 5), or it can be a textured structure of other shapes, such as a regular or irregular textured structure composed of at least one straight edge and / or at least one curved edge. The textured structure usually exhibits unevenness at the edges. It should be noted that the base 12 is a polished structure or an auxiliary structure on a polished surface, indicating that the area on the surface of the silicon substrate 1 where the transport layer is formed is a polished surface or relatively flat, resulting in better quality of the transport layer, passivation antireflection layer 4, and other films formed thereon, achieving good passivation effects such as surface passivation. For example, the passivation antireflection layer 4 or the passivation layer can passivate the surface of the transport layer, reduce its carrier recombination rate, and further improve the photoelectric conversion efficiency of the solar cell.

[0072] It is understandable that in solar cells, the film layer on the silicon substrate 1 is relatively thin, typically at the nanometer level. Therefore, after the transport layer is covered on the silicon substrate, the texture structure on the silicon substrate 1 will conform to the transport layer. On the surface of the transport layer away from the silicon substrate, the texture structure is still clearly visible. In determining the texture structure, the texture structure on the surface of the transport layer away from the silicon substrate can be used as the standard, or the texture structure on the first surface of the silicon substrate 1 can be used as the standard.

[0073] The transport layer and passivation / anti-reflection layer 4 are stacked on the textured structure of the first surface of the silicon substrate 1. The textured structure has a certain regular undulation feature. The textured structure on the silicon substrate allows for a larger contact area between the transport layer, passivation / anti-reflection layer 4, and other films formed thereon and the silicon substrate, achieving good passivation effects. The transport layer here can include a P-type transport layer and / or an N-type transport layer. Both the P-type and N-type transport layers can be located on the textured structure of the back surface of the silicon substrate 1, in which case it is a back-contact cell. Alternatively, either the P-type or N-type transport layer can be located on the textured structure of the first surface of the silicon substrate 1, and the other can be located on the second surface of the silicon substrate 1, in which case it is a double-sided contact cell. The morphology of the second surface is not limited. The specific material of the transport layer is not limited. For example, referring to Figures 1 and 7, the transport layer may include a polysilicon doped layer 2 containing polysilicon regions. The thickness of the polysilicon doped layer 2 can be from 50 nm to 250 nm. Unless otherwise specified, the direction of the thickness of the polysilicon doped layer 2, as well as the direction of the thickness mentioned in other structures in this application, is parallel to the thickness direction Q of the silicon substrate 1. Whether the transport layer includes other layers is not specifically limited.

[0074] It should be noted that the transport layer can include one or more of polycrystalline silicon, amorphous silicon, nanocrystalline silicon, and microcrystalline silicon. Doped polycrystalline silicon layers exhibit higher carrier transport characteristics; therefore, when the transport layer is a doped polycrystalline silicon layer or contains doped polycrystalline silicon, the carrier transport efficiency is higher, which is beneficial for improving the photoelectric conversion efficiency of the back contact cell. Of course, the transport layer can also be one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon.

[0075] The maximum size of opening 6 can refer to: the maximum size of opening 6 on the side away from the silicon substrate, or the maximum size of opening 6 on the side close to the silicon substrate, or the maximum size of opening 6 at a location between the side away from the silicon substrate and the side close to the silicon substrate, or the average of at least two of the above maximum sizes of an opening; or the average of the maximum sizes of multiple openings. For example, if opening 6 is a circular opening, then the maximum size of the opening is the diameter of the circle; if opening 6 is a square opening, then the maximum size of the opening is the side length of the square.

[0076] In some embodiments, the opening 6 is at least one of a circle, a near-circular shape, a rectangle, and an ellipse, and the shape of the contact area 71 matches the shape of the opening 6 at the corresponding position. The opening 6 of the above shapes is easily achieved through laser ablation. More importantly, the size and shape of the opening are easily controlled during the laser ablation process, resulting in more precise shape and size. It should be noted that "near-circular" in this application refers to an approximation of a circle. The shape of the opening 6 can also be a combination of at least two of the shapes selected from circles, near-circles, rectangles, and ellipses; no specific limitation is made in this regard.

[0077] For example, in Figures 2, 3, 11 to 14 and 17, the opening is circular. As another example, in Figures 4 to 6 and 8, the opening or contact area 71 is roughly circular.

[0078] The one-dimensional dimension of a texture structure can refer to: when a texture structure is a base, the one-dimensional dimension of the texture structure can be the side length of the base, or the diagonal of the base, or the average of both; when a texture structure is a closed shape, the one-dimensional dimension of the texture structure can be one side length of the texture structure, or the average of multiple side lengths, or the diagonal of the closed shape, or the average of at least two of the above; when a texture structure is a non-closed shape, the one-dimensional dimension of the texture structure can be one side length of the texture structure, or the average of multiple side lengths, or the total side length of the non-closed shape, or the average of at least two of the above; or, the average of the one-dimensional dimensions of multiple texture structures.

[0079] During the opening process, the passivation antireflection layer often causes damage to the film layer below and around the opening. The texture structure on the first surface exhibits regular unevenness, and the film layer deposited at the raised ridges is of poor quality and is more susceptible to damage during the opening process. When the ratio of the maximum size of the opening to the one-dimensional size of the texture structure is greater than 5, the opening is too large, and the opening area contains too much texture structure, causing greater damage to the film layer below and around the opening during the opening process, affecting the film quality, especially the passivation quality. When the ratio of the maximum size of the opening to the one-dimensional size of the texture structure is less than 0.5, the opening is too small. When the opening is too small, the contact area between the electrode and the exposed transport layer at the opening is too small, affecting the collection and conduction of current or charge carriers. Furthermore, the textured structure has a larger specific surface area and rougher raised ridges. If the opening is too small, the opening area will cover too little textured structure, resulting in insufficient roughness at the opening and poor bonding or contact between the electrode and the transport layer. In this application, the ratio of the maximum size of the opening to the one-dimensional size of the textured structure is 0.5 to 5, which is at least a balance between the damage to the film layer below and around the opening during the opening process and the bonding and contact performance between the electrode and the transport layer. On the one hand, it reduces damage to the film layer below and around the opening, resulting in better quality of the transport layer, passivation and antireflection layer, etc., ensuring good passivation and other effects. On the other hand, it enhances the bonding force between the electrode and the transport layer, avoiding the risk of pull-out in subsequent processes and improving reliability. At the same time, the contact performance between the electrode and the transport layer is improved, reducing contact resistance, thereby improving current collection and conduction, and thus improving the performance of the solar cell. In summary, this application achieves both good passivation effect and good contact performance.

[0080] For example, referring to Figure 5, the maximum size of an opening is d4. The texture structure can be considered as the base of the tower. The side length of the base, d5, is the one-dimensional size of the texture structure. At this time, d4 / d5 is the ratio of the maximum size of the opening to the one-dimensional size of the texture structure.

[0081] According to embodiments of this application, in order to form a ratio of the maximum size of the opening to the one-dimensional size of the texture structure of 0.5 to 5, for example, when the opening is achieved using a laser process, the size of the laser spot can be adjusted; or, when the texture structure is a base, the parameters of the polishing process, such as time and temperature, can be adjusted to adjust the one-dimensional size of the base structure; or, the opening process and the texture structure process can be adjusted simultaneously. Specifically, these can be flexibly adjusted according to the needs of the actual application.

[0082] The passivation antireflection layer 4 mentioned in this application can provide good passivation and antireflection effects, and its specific material is not limited. For example, the passivation antireflection layer 4 may include one or more of silicon nitride, silicon oxynitride, and silicon oxide, or the passivation antireflection layer 4 may include a stacked aluminum oxide layer and a silicon nitride layer, wherein the aluminum oxide layer is closer to the silicon substrate, the thickness of the aluminum oxide layer can be 4 nm to 10 nm, and the thickness of the silicon nitride layer can be 50 nm to 150 nm.

[0083] In some embodiments, referring to Figures 2, 3, and 17, the transport layer includes a first transport layer and a second transport layer. The first and second transport layers have different doping types, meaning that in this case, both the first and second transport layers are located on the textured structure of the backlight surface or the first surface of the silicon substrate. The first transport layer is either a P-type transport layer or an N-type transport layer, and the second transport layer is either a P-type transport layer or an N-type transport layer. For example, the first transport layer is a P-type transport layer, and the second transport layer is an N-type transport layer. Another example is that the second transport layer is a P-type transport layer, and the first transport layer is an N-type transport layer. The maximum size of the opening in the corresponding region of the first transport layer is 1 to 5 times the one-dimensional size of the aforementioned textured structure; the maximum size of the opening in the corresponding region of the second transport layer is 0.5 to 5 times the one-dimensional size of the aforementioned textured structure. For the corresponding regions of the first and second transport layers, the one-dimensional size of the textured structure can be the same or different. For the corresponding regions of the first and second transport layers in the passivation antireflection layer, the maximum sizes of the openings are different and fall within corresponding ranges. Specifically, the degree of damage to transport layers made of different materials varies during the opening process, and the contact performance between transport layers made of different materials and electrodes also varies. Here, the main difference lies in the material properties of the first and second transport layers. A suitable multiple of the one-dimensional size of the opening and texture structure was selected. This is the result of optimizing and balancing the damage to the corresponding transport layer during the opening process and the contact performance between the transport layer and the electrode. The transport layer can withstand the damage caused by the opening, and the contact performance between the transport layer and the electrode is good.

[0084] For example, this solar cell is a TBC solar cell. Referring to Figures 1, 7, and 17, the TBC solar cell is a back-contact solar cell. Here, the first transport layer is a P-type transport layer, specifically a P-type doped polycrystalline silicon layer, and the second transport layer is an N-type transport layer, specifically an N-type doped polycrystalline silicon layer. A tunneling oxide layer 3 is also present between the first and second transport layers and the silicon substrate 1. In the process of fabricating the TBC solar cell, the P-type doped polycrystalline silicon layer can be fabricated first, followed by the N-type doped polycrystalline silicon layer. In this TBC solar cell: the maximum size of the opening in the corresponding region of the P-type doped polycrystalline silicon layer is 1, 1.2, 1.4, 1.5, 1.8, 2, 2.3, 2.5, 2.8, 2.9, 3, 3.2, 3.4, 3.5, 3.6, 3.9, 4, 4.5, and 5 times the one-dimensional size of the textured structure; the maximum size of the opening in the corresponding region of the N-type doped polycrystalline silicon layer is 0.5, 0.7, 0.9, 1, 1.1, 1.3, 1.5, 1.8, 2, 2.2, 2.4, 2.5, 2.7, 2.8, 2.9, 3, 3.2, 3.3, 3.5, 3.6, 3.6, 4, 4.5, and 5 times the one-dimensional size of the textured structure.

[0085] Specifically, under the same opening process parameters, P-type doped polysilicon layers may suffer less damage than N-type doped polysilicon layers. Furthermore, the contact performance between P-type doped polysilicon layers and electrodes is typically slightly weaker than that between N-type doped polysilicon layers and electrodes. Therefore, the maximum size of the opening in the corresponding region of the P-type doped polysilicon layer in the passivation antireflection layer can be appropriately larger, or equal to the maximum size of the opening in the corresponding region of the N-type doped polysilicon layer, to optimize damage and contact performance. Simultaneously, openings should be made in both the corresponding regions of the P-type and N-type doped polysilicon layers in the passivation antireflection layer under the same opening process parameters to simplify the process and save production costs.

[0086] It should be noted that, in determining the maximum size of the opening in the region corresponding to the first transmission layer as a specific multiple of the one-dimensional size of the texture structure, the texture structure here can be the average one-dimensional size of the texture structure of the first surface, or it can be the one-dimensional size of any texture structure on the first surface, or it can be the one-dimensional size of any texture structure on the first surface corresponding to the first transmission layer, or it can be the average of multiple one-dimensional sizes of texture structures on the first surface corresponding to the first transmission layer, or it can be the one-dimensional size of any texture structure on the first surface corresponding to the second transmission layer, or it can be the average of multiple one-dimensional sizes of texture structures on the first surface corresponding to the second transmission layer. No limitation is imposed on any of these. The process of determining the maximum size of the opening in the region corresponding to the first transmission layer as a specific multiple of the one-dimensional size of the texture structure is similar and will not be elaborated further.

[0087] In some embodiments, the openings in the corresponding region of the first transmission layer and the openings in the corresponding region of the second transmission layer may have the same shape, size, and number, or they may be different. For example, the openings in the corresponding region of the first transmission layer and the openings in the corresponding region of the second transmission layer may have the same shape and size. With this configuration, if laser processing is used, the opening paths are simple and easy to process. Alternatively, the openings in the corresponding region of the first transmission layer and the openings in the corresponding region of the second transmission layer may have the same shape but different sizes and different numbers. This configuration facilitates the differentiation between the first and second transmission layers, making it easier to distinguish them during subsequent processing and improving process accuracy.

[0088] In some embodiments, referring to Figures 2, 3, 11, and 17, the transmission layer includes several transmission regions (or the transmission layer can be considered as being arranged in strips, with one strip corresponding to one transmission region). For example, the first transmission layer includes several transmission regions, and the second transmission layer includes several transmission regions. In Figures 2, 3, and 17, 73 can be a transmission region in the first transmission layer, and 74 can be a transmission region in the second transmission layer. The transmission regions of the first and second transmission layers are alternately distributed along the direction L. On a transmission region, the openings 6 are arranged at intervals to form at least one row or line of openings. On a transmission region, the openings 6 are arranged at intervals, so that there is an opening corresponding to different positions on the transmission region, and the transmission distance of current or charge carriers at each position of the transmission region is not too large, minimizing transmission loss as much as possible; forming an opening row, the corresponding opening process is relatively simple, and the opening cost is low. For example, the above-mentioned arrangement of openings is easy to obtain by laser processing, and the accuracy is easy to control.

[0089] Referring to Figures 2, 3, 11, and 17, the extension direction of the opening array here is parallel to the extension direction M of the transmission region; or, referring to Figures 11 to 14 and 17, the extension direction of the opening array here is parallel to the extension direction of the first electrode 50. It should be noted that the extension direction of the transmission region refers to the general orientation or overall orientation of the transmission region, and bending in other directions is permitted in certain parts of the transmission region.

[0090] In some embodiments, referring to Figures 2 and 3, within an opening row, the spacing d1 between adjacent openings 6 is 1 to 7 times the one-dimensional dimension of the texture structure. Specifically, in an opening row, if the ratio of the spacing d1 between adjacent openings 6 to the one-dimensional dimension of the texture structure is less than 1, and d1 is too small, the number of openings formed in a transmission area will be too large, resulting in more damage from the opening process. In addition, if the number of openings is too large, the opening area covered by the texture structure will be larger, and the texture structure will exhibit regular concave-convex changes, making the raised edges more susceptible to damage, further aggravating the degree of damage. In an opening row, if the ratio of the spacing d1 between adjacent openings 6 to the one-dimensional dimension of the texture structure is greater than 7, and d1 is too large, the number of openings formed in a transmission area will be too small. When an electrode is placed above the opening, on the one hand, the transmission distance of current or charge carriers will be too long, resulting in greater transmission loss and poor current collection and conduction effect. On the other hand, the roughness of the texture structure will be greater, and the opening area covered by the texture structure will be too small, resulting in poor bonding or contact effect between the electrode and the transmission layer. Therefore, in an open array, the spacing d1 between adjacent openings 6, which is 1 to 7 times the one-dimensional size of the texture structure, represents a balance between the damage caused by the openings and the current collection and conduction effect, resulting in less damage and better current collection and conduction. Here, d1 is in a direction parallel to the extension direction of the transmission region. d1 can be the spacing between the geometric centers of an adjacent pair of openings in an open array, or it can be the average of the spacings between the geometric centers of multiple adjacent pairs of openings in an open array.

[0091] For example, within an open row, the spacing d1 between adjacent openings 6 is 1, 1.5, 1.8, 2, 2.2, 2.5, 2.8, 3, 3.2, 3.5, 3.8, 4, 4.5, 4.7, 5, 5.2, 5.5, 5.8, 6, 6.5, or 7 times the one-dimensional size of the aforementioned texture structure.

[0092] In some embodiments, the value of d1 can be in the range of 10µm to 100µm. Specifically, in an open row or open array, the spacing between adjacent openings is d1 < 20µm. If d1 is too small, too many openings are formed in a transmission area, resulting in more damage caused by the process during opening. If d1 > 100µm, too many openings are formed in a transmission area, resulting in too few openings, too long transmission distance for current or charge carriers, greater transmission loss, and poor current collection and conduction effect. Therefore, d1 of 10µm to 100µm is the result of balancing the damage caused by the openings with the current collection and conduction effect, resulting in less damage caused by the openings and better current collection and conduction effect.

[0093] For example, d1 here can be 10um, 15um, 20um, 30um, 40um, 50um, 55um, 65um, 70um, 75um, 80um, 90um, or 100um.

[0094] It should be noted that, in determining the spacing d1 between adjacent openings within an open row as a specific multiple of the one-dimensional size of the texture structure, the texture structure here can be the average one-dimensional size of the texture structure on the first surface, or it can be the one-dimensional size of any texture structure on the first surface, or it can be the one-dimensional size of any texture structure on the first surface corresponding to the transport layer, or it can be the average of multiple one-dimensional sizes of texture structures on the first surface corresponding to the transport layer, or the spacing between adjacent openings and the one-dimensional size of the texture structure directly below them; none of these are limited.

[0095] In some embodiments, referring to FIG3, the number of opening rows or clusters in a transmission region is greater than or equal to 2. The spacing d2 between adjacent opening rows is 0.5 to 5 times the one-dimensional size of the texture structure. If the ratio of d2 to the one-dimensional size of the texture structure is less than 0.5, and d2 is too small, too many opening rows are formed in a transmission region, resulting in more damage caused by the openings and an increased area of ​​openings covering the texture structure, further increasing the damage. If the ratio of d2 to the one-dimensional size of the texture structure is greater than 5, and d2 is too large, too few opening rows are formed in a transmission region. On the one hand, the transmission distance of current or charge carriers is too long, resulting in greater transmission loss and poor current collection and conduction effect. On the other hand, the area of ​​openings covering the texture structure is less, resulting in poor bonding or contact effect between the electrode and the transmission layer. Therefore, the ratio of d2 to the one-dimensional size of the texture structure is 0.5 to 5, which is the result of balancing the damage caused by the openings and the current collection and conduction effect, resulting in less damage caused by the openings and better current collection and conduction effect. The direction L of d2 is perpendicular to the extension direction M of the transmission region. d2 can be the distance between the geometric centers of two openings 6 in adjacent opening rows in the direction L perpendicular to the extension direction M of the transmission region.

[0096] For example, d2 can be 0.5 times, 1 times, 1.3 times, 1.5 times, 1.8 times, 2 times, 2.2 times, 2.5 times, 2.8 times, 3 times, 3.2 times, 3.5 times, 3.9 times, 4 times, 4.2 times, 4.5 times, 4.7 times, or 5 times the one-dimensional size of the texture structure.

[0097] In some embodiments, the value of d2 can range from 8µm to 80µm, and more specifically, from 20µm to 50µm. Specifically, if the spacing between adjacent open rows is d2 < 8µm, too small a d2 results in too many open rows forming in a transmission region, leading to significant damage. If d2 > 80µm, too large a d2 results in too few open rows forming in a transmission region, resulting in excessively long transmission distances for current or charge carriers, greater transmission losses, and poor current collection and conduction performance. Therefore, a d2 value of 8µm to 80µm represents a balance between the damage caused by the open rows and the current collection and conduction performance, resulting in less damage and better current collection and conduction.

[0098] For example, d2 here can be 8um, 10um, 15um, 20um, 23um, 25um, 30um, 32um, 35um, 37um, 40um, 45um, 47um, 50um, 55um, 60um, 65um, 70um, 75um, or 80um.

[0099] It should be noted that, in determining the spacing between adjacent openings within an open row as a specific multiple of the one-dimensional size of the texture structure, the texture structure here can be the average one-dimensional size of the texture structure on the first surface, or it can be the one-dimensional size of any texture structure on the first surface, or it can be the one-dimensional size of any texture structure on the first surface corresponding to the transport layer, or it can be the average of multiple one-dimensional sizes of texture structures on the first surface corresponding to the transport layer, or the spacing between adjacent openings and the one-dimensional size of the texture structure directly below them; none of these are limited.

[0100] In some embodiments, referring to FIG3, the number of contact area rows in a transmission area is greater than or equal to 2, and the contact areas in adjacent contact area rows are staggered. That is, the number of opening rows at the location of a transmission area is greater than or equal to 2, and the openings 6 in adjacent opening rows are staggered. Compared with the alignment of openings 6 in adjacent opening rows, the staggered distribution makes the distribution of contact areas in a transmission area more uniform. As a result, the current transmission and collection distance at each location in a transmission area is approximately equal, which can achieve uniform current collection and conduction. The current collection and conduction effect is good, further ensuring the uniformity of current output.

[0101] For example, in Figure 3, there are 2 rows of contact areas in a transmission zone, and the contact areas in adjacent rows are staggered. Alternatively, there could be 3, 4, 5, or 6 rows of contact areas in a transmission zone, with the contact areas in adjacent rows also staggered.

[0102] In some embodiments, the number of contact area rows on a transmission area of ​​the first transmission layer and the number of contact area rows on a transmission area of ​​the second transmission layer may be the same or different, and can be flexibly adjusted according to the needs of the actual application.

[0103] In some embodiments, the aforementioned textured structure includes: a base, which protrudes from or is recessed into the aforementioned first surface; the one-dimensional dimension of the base is 5µm to 40µm. Specifically, the one-dimensional dimension of the base is related to the film formation quality of its upper film layer and the bonding force or contact effect between the electrode 5 and the transport layer. If the one-dimensional dimension of the base is too large, the film formation quality of its upper film layer is poor, and the passivation effect is poor. If the one-dimensional dimension of the base is too small, the enhancement effect on the bonding force or contact effect between the electrode 5 and the transport layer is poor. For the first transport layer and the second transport layer, the one-dimensional dimension of the base is 5µm to 40µm, which is an optimized balance of multiple factors such as the film formation quality, passivation effect, and current collection and conduction effect of its upper film layer, which can improve the performance of the solar cell.

[0104] It is understandable that the morphology of the tower base is related to the material of the silicon substrate and the texturing process. From a top view, its plane can be polygonal, such as the square shown in the frame marked 12 in Figure 5, but it is not limited to this; it can also be at least one of rhombus, square, trapezoid, approximately rhombus, approximately square, and approximately trapezoid. A suitable morphology of the tower base is beneficial for the subsequent formation of a better bonding force with the electrodes. Looking along the thickness direction, the tower base structure can protrude from the surface or be recessed into the surface, without limitation. Similarly, in solar cells, the film layer on the silicon substrate 1 is very thin. After the transport layer is covered on the silicon substrate, the tower bases on the silicon substrate 1 will basically conform to the transport layer. On the surface of the transport layer away from the silicon substrate, the tower bases are still clearly visible. In the process of determining the tower bases, the tower bases on the surface of the transport layer away from the silicon substrate or the tower bases on the first surface of the silicon substrate 1 can be used as the reference.

[0105] For example, the one-dimensional dimensions of the tower base can be 5um, 6um, 8um, 9um, 10um, 12um, 14um, 15um, 16um, 18um, 19um, 20um, 22um, 25um, 27um, 30um, 35um, 39um, or 40um.

[0106] It should be noted that the one-dimensional dimension of the tower base can refer to the side length of the tower base, the length of the diagonal of the tower base, etc.

[0107] In some embodiments, referring to Figures 4 to 6 and Figure 8, the area outside the contact region 71 on the side of the transport layer facing away from the silicon substrate 1 is the non-contact region 72; the roughness of the contact region 71 is greater than the roughness of the non-contact region 72. Specifically, the side of the transport layer exposed on the opening portion facing away from the silicon substrate is the contact region 71, and the side of the doped layer not exposed on the opening portion facing away from the silicon substrate is the non-contact region 72. The roughness of the contact region 71 can affect the bonding force or contact effect between the electrode 5 and the transport layer. Specifically, a rougher contact region 71 has a more significant effect on improving the bonding force or contact effect between the electrode 5 and the transport layer. The greater the surface roughness of the transport layer exposed on the opening portion, the larger the contact area between the transport layer and the electrode, which is more conducive to reducing contact resistance and improving the carrier transport capability. The transport layer in the non-contact region 72 also has a passivation and anti-reflection layer, which does not directly contact the electrode 5. The quality requirements for the transport layer and the film layer thereon are higher here. Therefore, the non-contact region 72 is relatively flat, and the quality of the film layer formed thereon is better, which can achieve a better passivation effect, thereby improving the performance of the solar cell.

[0108] It should be noted that the roughness of the contact area 71 and the roughness of the non-contact area 72 can both refer to surface roughness, specifically Ra roughness or Rz roughness. The methods for determining the roughness of the contact area 71 and the roughness of the non-contact area 72 are the same. Alternatively, the roughness of the contact area 71 can refer to the distance between the highest and lowest points along the thickness direction of the battery within the entire contact area 71 or a portion of the contact area, or the distance between the second highest and second lowest points along the thickness direction of the battery.

[0109] For example, the roughness or Ra roughness of the contact area 71 can be 0, 0.05 μm, 0.08 μm, 0.1 μm, 0.12 μm, 0.15 μm, 0.18 μm, 0.2 μm, 0.25 μm, 0.29 μm, 0.3 μm, 0.33 μm, 0.35 μm, 0.38 μm, 0.4 μm, 0.43 μm, 0.45 μm, or 0.5 μm, and the roughness or Ra roughness of the non-contact area 72 can be 0, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, or 100 nm.

[0110] In some embodiments, referring to Figures 4 to 6, the area corresponding to the opening on the side of the transport layer facing away from the silicon substrate is the contact area 71, which is the location where the electrode and the transport layer contact. At least one contact area 71 contains a portion of the base plate 12. In Figure 5, the roughly ring-shaped outline or structure within the labeled frame is a schematic diagram of the structure corresponding to the base plate 12 in the transport layer. Specifically, the transport layer is located on the first surface, and the thickness of the transport layer is typically at the nanometer level, so the base plate on the first surface will be approximately conformally aligned with the transport layer. At least one contact area 71 may contain a complete base plate or a partial base plate. The larger the opening, the more base plates are contained in the contact area 71. The base plate contains ridges, which include the edges of the base plate. These ridges can be straight and / or curved. The contact area may also include a regular or irregular shaped texture structure formed by at least one ridge, with the texture structure exhibiting unevenness at the ridge. The more ridges the laser hits during the opening process, the greater the potential damage to the film layer below and around the opening. Therefore, while ensuring the contact effect between the electrode and the transport layer, the opening can be made as small as possible. In this application, at least one contact area 71 contains a portion of the tower base, meaning that at least one contact area 71 may not be set on a complete tower base. Consequently, there are fewer ridges of the tower base corresponding to the contact area 71, resulting in less damage to the film layer below and around the opening. This ensures the quality of the film layer, such as a good passivation effect, and also satisfies the contact effect between the electrode and the transport layer.

[0111] In some embodiments, the individual tower bases are arranged in rows along the extension direction of the transport region; and / or, the individual openings are spaced apart and arranged in rows along the extension direction of the transport region. Line marks are primarily the cutting marks left by the dicing lines during the silicon wafer cutting process. During polishing, the etching of these line marks is relatively severe, causing at least some areas of the individual tower bases to be arranged in rows along the extension direction of the transport region. Polishing can remove or weaken these line marks as much as possible, minimizing their impact and reducing substrate defects, thus improving the performance of the solar cell. Since the extension direction of the transport region is parallel to the extension direction of the line marks, the openings are spaced apart and arranged in rows along the extension direction of the transport region, or in other words, the aforementioned rows of openings extend along the extension direction of the transport region. The area struck by the laser during the opening process may correspond to more line marks. The undulating line marks can further increase the contact area between the transport layer and the electrode, thereby improving the adhesion between the electrode and the transport layer.

[0112] In some embodiments, referring to Figures 4 to 6, at least one hole 9 is present at the location of the ridge 11 of the tower base 12 within the contact area 71. Specifically, the opening is typically formed by laser opening. Due to the uneven energy of the laser during the laser opening process, the laser energy is higher at certain locations, causing the transport layer to burst open at these locations, thus forming the hole 9. The hole 9 and its surrounding area are rougher, further increasing the surface roughness and specific surface area of ​​the opening region, giving the ridge of its surface an uneven feature. This further increases the bonding force or contact effect between the electrode 5 and the transport layer, improving the current collection and conduction effect, and thus enhancing the performance of the solar cell.

[0113] It should be noted that in this embodiment, the hole does not penetrate the transmission layer and is a blind hole.

[0114] For example, the maximum radial dimension of the hole 9 is greater than 0 μm and less than or equal to 3 μm. If the maximum radial dimension of the hole 9 is too large, for example, 3.5 μm, 4 μm or larger, the number of holes 9 will be reduced, reducing the overall roughness of the contact area, thereby reducing the contact area between the transport layer and the electrode, and reducing the bonding force between the electrode and the transport layer. Therefore, the maximum radial dimension of the hole 9 in this application is less than or equal to 3 μm.

[0115] It should be noted that, referring to Figures 4 to 6, the contact area 71 of the transport layer may also have holes distributed in the remaining parts other than the ridge line 11 of the tower base 12. The holes and the surrounding parts of the contact area 71 of the transport layer other than the ridge line 11 of the tower base 12 are rougher, which also increases the surface roughness, thereby further increasing the bonding force or contact effect between the electrode 5 and the transport layer, improving the current collection and conduction effect, and thus improving the performance of the solar cell.

[0116] In some embodiments, referring to Figures 4 to 6 and Figures 8 to 9, at least some of the holes 9 at the location of the ridge line 11 of the tower base in the contact area 71 are interconnected. After interconnection, the relatively rough surfaces in the contact area 71 are interconnected, which further increases the bonding force or contact effect between the electrode 5 and the transport layer, improves the current collection and conduction effect, and thus improves the performance of the solar cell.

[0117] It should be noted that, in this application, "at least some holes 9 at the location of the edge line 11 of the tower base within the contact area 71 are interconnected" specifically means that at least two holes 9 at the location of the edge line 11 of the tower base within the contact area 71 are interconnected, and the degree of interconnection is not limited. For example, in Figures 4 and 5, the distribution density of interconnected holes at the location of the edge line 11 of the tower base within the contact area 71 is relatively low, while in Figures 6 and 8, the distribution density of interconnected holes at the location of the edge line 11 of the tower base within the contact area 71 is relatively high; or, in other words, in Figures 4 and 5, the number of interconnected holes at the location of the edge line 11 of the tower base within the contact area 71 is relatively low, while in Figures 6 and 8, the number of interconnected holes at the location of the edge line 11 of the tower base within the contact area 71 is relatively high. In Figures 4 and 5, adjacent holes 9 at the location of the ridge line 11 of the tower base within the contact area 71 are adhered together. In Figures 6 and 8, the interconnection of holes 9 at the location of the ridge line 11 of the tower base within the contact area 71 is even higher, forming a bright linear shape. When a laser is used for the opening process, the degree of interconnection of holes 9 at the location of the ridge line 11 of the tower base within the contact area 71 is specifically related to the laser power during the laser opening process. With a higher laser power, the degree of interconnection of holes 9 at the location of the ridge line 11 of the tower base within the contact area 71 may be even higher.

[0118] In some embodiments, referring to Figures 4 to 6 and Figure 8, the density of pores at the inner ridge of the contact region 71 is greater than the density of pores in other regions. The contact region 71 has more pores 9 at its inner ridge, and the pores 9 and their surrounding areas are rougher, further increasing the surface roughness and specific surface area of ​​the opening region. This results in an uneven surface at the ridge, leading to a larger contact area between the electrode 5 and the transport layer. This further increases the bonding force or contact effect between the electrode 5 and the transport layer, improving current collection and conduction, avoiding the risk of electrode and transport layer detachment, and ultimately improving the performance and reliability of the solar cell.

[0119] The density of pores at the inner edge of contact region 71 refers to the number of pores per unit distance along the inner edge of contact region 71. The density of pores in other regions is similar. For example, in Figures 4 and 5, at least some of the pores 9 at the location of the inner edge 11 of contact region 71 are interconnected, and the density of pores at the edge is greater than that in other regions. The interconnection of at least some pores at the edge further increases the density of pores at the inner edge of contact region 71, further increasing the roughness at the edge, enhancing the bonding force and contact effect between electrode 5 and the opening area, thus improving current collection and conduction, and ultimately improving the performance of the solar cell.

[0120] In some embodiments, referring to Figures 2 and 3, the transport layer includes a first transport layer and a second transport layer, wherein the first transport layer and the second transport layer have different doping types, as described above. In the first surface: the side length of the base plate in the second transport layer is greater than the side length of the base plate in the first transport layer; and / or, the depth of the base plate in the second transport layer is less than the depth of the base plate in the first transport layer. And / or, the side length of the base plate 12 in the first transport layer is less than the side length of the base plate 12 in the second transport layer; and / or, the depth of the base plate 12 in the first transport layer is greater than the depth of the base plate 12 in the second transport layer. Specifically, the relative size relationship of the above dimensions is related to the number of etching cycles of the corresponding transport layer, the specific material and size of the transport layer, opening damage, etc. Under the above relative size relationship, different transport layers and substrates have better passivation effects, and the opening process causes relatively less damage to each film layer, ensuring that different regions have good transport performance and improving the conversion efficiency of the solar cell.

[0121] For example, this solar cell is a TBC solar cell. Referring to Figures 1 and 7, the TBC solar cell is a back-contact solar cell. Here, the first transport layer is a P-type transport layer, specifically a P-type doped polycrystalline silicon layer, and the second transport layer is an N-type transport layer, specifically an N-type doped polycrystalline silicon layer. A tunneling oxide layer 3 is also present between the first and second transport layers and the silicon substrate 1. In the fabrication of the TBC solar cell, the P-type doped polycrystalline silicon layer can be fabricated first, followed by the N-type doped polycrystalline silicon layer. In this TBC solar cell: the side length of the base in the P-type doped polycrystalline silicon layer is less than the length of the base in the N-type doped polycrystalline silicon layer; and / or, the depth of the base in the P-type doped polycrystalline silicon layer is greater than the depth of the base in the N-type doped polycrystalline silicon layer.

[0122] It should be noted that, in this application, the depth of the tower base refers to: when the tower base protrudes beyond other parts of the contact area, the depth of the tower base refers to the dimension of the protrusion beyond other parts of the contact area, which can be the dimension of the protrusion at one location within the tower base, or the average of the dimensions of the protrusions at multiple locations within the tower base; when the tower base is recessed within other parts of the contact area, the depth of the tower base refers to the dimension of the recess within the contact area, which can be the dimension of the recess at one location within the tower base, or the average of the dimensions of the recesses at multiple locations within the tower base. The method for determining the depth of the tower base is the same across different transmission layers.

[0123] In some embodiments, referring to Figures 2 and 3, there is a gap between the contact area and the edge of the transmission area in a transmission area. That is, at the location of a transmission area, there is a gap between the opening 6 and the edge of the transmission area, and a space is reserved between the opening 6 and the edge of the transmission area. On the one hand, it is conducive to alignment during the opening process, and the processing window of the opening is large. On the other hand, it can avoid the thermal effect of the laser on the edge passivation during the opening process, and the edge still has a good passivation effect.

[0124] In some embodiments, referring to Figures 2, 3, 11 to 14, and 17, there is a gap (d3) between the contact area and the edge of the transmission area in a transmission area. That is, at the location of a transmission area, there is a gap between the opening 6 and the edge of the transmission area, i.e., there is a reserved space between the opening 6 and the edge of the transmission area. On the one hand, it is beneficial to the alignment during the opening process, and the processing window of the opening is large. On the other hand, it can avoid the thermal effect of the laser on the edge passivation during the opening process, and the edge still has a good passivation effect.

[0125] In some embodiments, referring to Figures 3 and 5, the maximum size d4 of the opening 6 is 10 μm to 45 μm. If the maximum size of the opening 6 is less than 10 μm, the contact effect between the electrode 5 and the transport layer will be poor. If the maximum size of the opening 6 is greater than 45 μm, the damage caused by the opening process will be too great. In this application, the maximum size of the opening 6 is 10 μm to 45 μm, which is at least the result of optimizing the balance between the contact effect between the electrode 5 and the transport layer and the damage caused by the opening process. The contact effect between the electrode 5 and the transport layer is good, and the damage caused by the opening process is small.

[0126] For example, the maximum size d4 of the opening 6 can be 10μm, 10.5μm, 11μm, 12μm, 13μm, 15μm, 18μm, 20μm, 22μm, 25μm, 28μm, 30μm, 35μm, 40μm, or 45μm.

[0127] In some embodiments, referring to Figures 2 and 3, when both the first transmission layer and the second transmission layer are located on the first surface of the silicon substrate, i.e., both are located on the back surface of the silicon substrate, an isolation region 8 is further provided between the transmission regions 73 of the adjacent first transmission layer and the transmission regions 74 of the second transmission layer to avoid short circuits. The isolation region 8 can be a textured structure or a polished structure, and there is no limitation thereto. For example, the isolation region 8 can be a textured structure to increase the light trapping effect.

[0128] In some embodiments, the solar cell further includes an electrode 5, which can be an N-type electrode or a P-type electrode. The electrode 5 is disposed on the side of the passivation antireflection layer away from the silicon substrate, and the electrode 5 passes through the opening 6 to contact the transport layer. The electrode 5 can be a current collector grid line, or it can be an entire electrode structure including the current collector grid line, neither of which is limited. The electrode 5 can be a monolithic structure. In some embodiments, the electrode 5 in this application can include a stacked seed layer 51 and a non-burn-through paste layer 52. The paste layer can be formed using low-temperature silver-coated copper paste, low-temperature copper paste, low-temperature nickel paste, etc. The use of low-temperature silver-free metallization technology for the paste layer avoids the price and supply disadvantages of silver paste products, saves the resource consumption brought by high-temperature technology, and avoids the thermal effects introduced by high-temperature technology, which can effectively reduce production costs.

[0129] More specifically, the paste layer 52 here can be made of base metals, which can reduce the cost of solar cells. Base metals here mainly refer to those that do not contain silver or contain only a very small amount of silver. For example, the paste layer here can include: a copper paste layer, an aluminum paste layer, or a paste layer with a precious metal content of less than 50% by mass. The precious metal here can include silver. For example, the paste layer here can be a silver-coated copper paste layer, etc.

[0130] The seed layer 51 may contain a metallic element, which may be selected from at least one of the following: titanium (Ti), tungsten (W), chromium (Cr), nickel (Ni), cobalt (Co), molybdenum (Mo), tin (Sn), lead (Pb), palladium (Pd), copper (Cu), niobium (Nb), ruthenium (Ru), indium (In), zinc (Zn), tantalum (Ta), and vanadium (V). Specifically, the material of the seed layer 51 is selected from the above-mentioned materials, as their electrical resistance and barrier properties against metallic elements in the paste layer 52 are suitable for use as a seed layer. In particular, the selection of nickel and / or zinc as the material of the seed layer 51 is advantageous because: firstly, both nickel and zinc have good contact properties; secondly, nickel and zinc do not significantly penetrate into the silicon substrate, resulting in less recombination; and thirdly, nickel and zinc provide good barrier properties against metals in the paste layer 52 on the side opposite to the silicon substrate, preventing metals in the paste layer 52 from penetrating into the silicon substrate and reducing recombination.

[0131] The paste layer 52 may contain base metals. Compared to solar cells using silver paste, this application allows for metal plating, such as using mature and inexpensive nickel-copper-tin metals instead of silver paste, thereby reducing the cost of the solar cell. For example, the seed layer 51 may contain nickel, and the paste layer may contain copper. Nickel has good contact properties and virtually does not penetrate into the silicon substrate, resulting in less recombination. Furthermore, nickel provides good barrier properties against copper and other metals in the paste layer 52 on the side facing away from the silicon substrate, preventing them from penetrating into the silicon substrate, reducing recombination, and lowering costs. The solar cell of this application can achieve good contact performance between the metal and the silicon substrate at low temperatures (below 300°C, such as around 200°C), without the need for high-temperature furnace sintering, and introduces very little heat-affected zone into the solar cell.

[0132] This application also provides a method for preparing a solar cell, comprising the following steps.

[0133] Step 101, providing a silicon substrate; the silicon substrate has opposing first and second surfaces in the thickness direction; a textured structure is provided on the first surface.

[0134] Step 102: Sequentially prepare a transport layer and a passivation antireflection layer on the textured structure of the first surface.

[0135] The transport layer can be formed using methods such as LPCVD (low-pressure chemical vapor deposition), and there are no restrictions on the specific formation method. It can also be formed within the silicon substrate through diffusion, ion implantation, or other methods. The preparation method for the passivation antireflection layer is not specifically limited; for example, it can be formed using deposition.

[0136] Step 103: Laser-drilled openings are used to form a plurality of openings in the passivation antireflection layer; the area corresponding to the openings on the side of the transport layer away from the silicon substrate is the contact area; the ratio of the maximum size of the opening to the one-dimensional size of the texture structure is 0.5 to 4.

[0137] There are no restrictions on the specific parameters of the laser. For example, picosecond laser engraving technology can be used to engrave the passivation antireflection layer according to the designed collector grid pattern to form the required micron-scale trench structure.

[0138] The method may further include step 104, forming an electrode at the opening, the electrode being in contact with the transport layer.

[0139] The specific preparation method for the electrode is not limited. For example, a seed layer 51 can be prepared first, followed by screen printing paste on the side of the seed layer away from the silicon substrate and drying to form a paste layer 52. The paste layer can be formed using low-temperature silver-coated copper paste, low-temperature copper paste, low-temperature nickel paste, etc. The use of low-temperature silver-free metallization technology for the paste layer avoids the price and supply disadvantages of silver paste products, saves the resource consumption brought about by high-temperature technology, and avoids the thermal effects introduced by high-temperature technology, which can effectively reduce production costs.

[0140] In some embodiments, in step 103, a first laser power is used to create a laser opening, forming a plurality of first openings; a second laser power is used to create a laser opening, forming a plurality of second openings; at least one hole 9 is present at the location of the ridge line 11 of the tower base within the contact area 71; at least some of the holes 9 at the location of the ridge line of the tower base within the contact area 71 are interconnected. Here, the first laser power is greater than the second laser power; the number of interconnected holes at the location of the ridge line within the contact area corresponding to the first opening is greater than the number of interconnected holes at the location of the ridge line within the contact area corresponding to the second opening; and / or, the distribution density of interconnected holes at the location of the ridge line of the tower base within the contact area corresponding to the first opening is greater than the distribution density of interconnected holes at the location of the ridge line of the tower base within the contact area corresponding to the second opening. That is, the greater the laser power, the greater the degree of interconnection of the interconnected holes at the location of the ridge line of the tower base within the contact area. It should be noted that, in the process of comparison here, the number of interconnected holes or the distribution density of interconnected holes are determined within the same area or per unit area at the location of the tower base ridge line in the contact area.

[0141] It should be noted that the solar cells and their fabrication methods provided in this application are applicable to both N-type and P-type transport layers.

[0142] Next, we will introduce the content of the second layer. The silicon substrate, tower base, tower base edge, polycrystalline silicon doped layer, tunneling oxide layer, passivation antireflection layer, electrode, seed layer, slurry layer, opening, contact area, non-contact area, transport area of ​​the first transport layer, transport area of ​​the second transport layer, isolation area, holes and other related contents of the second layer can be referred to the content of the first layer mentioned above. In order to avoid repetition, they will not be repeated.

[0143] Referring to Figure 8, in this application, at least one contact region 71 has a ridge 11 (shown as a continuously extending line segment within the frame labeled 11 in the figure). The passivation antireflection layer 4 has several openings 6. The area corresponding to the opening 6 on the side of the transport layer facing away from the silicon substrate 1 is the contact region 71. The contact region 71 is the position where the electrode 5 contacts the transport layer, and at least one contact region 71 has a ridge 11. Based on this, electrodes can be formed at the openings 6 using a low-temperature metallization process, which can reduce the cost of the metallization process. Furthermore, compared to the prior art where electrodes are formed on relatively flat contact areas, at least one contact area in this application has an ridge, and the surface of the ridge 11 is relatively rough. On the one hand, compared to contact areas without ridges, contact areas with ridges have a larger specific surface area, thus increasing the contact area between the transport layer and the electrode, improving the contact performance between the electrode 5 and the transport layer, reducing the contact resistance, thereby improving the collection and conduction of current or charge carriers, and thus improving the performance of the solar cell. On the other hand, the rougher contact area with ridges makes the contact between the transport layer and the electrode more compact, improving the connection strength and bonding force between the two, effectively preventing pull-out in subsequent processes, avoiding the risk of the electrode falling off from the contact area, thereby improving the structural reliability of the solar cell.

[0144] It should be noted that the ridgeline here refers to a regularly shaped protrusion on the surface, with a rougher surface compared to other areas. The ridgeline can be straight and / or curved, and the contact area may also include a regular or irregular textured structure composed of at least one ridgeline, with variations in texture at the ridgeline. The ridgeline here can be: a ridgeline in the base structure of a polished structure on the surface of the silicon substrate (i.e., the aforementioned base structure), at least partially conforming to the shape of the transport layer on the side facing away from the silicon substrate; or, a ridgeline in the pyramid structure of a textured structure on the surface of the silicon substrate, at least partially conforming to the shape of the transport layer on the side facing away from the silicon substrate. No specific limitations are imposed on either approach.

[0145] In one embodiment, referring to Figures 5, 6, and 8, at least one contact area 71 has a base 12 (a roughly square outline or structure within the frame marked in Figure 5, equivalent to the aforementioned base or base structure, which can be referred to in the relevant descriptions and will not be repeated here), and the ridge line 11 includes the side length of the base 12. Meanwhile, the surface of the ridge line 11 is relatively rough. On the one hand, compared to a contact area without ridge lines, the contact area with ridge lines has a larger specific surface area, thus increasing the bonding area between the transport layer and the electrode, improving the contact performance between the electrode 5 and the transport layer, reducing the contact resistance, thereby improving the collection and conduction effect of current or charge carriers, and thus improving the performance of the solar cell. On the other hand, the rougher contact area with ridge lines makes the contact between the transport layer and the electrode tighter, improving the connection strength and bonding force between them, preventing pull-out in subsequent processes, and improving the structural reliability of the solar cell.

[0146] It should be noted that at least one tower base 12 within the contact area 71 is a complete or partial tower base structure of a polished structure on the surface of the silicon substrate, at least partially conforming to the shape of the transport layer facing away from the silicon substrate. For example, the contact area 71 in Figure 5 contains a relatively complete tower base 12. As another example, the contact area 71 in Figures 6 and 8 contains a partial tower base 12.

[0147] According to an embodiment of this application, in order to facilitate the formation of at least one contact area 71 with a base 12, when using a laser to open the passivation antireflection layer, the position and size of the contact area can be controlled by controlling laser parameters, such as spot size and irradiation area; the base can be adjusted by adjusting the polishing process, and the structure of the base, i.e., the shape and size of the ridge, can be controlled by controlling the process time, the type of additives, etc., as well as adjusting the size ratio and positional relationship between the opening and the base side length.

[0148] In one embodiment, referring to Figure 5, the ratio of the maximum size d4 of an opening to the side length d5 ​​of a tower base structure is between 0.5 and 5. The maximum size d4 of an opening refers to the maximum length of the opening. Specifically, if the ratio of d4 to d5 is less than 0.5, then d4 is too small, meaning the opening is too small. When an electrode is placed above the opening, not only is the contact area between the electrode and the exposed transport layer at the opening too small, affecting the current or carrier transport effect, but also, the side length of the tower base structure is rougher. If the opening is too small, the opening covers too little of the tower base side length, resulting in insufficient roughness at the opening, leading to poor bonding or contact effect between the electrode and the transport layer. When the ratio of d4 to d5 is greater than 5, then the opening is too large, covering too much of the tower base side length. The light absorption capacity at the tower base side length is stronger. When laser is used for the opening process, the laser causes greater damage to the film layer below and around the opening, affecting the film quality and hindering carrier transport. Therefore, in this application, the ratio of the maximum size of the opening to the side length of the tower base structure is 0.5 to 5. At least, this is the result of balancing the damage to the film layer below and around the opening during the opening process, as well as the bonding force and contact performance of the electrode and the transport layer. The quality of the film layers such as the transport layer and the passivation and antireflection layer below and around the opening is better, which can achieve good passivation and other effects. At the same time, the ridge line covered by the opening area can provide a large roughness, which makes the bonding force between the electrode and the transport layer larger, preventing pull-out in subsequent processes, resulting in high reliability. It also improves the contact effect between the electrode and the transport layer, while reducing the contact resistance and improving the current collection and conduction effect.

[0149] It should be noted that the side length of a base 12 refers to the length of the longest edge 11 among all the edges 11 of the base 12, or the average length of at least two edges 11 of the base 12.

[0150] In one embodiment, the side length d5 ​​of a base 12 is 5µm to 40µm. The effect here is similar to that of an edge 11 with a length of 5µm to 40µm, and will not be repeated here to avoid repetition. For example, the side length d5 ​​of a base 12 can be 5µm, 6.5µm, 9µm, 10µm, 11µm, 15µm, 16µm, 18µm, 20µm, 25µm, 27µm, 30µm, 35µm, or 40µm.

[0151] In one embodiment, the length of a ridge 11 is between 5 μm and 40 μm. A ridge 11 longer than 40 μm results in a longer ridge. The flatness at the location of the ridge 11 is typically poor, leading to stronger light absorption at the ridge 11. However, an excessively long ridge 11 causes greater laser damage to the transmission layer at that location. Furthermore, the poor flatness at the location of the ridge 11 results in slightly lower quality film formed on it. When using laser for the opening process, an excessively long ridge 11 causes laser damage to the film at that location. Larger lengths negatively impact passivation quality; if the length of the ridge 11 is less than 5 μm, the ridge 11 is too short, resulting in poor adhesion or contact between the electrode 5 and the transport layer at the location of the ridge 11, thus affecting current collection and conduction. Therefore, in this application, the length of a ridge 11 is between 5 μm and 40 μm, which is at least the result of optimizing and balancing multiple factors such as passivation quality, processing damage to the opening, and current collection and conduction. This not only ensures passivation quality and avoids significant processing damage but also guarantees current collection and conduction.

[0152] For example, the length of a ridge 11 can be 5um, 6um, 8um, 10um, 12um, 15um, 17um, 19um, 20um, 25um, 28um, 30um, 35um, or 40um.

[0153] In one embodiment, the side length d5 ​​of a base 12 is 5µm to 40µm, which has a similar effect to that of a ridge line 11 with a length of 5µm to 40µm. To avoid repetition, this will not be described again here.

[0154] In some embodiments, referring to Figures 4 to 9, at least one hole 9 is provided at the location of the ridge 11 within the contact area 71. Specifically, at least one hole 9 is provided at the ridge, and the hole 9 and its surrounding portion are rougher, further increasing the surface roughness and specific surface area of ​​the opening area. This gives the ridge surface an uneven feature, resulting in a larger contact area between the electrode 5 and the transport layer. This further increases the bonding force or contact effect between the electrode 5 and the transport layer, improves the current collection and conduction effect, avoids the risk of electrode and transport layer detachment, and thus improves the performance and reliability of the solar cell.

[0155] The maximum radial dimension of hole 9 can be referred to the aforementioned records regarding the maximum radial dimension of holes, and will not be repeated here to avoid repetition.

[0156] It should be noted that, referring to Figures 4 to 8, the contact area 71 of the transport layer, excluding the ridge line 11, may also contain holes. The holes and their surrounding areas in the contact area 71 of the transport layer, excluding the ridge line 11, are rougher, further increasing surface roughness. This, in turn, increases the bonding force or contact effect between the electrode 5 and the transport layer, improving current collection and conduction, and thus enhancing the performance of the solar cell. It should be noted that, in this embodiment, the holes do not penetrate the transport layer and are considered blind holes.

[0157] In one embodiment, referring to Figure 9, the edge of the hole 9 has annular protrusions 24. These protrusions can be continuously distributed (closed rings) or discontinuously distributed (non-closed rings). The circular area enclosed by the bright circle in the figure represents the hole 9, and the bright circle represents the annular protrusions 24 formed at the edge of the hole. In some examples, the annular protrusions can be formed by the material of the transport layer melting and then solidifying during the laser-driven opening of the passivation and antireflection layer, resulting in the protrusions 24 around the hole 9, similar to a raised crater structure. For example, in Figure 9, for the two marked holes 9, the hole 9 on the left has a non-closed protrusion 24 around it, while the hole 9 on the right has a closed protrusion 24 around it. In the transport layer: a three-dimensional structure is more easily formed at the protrusions 24, and the uniformly distributed non-two-dimensional layer structure increases the surface roughness, resulting in a stronger bond with the electrode 5. This further increases the bonding force or contact effect between the electrode 5 and the transport layer, improving current collection and conduction, and ultimately enhancing the performance and reliability of the solar cell.

[0158] It is understood that the annular protrusion 24 is formed by melting and resolidifying the transport layer. When the transport layer is doped polycrystalline silicon, the material of the annular protrusion 24 includes silicon.

[0159] In some embodiments, referring to Figures 4 to 8, the density of protrusions at the ridge line is greater than that in other areas. There are more protrusions at the ridge line in the contact area 71, and the protrusions and their surrounding parts are rougher, further increasing the surface roughness and specific surface area of ​​the opening area. This gives the ridge line of the surface an uneven feature, resulting in a larger contact area between the electrode 5 and the transport layer. This further increases the bonding force or contact effect between the electrode 5 and the transport layer, improves the current collection and conduction effect, avoids the risk of electrode and transport layer detachment, and thus improves the performance and reliability of the solar cell.

[0160] The density of protrusions at the inner edge of contact area 71 refers to the number of protrusions per unit distance on the inner edge of contact area 71, and / or the protrusion distance per unit distance on the inner edge of contact area 71. The density of protrusions in other areas is similar.

[0161] For example, in Figures 4 and 5, the density of protrusions at the location of the ridge line 11 within the contact area 71 is greater than the density of protrusions in other areas. As another example, in Figures 6 and 8, the interconnectedness of the holes 9 at the location of the ridge line 11 within the contact area 71 is greater, and the protrusions at the ridge line extend in a strip shape along the ridge line, resulting in a higher density of protrusions at the ridge line than in other areas. In some embodiments, referring to Figures 4 to 8, at least some of the holes 9 at the location of the ridge line 11 within the contact area 71 are interconnected. This interconnection of at least some holes at the ridge line further increases the density of holes at the ridge line within the contact area 71, leading to the connection of the annular protrusions at the edges of adjacent holes. This further increases the roughness at the ridge line, enhancing the bonding force and contact effect between the electrode 5 and the opening area, thereby improving not only current collection and conduction but also the performance of the solar cell.

[0162] In some embodiments, referring to Figures 6 to 8, the protrusion at the ridge 11 in the contact area 71 extends into a strip along the ridge, that is, the annular protrusions at the edges of adjacent holes are connected, which further increases the roughness at the ridge, increases the bonding force and contact effect between the electrode 5 and the opening area, and not only improves the current collection and conduction effect, but also improves the performance of the solar cell.

[0163] In one embodiment, the height and width of the protrusion 24 are both less than or equal to 0.5 μm. The direction of the height of the protrusion 24 is parallel to the direction Q of the thickness of the silicon substrate 1. The width of the protrusion 24 is the maximum dimension of the protrusion 24 on a plane perpendicular to the direction of its height. This can be one or more planes, the number of which is determined by the alignment of the various positions of the protrusion 24. Specifically, if the height of the protrusion 24 is greater than 0.5 μm and / or the width of the protrusion 24 is greater than 0.5 μm, the roughness of the opening region is too large, resulting in poor uniformity of the transport layer coverage within the opening region, which is detrimental to the collection and transport of charge carriers. Having both the height and width of the protrusion 24 less than or equal to 0.5 μm ensures that the roughness of the opening region is within a suitable range, satisfying the requirements of electrode bonding force while avoiding the problem of uneven transport layer coverage.

[0164] For example, the height and width of the protrusion 24 can be 0.5μm, 0.48μm, 0.45μm, 0.42μm, 0.4μm, 0.39μm, 0.38μm, 0.35μm, 0.32μm, 0.3μm, 0.28μm, 0.25μm, 0.22μm, 0.2μm, 0.18μm, 0.15μm, 0.12μm, 0.1μm, or 0.05μm.

[0165] In some embodiments, referring to Figures 4 to 6 and Figure 8, the contact area has at least one hole 9. This hole 9 can be located at the edge 11, or outside the edge 11 within the contact area, etc., without specific limitation. The contact area 71 includes a central region and an edge region surrounding the central region. The central region may include the geometric center of the contact area 71 or a region further inside the contact area 71. For a contact area 71, the size of the hole 9 in the central region is larger than the size of the hole 9 in the edge region. The size of the hole 9 here can refer to the area of ​​the hole 9, the maximum size of the hole 9, etc., without specific limitation. The central region of the contact area 71 contributes more to the bonding force or contact effect between the electrode 5 and the transport layer. The larger size of the hole 9 in the central region of the contact area 71 results in a better bonding force or contact effect between the central region of the contact area 71 and the electrode 5, thus significantly improving the bonding force or contact effect between the electrode 5 and the transport layer, further enhancing current collection and conduction effects, and thereby improving the performance of the solar cell.

[0166] It should be noted that, for a contact area 71, the relative size of the central area and the edge area is not limited. The two areas can be equal, or the central area can be larger than the edge area, or the edge area can be larger than the central area.

[0167] In one embodiment, referring to Figures 2 and 3, when both the first transmission layer and the second transmission layer are located on the same surface of the silicon substrate, i.e., both on the backlight side of the silicon substrate, an isolation region 8 is further provided between adjacent transmission regions 73 of the first transmission layer and transmission regions 74 of the second transmission layer to avoid short circuits. The isolation region 8 can be a textured structure or a polished structure, and there is no limitation thereto. For example, the isolation region 8 can be a textured structure to increase the light trapping effect.

[0168] In some embodiments, the depth of the base 12 in the first transport layer is 0.4 μm to 2 μm, and the depth of the base 12 in the second transport layer is 0.4 μm to 1.5 μm. Specifically, the depth of the base 12 is related to the film formation quality of its upper film layer, as well as the bonding force or contact effect between the electrode 5 and the transport layer. If the depth of the base 12 is too large, the film formation quality of its upper film layer is poor, and the passivation effect is also poor. If the depth of the base 12 is too small, the enhancement effect on the bonding force or contact effect between the electrode 5 and the transport layer is poor. For the first and second transport layers, the base 12 is within the above-mentioned range, which is an optimized balance of multiple factors such as the film formation quality, passivation effect, and current collection and conduction effect of its upper film layer, and can improve the performance of the solar cell.

[0169] For example, in the aforementioned TBC solar cell, the depth of the base structure in the P-type doped polycrystalline silicon layer can be from 0.4 μm to 2 μm, and the depth of the base structure in the N-type doped polycrystalline silicon layer can be from 0.4 μm to 1.5 μm. As another example, the depth of the base 12 in the first transport layer and the P-type doped polycrystalline silicon layer can be 0.4 μm, 0.5 μm, 0.8 μm, 0.9 μm, 1 μm, 1.2 μm, 1.4 μm, 1.5 μm, 1.6 μm, 1.8 μm, 1.9 μm, or 2 μm, and the depth of the base 12 in the second transport layer and the N-type doped polycrystalline silicon layer can be 0.4 μm, 0.5 μm, 0.6 μm, 0.8 μm, 0.92 μm, 1 μm, 1.1 μm, 1.2 μm, 1.4 μm, or 1.5 μm. It should be noted that, in the process of determining the depth of the tower base structure in the first transmission layer and the depth of the tower base structure in the second transmission layer in the same solar cell, it is necessary to ensure that the depth of the tower base structure in the first transmission layer is greater than the depth of the tower base structure in the second transmission layer.

[0170] In one embodiment, the side length of the base 12 in the first transport layer is 5 μm to 20 μm, and the side length of the base 12 in the second transport layer is 10 μm to 40 μm. Specifically, the side length of the base 12 is related to the film formation quality of its upper film layer and the bonding force or contact effect between the electrode 5 and the transport layer. If the side length of the base 12 is too long, the film formation quality of its upper film layer is poor, and the passivation effect is poor. If the side length of the base 12 is too short, the enhancement effect on the bonding force or contact effect between the electrode 5 and the transport layer is poor. For the first transport layer and the second transport layer, the base 12 is within the above range, which is an optimized balance of multiple factors such as the film formation quality, passivation effect, and current collection and conduction effect of its upper film layer, which can improve the performance of the solar cell.

[0171] For example, in the aforementioned TBC solar cell, the side length of the base structure in the P-type doped polycrystalline silicon layer can be 5µm to 20µm, and the side length of the base structure in the N-type doped polycrystalline silicon layer can be 10µm to 40µm. As another example, the side length of the base 12 in the first transport layer and P-type doped polycrystalline silicon layer can be 5µm, 6µm, 8µm, 9µm, 10µm, 12µm, 14µm, 15µm, 16µm, 18µm, 19µm, or 20µm, and the side length of the base 12 in the second transport layer and N-type doped polycrystalline silicon layer can be 10µm, 12.5µm, 14µm, 15µm, 17µm, 20µm, 22µm, 25µm, 27µm, 30µm, 35µm, or 40µm. It should be noted that, in the same solar cell, when determining the side lengths of the base structures in the first and second transport layers, it is necessary to ensure that the side length of the base structure in the first transport layer is less than the side length of the base structure in the second transport layer.

[0172] In some embodiments, referring to Figures 1, 7, and 10, the transport layer includes a polycrystalline silicon doped layer 2 containing polycrystalline silicon regions. The polycrystalline silicon doped layer 2 also includes an amorphous silicon region 21 containing amorphous silicon. The amorphous silicon region 21 is located on the side of the polycrystalline silicon doped layer 2 facing away from the silicon substrate 1. The amorphous silicon region 21 is located below the opening 6 and is also located between the passivation antireflection layer 4 and the polycrystalline silicon region, at the location of the opening 6. It should be noted that in the thickness direction Q of the silicon substrate 1, the polycrystalline silicon region is closer to the silicon substrate than the amorphous silicon region 21. The electrode 5 is located in this contact area and contacts the amorphous silicon region 21 to achieve current collection and conduction. Compared to the polycrystalline silicon doped layer 2, the amorphous silicon in the amorphous silicon region 21 is more resistant to acid corrosion. Therefore, the amorphous silicon region 21, located below the opening 6 and between the passivation antireflection layer 4 and the polycrystalline silicon region, and near the opening 6, can protect the film layer beneath the amorphous silicon region 21, such as protecting the polycrystalline silicon doped layer 2. This results in better weather resistance of the film layer under it during long-term service, maintaining the reliability and stability of the solar cell during long-term service. Moreover, the passivation antireflection layer 4 is located between the polycrystalline silicon region and near the opening 6. The non-contact region, amorphous silicon, has slightly weaker conductivity than the polycrystalline silicon doped layer 2. Located between the passivation and antireflection layer 4 and the polycrystalline silicon region, and near the opening 6, the amorphous silicon region 21 can block charge carriers in the non-contact region, thereby reducing recombination between the polycrystalline silicon doped layer 2 and the metal in the electrode 5. Furthermore, compared to the polycrystalline silicon doped layer 2 and the passivation and antireflection layer 4, amorphous silicon has a higher refractive index, increasing the light path in the solar cell and reducing reflected light, thus improving the light-trapping effect and enhancing cell performance. For example, the layer furthest from the silicon substrate in the passivation and antireflection layer 4 is the silicon nitride layer. The refractive index of amorphous silicon is approximately 4.0, greater than that of the silicon nitride layer and the polycrystalline silicon doped layer 2. Therefore, it increases the light path in the solar cell, reduces reflected light, and improves the light-trapping effect, thus enhancing cell performance.

[0173] In some embodiments, the thickness of the amorphous silicon at the edge is greater than that in other regions, which can fully protect the film layer under the amorphous silicon region 21 at the edge. For example, it can protect the polycrystalline silicon doped layer 2, so that the film layer under it has better weather resistance during long-term service and maintains the reliability and stability of the solar cell during long-term service.

[0174] In one embodiment, as shown in Figures 1 and 7, direction M represents the width of opening 6, which can also be understood as a direction parallel to the silicon substrate or perpendicular to the thickness of the silicon substrate. On one side of opening 6, the amorphous silicon region 21 extends along the width of the opening in the direction away from the opening by a length less than or equal to 6 μm. This extension length is greater than 0, as an excessively long extension may hinder carrier transport and collection. Since opening 6 is typically formed using lasers, excessively long extensions can lead to significant laser damage. For example, the amorphous silicon region 21 located on the side of the passivation antireflection layer 4 near the silicon substrate extends approximately 2.42 μm along the width of opening 6 in the direction away from the opening. Alternatively, this extension length can be 6 μm, 5.5 μm, 5.3 μm, 5 μm, 4.5 μm, 4 μm, 3.5 μm, 3 μm, 2.5 μm, 2 μm, 1.5 μm, 1 μm, 0.5 μm, or 0.2 μm.

[0175] It should be noted that, in this application, the direction away from the opening along the width of the opening refers to the direction parallel to the direction M where the width of the opening is located, and the direction away from the geometric center of the opening.

[0176] In one embodiment, the thickness of the amorphous silicon region 21 in the direction Q along which the thickness of the silicon substrate 1 is located is 1 nm to 70 nm. In a solar cell, if the thickness of the amorphous silicon region 21 is greater than 70 nm, the carrier transport capability will be affected; if the thickness of the amorphous silicon region 21 is less than 1 nm, the blocking effect on recombination is poor. The thickness of the amorphous silicon region 21 is 1 nm to 70 nm, which at least achieves an optimized balance between carrier transport capability and recombination blocking, providing not only good carrier transport but also good recombination blocking. For example, if the average thickness of the amorphous silicon region 21 is about 15 nm, an amorphous silicon region with a thickness of 52.84 nm may appear. This is mainly due to the uneven energy of the laser; the location with higher laser energy has higher heat, resulting in a thicker amorphous silicon layer.

[0177] For example, the thickness at different locations in the amorphous silicon region 21 can be 8.38 nm, 13.04 nm, or 12.18 nm, or the thickness at different locations in the amorphous silicon region 21 can be 8.65 nm or 12.01 nm. Furthermore, the thickness of the amorphous silicon region 21 can be 1 nm, 10 nm, 12.55 nm, 9.19 nm, 14.07 nm, 14.58 nm, 16.36 nm, 18.99 nm, 20 nm, 25 nm, 30 nm, 31.05 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, or 70 nm.

[0178] For example, at the edge of the opening 6, the thickness of the amorphous silicon region 21 can be 14nm, 14.8nm, 14.5nm, 15nm, 15.5nm, 16nm, 16.5nm, or 17nm. For example, below the opening 6, the thickness of the amorphous silicon region 21 can be 8nm, 9nm, 8.5nm, 9.5nm, 10nm, 10.5nm, 10.8nm, 11nm, 11.5nm, 11.8nm, 12nm, 12.5nm, 13nm, or 16nm.

[0179] In one embodiment, referring to FIG10, the polycrystalline silicon doped layer further comprises: microcrystalline and / or nanocrystalline 22. In the direction Q in which the thickness of the silicon substrate 1 is located, the microcrystalline and / or nanocrystalline 22 are closer to the silicon substrate 1 than the amorphous silicon region 21. The nanocrystalline silicon and / or microcrystalline silicon has higher conductivity than amorphous silicon, which can improve the carrier transport efficiency.

[0180] In one embodiment, the orthographic projection of the microcrystals and / or nanocrystals 22 onto the first surface at least partially coincides with the orthographic projection of the opening onto the first surface. This can mean that the orthographic projection of the microcrystals and / or nanocrystals 22 onto the first surface completely coincides with the orthographic projection of the opening onto the first surface, and the areas of the two orthographic projections are equal; or, the orthographic projection of the microcrystals and / or nanocrystals 22 onto the first surface covers the orthographic projection of the opening onto the first surface and is larger than the orthographic projection of the opening onto the first surface; or, the orthographic projection of the opening onto the first surface covers the microcrystals and / or nanocrystals. The orthographic projection of 22 on the first surface is greater than the orthographic projection of microcrystalline and / or nanocrystalline 22 on the first surface; or, the orthographic projection of microcrystalline and / or nanocrystalline 22 on the first surface covers a portion of the orthographic projection of the opening on the first surface and is greater than the orthographic projection of the opening on the first surface; or, the orthographic projection of the opening on the first surface covers a portion of the orthographic projection of microcrystalline and / or nanocrystalline 22 on the first surface and is greater than the orthographic projection of microcrystalline and / or nanocrystalline 22 on the first surface. Nanocrystalline silicon and / or microcrystalline silicon have higher conductivity than amorphous silicon, which can improve the carrier transport efficiency.

[0181] The orthographic projection of the micron-crystals and / or nano-crystals 22 onto the first surface refers to the projection of the micron-crystals and / or nano-crystals 22 onto the first surface when illuminated with light perpendicular to the first surface. The orthographic projection of the opening onto the first surface is similar.

[0182] In one embodiment, referring to FIG10, the polycrystalline silicon doped layer 2 includes a polycrystalline silicon region 23 containing polycrystalline silicon. The lattice size of the microcrystalline and / or nanocrystalline 22 and the polycrystalline silicon region 23 is 0.01 nm to 1 nm. Specifically, changes in the lattice size of the microcrystalline and / or nanocrystalline 22 and the polycrystalline silicon region 23 can lead to changes in the band structure, thereby affecting the behavior of charge carriers and their movement and recombination process. When the lattice size of the microcrystalline and / or nanocrystalline 22 and the polycrystalline silicon region 23 is within the above range, it can increase the lifetime of charge carriers and produce a higher absorption peak, which is beneficial to improving the photoelectric conversion efficiency and reducing recombination. That is to say, when the lattice size of the microcrystalline and / or nanocrystalline 22 and the polycrystalline silicon region 23 is within the above range, it is the result of a balance of at least three factors: charge carrier lifetime, photoelectric conversion efficiency, and recombination.

[0183] For example, the lattice sizes in the micron-crystals and / or nanocrystals 22 and the polycrystalline silicon region 23 can be 0.01 nm, 0.02 nm, 0.05 nm, 0.1 nm, 0.15 nm, 0.2 nm, 0.25 nm, 0.3 nm, 0.35 nm, 0.4 nm, 0.45 nm, 0.5 nm, 0.55 nm, 0.6 nm, 0.65 nm, 0.7 nm, 0.75 nm, 0.8 nm, 0.85 nm, 0.9 nm, 0.95 nm, or 1 nm.

[0184] It should be noted that the lattice size may be consistent or may increase from the microcrystalline and / or nanocrystalline 22 to the polycrystalline silicon region 23. The lattice size of the microcrystalline and / or nanocrystalline 22 and the polycrystalline silicon region 23 is preferably 0.31 nm. The lattice size in the microcrystalline and / or nanocrystalline 22 can refer to the size of a single lattice within that microcrystalline and / or nanocrystalline material, or the average of multiple lattice sizes; the lattice size of the polycrystalline silicon region 23 is similar.

[0185] Next, we will introduce the content of the third layer. The silicon substrate, passivation and antireflection layer, electrode, seed layer, paste layer, opening, transport region of the first transport layer, transport region of the second transport layer, and other related contents of the third layer can be referred to the contents of the first and second layers mentioned above. To avoid repetition, they will not be repeated.

[0186] As mentioned earlier, during the manufacturing process of solar cells, the passivation layer or passivation antireflection layer 4 of the solar cell generally needs to be grooved or opened to expose the transport layer, so that the electrode paste can directly contact the transport layer through the grooved area or opening, thereby achieving electrical connection to form the electrode structure. However, in the EL or PL tests of solar cells, we found that the passivation effect of the edge region of the solar cell is poor.

[0187] In view of the above, the applicant has found through research that, due to the thin edge of the transport layer, openings or openings in the passivation and antireflection layer 4 on the outside of the thin transport layer can cause the transport layer to be damaged and blackened, reducing the passivation effect and thus affecting the photoelectric conversion efficiency of the entire solar cell.

[0188] To reduce the blackening and damage to the transport layer at the edge of solar cells and improve the passivation effect at the edge, this application provides a solar cell where the transport layer includes a first transport layer 70 and the electrode includes a first electrode 50. The first transport layer 70 can be either an N-type or a P-type transport layer. The first electrode 50 contacts the first transport layer 70 through an opening in the passivation layer or passivation antireflection layer to achieve current collection and conduction.

[0189] The first transport layer 70 is disposed on the first surface of the silicon substrate 1. Specifically, the first transport layer 70 can be disposed entirely on the first surface or partially on the first surface, as shown in Figures 2, 3, 11 and 17. The first transport layer 70 is disposed in a strip shape on the first surface, or in other words, the first transport layer 70 includes several transport regions.

[0190] The first electrode 50 extends along a first direction (i.e., direction M), meaning the length of the first electrode 50 is set along the first direction. The extension direction of the first electrode 50 is the same as the extension direction (i.e., direction M) of the transport region or the aforementioned strip-shaped extension region. The first electrode 50 is disposed on the passivation antireflection layer 4, meaning the first electrode 50 is disposed on the side of the passivation antireflection layer 4 opposite to the silicon substrate 1, and a portion of the first electrode 50 penetrates the opening and is electrically connected to the first transport layer 70, so as to extract the charge carriers collected by the first transport layer 70 using the first electrode 50. The first electrode 50 can be formed from a non-burn-through paste, which may include one or more of low-temperature silver paste, copper paste, and aluminum paste. The first electrode 50 can be formed corresponding to the opening region using processes such as screen printing, electroplating, sputtering, or vapor deposition. The non-burn-through paste refers to a paste that cannot directly penetrate the passivation antireflection layer 4 through sintering to achieve contact with the first transport layer 70. Generally, the first electrode 50 formed from this non-burn-through paste still retains a binder material, such as organic components.

[0191] Along the first direction, the silicon substrate 1 includes a first edge 1a and a second edge disposed opposite to each other, that is, the first edge 1a and the second edge are arranged along the first direction, and both the first edge 1a and the second edge intersect the first direction. Among the multiple openings of the passivation antireflection layer 4, the opening closest to the first edge 1a is the first opening 61. Referring to FIG12, the distance between the edge of the first opening 61 and the first edge 1a is b1, where 1000μm ≥ b1 ≥ 150μm.

[0192] Using the above technical solution, along the first direction, the distance between the first opening 61 and the first edge 1a of the silicon substrate 1 is greater than or equal to 150 μm. That is, sufficient distance is reserved between the first opening 61 and the first edge 1a of the silicon substrate 1, which also ensures that all openings along the first direction are reserved with sufficient distance from the edge of the silicon substrate 1. This avoids openings in the thinner edge region of the first transport layer 70 to the passivation layer or passivation antireflection layer 4, preventing the openings from causing damage and blackening of the first transport layer 70, thereby improving the passivation effect of the thinner edge region of the first transport layer 70. Furthermore, the distance between the first opening 61 and the first edge 1a of the silicon substrate 1 is less than or equal to 1000 μm, preventing the distance between the first opening 61 and the first edge 1a of the silicon substrate 1 from being too large, thereby avoiding the situation where the charge carriers collected in the edge region of the first transport layer 70 cannot be discharged through the first electrode 50 in time. As can be seen from the above, in this application, b1 is placed within a reasonable range of 150μm to 1000μm. This not only prevents the first transport layer 70 from being damaged and blackened, thus improving the passivation effect of the first transport layer 70, but also ensures that the charge carriers collected in the edge region of the first transport layer 70 are promptly discharged through the first electrode 50, thereby improving the photoelectric conversion efficiency of the entire solar cell.

[0193] For example, b1 can be 150μm, 200μm, 250μm, 300μm, 350μm, 400μm, 450μm, 500μm, 550μm, 600μm, 650μm, 700μm, 750μm, 800μm, 850μm, 900μm, 950μm, 1000μm, etc.

[0194] In some embodiments, referring to Figures 2, 3, and 12, the distance between the edge of the first opening 61 and the edge of the first transmission layer 70 along the first direction is d3. Wherein, b1-d3≤20μm; or, 50μm≤d3≤550μm.

[0195] In some embodiments, the first transport layer 70 has the same doping type as the silicon substrate 1, thus eliminating concerns about recombination between the first transport layer 70 and the silicon substrate 1. Therefore, during the deposition of the first transport layer 70, the spacing between the opposite edges of the first transport layer 70 along the first direction and the edge of the silicon substrate 1 can be small or coincident, specifically, b1-d3 ≤ 20 μm, to increase the area of ​​the first transport layer 70 and improve its carrier collection efficiency. Exemplarily, b1-d3 can be 20 μm, 18 μm, 15 μm, 12 μm, 10 μm, 8 μm, 6 μm, 5 μm, 3 μm, 1 μm, or 0, etc.

[0196] In other embodiments, the doping type of the first transport layer 70 is opposite to that of the silicon substrate 1. In this case, if the distance between the edge of the first transport layer 70 and the edge of the silicon substrate 1 is small or coincides, recombination loss between the first transport layer 70 and the silicon substrate 1 is likely to occur. Therefore, during the deposition of the first transport layer 70, a certain distance is maintained between the opposite edges of the first transport layer 70 along the first direction and the edge of the silicon substrate 1 to prevent recombination between the first transport layer 70 and the side of the silicon substrate 1, which would lead to leakage. Based on this, 50μm≤d3≤550μm, along the first direction, ensures that the distance d3 between the first opening 61 and the edge of the first transport layer 70 is within a reasonable range, which reduces recombination loss, lowers the risk of leakage, and prevents the first transport layer 70 from being damaged and blackened, thus improving the passivation effect of the first transport layer 70. It can be understood that in this technical solution, the solar cell can be in back contact with the cell, and both the first transport layer 70 and the second transport layer 9 are located on the first surface, with the first transport layer 70 and the second transport layer 9 arranged at intervals along the second direction.

[0197] For example, d3 can be 50μm, 80μm, 100μm, 120μm, 150μm, 180μm, 200μm, 220μm, 250μm, 280μm , 300μm, 320μm, 350μm, 380μm, 400μm, 420μm, 450μm, 480μm, 500μm, 520μm or 550μm, etc.

[0198] In some embodiments, as shown in FIG12, the distance between the edge of the first opening 61 and the edge of the first electrode 50 along the first direction is b2. If b2 is too large, the distance of the first electrode 50 beyond the first opening 61 will be too large, resulting in waste of the raw material of the first electrode 50; if b2 is too small, deviations during the laser opening process and deviations generated by printing the first electrode 50 may cause the first electrode 50 to fail to cover the first opening 61, thereby affecting the carrier extraction efficiency. In view of the above, in this application, 50μm≤b2≤500μm is used to prevent waste of the raw material of the first electrode 50, and at the same time to prevent processing deviations from causing the first electrode 50 to fail to cover the first opening 61, thus ensuring the carrier extraction efficiency.

[0199] For example, b2 can be 50μm, 80μm, 100μm, 120μm, 150μm, 180μm, 200μm, 220μm, 250μm, 280μm, 300μm, 320μm, 350μm, 380μm, 400μm, 420μm, 450μm, 480μm or 500μm, etc.

[0200] In other embodiments, as shown in Figures 12 and 14, the opening closest to the edge of the first transport layer 70 along the second direction (direction L) is called the second opening. The second direction (direction L) intersects the first direction (direction M), and in some embodiments, the first and second directions are perpendicular to each other. Along the second direction, the distance between the edge of the second opening and the edge of the first transport layer 70 is S. If S is too small, the first electrode 50 may extend beyond the first transport layer 70, causing leakage. If S is too large, it may affect the extraction efficiency of carriers collected at the edge of the first transport layer 70. Based on this, in this technical solution, 50 μm ≤ S ≤ 550 μm to ensure the extraction efficiency of carriers at the edge of the first transport layer 70 while reducing the risk of leakage.

[0201] For example, S can be 50 μm, 80 μm, 100 μm, 120 μm, 150 μm, 180 μm, 200 μm, 220 μm, 250 μm, 280 μm, 300μm, 320μm, 350μm, 380μm, 400μm, 420μm, 450μm, 480μm, 500μm, 520μm or 550μm, etc.

[0202] In some embodiments, as shown in Figures 12 and 13, the passivation layer or passivation antireflection layer 4 has a heat-affected zone 13 surrounding the opening. Specifically, during the laser-assisted grooving process of the passivation antireflection layer 4, the area near the edge of the opening, although not removed, is affected by laser heat and is called the heat-affected zone 13. This heat-affected zone 13 is formed around the opening. The shape of the opening can be circular, elliptical, rectangular, or other shapes, and the surrounding shape of the heat-affected zone 13 also changes with the shape of the opening; its annular shape can be a circular ring, an elliptical ring, or a rectangular ring, etc.

[0203] In some embodiments, the width of the heat-affected zone 13 is W, where 1μm ≤ W ≤ 5μm. This avoids the heat-affected zone 13 being too wide, which would reduce the passivation effect. For example, W can be 1μm, 2μm, 3μm, 4μm, or 5μm, etc.

[0204] In addition, in order to avoid the heat-affected zone 13 reaching the edge of the first transport layer 70 and affecting the collection of charge carriers, S > W in this technical solution. At the same time, it also avoids the heat-affected zone 13 covering the edge of the first transport layer 70, thus ensuring the passivation effect of the edge of the first transport layer 70.

[0205] In some embodiments, as shown in Figures 15 and 16, during the laser opening process, the laser energy at the edge position is appropriately increased, for example, greater than 200 J / cm², which opens the passivation layer material of the heat-affected zone 13, thereby forming multiple openings around the opening. The purpose of this arrangement is that if no openings are formed in the heat-affected zone 13, the thermal damage to the first transmission layer 70 corresponding to the heat-affected zone position cannot be repaired. In this embodiment, the openings are filled with conductive material 15, which is electrically connected to the first transmission layer 70. With this arrangement, the first electrode 50 can be electrically connected to the first transmission layer 70 while passing through the opening, and can also be electrically connected to the first transmission layer 70 through the conductive material 15. Furthermore, the first transmission layer 70 at the position corresponding to the opening is also a heat concentration area with significant damage (heat concentration areas are prone to forming openings), and the conductive material 15 can repair the damage at this position. The conductive material 15 is distributed in a granular manner within the heat-affected zone 13, and the granular conductive material 15 at the position farthest from the center of the opening defines the width W of the heat-affected zone 13.

[0206] The conductive material 15 can be one or more of materials such as titanium, copper, silver, aluminum, tungsten, and nickel, and is preferably formed by electroplating or chemical plating.

[0207] In some embodiments, referring to Figures 1, 7, and 15, the first electrode 50 includes a seed layer 51 filled with multiple openings. The first electrode 50 covers the seed layer 51 and the conductive material 15 on the side facing away from the silicon substrate 1. In this technical solution, the seed layer 51 enables a good electrical connection between the first electrode 50 and the first transport layer 70, and prevents metal elements in the first electrode 50 from diffusing into the silicon substrate 1, thus reducing recombination. Simultaneously, the first electrode 50 offers more options; mature and inexpensive metals (such as base metals like copper or aluminum) can be used instead of silver, reducing electrode costs and consequently lowering the cost of the solar cell.

[0208] In some embodiments, referring to Figures 12 and 13, the orthographic projections of the heat-affected zones 13 surrounding two adjacent openings on the first surface do not overlap, that is, the heat-affected zones 13 of two adjacent openings are not overlapped. This arrangement can prevent the heat-affected zones 13 of two adjacent openings from having an excessive impact on the first transport layer 70, thus affecting the collection of charge carriers.

[0209] In some embodiments, as shown in FIG12, the orthographic projection of the plurality of openings on the first surface is located inside the orthographic projection of the first electrode 50 on the first surface. That is, the plurality of openings are all covered by the first electrode 50, thereby improving the conductivity efficiency of the first electrode 50.

[0210] In another embodiment, referring to FIG13, the first opening 61 is partially or entirely located outside the orthographic projection of the first electrode 50 onto the first surface. In other words, the first electrode 50 may cover a portion of the opening closest to the first edge 1a, or the first electrode 50 may not cover the opening closest to the first edge 1a. Using this technical solution, the extension distance of the first electrode 50 along the first direction can be adjusted according to actual conditions, without being limited by the position of the first opening 61, thus reducing the processing difficulty of the first electrode 50 and improving processing efficiency.

[0211] In some embodiments, the first transmission layer 70 may be partially or entirely disposed on the first surface. When the first transmission layer 70 is partially disposed on the first surface, the first transmission layer 70 may be distributed in a strip shape (i.e., transmission area), and the strip-shaped first transmission layer 70 extends along a first direction, and a plurality of first transmission layers 70 are arranged at intervals along a second direction.

[0212] The solar cell also includes a second transport layer, which can be an integral layer or exist as a transport region, such as transport region 74 in Figure 17. The second transport layer has the opposite conductivity type to the first transport layer 70 to collect and export electrons and holes respectively, which is beneficial for forming photocurrent. A second electrode is disposed on the side of the second transport layer away from the silicon substrate 1 to export the charge carriers collected by the second transport layer.

[0213] The solar cell can be a back-contact cell or a bifacial cell. If it is a back-contact cell, the back-contact cell can be a TBC (Tunnel Oxide Passivated Contact Back Contact) or HPBC (Hybrid Passivated Back Contact), etc.; if it is a bifacial cell, the bifacial cell can be a PREC (Passivated Emitter Rear Cell) solar cell or TOPCon (Tunnel Oxide Passivated Contact) solar cell, etc. Of course, the solar cell can also be a single-sided hybrid cell or a bifacial hybrid cell.

[0214] In the case of a bifacial solar cell, the second transport layer covers at least a portion of the second surface of the silicon substrate 1. Referring to Figures 2, 3, and 17, in the case of a back-contact solar cell, the second transport layer covers at least a portion of the first surface of the silicon substrate 1, and the first transport layer 70 and the second transport layer are arranged at intervals along a second direction. Specifically, the second transport layer and the first transport layer 70 can both be arranged in alternating stripe patterns or in alternating interdigitated patterns.

[0215] In some embodiments, referring to FIG15, a first interface layer 14 is disposed between the first transport layer 70 and the silicon substrate 1, and a second interface layer is disposed between the second transport layer and the silicon substrate 1. The passivated contact structure composed of the interface layer and the semiconductor layer has excellent interface passivation effect and can achieve selective collection of charge carriers, reduce the carrier recombination rate in the region on the surface of the silicon substrate 1 where the semiconductor layer is formed, and further improve the photoelectric conversion efficiency of the solar cell. The material and thickness of the first interface layer 14 can be set according to the material of the first transport layer 70 and actual needs, and the material and thickness of the second interface layer can be set according to the material of the second transport layer and actual needs, and are not specifically limited here.

[0216] For example, the first transport layer 70 can be a doped polysilicon layer, and the first interface layer 14 can be a tunneling oxide layer. The second transport layer can be a doped polysilicon layer, and the second interface layer can be a tunneling oxide layer.

[0217] Of course, when the first transport layer 70 includes one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon, the first interface layer 14 includes one or more of intrinsic amorphous silicon, intrinsic microcrystalline silicon, and intrinsic nanocrystalline silicon. When the second transport layer includes one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon, the second interface layer includes one or more of intrinsic amorphous silicon, intrinsic microcrystalline silicon, and intrinsic nanocrystalline silicon.

[0218] The materials of the first transport layer 70 and the second transport layer can be silicon (Si), germanium (Ge), silicon carbide (SiCx), or gallium arsenide (GaAs), etc.

[0219] This application also provides a photovoltaic module, including any of the aforementioned solar cells. The photovoltaic module may further include encapsulating films located on both sides of the solar cells, and other structures within the photovoltaic module are not specifically limited. The photovoltaic module may also include electrical connectors, which serve as conductive interconnects. For example, the electrical connector may be a solder strip or a conductive backsheet, and the specific type of electrical connector is not limited. The electrical connectors are electrically connected to the aforementioned electrodes in at least two of the aforementioned solar cells. This connection can be direct or indirect, and neither is limited. The electrical connectors can electrically connect the positive electrode of one of two adjacent aforementioned solar cells to the negative electrode of the other solar cell, achieving conductive interconnection.

[0220] It should be noted that in this application, the photovoltaic module, solar cell and the method for preparing the solar cell are related to each other and can achieve the same or similar beneficial effects. To avoid repetition, they will not be described again here.

[0221] It should be noted that, in this application, the aforementioned first, second, and third levels of content can be combined or implemented individually, provided there is no contradiction or conflict, and all such combinations are within the scope of protection of this application. The content of the first, second, and third levels can be referenced interchangeably; to avoid repetition, relevant parts have been omitted or briefly described.

[0222] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0223] Those skilled in the art should understand that, in the disclosure of this application, the terms "first," "second," "third," "fourth," "fifth," etc., are only used to distinguish different structures and do not limit the number of specific structures, connection relationships, etc.; in addition, the orientation or positional relationship indicated by "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," etc., is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this application and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the above terms should not be construed as limitations on this application.

Claims

1. A solar cell, wherein, include: Silicon substrate; In the direction of the thickness of the silicon substrate, the silicon substrate has opposing first and second surfaces; A textured structure is provided on the first surface; a transport layer and a passivation antireflection layer are stacked on the textured structure; in the direction of the thickness of the silicon substrate, the transport layer is located between the silicon substrate and the passivation antireflection layer; the passivation antireflection layer has a plurality of openings; the ratio of the maximum size of the openings to the one-dimensional size of the textured structure is 0.5 to 5.

2. The solar cell according to claim 1, wherein, The transport layer includes a first transport layer and a second transport layer, wherein the first transport layer and the second transport layer have different doping types; The maximum size of the opening in the corresponding region of the first transport layer is 1 to 5 times the one-dimensional size of the texture structure; The maximum size of the opening in the corresponding region of the second transport layer is 0.5 to 5 times the one-dimensional size of the texture structure.

3. The solar cell according to claim 1, wherein, The transmission layer includes several transmission regions. In one of the transmission regions, the openings are arranged at least one row of openings, and the extension direction of the row of openings is parallel to the extension direction of the transmission region.

4. The solar cell according to claim 3, wherein, In one of the transmission areas, the number of the open rows is greater than or equal to 2; the spacing d2 between adjacent open rows is 0.5 to 5 times the one-dimensional size of the texture structure.

5. The solar cell according to claim 4, wherein, The openings in adjacent rows of openings are staggered.

6. The solar cell according to claim 3, wherein, Within one of the said open rows, the spacing d1 between adjacent said open rows is 1 to 7 times the one-dimensional dimension of the texture structure.

7. The solar cell according to claim 1, wherein, The texture structure includes: a base; the one-dimensional dimension of the base is 5µm to 40µm, and / or the side length of the base is 5µm to 40µm.

8. The solar cell according to claim 7, wherein, The transmission layer includes several transmission zones, with each of the tower bases arranged in a row along the extension direction of the transmission zone; and / or, each of the openings is spaced apart and arranged in a row along the extension direction of the transmission zone.

9. The solar cell according to claim 4, wherein, Within one of the said open rows, the spacing d1 between adjacent open rows is 10 μm to 100 μm; and / or, the spacing d2 between adjacent open rows is 8 μm to 80 μm.

10. The solar cell according to claim 7, wherein, The transport layer includes: a first transport layer and a second transport layer, wherein the first transport layer and the second transport layer have different doping types; the side length of the base in the second transport layer is greater than the side length of the base in the first transport layer; and / or, the depth of the base in the second transport layer is less than the depth of the base in the first transport layer.

11. The solar cell according to any one of claims 1 to 10, wherein, The maximum size of the opening is 10 μm to 45 μm.

12. The solar cell according to claim 1, wherein, The region corresponding to the opening on the side of the transport layer opposite to the silicon substrate is a contact region; at least one of the contact regions has a ridge line; The solar cell also includes an electrode disposed on the side of the passivation antireflection layer away from the silicon substrate, the electrode passing through the opening and contacting the transport layer.

13. The solar cell according to claim 12, wherein, At least one of the contact areas has a base, and the ridge includes the side length of the base.

14. The solar cell according to claim 12, wherein, There is at least one hole at the location of the ridge line within the contact area.

15. The solar cell according to claim 14, wherein, The edge of the hole has annular protrusions.

16. The solar cell according to claim 15, wherein, The density of holes at the ridge line is greater than the density of holes in other areas, and / or the density of protrusions at the ridge line is greater than the density of protrusions in other areas.

17. The solar cell according to claim 15, wherein, At least some of the holes at the location of the ridge are interconnected, and / or the protrusions at the ridge extend along the ridge in a strip shape.

18. The solar cell according to claim 12, wherein, The contact area has multiple holes; the contact area includes a central region and an edge region surrounding the central region; for a given contact area: the size of the hole in the central region is larger than the size of the hole in the edge region.

19. The solar cell according to claim 12, wherein, The area outside the contact area on the side of the transport layer opposite to the silicon substrate is the non-contact area; The roughness of the contact area is greater than that of the non-contact area.

20. The solar cell according to claim 12, wherein, The transmission layer includes several transmission zones, and in one of the transmission zones, there is a gap between the contact area and the edge of the transmission zone.

21. The solar cell according to claim 15, wherein, The height and width of the protrusion are both less than or equal to 0.5 μm; the direction of the height is parallel to the direction of the thickness of the silicon substrate, and the width is the maximum dimension of the protrusion on a plane perpendicular to the direction of the height.

22. The solar cell according to any one of claims 12 to 21, wherein, The transport layer includes a polycrystalline silicon doped layer; the polycrystalline silicon doped layer has a polycrystalline silicon region and an amorphous silicon region, the amorphous silicon region being located on the side of the polycrystalline silicon doped layer opposite to the silicon substrate; the amorphous silicon region is located between the passivation antireflection layer and the polycrystalline silicon region, and is located at the opening.

23. The solar cell according to claim 22, wherein, The thickness of the amorphous silicon at the ridge line is greater than the thickness of the amorphous silicon in other regions.

24. The solar cell according to any one of claims 12 to 23, wherein, The electrode comprises a layered seed layer and a non-burn-through slurry layer.

25. The solar cell according to claim 1, wherein, The transport layer includes a first transport layer, and the solar cell further includes a first electrode disposed on the side of the passivation antireflection layer away from the silicon substrate, the first electrode passing through the opening and contacting the first transport layer; Along the extension direction of the first electrode, the silicon substrate includes a first edge and a second edge disposed opposite to each other, and the plurality of openings includes a first opening closest to the first edge, the distance between the edge of the first opening and the first edge being b1, 1000μm≥b1≥150μm.

26. The solar cell according to claim 25, wherein, Along the extending direction of the first electrode, the distance between the edge of the first opening and the edge of the first transmission layer is d3; The first transport layer has the same doping type as the silicon substrate, b1-d3≤20μm; or, the first transport layer has the opposite doping type to the silicon substrate, 50μm≤d3≤550μm.

27. The solar cell according to claim 25, wherein, Along the extending direction of the first electrode, the distance between the edge of the first opening and the edge of the electrode is b2, 50μm≤b2≤500μm.

28. The solar cell according to claim 25, wherein, The opening closest to the edge of the first transmission layer along the second direction is the second opening, and the second direction intersects the extension direction of the first electrode; Along the second direction, the distance between the edge of the second opening and the edge of the first transmission layer is S, where 50μm≤S≤550μm.

29. The solar cell according to claim 28, wherein, The passivation antireflection layer has a heat-affected zone surrounding the opening, the width of which is W; 1μm≤W≤5μm, or S>W.

30. The solar cell according to claim 29, wherein, The heat-affected zone includes multiple openings, each filled with a conductive material, which is electrically connected to the first transport layer.

31. The solar cell according to claim 30, wherein, The first electrode includes a seed layer and a paste layer of transport stacks, the seed layer filling a plurality of the openings, and the electrode paste layer covering the seed layer and the conductive material on the side opposite to the silicon substrate.

32. The solar cell according to claim 29, wherein, The orthographic projections of the heat-affected zones surrounding two adjacent openings onto the first surface do not overlap.

33. The solar cell according to claim 25, wherein, The orthographic projections of the plurality of openings on the first surface are located inside the orthographic projection of the first electrode on the first surface; or, part or all of the orthographic projections of the first openings on the first surface are located outside the orthographic projection of the first electrode on the first surface.

34. The solar cell according to any one of claims 25 to 33, wherein, The first transmission layer is a strip extending along the extension direction of the first electrode, and a plurality of the first transmission layers are arranged at intervals along the second direction; or, the entire first transmission layer is disposed on the first surface.

35. The solar cell according to any one of claims 25 to 33, wherein, The transport layer further includes a second transport layer, which has the opposite conductivity type to the first transport layer; The second transport layer covers at least a portion of the second surface of the silicon substrate; or, the second transport layer covers at least a portion of the first surface of the silicon substrate, and the first transport layer and the second transport layer are spaced apart along a second direction.

36. The solar cell according to claim 35, wherein, The first transport layer comprises one or more of polycrystalline silicon, amorphous silicon, nanocrystalline silicon, and microcrystalline silicon; the solar cell further comprises a first interface layer located on the side of the first transport layer near the silicon substrate; The second transport layer includes one or more of polycrystalline silicon, amorphous silicon, nanocrystalline silicon, and microcrystalline silicon; the solar cell also includes a second interface layer located on the side of the second transport layer near the silicon substrate.

37. A photovoltaic module, wherein, A photovoltaic module includes multiple cell strings, each cell string including multiple solar cells and multiple interconnects, the interconnects being used to connect the multiple solar cells in series; wherein the solar cells are the solar cells according to any one of claims 1-36.

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