Reference circuits and methods for operating thereof

Abstract

A reference circuit includes a first metal-oxide-semiconductor (MOS) transistor arrangement comprising a first current mirror configured to generate at least a first mirror current. The circuit further includes a second MOS transistor arrangement coupled to the first MOS transistor arrangement and comprising a first MOS transistor and second MOS transistor arranged in a cross-coupling configuration so that a gate terminal of the first MOS transistor is electrically coupled to a first terminal of the second MOS transistor, and a gate terminal of the second MOS transistor is electrically coupled to a first terminal of the first transistor. The circuit further includes a discharge circuit electrically coupled to a first node and configured to generate a discharge current from the first node, wherein the first node is electrically coupled between first MOS transistor arrangement and the second MOS transistor arrangement.

Description

[0001] 2024P01194 P97457

[0002] - 1 -

[0003] REFERENCE CIRCUITS AND METHODS FOR OPERATING THEREOF

[0004] Field

[0005] This present disclosure relates to reference circuits and methods for operating thereof.

[0006] Background

[0007] High-performance circuits require robust current reference circuits that are ideally independent of process and supply voltage variations. Robustness in this context entails not only insensitivity to these variations but also predictable and controlled behavior in relation to them. In particular, Proportional to Absolute Temperature (PTAT) reference circuits have become widely adopted across various applications thanks either to their accuracy and the systematic and foreseeable dependence versus temperature.

[0008] PTAT reference circuits can be implemented using either bipolar junction transistors (BJTs) or CMOS transistors operating in weak inversion. BJT-based implementations are particularly valued for their precision and linearity, stemming from the predictable voltage-temperature relationship of BJTs and their inherent sensitivity to temperature changes. These attributes enable BJT-based circuits to generate highly accurate and stable PTAT currents, with reduced sensitivity to process variations, making them a reliable choice for temperature-sensing applications.

[0009] However, the adoption of BJT devices faces a significant technological limitation. While vertical BJTs exhibit excellent electrical characteristics, their integration into low-cost processes is constrained by the need for their collectors to coincide with the grounded substrate. This constraint complicates the design of high-impedance current generators at the collector, often requiring specialized2024P01194 P97457

[0010] - 2 -

[0011] fabrication processes that substantially increase production costs.

[0012] Description

[0013] In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the disclosure. In the following description, various aspects of the disclosure are described with reference to the following drawings, in which:

[0014] FIGS. 1A and 1B each depict a reference circuit implemented using bipolar junction transistors;

[0015] FIG. 2 shows a reference circuit implemented using Complementary Metal-Oxide- Semiconductor (CMOS) transistors;

[0016] FIG. 3 a proportional to absolute temperature (PTAT) reference circuit according to at least one aspect of the present disclosure;

[0017] FIG. 4 a proportional to absolute temperature (PTAT) reference circuit according to at least one aspect of the present disclosure;

[0018] FIG. 5 shows a graph of plots of reference circuits;

[0019] FIG. 6 shows a flow diagram for operating a PTAT circuit according to at least one aspect of the present disclosure.

[0020] The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and aspects in which the disclosure may be practiced. One or more aspects are described in sufficient detail to enable those2024P01194 P97457

[0021] skilled in the art to practice the disclosure. Other aspects may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the disclosure. The various aspects described herein are not necessarily mutually exclusive, as some aspects can be combined with one or more other aspects to form new aspects. Various aspects are described in connection with methods and various aspects are described in connection with devices. However, it may be understood that aspects described in connection with methods may similarly apply to the devices, and vice versa. Throughout the drawings, it should be noted that like reference numbers are used to depict the same or similar elements, features, and structures. That is, it should be understood that, for clarity and consistency, the same or similar reference numerals are used throughout the figures to denote the same or similar elements, components, or features. Variations of the embodiments may include different combinations of these elements, but the reference numerals will maintain their correspondence to the particular elements where applicable. Throughout the drawings, it should be noted that proportions are not necessary to scale and that the size of features may be emphasized for ease of illustration.

[0022] FIGS. 1A and 1B each shows a conventional bipolar junction transistor (BJT) based proportional to absolute temperature (PTAT) circuit or generator, which are respectively denoted 100a and 100b.

[0023] The PTAT circuit 100a includes four BJT transistors including pnp BJT Pl an pnp BJT P2, npn BJT QI and npn BJT Q2. These transistors are arranged or configured as two mirror circuits, e. g., a PMOS mirror (implemented with Pl and P2 ) and an NMOS mirror (implemented with transistors QI and Q2 ).

[0024] For the PTAT circuit 100a of FIG. 1A, a PTAT current can be generated in the case the currents where in the two BJTs QI and Q2 are matched and where A is the aspect ratio of Q2. The2024P01194 P97457

[0025] following expression shows the relationship between the PTAT voltage (VP A) and the currents in the circuit 100a.

[0026] VPTAT = VT* [ln + ln(A)] = R * IOUT [1]

[0027]

[0028] where VT is the thermal voltage (nearly 25mV at room temperature and proportional to the temperature expressed in Kelvin),

[0029] R is resistance of resistor R

[0030] IQ1 is current flowing into Q1

[0031] IOUT is current flowing into Q2

[0032] Once the PNP mirror produces a current of IQ1=A× IQ1, it follows that the value for the current IOUTis dependent only on the thermal voltage and geometrical ratios. This can ensure large accuracy.

[0033] However, the above expression has IOUTT=0 has a second possible solution or another equilibrium state for the circuit 100a. Accordingly, a startup circuit is necessary for inj ecting a current into the circuit 100a to exclude this second possible equilibrium point or second state in which the circuit 100 does not operate as a reference circuit. Unfortunately, the inclusion of a startup circuit introduces some complexity, cost and some cumbersome design effort. For example:

[0034] 1) a coarse generator ICOARSE must be provided to turn on the device by contributing to IQI or IOUTT value

[0035] 2) replica currents for IOUTand ICOARSEmust be produced and compared to verify if the solution IOUT= 0 holds or not 3) a switch plus a Schmitt trigger are used to turn-off the startup contribute which would otherwise generate an accuracy error. In fact, in expression

[0001] it is explicit the contribute of both currents IQI and IOUT - As the startup current is always superimposed to one of them, an error will result.

[0036] 4) the replica current for IOUTmust be always higher that the coarse replica, otherwise the startup contribute2024P01194 P97457

[0037] 5

[0038] would not be turned off. A dedicated investigation is needed to verify that this always holds for every PVT and realistic matching condition

[0039] 5) care must be paid where to inject the startup current and where the replica for IOUT must be collected: a wrong placement of the injection and sensing point could cause startup failures depending on operating conditions.

[0040] All these problems considered, an alternative approach can obviate the need for startup circuit issue by arranging the BJTs Q1 and Q2 in a cross coupled configuration as shown for the reference circuit 100b of FIG. 1B.

[0041] In such an implementation for a PTAT reference circuit, the ratio of the BJTs no longer must be equal to 1: A in both pairs of transistors (Q1-Q2) and (Q3-Q4). By applying the Kirchhoff' s law at the loop made by the 4 BJTs and the resistor R, the following formula is obtained

[0042] VPTAT = VT * ln = VT * ln(A2) = R * IOUT

[0043] \ IBIAS*IOUT Jk 7

[0044]

[0045]

[0002]

[0046] Unlike the case for the circuit 100a, the above expression for the circuit 100b is independent in regards to the value of the current IBIAS flowing in one BJT branch. Hence, it follows that the current across resistor R is insensitive to the current flowing in the other branch while it still preserves the desired PTAT nature or functionality.

[0047] The expression or relationship immediately-above has a unique solution. Thus, once a generated current is inj ected into Q4, a single equilibrium point or state for the circuit 100b is precisely defined and the solution or situation where IOUT=0 cannot occur. As a result, there is no need for a startup current. This provides a relevant advantage in comparison to the circuit of FIG. 1A. Further, the dependence of the drop2024P01194 P97457

[0048] 6

[0049] across the resistor R is expected to be quite larger because of the dependence on A2which increases the insensitivity against any possible offset from the BJT devices.

[0050] However, BJT implementations for (PTAT) reference circuits have distinct disadvantages. Therefore, porting such implementations to CMOS technology could be advantageous in terms of cost considerations. Again, the circuits 100a and 100b respectively of FIGS. 1A and 1B explicitly require the presence of an unconstrained collector due to being implemented with BJTs, which is incompatible with cheap manufacturing processes.

[0051] FIG. 2 illustrates a conventional CMOS version of a PTAT (Proportional to Absolute Temperature) reference circuit or current generator 200. The transistors Pl, P2, Ml, and M2 are MOSFET transistors, and in this example, the transistors Pl and P2 are PMOS transistors and the transistors Ml and M2 are NMOS transistors.

[0052] Specifically, the circuit 200 can represent a CMOS counterpart to circuit 100a shown in FIG. 1A and share several advantages and disadvantages with its BJT-based equivalent. One notable benefit of the CMOS design is its cost-effectiveness in terms of being realized using a less expensive manufacturing process. However, this cost savings comes at the expense of reduced accuracy, primarily due to the inherently poorer matching characteristics of CMOS transistors compared to BJTs.

[0053] FIG. 3 shows, according to one example of the present disclosure, a PTAT reference circuit 300. The reference circuit 300 can be considered as an equivalent CMOS solution for the circuit 100b of FIG. 1B.

[0054] This circuit 300 has some of the same advantages as its BJT equivalent, e. g., the circuit 100b of FIG. 1B. However, unlike2024P01194 P97457

[0055] 7

[0056] the BJT version, the circuit 300 does not necessarily start or properly operate correctly.

[0057] Without being bound by theory, it is believed that presence of parasitic capacitance inj ecting from the power supply (Vdd) leads to a spurious initial condition or state in which the circuit does not start properly. In such a state, it is believed that the voltage on the Vy node becomes so high that the Ml transistor highly conducts, which in turn causes the M2 transistor to turn OFF. In such a scenario there no way to discharge the Vy node. In any event, the circuit 300 does not work as a PTAT reference circuit.

[0058] FIG. 4 illustrates another PTAT reference circuit 400 according to at least one aspect of the present disclosure. The circuit 400 shares many similarities with circuit 300 depicted in FIG. 3. Accordingly, identical reference numbers / characters can be used to denote the same elements, and a detailed description of these elements need not repeated here to avoid redundancy.

[0059] The circuit 400 is configured to generate or provide a PTAT reference current IPTAT - The reference current IPTAT, provided across the resistor R, is proportional to absolute temperature. The circuit 400 includes an output node OUT is electrically coupled to the first terminal of the transistor M3.

[0060] Like the circuit 300, the circuit 400 includes a first metal-oxide-semiconductor (MOS) transistor arrangement which includes a first (e. g., NMOS) current mirror configured to generate at least a first mirror current. The first current mirror can include the MOS transistors M3 and M4. In this example, the gate terminal of the M4 transistor is electrically coupled to the gate terminal of the M3 transistor and is further electrically coupled to the first terminal of the M4 transistor.2024P01194 P97457

[0061] In the example of FIG. 4, the circuit 400 includes a biasing circuit in which a resistor is coupled between a power supply (Vdd) terminal and to a first terminal (e. g., source) of the transistor M4.

[0062] The circuit 400 further includes a second MOS transistor arrangement coupled to the first MOS transistor arrangement. The second MOS transistor arrangement includes a first MOS transistor Ml and second MOS transistor M2 arranged in a cross-coupling configuration so that a gate terminal of the first MOS transistor Ml is electrically coupled to a first terminal of the second MOS transistor M2, and a gate terminal of the second MOS transistor M2 is electrically coupled to a first terminal of the first transistor Ml.

[0063] However, the circuit 400 includes include one or more additional circuits or circuitries.

[0064] In FIG. 4, the circuit 400 includes a discharge circuit 410. As shown in this case, the discharge circuit 410 is electrically coupled to the node Vy, which is a node electrically coupled to the second terminal of the M3 transistor, the first terminal of the M2 transistor, and the gate terminal of the Ml transistor. In at least one example, the discharge circuit 410 is configured to generate a current, a discharge current, from the node Vy. Thus by means of the discharge circuit 410, the voltage at node Vy is pulled down.

[0065] The discharge current can occur or be produced by the discharge circuit 410 even if the transistor M2 is in an OFF state. In view of that, the overdrive condition that was occurring at the gate terminal of the transistor Ml, as described with respect to the circuit 300 of FIG. 3, is (largely) reduced enabling the M2 transistor to turn M2 on.2024P01194 P97457

[0066] 9

[0067] The discharge current may be relatively small but can be higher than the overall leakage contributing to pull M2 source node.

[0068] As shown, the wherein the discharge circuit 410 can be arranged between the node Vy and a reference terminal. The reference terminal may be a ground reference.

[0069] In one or more instances, the discharge circuit 410 may be realized as a diode circuit, arranged and electrically coupled between the Vy node and a reference terminal. Said differently, such a diode circuit can be arranged between the source or second terminal of the M2 transistor and a reference terminal / ground terminal.

[0070] In at least one case (e. g., FIG. 4 ), the discharge circuit 410 may be a diode circuit implemented by means of a transistor (e. g., Md) configured / arranged in a diode configuration. As such, the transistor Md has its gate terminal electrically coupled to its first / source terminal. The first terminal of the transistor Md is further electrically coupled to the node Vy. Further, the drain / second terminal of the transistor Md is electrically coupled to the reference terminal.

[0071] The transistor Md has an aspect ratio p times smaller than the transistor Ml. Herein, aspect ratio, e. g., for transistors refers to the ratio of the transistor width

[0072]

[0073] to length L of the transistor channel ( W / L). This can allow the Md transistor, arranged in the diode configuration, to generate or produce a sinking current from node Vy as would be similarly generated in the BJT equivalent reference circuit 100b at the base of a BJT transistor. That is, the inclusion of the discharge circuit 410 in FIG. 4 ensures that the discharge current is properly control as just a fraction of the current I BIAS •2024P01194 P97457

[0074] Without being bound by theory, it is believed the base current in the BJT transistor QI of the circuit 100b is responsible or at least an important factor for allowing or enabling the startup of the circuit 100b. Therefore, the discharge circuit 410 producing the discharge current, which can be considered as essentially mimicking the base current in the reference circuit 400. Thus, the circuit 400 can reach a startup state and avoid the non-working / non-functioning equilibrium state that occurs in the circuit 300 of FIG. 3.

[0075] In one or more instances, the circuit 400 may further include a compensation circuit 420, as is the case in the example of FIG. 4. ( In cases where there is no compensation circuit, the M3 transistor may be electrically coupled to the Vdd power supply terminal).

[0076] The compensation circuit 420 can include a transistor M5 arranged with its gate terminal electrically coupled to the gate terminal and first terminal of the Md transistor. The transistor M5 can be configured to (re) generate the discharge current produced by the discharge circuit 410 (e. g., by the further / Md transistor).

[0077] The compensation circuit 420 also includes another current mirror which is formed by the MOS (e. g., PMOS) transistors Pl and P2. The (PMOS) current mirror, formed by transistors Pl and P2, is electrically coupled to the M5 transistor, e. g. to the first terminal of the M5 transistor.

[0078] Accordingly, the transistors Pl and P2 are configured to produce or generate a current substantially or nominally equal to the discharge current, e. g., substantially / nominally equal to the current produced by the M5 transistor. Further, the PMOS current mirror is arranged or configured to inj ect or provide this "compensation" current to the first current mirror. In other words, the compensation circuit 420 can be configured to compensate for the discharge current generated2024P01194 P97457

[0079] at node Vy (caused by the discharge circuit 410) by inj ecting a compensation current substantially equal to the discharge current into the first current mirror, e. g., into a first terminal of the M3 transistor and into an output node (out).

[0080] As shown in at least the example of FIG. 4, the compensation circuit 420 is arranged so that the transistors Pl and P2 each electrically coupled to a power supply terminal (e. g., coupled to power supply terminal of Vdd). A first terminal of each transistor Pl and P2 is electrically coupled to the power supply terminal. The gate terminal of the Pl transistor is electrically coupled to its second (drain) terminal, which in turn is electrically coupled to the first terminal of the M5 transistor. The gate terminal of the P2 transistor is electrically coupled to the gate terminal and second terminal of the Pl transistor.

[0081] In short, a compensation circuit such as compensation circuit 420 can be included in circuit like circuit 400 and configured to cancel the loss of the discharge current (produced by the discharge circuit 410) by reinj ecting it at the output node. This leads to the current at the output terminal being substantially equal to the current ( IPTAT) across resistor R. This results in improved performance for the circuit 400 as a PTAT reference circuit because the properties of reference current IPTATare improved, e. g., in terms of ( in- ) sensitivity.

[0082] The compensation circuit 420 may optionally include a further, cascode transistor arranged between the Pl transistor and the M5 transistor. That is, the second terminal of the Pl transistor may be coupled to the M5 transistor through the cascode transistor, MCAS. The cascade transistor can be a MOSFET (e. g., NMOS) or BJT. For instance, the first terminal of the MCAStransistor can be electrically coupled to the second terminal of the Pl transistor and the second terminal of the MCAStransistor can be electrically coupled to the first terminal of the M5 transistor. The gate terminal of the MCAS2024P01194 P97457

[0083] 12

[0084] transistor can be electrically coupled to first current mirror, e. g., to the gate terminal of the M3 transistor.

[0085] The MCAStransistor can be any suitable type of transistor, including, for example, e. g., a BJT (e. g., npn) or a MOSFET (NMOS), to name a couple.

[0086] Referring back to the discharge circuit 410, its effectiveness can be shown by inspection, especially with focus on the M2 transistor. That is, to verify or show that M2 transistor is turned ON by means of the addition of the discharge circuit 410, e. g., by means of the transistor Md arranged as diode, it is sufficient to examine the open loop at the gate terminal of M2 transistor and verify whether this voltage is compatible with conduction or not.

[0087] vgsM2 = vgsMl + vgsM3 — vgsM4

[0003] Where

[0088] vgsX is the voltage difference between gate terminal and first or source terminals of X transistor

[0089] The drop across R is neglected otherwise it will be implied that M2is ON

[0090] Assuming the Md diode (e. g., Md transistor arranged as a diode) is a times smaller than M2, it follows that its current should be equal or higher to IBIAS / α (it is higher in case M2is in triode). If the Md transistor is high or ON, this helps to pull or bring VYlow, so it can be assumed to be equal. For explanations purposes, it can be supposed that M2does not conduct.

[0091] It follows that

[0092] vgsM4 — vgsM3 = VT * In [a / A]

[0004]

[0093] Accordingly:2024P01194 P97457

[0094] 13

[0095] vgsMl — vgsM2 = VT * In [a / A]

[0005]

[0096] That shows that the M2 transistor must necessarily conduct a current thereby proving the effectiveness of the use of the discharge circuit 410, e. g., the introduction of and the Md transistor as arranged in FIG. 4.

[0097] Additionally, the discharge circuit 410 and the compensation circuit 420 provide an additional benefit because that the current across the M5 transistor is matched to the one across diode Md, e. g., using the cascode transistor Meas biased with the voltage Vcas at its gate terminal, which is electrically coupled to the gate terminal of the M4 transistor.

[0098] The PTAT reference circuit 400 with its CMOS implementation uses a discharge circuit 410 (e. g., incorporation of a diode circuit) to eliminate or avoid the spurious steady state point and to ensure that it will function properly as a PTAT reference circuit / generator. The circuit 400 shares with the BJT counterpart (e. g., circuit 100b) all the original benefits (e. g., larger drop across resistor R and no need to remove the startup current) plus additional improvements:

[0099] - Base / gate terminal currents do not affect any longer the generated current accuracy

[0100] - The circuit 400 can be implemented using less costly technologies (e. g., CMOS).

[0101] FIG. 5 is graph 500 includes plots 510, 520, and 520 showing a comparison of the output current ( IOUT) as a function of changes in supply voltage for a difference PTAT reference circuits including the circuit 400 (plot 510), the BJT-based circuit 100b shown in FIG IB (520), and the plot 530 is for the current for the circuit 400 in which the body effect occurs or is taken into consideration.2024P01194 P97457

[0102] The graph 500 shows the worst-case scenarios for each structure or circuit under process variations. For circuits such as the circuit 400, the analysis includes both the case with substrate effects (530) and the case where these effects are eliminated (510). FIG. 5 shows circuits such as circuit 400 have significant robustness to supply voltage variations (and consequently variations in IBIAS), with the exception of the substrate effect. This substrate effect can be a limitation; however, it can be effectively mitigated by using p-type transistors instead of n-type transistors, allowing the source and body to be short-circuited. That is, as shown in FIG. 4, the described or shown NMOS transistors can be replaced with PMOS transistors (or npn transistors replaced with pnp transistors) and vice versa, mutandis mutatis.

[0103] FIG. 6 is a flow-diagram of a method 600 of operating a circuit. For example, the circuit can be a PTAT reference circuit described herein, e. g., the circuit 400 of FIG. 4. The method 600 includes, at 610, generating a first mirror current by a first metal-oxide-semiconductor (MOS) transistor arrangement comprising a first current mirror. Next, at 620, the method 600 includes generating a proportional to absolute temperature reference (PTAT) current by a second MOS transistor arrangement coupled to the first MOS transistor arrangement and comprising a first MOS transistor and second MOS transistor arranged in a cross-coupling configuration so that a gate terminal of the first MOS transistor is electrically coupled to a first terminal of the second MOS transistor, and a gate terminal of the second MOS transistor is electrically coupled to a first terminal of the first transistor. At 630, the method 600 includes generating a discharge current from a discharge circuit, wherein the discharge circuit is electrically coupled to a first node electrically coupled between first MOS transistor arrangement and the second MOS transistor arrangement. At 640, the method includes generating a compensation current, by a compensation circuit, and providing the compensation current to the first2024P01194 P97457

[0104] - 15 -

[0105] MOS transistor arrangement, wherein the compensation current is substantially equal to the discharge current.

[0106] The following examples concern or relate to aspects of the present disclosure.

[0107] Example 1 is a circuit including: a first transistor including a first terminal, a gate terminal, and second terminal, wherein the second terminal is electrically coupled to a reference terminal; a second transistor including a first terminal, a gate terminal, and second terminal, wherein the first terminal of the second transistor is electrically coupled to the gate terminal of the first transistor and the gate terminal of the second transistor is electrically coupled to the first terminal of the first transistor; a third transistor including a first terminal, a gate terminal, and second terminal, wherein the second terminal of the third transistor is electrically coupled to the first terminal of the second transistor;

[0108] a fourth transistor including a first terminal, a gate terminal, and second terminal, wherein the first terminal of the fourth transistor is electrically coupled to a power supply terminal and is further electrically coupled to the gate terminals of the third and fourth transistors; a first resistive element electrically coupled between the second terminal of the second transistor and the reference terminal; and a discharge circuit electrically coupled to a first node, wherein the first node is electrically coupled to the second terminal of the third transistor, the first terminal of the second transistor, and the gate terminal of the first transistor, wherein each of the first, second, third, and fourth transistors is a metal-oxide-semiconductor (MOS) transistor.

[0109] Example 2 is the subject matter of Example 1, wherein the discharge circuit is optionally configured to generate a discharge current from the first node.2024P01194 P97457

[0110] - 16 -

[0111] Example 3 is the subject matter of Example 2, wherein the discharge circuit optionally includes a diode circuit arranged between the first node and the reference terminal.

[0112] Example 4 is the subject matter of Example 3, wherein the diode circuit optionally includes a further transistor including a first terminal, a second terminal, and a gate terminal, and wherein the first terminal of the further transistor is electrically coupled to both the first node and the gate terminal of the further transistor, and wherein the second terminal of the further transistor is electrically coupled to the reference terminal.

[0113] Example 5 is the subject matter of Example 4, which optionally further includes: a compensation circuit configured to provide a current to a first terminal of the third transistor, wherein the provided current is substantially equal to the current caused to be discharged from the first node by the discharge circuit.

[0114] Example 6 is the subject matter of Example 5, wherein the compensation circuit optionally includes: a fifth transistor including a first terminal, a gate terminal, and second terminal, wherein the gate terminal of the fifth transistor is electrically coupled to the gate terminal of further transistor and the second terminal of the fifth transistor is electrically coupled to the reference terminal, a sixth transistor including a first terminal, a gate terminal, and second terminal, wherein the first terminal of the sixth transistor is electrically coupled to the power supply terminal, and the gate terminal of the sixth transistor is electrically coupled to the second terminal of the sixth transistor, a seventh transistor including a first terminal, a gate terminal, and second terminal, wherein the first terminal of the seventh transistor is electrically coupled to the power supply terminal, the gate terminal of the seventh transistor is electrically coupled to the gate terminal of2024P01194 P97457

[0115] 17

[0116] the sixth transistor, and the second terminal of the seventh transistor is electrically coupled to the first terminal of the third transistor.

[0117] Example 7 is the subject matter of Example 6, wherein the compensation circuit further optionally includes: a cascode transistor including a first terminal, a gate terminal, and second terminal, wherein the first terminal of the cascode transistor is electrically coupled to the second terminal of the sixth transistor and the second terminal of the cascode transistor is electrically coupled to a first terminal of the fifth transistor, and the gate terminal is electrically coupled to the gate terminal of the third transistor.

[0118] Example 8 is the subject matter of Example 6 or 7, wherein each of the fifth, sixth, seventh, cascode and further transistors is optionally a metal-oxide-semiconductor (MOS) transistor.

[0119] Example 9 is the subject matter of Example 7, wherein the each of the first, second, third, fourth, fifth, cascade, and further transistors is optionally a NMOS transistor.

[0120] Example 10 is the subject matter of Example 8 or 9, wherein the each of the sixth and seventh transistors is optionally a PMOS transistor.

[0121] Example 11 is the subject matter of any of Examples 1 to 10, wherein the first terminal of the fourth transistor is optionally electrically coupled to the power supply terminal through a resistive element.

[0122] Example 12 is the subject matter of any of Examples 1 to 11, wherein an aspect ratio of the fourth transistor is optionally at least Al times larger than an aspect ratio of the third transistor, wherein an aspect ratio of the second transistor is optionally at least A2 times larger than an aspect ratio2024P01194 P97457

[0123] of the first transistor, wherein Al x A2 > 1, and wherein an aspect ratio of a transistor is defined as the ratio of a width W of the transistor channel to length L of the transistor channel (W / L).

[0124] Example 13 is the subject matter of any of Examples 1 to 12, wherein the reference terminal is optionally a ground terminal.

[0125] Example 14 is the subject matter of any of Examples 1 to 13, wherein the circuit is optionally configured to provide a reference current at an output node, and wherein the output node is electrically coupled to the second terminal of the seventh transistor and is electrically coupled to the first terminal of the third transistor.

[0126] Example 15 is the subject matter of Example 14, wherein the reference current is proportional to absolute temperature.

[0127] Example 1A is a circuit including a first metal-oxide-semiconductor (MOS) transistor arrangement comprising a first current mirror configured to generate at least a first mirror current; a second MOS transistor arrangement coupled to the first MOS transistor arrangement and comprising a first MOS transistor and second MOS transistor arranged in a crosscoupling configuration so that a gate terminal of the first MOS transistor is electrically coupled to a first terminal of the second MOS transistor, and a gate terminal of the second MOS transistor is electrically coupled to a first terminal of the first transistor; and a discharge circuit electrically coupled to a first node and configured to generate a discharge current from the first node, wherein the first node is electrically coupled between first MOS transistor arrangement and the second MOS transistor arrangement.

[0128] Example 2A is the subject matter of Example 1A, wherein the discharge circuit optionally includes a further MOS2024P01194 P97457

[0129] transistor, and wherein a first terminal of the further MOS transistor is optionally electrically coupled to the first node and is electrically coupled to the gate terminal of the further MOS transistor.

[0130] Example 3A is the subject matter of Example 1A or 2A, which optionally further includes a compensation circuit configured to provide a current to the first MOS transistor arrangement, wherein the provided current is substantially equal to the discharge current.

[0131] Example 4A is the subject matter of any of Examples 1A to 3A, wherein optionally the first current mirror optionally includes a third MOS transistor and a fourth MOS transistor, a second terminal of the third MOS transistor is electrically coupled to the first node and to the first terminal of the second MOS transistor, the fourth MOS transistor is arranged in a diode configuration so that a gate terminal of the fourth MOS transistor is electrically coupled to a gate terminal of the third MOS transistor, and a second terminal of the fourth MOS transistor is electrically coupled to a first terminal of the first MOS transistor.

[0132] Example 5A is the subject matter of Example 4A, wherein the compensation circuit optionally includes: a fifth MOS transistor configured to generate a current that mirrors the discharge current, a second mirror electrically coupled to the third MOS transistor and further coupled to the fifth MOS transistor, wherein the second mirror is configured to provide a current to the third MOS transistor.

[0133] Example 6A is the subject matter of Example 5A, wherein the compensation circuit optionally further includes a cascode transistor, wherein the second mirror is electrically connected to the fifth MOS transistor through the cascode transistor.2024P01194 P97457

[0134] - 20 -

[0135] Example 7A is the subject matter of Example 5A or 6A, wherein the second mirror optionally includes a sixth MOS transistor and seventh MOS transistor.

[0136] Example 8A is the subject matter of Example 7A, wherein the each of the first, second, third, fourth, fifth, cascade, and further transistors optionally is a NMOS transistor.

[0137] Example 9A is the subject matter of Example 8A, wherein the each of the sixth and seventh transistors is optionally a PMOS transistor.

[0138] Example 10A is the subject matter of Example 1A to 9A, wherein the circuit is optionally configured to provide a reference current at an output node electrically coupled to the first current mirror.

[0139] Example 11A is the subject matter of Example 10A, wherein the reference current is proportional to absolute temperature.

[0140] Example 12A is the subject matter of Example 6A, wherein the cascode transistor is a MOS transistor.

[0141] Example IB is a method for operating circuit including: generating a first mirror current by a first metal-oxide-semiconductor (MOS) transistor arrangement comprising a first current mirror;

[0142] generating a proportional to absolute temperature reference circuit by a second MOS transistor arrangement coupled to the first MOS transistor arrangement and comprising a first MOS transistor and second MOS transistor arranged in a crosscoupling configuration so that a gate terminal of the first MOS transistor is electrically coupled to a first terminal of the second MOS transistor, and a gate terminal of the second MOS transistor is electrically coupled to a first terminal of the first transistor;2024P01194 P97457

[0143] - 21 -

[0144] generating a discharge current from a discharge circuit, wherein the discharge circuit is electrically coupled to a first node electrically coupled between first MOS transistor arrangement and the second MOS transistor arrangement.

[0145] Example 2B is the subject matter of Example IB, further including generating a compensation current, by a compensation circuit, and providing the compensation current to the first MOS transistor arrangement, wherein the compensation current is substantially equal to the discharge current.

[0146] Any of the aspects, examples, and / or embodiments described herein may be suitable or appropriately combined including combined with the embodiments or examples described herein.

[0147] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any example or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other examples or designs.

[0148] For the purposes of the present disclosure, the phrase " A and / or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase " A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0149] Reference to "one embodiment" or "an embodiment" in the present disclosure means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The appearances of the phrase "in one embodiment" or "in an embodiment" are not necessarily all referring to the same embodiment. The appearances of the phrase "for example, " "in an example, " or "in some examples" are not necessarily all referring to the same example.2024P01194 P97457

[0150] The words "plurality" and "multiple" in the description or the claims expressly refer to a quantity greater than one. The terms "group ( of ) ", " set [ of ] ", "collection ( of ) ", " series (of ) ", " sequence ( of ) ", "grouping ( of ) ", etc., and the like in the description or in the claims refer to a quantity equal to or greater than one, i. e. one or more. Any term expressed in plural form that does not expressly state "plurality" or "multiple" likewise refers to a quantity equal to or greater than one.

[0151] The term "connected" or "coupled" can be understood in the sense of a ( e. g. mechanical, optical and / or electrical ), e. g. direct or indirect, connection and / or interaction. For example, several elements can be connected together mechanically such that they are physically retained ( e. g., a plug connected to a socket ) and electrically such that they have an electrically conductive path ( e. g., signal paths exist along a communicative chain).

[0152] As used herein, unless otherwise specified the use of the ordinal adjectives " first", " second", "third" etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner.

[0153] As utilized herein, terms "module", " component, " " system, " "circuit, " " element, " " slice, " " circuitry, " and the like are intended to refer to a set of one or more electronic components, a computer-related entity, hardware, software ( e. g., in execution), and / or firmware. For example, circuitry or a similar term can be a processor, a process running on a processor, a controller, an object, an executable program, a storage device, and / or a computer with a processing device. By way of illustration, an application running on a server and the server can also be circuitry. One or more circuits2024P01194 P97457

[0154] can reside within the same circuitry, and circuitry can be localized on one computer and / or distributed between two or more computers. A set of elements or a set of other circuits can be described herein, in which the term "set" can be interpreted as "one or more. "

[0155] Such electric or electronic circuitry can be operated by a software application or a firmware application executed by one or more processors. The one or more processors can be internal or external to the apparatus and can execute at least a part of the software or firmware application. As yet another example, circuitry can be an apparatus that provides specific functionality through electronic components without mechanical parts; the electronic components can include one or more processors therein to execute executable instructions stored in computer readable storage medium and / or firmware that confer (s), at least in part, the functionality of the electronic components. As another example, circuitry or similar term can be implemented in hardware such as application specific integrated circuit (ASIC), programmable gate array (PGA), discrete digital circuits, etc. ) or in a combination of hardware and software (e. g., a software model executed by a corresponding processor).

[0156] The term "semiconductor substrate" can mean any construction comprising semiconductor material, for example, a silicon substrate with or without an epitaxial layer, a silicon-on-insulator substrate containing a buried insulator layer, or a substrate with a silicon germanium layer.

[0157] A lateral direction is understood to mean a direction that runs, in particular, parallel to a main extension surface of the component, in particular of a layer. A vertical direction is understood to mean a direction that is oriented, in particular, perpendicular to the main extension surface of the component and / or layer. The vertical direction and the lateral direction are approximately orthogonal to each other.2024P01194 P97457

[0158] Further, spatially relative terms, such as "beneath, " "below, " "lower, " "above, " "upper" and the like, may be used herein for ease of description to describe one element or feature ' s relationship to another element (s) or feature (s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0159] The term "data" as used herein may be understood to include information in any suitable analog or digital form, e. g., provided as a file, a portion of a file, a set of files, a signal or stream, a portion of a signal or stream, a set of signals or streams, and the like. Further, the term "data" may also be used to mean a reference to information, e. g., in form of a pointer. The term data, however, is not limited to the aforementioned examples and may take various forms and represent any information as understood in the art.

[0160] As used herein, a signal that is "indicative of" a value or other information may be a digital or analog signal that encodes or otherwise communicates the value or other information in a manner that can be decoded by and / or cause a responsive action in a component receiving the signal. The signal may be stored or buffered in computer readable storage medium prior to its receipt by the receiving component and the receiving component may retrieve the signal from the storage medium. Further, a "value" that is "indicative of" some quantity, state, or parameter may be physically embodied as a digital signal, an analog signal, or stored bits that encode or otherwise communicate the value.2024P01194 P97457

[0161] 25

[0162] Unless otherwise stated, the words "about" and "substantially" as used herein are to be construed as meaning the normal measuring and / or fabrication limitations related to the value or condition which the word "about" or "substantially" modifies. Unless expressly stated otherwise, the term "embodiment" is used herein to mean an embodiment of the present disclosure.

[0163] As used herein, a signal may be transmitted or conducted through a signal chain in which the signal is processed to change characteristics such as phase, amplitude, frequency, and so on. The signal may be referred to as the same signal even as such characteristics are adapted. In general, so long as a signal continues to encode the same information, the signal may be considered as the same signal. For example, a transmit signal may be considered as referring to the transmit signal in baseband, intermediate, and radio frequencies.

[0164] While the above descriptions and connected figures may depict device components as separate elements, skilled persons will appreciate the various possibilities to combine or integrate discrete features, functions into a single element. Such may include combining two or more components into a single component. Conversely, skilled persons will recognize the possibility to separate a single element into two or more discrete elements, such as splitting a single component into two or more separate components.

[0165] It is appreciated that implementations of methods detailed herein are exemplary in nature, and are thus understood as capable of being implemented in a corresponding device. Likewise, it is appreciated that implementations of devices detailed herein are understood as capable of being implemented as a corresponding method. It is thus understood that a device corresponding to a method detailed herein may include one or more components configured to perform each aspect of the related method.2024P01194 P97457

[0166] 26

[0167] All acronyms defined in the above description additionally hold in all claims included herein.

[0168] While embodiments of the present disclosure have been described above, it is obvious that further embodiments may be implemented. For example, further embodiments may comprise any subcombination of features recited in the claims or any subcombination of elements described in the examples given above. Accordingly, this spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

[0169] While the disclosure has been particularly shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the disclosure as defined by the appended claims. The scope of the disclosure is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced.2024P01194 P97457

[0170] 27

[0171] Reference Numeral List

[0172] 100a PTAT reference circuit / generator

[0173] 100b PTAT reference circuit / generator

[0174] 200 PTAT reference circuit / generator

[0175] 300 PTAT reference circuit / generator

[0176] 400 PTAT reference circuit / generator

[0177] 410 discharge circuit

[0178] 420 compensation circuit

[0179] 500 graph

[0180] 510-530 plots

[0181] 600 method

[0182] 610-640 method steps

[0183] IBIAS biasing current

[0184] IQU output current

[0185] I PT PTAT current

[0186] OUT node

[0187] Pl, P2, QI, Q2, Q3, Q4, Ml, M2, M3, M4, M5, Md, MCAS transistors R resistor

[0188] Vcas biasing voltage

[0189] Vdd power supply

[0190] Vy node

Claims

2024P01194 P9745728CLAIMS1. A circuit comprising:a first transistor including a first terminal, a gate terminal, and second terminal, wherein the second terminal is electrically coupled to a reference terminal;a second transistor including a first terminal, a gate terminal, and second terminal, wherein the first terminal of the second transistor is electrically coupled to the gate terminal of the first transistor and the gate terminal of the second transistor is electrically coupled to the first terminal of the first transistor;a third transistor including a first terminal, a gate terminal, and second terminal, wherein the second terminal of the third transistor is electrically coupled to the first terminal of the second transistor;a fourth transistor including a first terminal, a gate terminal, and second terminal, wherein the first terminal of the fourth transistor is electrically coupled to a power supply terminal and is further electrically coupled to the gate terminals of the third and fourth transistors;a first resistive element electrically coupled between the second terminal of the second transistor and the reference terminal; anda discharge circuit electrically coupled to a first node, wherein the first node is electrically coupled to the second terminal of the third transistor, the first terminal of the second transistor, and the gate terminal of the first transistor,wherein each of the first, second, third, and fourth transistors is a metal-oxide-semiconductor (MOS) transistor.

2. The circuit of claim 1,wherein the discharge circuit is configured to generate a discharge current from the first node.2024P01194 P97457293. The circuit of claim 2,wherein the discharge circuit comprises a diode circuit arranged between the first node and the reference terminal.

4. The circuit of claim 3,wherein the diode circuit comprises a further transistor including a first terminal, a second terminal, and a gate terminal, andwherein the first terminal of the further transistor is electrically coupled to both the first node and the gate terminal of the further transistor, andwherein the second terminal of the further transistor is electrically coupled to the reference terminal.

5. The circuit of claim 4, further comprising:a compensation circuit configured to provide a current to a first terminal of the third transistor, wherein the provided current is substantially equal to the current caused to be discharged from the first node by the discharge circuit.

6. The circuit of claim 5,wherein the compensation circuit comprises:a fifth transistor including a first terminal, a gate terminal, and second terminal,wherein the gate terminal of the fifth transistor is electrically coupled to the gate terminal of further transistor and the second terminal of the fifth transistor is electrically coupled to the reference terminal, a sixth transistor including a first terminal, a gate terminal, and second terminal,wherein the first terminal of the sixth transistor is electrically coupled to the power supply terminal, and the gate terminal of the sixth transistor is electrically coupled to the second terminal of the sixth transistor, a seventh transistor including a first terminal, a gate terminal, and second terminal,2024P01194 P9745730wherein the first terminal of the seventh transistor is electrically coupled to the power supply terminal, the gate terminal of the seventh transistor is electrically coupled to the gate terminal of the sixth transistor, and the second terminal of the seventh transistor is electrically coupled to the first terminal of the third transistor.

7. The circuit of claim 6,wherein the compensation circuit further comprises:a cascode transistor including a first terminal, a gate terminal, and second terminal,wherein the first terminal of the cascode transistor is electrically coupled to the second terminal of the sixth transistor and the second terminal of the cascode transistor is electrically coupled to a first terminal of the fifth transistor, and the gate terminal is electrically coupled to the gate terminal of the third transistor.

8. The circuit of claim 6 or 7,wherein each of the fifth, sixth, seventh, cascode and further transistors is a metal-oxide-semiconductor (MOS) transistor.

9. The circuit of claim 7,wherein the each of the first, second, third, fourth, fifth, cascade, and further transistors is a NMOS transistor.

10. The circuit of claim 8 or 9,wherein the each of the sixth and seventh transistors is a PMOS transistor.

11. The circuit of any of claims 1 to 10,wherein an aspect ratio of the fourth transistor is at least Al times larger than an aspect ratio of the third transistor,2024P01194 P97457wherein an aspect ratio of the second transistor is at least A2 times larger than an aspect ratio of the first transistor, wherein Al x A2 > 1, andwherein an aspect ratio of a transistor is defined as the ratio of a width EV of the transistor channel to length L of the transistor channel ( EV / 1,).

12. The circuit of any of claims 1 to 11,wherein the circuit is configured to provide a reference current at an output node, and wherein the output node is electrically coupled to the second terminal of the seventh transistor and is electrically coupled to the first terminal of the third transistor.

13. The circuit of claim 12, wherein the reference current is proportional to absolute temperature.

14. A circuit comprising:a first metal-oxide-semiconductor (MOS) transistor arrangement comprising a first current mirror configured to generate at least a first mirror current;a second MOS transistor arrangement coupled to the first MOS transistor arrangement and comprising a first MOS transistor and second MOS transistor arranged in a crosscoupling configuration so that a gate terminal of the first MOS transistor is electrically coupled to a first terminal of the second MOS transistor, and a gate terminal of the second MOS transistor is electrically coupled to a first terminal of the first transistor; anda discharge circuit electrically coupled to a first node and configured to generate a discharge current from the first node, wherein the first node is electrically coupled between first MOS transistor arrangement and the second MOS transistor arrangement.2024P01194 P97457- 32 -15. The circuit of claim 14,wherein the discharge circuit comprises a further MOS transistor, andwherein a first terminal of the further MOS transistor is electrically coupled to the first node and is electrically coupled to the gate terminal of the further MOS transistor.

16. The circuit of claim 14 or 15, further comprisinga compensation circuit configured to provide a current to the first MOS transistor arrangement, wherein the provided current is substantially equal to the discharge current.

17. The circuit of any of claims 14 to 16,wherein the first current mirror comprises a third MOS transistor and a fourth MOS transistor,wherein a second terminal of the third MOS transistor is electrically coupled to the first node and to the first terminal of the second MOS transistor,wherein the fourth MOS transistor is arranged in a diode configuration so that a gate terminal of the fourth MOS transistor is electrically coupled to a gate terminal of the third MOS transistor, and a second terminal of the fourth MOS transistor is electrically coupled to a first terminal of the first MOS transistor.

18. The circuit of claim 17,wherein the compensation circuit comprises:a fifth MOS transistor configured to generate a current that mirrors the discharge current,a second mirror electrically coupled to the third MOS transistor and further coupled to the fifth MOS transistor, wherein the second mirror is configured to provide a current to the third MOS transistor.

19. The circuit of claim 18,wherein the compensation circuit further comprises a cascode transistor, wherein the second mirror is electrically2024P01194 P9745733connected to the fifth MOS transistor through the cascode transistor.

20. A method for operating circuit comprising:generating a first mirror current by a first metal-oxide-semiconductor (MOS) transistor arrangement comprising a first current mirror;generating a proportional to absolute temperature reference circuit by a second MOS transistor arrangement coupled to the first MOS transistor arrangement and comprising a first MOS transistor and second MOS transistor arranged in a cross-coupling configuration so that a gate terminal of the first MOS transistor is electrically coupled to a first terminal of the second MOS transistor, and a gate terminal of the second MOS transistor is electrically coupled to a first terminal of the first transistor; andgenerating a discharge current from a discharge circuit, wherein the discharge circuit is electrically coupled to a first node electrically coupled between first MOS transistor arrangement and the second MOS transistor arrangement.

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