Device and method for dynamically switching semiconductor switches of an inverter
By dividing semiconductor switches into parallel units and controlling their sequential activation with controlled dead times, the energy losses and inefficiencies associated with high-frequency switching in inverters are mitigated, improving the efficiency of electric drive systems.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- ROBERT BOSCH GMBH
- Filing Date
- 2026-01-08
- Publication Date
- 2026-07-23
AI Technical Summary
Switching semiconductor switches in inverters results in energy losses due to high switching frequencies, leading to inefficiency and component heating, particularly in electrically powered systems like electric vehicles.
The semiconductor switches are divided into multiple parallel switches, which are sequentially switched on and off with controlled dead times to reduce energy losses and improve efficiency.
This approach reduces energy losses by up to 0.95% and decreases switching times, enhancing the overall efficiency of the inverter system.
Smart Images
Figure EP2026050258_23072026_PF_FP_ABST
Abstract
Description
[0001] R. 415288
[0002] - 1 -
[0003] Description
[0004] title
[0005] Device and method for dynamically switching semiconductor switches of an inverter
[0006] The invention relates to a device with an inverter and a control device for dynamically switching a semiconductor switch of the inverter, as well as a method for dynamically switching the semiconductor switch.
[0007] State of the art
[0008] Electrically powered systems, such as electric vehicles, feature high-performance circuit components in the drive system between an energy source, such as a traction battery, and an electric motor. These circuit components include an inverter, which is configured to transfer electrical energy from the energy source to the electric motor.
[0009] The inverter can use a power semiconductor such as a silicon carbide transistor (SiC transistor), an IGBT (insulated gate bipolar transistor) with an antiparallel diode, a MOSFET (metal oxide field-effect transistor), or a high electron mobility transistor (HEMT) based on gallium nitride (GaN) to control the transfer of electrical energy to the electric machine.
[0010] Switching power semiconductors on and / or off can result in energy losses due to the switching and conduction of current through the semiconductor. These energy losses reduce efficiency and, especially at higher switching frequencies, can cause the power semiconductor and other components to heat up. R. 415288
[0011] - 2 -
[0012] It would therefore be desirable to reduce the energy losses when switching semiconductor switches.
[0013] For power semiconductors with a wide bandgap, an increase in clock frequency and a shortening of switching edges are particularly desirable, while overshooting and / or undershooting must be avoided and oscillations suppressed.
[0014] Disclosure of the invention
[0015] The invention provides a device with an inverter and a control device for dynamically switching a semiconductor switch of the inverter, as well as a method for dynamically switching the semiconductor switches with the features of the independent claims.
[0016] Preferred embodiments are the subject of the respective dependent claims.
[0017] According to a first aspect, the invention relates to an inverter with a semiconductor switch, wherein the semiconductor switch comprises: a high-side switch, HS switch; and a low-side switch, LS switch; wherein the LS switch is divided into several parallel LS switches and is configured to sequentially switch on the several parallel LS switches.
[0018] According to a further development, the multiple parallel circuit breakers comprise a first circuit breaker and a second circuit breaker, wherein: the first circuit breaker has a first channel resistance; the second circuit breaker has a second channel resistance; and the first channel resistance and the second channel resistance are equal or different.
[0019] According to a further development, the multiple parallel circuit breakers comprise a first circuit breaker and a second circuit breaker, wherein: the first circuit breaker has a first output capacitance; the second circuit breaker has a second output capacitance; and the first output capacitance and the second output capacitance are equal or different.
[0020] According to further training, the first circuit breaker has a gate width in the range of 5 to 35 mm, and the second circuit breaker also has a gate width in the range of 5 to 35 mm. R. 415288
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[0022] According to further training, the LS switch has a gate width such that the ratio of load current to gate width is 5mA per mm gate width.
[0023] According to a further training, the sequential switching on of several parallel circuit breakers includes: switching off the main breaker; waiting during a first dead time; switching on the first circuit breaker while the second circuit breaker remains off; waiting during a second dead time; and switching on the second circuit breaker while the first circuit breaker remains on.
[0024] According to a further development, the multiple parallel LS switches include a third LS switch, wherein: the third LS switch has a third channel resistance that is different from both the first channel resistance and the second channel resistance; and / or the third LS switch has a third output capacitance that is different from both the first output capacitance and the second output capacitance.
[0025] According to further training, the sequential switching on of several parallel circuit breakers includes: switching off the main circuit breaker; waiting during a first dead time; switching on the first circuit breaker while the second circuit breaker and / or the third circuit breaker remain off; waiting during a second dead time; switching on the second circuit breaker and / or the third circuit breaker while the first circuit breaker remains on; waiting during a third dead time; and switching on the third circuit breaker while the first circuit breaker and / or the second circuit breaker remain on.
[0026] According to a second aspect, the invention relates to a method for controlling an inverter as described above, wherein the method comprises: switching off the high-voltage switch; waiting during a first dead time; switching on the first low-voltage switch while the second low-voltage switch remains off; waiting during a second dead time; switching on the second low-voltage switch while the first low-voltage switch remains on.
[0027] According to a third aspect, the invention relates to a device comprising: a processor; an inverter as described above; and a non-volatile, computer-readable storage medium containing code stored thereon. 415288
[0028] - 4 -
[0029] includes a process which, when executed by the processor, causes the processor to perform the procedure as described above.
[0030] Brief description of the drawings
[0031] They show:
[0032] Fig. 1 shows a schematic representation of an electric drive system with an electrically operated machine and a control device for controlling a semiconductor switch according to an exemplary embodiment of the invention;
[0033] Fig. 2 shows a schematic representation of a part of an electric drive system according to an exemplary embodiment of the invention;
[0034] Fig. 3 shows a schematic representation of a half-bridge with a low-side switch (LS switch) divided into several switches according to an exemplary embodiment of the invention;
[0035] Fig. 4 Voltages and currents across a low-side switch split into two switches during dynamic switching of the low-side switch;
[0036] Fig. 5 Capacitance of the switching node equivalent during conventional switching on of a low-side switch (dashed line) and during dynamic switching of a low-side switch split into two switches (solid line);
[0037] Fig. 6 Power loss when conventionally switching on a low-side switch (dashed line) and when dynamically switching a low-side switch divided into two switches (solid line);
[0038] Fig. 7 Voltages and currents across a low-side switch divided into three switches with different channel resistances during dynamic switching of the low-side switch;
[0039] Fig. 8 Energy loss during conventional switching on of a low-side switch (dashed line) and during dynamic switching of a low-side switch divided into three switches (solid line); R.415288
[0040] - 5 -
[0041] Fig. 9 Power loss due to conduction (top) and switching (bottom) as a function of load current and gate width at four different temperatures TG{-40;25;85, 175}°C; and
[0042] Fig. 10 shows a method for dynamically switching a low-side switch divided into several switches.
[0043] In all figures, identical or functionally equivalent elements and devices are designated with the same reference numerals. The numbering of process steps serves for clarity and generally does not imply a specific chronological order. In particular, several process steps can be performed simultaneously.
[0044] Description of the exemplary implementations
[0045] Fig. 1 shows a schematic representation of an electric drive system 100 with an electrically driven machine 130. The electric drive system 100 comprises two input terminals VDD and VSS, which can be supplied, for example, by an energy storage device such as a high-voltage battery or a traction battery. In this example, the input terminals VDD and VSS are connected to a DC link, which includes a DC link capacitor 110. The DC link capacitor 110 is connected via output terminals to the input terminals of an inverter 120. The DC link inverter with the DC link capacitor 110 and the inverter 120 shown in Fig. 1 is depicted as three-phase by way of example. Each of the three phases is connected to the electric machine 130. The inverter 120 can also have only one phase, two phases, or more than three phases.
[0046] The inverter 120 shown in Fig. 1 comprises three bridge branches, each with two semiconductor switches 121. The first bridge branch includes the semiconductor switches 121 connected to the first phase of the electric machine 130. The second bridge branch includes the semiconductor switches 121 connected to the second phase of the electric machine 130. The third bridge branch includes the semiconductor switches 121 connected to the third phase of the electric machine 130. R.415288
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[0048] The semiconductor switches 121 on one side of the bridge are called high-side switches (HS switches). The semiconductor switches 121 on the other side of the bridge are called low-side switches (LS switches). Any other number of bridge branches is also possible, e.g., one bridge branch, two bridge branches, or more than three bridge branches.
[0049] The semiconductor switches 121 shown in Fig. 1 can be used, for example, to
[0050] The semiconductor switches 121 include field-effect transistors (FETs). In one example, they comprise one or more SiC transistors, IGBTs, MOSFETs, and high-electron mobility transistors (HEMTs) based on gallium nitride (GaN). A diode may be connected antiparallel to each transistor.
[0051] The electric drive system 100 shown in Fig. 1 further comprises a control unit 150, which is designed to generate switching signals 153 containing information to control semiconductor switches 121 based on an operating point of the system. The control unit 150 may include a microprocessor 151 and / or safety logic 152.
[0052] The control unit 150 feeds the switching signals 153 into corresponding control devices 140, each configured to control one of the semiconductor switches 121. The switching signals 153 can be transmitted via a single line, e.g., UART only, or via multiple lines, e.g., UART and NABE.
[0053] The control devices 140 can each comprise logic, e.g., a microprocessor. The respective logic can be configured to control the semiconductor circuit coupled to it. The control can be based on the switching signals 153. The control can, for example, define the gate drive voltage.
[0054] The coupling of a control device 140 with a semiconductor switch 121 is described below. The other control devices, if present, can be coupled analogously with a different semiconductor switch, as shown in Fig. 1.
[0055] The control device 140 has a control output, which sends a control signal 141 to a control input of the semiconductor switch 121. R. 415288
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[0057] The control device 140 can be used to control the semiconductor switch 121. The control device 140 can receive measurement signals from the semiconductor switch 121. The measurement signal 122 can, for example, indicate an instantaneous current through the semiconductor switch 121. For this purpose, the measuring line through which the measurement signal 122 is acquired can, for example, be coupled to a current measurement output of the semiconductor switch 121. The measurement signal 123 can indicate an instantaneous voltage at a connection terminal of the semiconductor switch 121.
[0058] Fig. 2 shows a schematic representation of part 200 of an electric drive system of a vehicle according to an embodiment of the invention. This electric drive system can be the same as, or different from, the electric drive system 100 shown in Fig. 1. The drive system of Fig. 2 has three phases, which are graphically represented by a staggered arrangement of the frames. A different number of phases is also possible. Only the components of the first phase are shown, while the analogous components of the other phases are only indicated by the staggered arrangement.
[0059] The control unit 250 can be a processor or comprise multiple processors. The control unit 250 has connections to each of the control devices 240. These connections can each have two channels: one for a communication interface (UART) and one for a PWM control signal. Alternatively, there can be only one UART connection. Information regarding the activation of the semiconductor switches 221 can be transmitted to the corresponding control devices 240 via the communication interface (UART).
[0060] Fig. 3 shows a schematic representation of a half-bridge, 321 (HS) and 321 (LS), of an inverter with an LS switch 321 (LS) divided into several switches 321-1 (LS) to 321-3 (LS) according to an exemplary embodiment of the invention. The LS switch can also be divided into 2, 4, 8, 16, ..., 1024 LS switches. Each switch, e.g., 321-1, comprises a transistor with a channel resistance R and an output capacitance C. In the example shown, the resistances R1 to R3 and the capacitances C1 to C3 thus represent the channel resistances and output capacitances of the individual transistors T1 to T3.
[0061] The HS switch 321 (HS) is coupled to VDD. The LS switch 321 (LS) is coupled to VSS. R. 415288
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[0063] Fig. 4 shows voltages and currents across a low-side switch LS, divided into two switches, LS1 and LS2, during dynamic switching of the low-side switch LS, while Fig. 5 shows the capacitance of a switching node equivalent during conventional switching of a low-side switch (dashed line) and during dynamic switching of the low-side switch divided into two switches (solid line). By dividing the LS switch into two parallel switches, LS1 and LS2, the capacitance of the switching node equivalent can be modulated during the switching on of the LS switch. Therefore, shorter dead times are required after the switching off of the high-side switch and the switching on of the LS switch.A sequence may include switching off an HS switch; waiting during a first dead time; switching on a first LS switch LS1 while a second LS switch LS2 remains off; waiting during a second dead time; and switching on the second LS switch LS2 while the first LS switch LS1 remains on.
[0064] Fig. 6 shows the power loss during the conventional switching on of a low-side switch (dashed line) and during the dynamic switching of a low-side switch divided into two switches (solid line) as described with reference to Figs. 4 and 5. By dividing the switch into several smaller switches and switching them on sequentially, the energy loss during the switching on of the low-side switch can be reduced.
[0065] In the example shown in Fig. 6, the energy loss in the case of a non-parallelized switch is 60.3nJ compared to 58.4nJ in the case of a parallelized switch LS1 and LS2.
[0066] In comparison to a dead time of 3.75ns in the case of a non-parallelized switch LS, a dead time of 3ns is realized in the case of a parallelized switch LS1 and LS2.
[0067] Due to the lower equivalent output capacitance, a shorter dead time is required because the output capacitance discharges faster at a fixed load current. Compared to a conventional non-parallelized switch with an efficiency of 95%, the efficiency of a parallelized switch is increased by 0.95% to approximately 96%. R.415288
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[0069] Figure 7 shows voltages and currents across a low-side switch divided into three switches with different channel resistances during dynamic switching of the low-side switch. By dividing the switch into several smaller switches and turning them on sequentially, the channel resistance of the switch can be modulated. The gate widths of the individual low-side switches can be the same or different. The gate width of a first switch, LS1, can be, for example, 5, 10, 15, 20, 25, 30, or 35 mm. The gate width of a second switch, LS2, can be, for example, 5, 10, 15, 20, 25, 30, or 35 mm, and so on. The sum of the gate widths of the several parallelized switches can be 5, 10, 15, 20, 25, 30, or 35 mm.
[0070] Figure 8 shows the energy loss during the conventional switching on of a low-side circuit breaker (dashed line) and during the dynamic switching of a low-side circuit breaker divided into three switches (solid line). The energy loss increases with increasing dead time. This is due to the longer time the circuit breaker spends in reverse diode conduction mode. This conduction mode leads to significant losses, depending on the dead time and load current. By segmenting the circuit breaker into smaller segments that are switched on sequentially, the energy loss decreases.
[0071] Without considering the physical units, the energy loss of a non-parallelized switch LS is given by the equation
[0072] AE At) / nJ = 5.738321 t / ns + 37.453
[0073] Given that in the case of several parallel switches, the energy loss is given by the equation
[0074] AE At) / nJ = 4.1215At / ns + 36.848
[0075] As shown in Fig. 8, the energy loss is reduced for the same dead time. The reduced dead time of the parallel switch further reduces the energy loss.
[0076] Fig. 9 shows the power loss due to conduction (top) and switching (bottom) as a function of load current and gate width at four different temperatures TG{-40;25;85, 175}°C. As shown in Fig. 9, there is an optimum between the active region of the circuit breaker and the load current. The optimum R.415288
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[0078] In the example shown, the gate width is located at the intersection of all planes and is given by 5 mA / mm gate width in this case. For optimal efficiency, the power switches should be designed so that the switching losses equal the line losses.
[0079] Fig. 10 shows a schematic representation of an exemplary method 1000 for controlling an inverter with a semiconductor switch comprising an HS switch and an LS switch.
[0080] In step 1010, procedure 1000 can include switching off the HS switch.
[0081] Step 1020 of procedure 1000 can include waiting during an initial dead time. Step 1020 can occur after step 1010.
[0082] In step 1030, procedure 1000 can include switching on a first circuit breaker LS1 while a second circuit breaker LS2 remains off. Step 1030 can occur after step 1020.
[0083] Step 1040 in procedure 1000 can include waiting during a second dead time. Step 1040 can occur after step 1030.
[0084] In step 1050, procedure 1000 can include switching on the second circuit breaker LS2 while the first circuit breaker LS1 remains switched on. Step 1050 can occur after step 1040.
Claims
R. 415288 - 11 - Claims 1. Inverter (120; 220) with a semiconductor switch (121 ; 221 , 321), wherein the semiconductor switch (121 ; 221 , 321) comprises: a high-side switch, HS switch (321 (HS)); and a low-side switch, LS switch (321 (LS)); wherein the circuit breaker (321 (LS)) is divided into several parallel circuit breakers (321 -1 (LS), 321 -2 (LS), 321 -3 (LS)) and is configured to sequentially switch on the several parallel circuit breakers (321-1 (LS), 321 -2 (LS), 321 -3 (LS)).
2. Inverter (120; 220) according to claim 1, wherein the multiple parallel circuit breakers (321-1 (CB), 321-2 (CB), 321-3 (CB)) comprise a first circuit breaker (321-1 (CB)) and a second circuit breaker (321-2 (CB)), wherein: the first LS switch (321-1 (LS)) has a first channel resistance; the second LS switch (321-2 (LS)) has a second channel resistance; and the first channel resistance and the second channel resistance are the same or different.
3. Inverter (120; 220) according to claim 1, wherein the multiple parallel circuit breakers (321-1 (CB), 321-2 (CB), 321-3 (CB)) comprise a first circuit breaker (321-1 (CB)) and a second circuit breaker (321-2 (CB)), wherein: the first circuit breaker (321 -1 (LS)) has a first output capacitance; the second LS switch (321-2 (LS)) has a second output capacitance; and The first output capacity and the second output capacity are the same or different. R.415288 - 12 - 4. Inverter (120; 220) according to any one of claims 2 to 3, wherein the first circuit breaker (321-1 (LS)) has a gate width in the range between 5 and 35 mm and the second circuit breaker (321-2 (LS)) has a gate width in the range between 5 and 35 mm.
5. Inverter (120; 220) according to any one of claims 1 to 4, wherein the circuit breaker (321) has a gate width such that the ratio of load current to gate width is 5mA per mm gate width.
6. Inverter (120; 220) according to any one of claims 2 to 5, comprising the sequential switching on of the multiple parallel circuit breakers (321-1 (CB), 321-2 (CB), 321-3 (CB)): Switching off the HS switch (321 (HS)); Waiting during an initial period of inactivity; Switching on the first circuit breaker (321-2 (LS)) while the second circuit breaker (321-2 (LS)) remains switched off; Waiting during a second dead time; Switching on the second circuit breaker (321-2 (LS)) while the first circuit breaker (321-1 (LS)) remains switched on.
7. Inverter (120; 220) according to any one of claims 2 to 6, wherein the multiple parallel circuit breakers (321-1 (CB), 321-2 (CB), 321-3 (CB)) comprise a third circuit breaker (321-3 (CB)), wherein: the third LS switch (321-3 (LS)) has a third channel resistance that is different from both the first channel resistance and the second channel resistance; and / or the third LS switch (321-3 (LS)) has a third output capacitance that is different from both the first output capacitance and the second output capacitance.
8. Inverter (120; 220) according to claim 6 or 7, comprising the sequential switching on of the multiple parallel circuit breakers (321-1 (CB), 321-2 (CB), 321-3 (CB)): Switching off the HS switch (321 (HS)); Waiting during an initial period of inactivity; Switching on the first circuit breaker (321-2 (LS)) while the second circuit breaker (321-2 (LS)) and / or the third circuit breaker (321-3 (LS)) remain switched off; R.415288 - 13 - Waiting during a second dead time; Switching on the second circuit breaker (321-2 (LS)) and / or the third circuit breaker (321-3 (LS)) while the first circuit breaker (321-1 (LS)) remains switched on; Waiting during a third dead time; Switching on the third circuit breaker (321-3 (LS)) while the first circuit breaker (321-1 (LS)) and / or the second circuit breaker (321-2 (LS)) remain switched on.
9. Method (1000) for controlling an inverter (120; 220) according to any one of claims 1 to 8, wherein the method (1000) comprises: Switching off (1010) the HS switch (321 (HS)); Waiting (1020) during an initial dead time; Switching on (1030) of the first circuit breaker (321-2 (LS)) while the second circuit breaker (321-2 (LS)) remains switched off; Waiting (1040) during a second dead time; Switching on (1050) the second circuit breaker (321-2 (LS)) while the first circuit breaker (321-1 (LS)) remains switched on.
10. Device (100) comprising: a processor; an inverter (120; 220) according to any one of claims 1 to 8; and a non-volatile, computer-readable storage medium comprising code stored thereon which, when executed by the processor, causes the processor to perform the method according to claim 9.