Method for manufacturing a semiconductor device

Abstract

A method for manufacturing a semiconductor device (1000) comprises forming (S110) an epitaxial semiconductor layer (110, 120, 130) over a substrate (100), patterning (S120) the epitaxial semiconductor layer sequence (1) to a mesa (10) using plasma etching, forming (S130) an oxide layer (140) by oxidizing a sidewall portion (12) of the mesa (10) using a remote plasma oxidation, and wet etching (S140) the oxide layer (140).

Description

[0001] 2024PF00794 1

[0002] METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

[0003] Gallium nitride (GaN) based optoelectronic and electronic semiconductor devices such as light-emitting diodes (LEDs) are widely used, and their reliability is of great importance for many applications . Generally, semiconductor devices may comprise an underlying epitaxial (EPI ) structure including an n-type semiconductor layer and a p-type semiconductor layer .

[0004] Such an EPI structure, which may be configured, for example, as an LED chip, comprises a p-n junction. When electrons and holes recombine with each other in a region of the p-n junction, for example, since a suitable voltage is applied, electromagnetic radiation is generated.

[0005] When defining LED or laser mesas using etching process, e . g. a plasma etching process, the semiconductor material at the sidewalls of the mesa may be damaged leading to loss of performance .

[0006] Therefore, it is an obj ect of the present invention to provide an improved method for manufacturing a semiconductor device .

[0007] According to embodiments, the obj ect is achieved by the claimed subj ect-matter of the independent claims . Further developments are defined in the dependent claims .

[0008] SUMMARY

[0009] A method for manufacturing a semiconductor device comprises forming an epitaxial semiconductor layer over a substrate, patterning the epitaxial semiconductor layer to a mesa using plasma etching, forming an oxide layer by oxidizing a sidewall portion of the mesa using a remote plasma oxidation, and wet etching the oxide layer .2024PF00794 2

[0010] Selectively wet etching the oxide layer allows removing surface defects due to plasma etching while maintaining any geometry of the sidewall portion of the mesa obtained through the plasma etching. In other words, forming the oxide layer enables a fast and controllable wet etching with minimal impact on dimension tolerances using standard semiconductor processing equipment . This provides a high flexibility in design of mesa geometry, a high repeatability and an increased flexibility of the order of processing before the mesa etch step giving additional degrees of freedom in designing a semiconductor device .

[0011] Furthermore, the above-described method provides an increased flexibility in using a wider range of materials that do not need to be robust against conventional etchants such as Potassium hydroxide (KOH) .

[0012] After wet etching the oxide layer, the sidewall portion of the mesa may be passivated by forming a passivation layer . The passivation layer may allow to cover steps in the sidewall portion resulting from wet etching the oxide layer that may comprise different thicknesses due to different depths of oxidation.

[0013] In addition, an etch mask layer may be formed on a top surface of the epitaxial semiconductor layer .

[0014] According to embodiments, an additional plasma cleaning may be applied after the plasma etching.

[0015] Furthermore, forming the oxide layer may comprise oxidizing the semiconductor layer at the sidewall portion of the mesa using the remote plasma oxidation.

[0016] The semiconductor layer may comprise AlxGayn1-x-yN, GaN, InxA-lyGai_x-yAs , or InxGayAl1-x-yP .2024PF00794 3

[0017] The wet etching may comprise a liquid-phase etchant including hydrogen fluoride, HF, or ammonia, NH3.

[0018] The passivation layer may comprise A12O3, SiO2, HfO2, Nb2O5, or Ta2O3. According to further examples, the passivation layer may comprise GaAs, ZnSe or GaN. For example, a passivation layer comprising GaAs or ZnSe may be formed over GaAs-containing material . Further, GaN may be formed over GaN-containing material . For example, such a passivation layer comprising GaAs, ZnSe or GaN may be epitaxially grown.

[0019] And the etch mask layer may comprise Si3N4, SiO2, A12O3, or photoresist .

[0020] According to embodiments, the semiconductor layer may comprise an epitaxial semiconductor layer sequence including an n-type semiconductor layer and an p-type semiconductor layer over the substrate .

[0021] The epitaxial semiconductor layer sequence may further comprise an active layer configured to generate and / or absorb electromagnetic radiation. The active layer may be arranged between the n-type semiconductor layer and the p-type semiconductor layer .

[0022] In greater detail, the active layer may comprise alternatingly stacked InGaN and AlGaN layers .

[0023] In addition, a semiconductor device manufactured by a method as described above may be provided.

[0024] BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings serve to provide an understanding of exemplary embodiments of the invention. The drawings illustrate2024PF00794 4

[0026] exemplary embodiments and, together with the description, serve for explanation thereof . Further exemplary embodiments and many of the intended advantages will become apparent directly from the following detailed description. The elements and structures shown in the drawings are not necessarily shown to scale relative to each other . Like reference numerals refer to like or corresponding elements and structures .

[0027] Fig. 1A to Fig. IE show cross-sectional views of a semiconductor device at different stages of manufacturing according to embodiments .

[0028] Fig. 2 shows a method for manufacturing the semiconductor device according to embodiments .

[0029] DETAILED DESCRIPTION

[0030] In the following detailed description, reference is made to the accompanying drawings, which form a part of the disclosure and in which specific exemplary embodiments are shown for purposes of illustration. In this context, directional terminology such as "top", "bottom", "front", "back", "over", "on", "in front", "behind", "leading", "trailing", etc . refers to the orientation of the figures just described. As the components of the exemplary embodiments may be positioned in different orientations, the directional terminology is used by way of explanation only and is in no way intended to be limiting.

[0031] The description of the exemplary embodiments is not limiting, since there are also other exemplary embodiments, and structural or logical changes may be made without departing from the scope as defined by the patent claims . In particular, elements of the exemplary embodiments described below may be combined with ele-2024PF00794 5

[0032] ments from others of the exemplary embodiments described, unless the context indicates otherwise .

[0033] The terms "wafer" or "semiconductor substrate" used in the following description may include any semiconductor-based structure that has a semiconductor surface . Wafer and structure are to be understood to include doped and undoped semiconductors, epitaxial semiconductor layers, e . g. , supported by a base semiconductor foundation, and other semiconductor structures . For example, a layer of a first semiconductor material may be grown on a growth substrate of a second semiconductor material . According to further embodiments, the growth substrate may be an insulating substrate such as a sapphire substrate . Depending on the purpose of use, the semiconductor may be based on a direct or an indirect semiconductor material . Examples of semiconductor materials particularly suitable for generation of electromagnetic radiation comprise nitride-compound semiconductors, by which e . g. ultraviolet or blue light or longer wavelength light may be generated, such as GaN, InGaN, AIN, AlGaN, AlGalnN, phosphide-compound semiconductors, by which e . g. green or longer wavelength light may be generated such as GaAsP, AlGalnP, GaP, AlGaP, as well as further semiconductor materials including AlGaAs, SiC, ZnSe, GaAs, ZnO, Ga2O3, diamond, hexagonal BN und combinations of these materials . The stoichiometric ratio of the compound semiconductor materials may vary.

[0034] The term "substrate" generally refers to semiconductor substrates, conductive or insulating substrates .

[0035] The terms "lateral" and "horizontal", as used in the present description, are intended to describe an orientation or alignment which extends essentially parallel to a first surface of a semiconductor substrate or semiconductor body. This may be the surface of a wafer or a chip (die) , for example .2024PF00794 6

[0036] The horizontal direction may, for example, be in a plane perpendicular to a direction of growth when layers are grown .

[0037] The term "vertical" as used in this description is intended to describe an orientation which is essentially perpendicular to the first surface of the semiconductor substrate or semiconductor body. The vertical direction may correspond, for example, to a direction of growth when layers are grown.

[0038] To the extent used herein, the terms "have", "include", "comprise", and the like are open-ended terms that indicate the presence of said elements or features, but do not exclude the presence of further elements or features . The indefinite articles and the definite articles include both the plural and the singular, unless the context clearly indicates otherwise .

[0039] The term "layer" as used herein may refer to a single layer as well refer to a layer stack comprising a plurality of partial layers .

[0040] Figs . 1A to IE show cross-sectional views of a semiconductor device 1000 at different stages of manufacturing according to embodiments .

[0041] As shown in Fig. 1A, an epitaxial semiconductor layer 110, 120, 130 is formed over a substrate 100. The epitaxial semiconductor layer 110, 120, 130 may be a single layer (not shown in Figs . 1A to IE) or may comprise an epitaxial semiconductor layer sequence 1 including a first semiconductor layer 110 of a first conductivity type, e . g. n-type and a second semiconductor layer 130 of a second conductivity type, e . g. p-type over the substrate 100. The combination of these two semiconductor layers 110, 130 may result in a p-n-j unction .2024PF00794 7

[0042] In addition, the epitaxial semiconductor layer sequence 1 may further comprise an active layer 120 configured to generate and / or absorb electromagnetic radiation. As can be seen in Figs .

[0043] 1A to IE, the active layer 120 may be arranged between the n-type semiconductor layer 110 and the p-type semiconductor layer 130 .

[0044] The active layer 120 or active zone may, for example, comprise the p-n junction, a double heterostructure, a single quantum well structure (SQW, single quantum well) or a multiple quantum well structure (MQW, multi quantum well) for generating radiation. The term "quantum well structure" does not imply any particular meaning here with regard to the dimensionality of the quantization. Therefore, it includes, among other things, quantum wells, quantum wires and quantum dots as well as any combination of these layers .

[0045] The semiconductor layer 110, 120, 130 as described in the present application represents both, the single epitaxial semiconductor layer or the epitaxial semiconductor layer sequence 1 .

[0046] The epitaxial semiconductor layer 110, 120, 130 is patterned to a mesa 10 using plasma etching, which is illustrated in Fig. IB by a large arrow.

[0047] In general, plasma etching, such as ion etching and reactiveplasma etching (RTE) (simply referred to as plasma etching or plasma etching process in the present application) , is a dry etching technique widely used in semiconductor manufacturing to create patterns on the surface of various materials with high resolution and anisotropy.

[0048] For example, RIE uses reactive gases in a plasma state to chemically and physically remove the material from the surface of a2024PF00794 8

[0049] substrate, for example, a semiconductor wafer . The substrate may be covered with a patterned mask. Such a mask or etch mask layer 150 (which is explained in detail later on) is shown in Figs . IB to IE and protects parts of the surface that should not be etched. The plasma is generated by applying an electric field and may comprise a mixture of ions, free electrons, and neutral particles . The electric field accelerates the ions in the plasma towards the substrate, resulting in both chemical reactions and physical sputtering at the surface . The combination of these two mechanisms may remove the material, which is not covered by the mask, to create a desired pattern. Plasma etching also uses ionized gases to remove material from a substrate, but the bombardment of ions is more random than in RIE .

[0050] More specifically, as indicated in Fig. IB, such a plasma etch process may be applied to the epitaxial semiconductor layer to remove the material from the substrate 100 (i . e . , the material not covered by the etch mask layer 150) in order to form the mesa 10. The ion bombardment is indicated by small arrows . A horizontal surface of the second semiconductor layer 130 which is covered by the etching mask 150 is not etched during the plasma etch process .

[0051] According to embodiments, an oxide layer 140 is then formed by oxidizing the sidewall portion 12 of the mesa 10 using a remote plasma oxidation. This is shown in Fig. 1C .

[0052] In this context, remote plasma (also known as downstream plasma or afterglow plasma) is a plasma processing method in which the plasma and material interaction occurs at a location that is remote from the plasma . In more detail, the plasma and material interaction occurs in the plasma afterglow. The plasma afterglow is the radiation emitted from a plasma after the source of ionization is removed. For example, the plasma may be generated by2024PF00794 9

[0053] a remote plasma source . Radicals may be extracted out of the remote plasma source and may then be used to further process a substrate . For example, an external electromagnetic field that generates and sustains the plasma may be absent from the plasma afterglow. As a result, ion bombardment and high thermal strain may be avoided in the plasma afterglow.

[0054] In the present application, the remote plasma is used to oxidate a few nm of the sidewall portion 12 in a non-violent manner . These oxidized parts, indicated by shaded areas in Fig. 1C, may contain surface defects due to the plasma etching as explained in the following.

[0055] For example, the plasma etching may damage the semiconductor material at the sidewall of the mesa 10. For example, the plasma etching may expose the p-n junction of the semiconductor device 1000 (e . g. , the interface between the n-type semiconductor layer 110 and the p-type semiconductor layer 130) and may lead to surface defects at an etched p-n-junction sidewall 12 of the mesa 10. The surface defects, or more precisely, the damage to the semiconductor crystal lattice, are caused by the ion bombardment . These defects may give raise to non-radiative recombination and leakage across the p-n junction which leads to degradation of performance and may also affect the lifetime of the semiconductor device 1000.

[0056] Oxidizing the sidewall portion 12 by the remote plasma allows to remove the damages in the crystal lattice at the p-n junction in a later wet etching process . The oxidation process does not cause further ion damage to the crystal lattice . Such an oxidation is typically slowed down after a certain depth has been obtained. Hence, it is further possible to make the process reproducible .2024PF00794 10

[0057] More precisely, the oxide layer 140 is removed by wet etching as illustrated in Fig. ID. That is, the oxidized parts that may contain the damages caused by the plasma etching are selectively cleaned off via the wet etching. As a result, nearly exactly the geometry of the sidewall portion 12 that was obtained through the plasma etching may be maintained.

[0058] Specifically, the oxide layer 140 is removed by selectively wet etching only the oxide layer 140, but not the substrate 100, e . g. , the underlying bulk semiconductor . In this way it is possible to remove the damaged crystal layers with high precision.

[0059] Generally, wet etching is a material removal process that uses liquid chemicals or etchants to remove materials from e . g. , a wafer . Anisotropic wet etching (or orientation dependent etching) uses wet etchants that etch crystalline materials at very different rates depending upon which crystal face is exposed. In single-crystal materials (e . g. , silicon wafers) , this may allow very high anisotropy. For example, wet etching may be performed using Potassium hydroxide (KOH) . This etchant may leave a perfectly clean vertical surface after removing damaged parts . Generally, using a strong etchant such as KOH may limit the materials used to manufacture a semiconductor device .

[0060] The oxide layer 140 allows to use a wider range of materials that do not need to be robust against KOH. Furthermore, as described above, this allows to maintain the geometry of the mesa 10. The wet etching process may thus more flexible and more controllable .

[0061] According to embodiments, the wet etching may comprise a liquidphase etchant including hydrogen fluoride (HF) , ammonia (NH3) , or a buffered oxide etch (BOE) , also known as buffered HF or BHF.2024PF00794 11

[0062] The oxide layer 140 may have different thicknesses across the sidewall portion 12 depending on the depth of oxidation of the underlying materials . More precisely, when the oxide layer 140 is formed, the n-type semiconductor layer 110, the active layer 130, and the p-type semiconductor layer 130 at the sidewall portion 12 of the mesa 10 may be oxidized using the remote plasma oxidation to different thicknesses . The depth of oxidation may depend on the material and the doping of the layer 110, 120, 130. The different thicknesses of the oxide layer 140 are indicated in Fig. 1C by the different thicknesses of the shaded areas .

[0063] After wet etching the oxide layer 140, the sidewall portion 12 of the mesa 10 may have, depending on the different thicknesses of the oxide layer 140, steps in the sidewall portion 12. These steps are highlighted by a dashed circle shown in Fig. ID. To avoid overly large steps in the sidewall portion 12, remote plasma oxidation may be applied such that only a minimum thickness of the corresponding materials is oxidized to remove damage in the crystal lattice .

[0064] Furthermore, after wet etching the oxide layer 140, the sidewall portion 12 of the mesa 10 may be passivated to form a passivation layer 160. This is indicated in Fig. IE .

[0065] The passivation layer 160 may be formed, for example, by means of atomic layer deposition to fully cover the steps in the sidewall portion 12. This may prevent overhanging material from not being passivated properly.

[0066] The passivation layer 160 may comprise A12O3, SiO2, HfO2, Nb2O5, or Ta2O3.2024PF00794 12

[0067] According to further examples, the passivation layer 160 may comprise GaAs or ZnSe which may be formed over GaAs-containing semiconductor material . According to further examples, the passivation layer 160 may comprise GaN which may be formed over GaN-containing semiconductor material . For example, the passivation layer 160 comprising GaAs, ZnSe or GaN may be epitaxially grown. For example, in this way, a lattice matched surface coating may be formed over the semiconductor material . For example, such a passivation layer 160 may be useful for semiconductor lasers .

[0068] In addition, as described briefly above, the etch mask layer 150 may be formed on a top surface of the epitaxial semiconductor layer sequence 1, which is shown in Fig. IB to IE .

[0069] According to embodiments, the etch mask layer 150 may comprise Si3N4, SiO2, A12O3, or photoresist . Depending on what material was used for the etch mask layer 150, it may remain in place, or may be removed during the etching processes . In the examples shown in Fig. IB to IE, the etch mask layer 150 remains in place .

[0070] The n-type semiconductor layer 110 and the p-type semiconductor layer 130 may comprise AlxGayn2-x-yN, GaN, InxAlyGai-x-yAs , or Inx_ GayAl2-x-yP .

[0071] The active layer 120 may comprise, for example, alternatingly stacked InGaN and AlGaN layers . These layers may also be oxidized to different thicknesses and may result in a further step in the sidewall portion 12 of the mesa 10 after wet etching.

[0072] Fig. 2 illustrates the method to manufacture the semiconductor device 1000 described above .2024PF00794 13

[0073] In operation S110, the epitaxial semiconductor layer 110, 120, 130 is formed.

[0074] Optionally, in step S112, the etch mask layer 150 may be formed on the top surface of the epitaxial semiconductor layerllO, 120, 130 .

[0075] In operation S120, the epitaxial semiconductor layer 110, 120, 130 is patterned to the mesa 10 using plasma etching as described above . In greater detail, the epitaxial semiconductor layer 110, 120, 130 may be processed by applying plasma etching to the layers 110, 120, 130 comprising, for example, GaN, AlGaN, InGaN. The sidewall portion 12 of the mesa 10 may have any slope (geometry) at this point .

[0076] In operation S122, an additional plasma cleaning step may be performed after the plasma etching, since plasma ion damage will be removed in any case .

[0077] In addition, as already described, depending on what material was used for the etch mask layer 150, it may remain in place, or may be removed during the etching.

[0078] In operation S130, the oxide layer 140 is formed by oxidizing the sidewall portion 12 of the mesa 10 using the remote plasma oxidation. The aim is to remove the ion damaged part of the layers 110, 120, 130 in the sidewall portion 12 (e . g. , in the p-n-junction) .

[0079] For example, the active layer 120 comprising e . g. , a quantum well structure comprising alternatingly stacked AlGaN and InGaN layer may oxidize to different depths . Moreover, GaN may oxidize differently depending on doping as well . For example, the oxidation may be a few nm, preferably, 1 to 10 nm of GaN by remote2024PF00794 14

[0080] oxygen plasma . The oxide layer 140 comprising, e . g. , AlGaOx, InGaOx, GaOx, as indicated by the shaded areas in Fig. 1C, may thus have slightly different thicknesses .

[0081] In operation S140, the oxide layer 140 is processed by wet etching. Wet etching may be performed, e . g. , using a buffered HF or any other etchant that etches A1-, Ga-, and In-oxides . Depending on the thickness of the oxide layer 140, the resulting sidewall portion 12 of the mesa 10 may have steps in the etched sidewall 12 as shown in Figs . ID and IE . To avoid overly large steps, an oxidation depth of the corresponding layers 110, 120, 130 may be reduced to a thickness necessary to remove crystal damage .

[0082] In operation S150, after wet etching the oxide layer 140, the sidewall portion 12 of the mesa 10 may be passivated by forming the passivation layer 160. This passivation, e . g. , by means of atomic layer deposition or epitaxial growth, may be useful in order to fully cover the steps in the sidewall portion 12.

[0083] The embodiments above have been explained on basis of Ga (Al, In) N semiconductor materials . But the principles and the method described therein is also valid for other semiconductor materials such as InAlGaAs or InGaAlP .

[0084] Although specific embodiments have been illustrated and described herein, those skilled in the art will recognize that the specific embodiments shown and described may be replaced by a multiplicity of alternative and / or equivalent configurations without departing from the scope of the invention. The application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, the invention is to be limited by the claims and their equivalents only.2024PF00794 15

[0085] LIST OF REFERENCES

[0086] 1 epitaxial semiconductor layer sequence 10 mesa

[0087] 12 sidewall portion

[0088] 100 substrate

[0089] 110 first semiconductor layer

[0090] 120 active layer

[0091] 130 second semiconductor layer

[0092] 140 oxide layer

[0093] 150 etch mask layer

[0094] 160 passivation layer

[0095] 1000 semiconductor device

Claims

2024PF00794 16CLAIMS1 . A method for manufacturing a semiconductor device ( 1000) , the method comprising:forming (S110) an epitaxial semiconductor layer ( 110, 120, 130) over a substrate ( 100) ;patterning (S120) the epitaxial semiconductor layer ( 110, 120, 130) to a mesa ( 10) using plasma etching;forming (S130) an oxide layer ( 140) by oxidizing a sidewall portion ( 12 ) of the mesa ( 10) using a remote plasma oxidation;wet etching (S140) the oxide layer ( 140) , and epitaxially growing a passivation layer ( 160) over the sidewall portion ( 12 ) of the mesa ( 10) after wet etching the oxide layer ( 140) .

2. The method according to claim 1, further comprising forming (S112 ) an etch mask layer ( 150) on a top surface of the epitaxial semiconductor layer ( 110, 120, 130) before wet etching .

3. The method according to any one of the preceding claims, further comprising applying (S122 ) an additional plasma cleaning after the plasma etching.

4. The method according to any one of the preceding claims, wherein forming the oxide layer ( 140) comprises oxidizing the semiconductor layer ( 110, 120, 130) at the sidewall portion ( 12 ) of the mesa ( 10) using the remote plasma oxidation .

5. The method according to any one of the preceding claims, wherein the semiconductor layer ( 110, 120) comprises AlxGayn1-x-yN, GaN, InxAlyGai-x-yAs , or InxGayAl1-x-yP .2024PF00794 176. The method according to any one of the preceding claims, wherein the wet etching comprises a liquid-phase etchant including hydrogen fluoride, HF, or ammonia, NH37 . The method according to any of the preceding claims, wherein the passivation layer ( 160) comprises a semiconductor material .

8. The method according to any one of claims 2 to 7, wherein the etch mask layer ( 150) comprises Si3N4, SiO2, A12O3, or photoresist .

9. The method according to any one of the preceding claims, wherein the semiconductor layer ( 110, 120, 130) comprises an epitaxial semiconductor layer sequence ( 1 ) including an n-type semiconductor layer ( 110) and a p-type semiconductor layer ( 130) over the substrate ( 100) .

10. The method according to claim 9, wherein the epitaxial semiconductor layer sequence ( 1 ) further comprises an active layer ( 120) configured to generate and / or absorb electromagnetic radiation, wherein the active layer ( 120) is arranged between the n-type semiconductor layer ( 110) and the p-type semiconductor layer ( 130) .

11. The method according to claim 10, wherein the active layer ( 120) comprises alternatingly stacked InGaN and AlGaN layers .

12. A semiconductor device ( 1000) manufactured by a method according to any one of the preceding claims .

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