Piezoelectric micromachined ultrasonic transducer and its fabrication method

Abstract

Piezoelectric micromachined ultrasonic transducer and its fabrication method are disclosed. A first etch stop layer (104) and a sacrificial layer (106) are deposited (700, 702) to form a structure. A trench (108) extends (704) to the first etch stop layer (104) defining a boundary to a cavity area (110). A refill is deposited (706), forming a barrier being resistive to an etching process of sacrificial material. A second etch stop layer (112) is deposited (708). An opening (114) is etched (710) above the cavity area. A layer of sacrificial layer material (116) is deposited (712) as a horizontal line covering the opening and the other end of the horizontal line not being above the cavity area (110). A third etch stop layer (118) is deposited (714) and a hole (120) formed (716) to horizontal sacrificial layer material line (118) not being above the cavity area (110). Sacrificial material is removed (718) from the cavity area (106) through the hole (120) for forming at least one cavity (122) within the layered structure. First and second metal electrodes (722, 728) and piezo layer (724) are deposited.

Description

[0001] PIEZOELECTRIC MICROMACHINED ULTRASONIC TRANSDUCER AND ITS FABRICATION METHOD

[0002] Technical Field

[0003] The exemplary and non-limiting embodiments of the invention relate generally to a piezoelectric micromachined ultrasonic transducer and its fabrication method.

[0004] Background

[0005] Piezoelectric micromachined ultrasonic transducers (PMUTs) are used in a wide range of applications, including medical imaging, non-destructive testing, distance measurement, and gesture recognition. By converting electrical signals into ultrasonic waves and vice versa, PMUTs provide miniature, low-power solutions for precision sensing and actuation tasks.

[0006] The most common method for fabricating conventional PMUTs involves defining membrane dimensions using backside Deep Reactive Ion Etching (DR1E). Although DR1E is effective, it inherently introduces lateral dimensional variations that can alter the resonant frequency and reduce yield. Additionally, the resulting open cavities can lead to acoustic losses. An alternative approach utilizes cavity silicon-on-insulator (CS01) wafers, which offer improved lateral dimensional control, vacuum-sealed cavities for enhanced acoustic performance, and potentially better uniformity. However, CSOl-based methods also have limitations: thinning the structural layer of the membrane below a certain limit is challenging, the inherent structure of CSOl-based PMUT arrays can limit device density, and the process requires high-temperature steps that may complicate integration with other components.

[0007] Brief description

[0008] The invention is defined by the independent claims. The scope of protection sought for various embodiments of the invention is set out by the independent claims.

[0009] The embodiments and or examples and features, if any, described in this specification that do not fall under the scope of the independent claims are to beinterpreted as examples useful for understanding various embodiments of the invention.

[0010] Brief description of the drawings

[0011] In the following the invention will be described in greater detail by means of preferred embodiments with reference to the accompanying drawings, in which

[0012] Figures 1A to IK and 2A to 2E illustrate examples of fabrication phases of a piezoelectric micromachined ultrasonic transducer;

[0013] Figure 3A illustrates an example of a circular unit of a microelectromechanical system apparatus;

[0014] Figure 3B illustrates an example of a conical unit of a microelectromechanical system apparatus;

[0015] Figure 4A illustrates an example of a matrix of circular units of a microelectromechanical system apparatus;

[0016] Figure 4B illustrates an example of a matrix of conical units of a microelectromechanical system apparatus;

[0017] Figures 5A - 5D illustrate phases of creating a trench of a trench pattern; Figures 6A and 6B illustrate examples of a cross section of a trench; Figures 7A and 7B are flowcharts illustrating some embodiments of the invention; and

[0018] Figure 8 illustrates an array of membranes featuring trench patterns.

[0019] Detailed description of some embodiments

[0020] The following embodiments are only examples. Although the specification may refer to “an” embodiment in several locations, this does not necessarily mean that each such reference is to the same embodiment(s), or that the feature only applies to a single embodiment.

[0021] The articles “a” and “an” give a general sense of entities, structures, components, compositions, operations, functions, connections or the like in this document. Note also that singular terms may include pluralities.

[0022] Single features of different embodiments may also be combined to provide other embodiments. Furthermore, words "comprising" and "including" should be understood as not limiting the described embodiments to consist of only those features that have been mentioned and such embodiments may also contain features / structures that have not been specifically mentioned. All combinations ofthe embodiments are considered possible if their combination does not lead to structural or logical contradiction.

[0023] The microelectromechanical system apparatus described in this document offers a viable alternative to PMUT built on Cavity SOI wafers that require advanced bonding processes. The use of confining barriers described here provides greater flexibility to the designer compared to surface micromachining processes along with reduced fabrication costs compared to Cavity-Silicon-on-Insulator (C-S01) wafers.

[0024] PMUTs benefit significantly from the use of customized substrates that incorporate vacuum cavities, particularly in diverse applications such as medical sensors. These vacuum cavities facilitate the fabrication of PMUTs directly over the substrate, aiding in the release of the structures and enhancing their overall performance. A prime example of this is the use of Cavity-Silicon-on-lnsulator (C-SO1) wafers for PMUT fabrication. These wafers are designed with cavities located in the handle wafer, which is bonded to a device wafer. The cavities are positioned directly beneath the areas where the resonators are patterned. This design not only supports the release process but also improves the functionality and efficiency of the PMUTs.

[0025] Figs. 1A to IK and 2A to 2E show an example of a stack of layers from side in various phases of a fabricating process of a piezoelectric micromachined ultrasonic transducer.

[0026] A purpose of the fabrication method is to form one or more sacrificial layers and surround them by material layers. The surrounding layers are resistive to etchant(s) used to etch the one or more sacrificial layers. Removal of the one or more sacrificial layers results in one or more cavities within the material layers, which form a barrier limiting the cavity. In this document, the word resistive may also mean resistant.

[0027] It is known to utilise substrates with vacuum cavities for PMUT fabrication. Cavity Silicon on Insulator (C-S01) wafers are the preferred substrates for constructing PMUT devices for these applications. The C-S01 structure is created by bonding a substrate wafer with etched cavities to a device wafer, thinned to target specifications. The bonding techniques for such a process are demanding and require a high degree of process quality. Nevertheless, despite the high demands and corresponding costs, Cavity SOI wafers offer significant benefits such as precise control of cavity dimensions and device layer thickness and thus remain a viable choice for PMUT platforms. However, there remainspotential for further enhancements in substrate performance for these applications.

[0028] It is a known problem that creating a thin device layer with large-diameter cavities using C-S01 wafers is difficult. Increasing the membrane diameter while reducing the device layer thickness creates significant difficulties, resulting in the limited use of C-S01 wafers in PMUT applications. For example, the current thickness limitation of C-S01 wafers is 2.5 pm when the diameter is 100 pm. Due to this limitation it is challenging to fabricate PMUT lower than 1 MHz. The current C-SO1 manufacturing technology allows to reliably achieve a minimum spacing between sensors of (approximately 20 pm). It would be highly advantageous to reduce these spacings. In PMUT arrays, this could increase device density and help to improve performance.

[0029] In PMUTs, it would be beneficial to minimize or control the cavity dimensions, thickness of the device layer, and improve device layer thickness uniformity. For instance, this benefit in building a platform / substrate for producing PMUTs with a frequency range of 250 kHz to 100 MHz.

[0030] A purpose of the proposed fabrication method is the creation of PMUT with vacuum (or filled) cavities beneath released membranes. The proposed PMUT fabrication process utilises a unique application of an etch stop barrier to confine the release of a sacrificial layer thus precisely defining the microcavity. One or more sacrificial layers are formed and surrounded by etch stop barrier layers. The etch stop barrier layers are resistive to etchant(s) used to etch the one or more sacrificial layers. Removal of the one or more sacrificial layers results in one or more cavities. The cavity is released through a small etch access hole and a channel that reaches beyond cavity. The access holes and channel are then sealed under vacuum (or potentially in other atmospheres).

[0031] Further, precision is improved by this method compared to backside DR1E etching or customized CS01, and it can be utilized as a multipurpose platform / substrate for building MEMS devices and resonators like piezoelectric micromachined ultrasonic transducers (PMUTs), capacitive micromachined ultrasonic transducers (CMUTs), microphones, pressure sensors, acoustic emission sensors, among others. The proposed solution enables achieving a minimum spacing between PMUT membranes as narrow as 2 pm.

[0032] In general, the multilayer piezoelectric micromachined ultrasonic transducer 100 is fabricated on a substrate 102. The material of the substrate 102 may be freely chosen taking into account the process conditions the applicationsand / or the knowledge of a person skilled in the art. For example, the substrate may be Silicon (Si), Silicon on Insulator (SOI), or an application specific integrated circuit (ASIC).

[0033] In fabrication phase of Fig. 1A, a first etch stop layer 104 and a sacrificial layer 106 are deposited on the substrate 102. The etch stop layer 104 may be Silicon dioxide, Silicon Nitride, Aluminium oxide etc., for example. The material of the sacrificial layer 106 may be crystalline, amorphous or poly-crystalline silicon, or metals such as molybdenum (Mo), titanium (Ti), titanium tungsten (TiW), or metals that are etched by xenon difluoride, for example.

[0034] In fabrication phase of Fig. IB, a trench 108 of a trench pattern 300 is formed to the sacrificial layer 106. The trench 108 can be considered a groove. The trench 108 can be formed by etching, for example. The trench 108 of the trench pattern 300 extends in a direction of a normal N of a surface of the sacrificial layer 106 through the sacrificial layer. The trench 108 forms the trench pattern 300 to the sacrificial layer 106 in lateral directions i.e. the pattern can be observed from above of the multilayer structure.

[0035] Examples of trench patterns 300 are shown in Figs. 3A and 3B. The trench pattern 300 of the trench 108 may laterally confine a desired section of the sacrificial layer 106 and it may be of any shape such as circular or conical, for example. The trench pattern 300 thus defines a boundary that may enclose a cavity area of a PMUT apparatus within the trench pattern 300.

[0036] A plurality of trench patterns 300 may then define boundaries that may enclose the plurality of cavity areas that may be utilized for fabrication of an array of PMUTs. In other words, the first etch stop layer and the trench pattern define a boundary to at least one cavity area to be formed in the micro-electromechanical system apparatus. It is a technical advantage that the trench 108 may be about micron in size / width or a sub-micron in size / width. That small size enables reducing dishing during chemical mechanical planarization (CMP), which results in improved planarity. Examples of a plurality of trench patterns 300 are shown in Figs.4A and 4B.

[0037] An example of the creation of the trench is explained further below in connection with Figs. 5A-5D.

[0038] Fig. 1C illustrates an example of a refill layer 111 in the trench 108. The refill layer 111 may be deposited on the sacrificial layer 106. The refill layer may be Silicon dioxide for example. In that manner, the trench 108 may be refilled. Instead, an etchant resistive wall arrangement 506 may be added to the trench 108.In this manner, the etchant resistive material will become the barrier structure 506 around the cavity to be formed. The barrier structure 506 may be formed by a thermal oxidation or a deposition process of Silicon dioxide, Silicon Nitride, or Aluminium oxide, for example. Additionally amorphous or poly-crystalline silicon is deposited as a refill layer 111 for completing refilling for planarization. No voids are present after depositing refill layer. Thickness of the refill layer can be 100 nm to 1 pm, for example.

[0039] As shown in Fig. 1C, the refill refills the trench 108 may be planarized. The planarization may be performed by a chemical mechanical polishing (CMP), for example, which the person skilled in the art is familiar with. The purpose of the planarization is to make the surface flat. The refill may be etchant resistive. As Fig.

[0040] 1C illustrates, after the planarization, the refill 111 remains only inside of the trench 108. The material inside the trench 108 can be thermally oxidized, or oxide layer(s) or other suitable layers may be deposited on it.

[0041] In fabrication phase of Fig. ID, a second etch stop layer 112 is deposited on the multilayer structure on top of sacrificial layer 106 and the filled trenches 108. The second etch stop layer 112 may be Silicon dioxide, Silicon Nitride, Aluminum oxide etc., for example.

[0042] In fabrication phase of Fig. IE, an opening 114 is etched on the second etch stop layer 112 inside the at least one cavity area 110. The opening goes through the second etch stop layer 112 and reaches the sacrificial layer 106.

[0043] In fabrication phase of Fig. IF, a layer of sacrificial layer material 116 is deposited as a number of horizontal lines each covering the opening 114. The other end of the horizontal line is outside the at least one cavity area 106. A thin layer of materials

[0044]

[0045] 50 nm) can be used as the sacrificial layer 116 material.

[0046] In fabrication phase of Fig. 1G, a third etch stop layer 118 is deposited on the second etch stop layer and the horizontal sacrificial layer material lines. Typically, the third etch stop layer 118 may be Silicon dioxide, Silicon Nitride or Aluminium oxide, for example.

[0047] In fabrication phase of Fig. 1H, at least one hole 120 is formed through the third etch stop layer 118 to horizontal sacrificial layer material line 116 outside the at least one cavity area 106.

[0048] The fabrication phase of Fig. II comprises removing sacrificial material of the sacrificial layer 106 from the at least one cavity area by a process of etching for forming at least one cavity 122 within the layered structure, each of the at least one cavity being laterally confined by the barrier structure.The sacrificial material is removed through the at least one hole 120 and the horizontal lines 116 of the sacrificial material.

[0049] In an embodiment, etching agent of the etching process to remove the sacrificial material includes xenon difluoride.

[0050] In fabrication phase of Fig. IK, the cavity 122 is sealed by depositing a fourth layer 124 on top of the third etch stop layer 118. The at least one hole 120 and the horizontal lines 116 are also filled with the fourth layer material.

[0051] The fourth layer may be, for example, crystalline silicon, polycrystalline or amorphous silicon, oxides, nitrides, or metals etc. or combination of these.

[0052] The process continues as illustrated in Figs 2A to 2E.

[0053] In fabrication phase of Fig.2A, a first metal electrode 200, which may be patterned or unpatterned, is deposited on the fourth layer 124.

[0054] In fabrication phase of Fig.2B, piezo layer 202 is deposited on top of the first metal electrode 200. Further, the piezo layer 202 is patterned and at least one hole 204 is etched through the piezo layer 202 to provide access to the first metal electrode 200.

[0055] In fabrication phase of Fig.2C, a second metal electrode 206 is deposited and patterned on top of the piezo layer 202.

[0056] In fabrication phases of Fig.2D and 2E, a protection layer 201A, 210B is deposited and patterned on top of the metal electrodes and piezo layer. The protective layer protects the other layers. The protective layer may be made of oxides, nitrides, for example.

[0057] Fig. 2D and 2E illustrate alternative examples of using the protective layer. In the example of Fig. 2D, the third etch stop layer and the fourth layer 124 functions as the structural layer in PMUTs. The purpose of the structural layer is to move the stress neutral plane away from the piezoelectric layer. The protective layer 210A is smaller than in the example of Fig. 2E.

[0058] In the example of Fig. 2E, the protective layer 210B may serve as both the protective and structural layer.

[0059] One of the advantages of the proposed solution is that the combined thickness of the third and fourth layers can be thinner than the current smallest achievable thickness of the device layers obtainable on cavity silicon on insulator wafers. Further, the thickness uniformity of the combined third and fourth layers can be within 50 nm, which is better than the current achievable thickness uniformity in CS01 wafer device layers.Figs 5A to 5D illustrate examples of some fabrication phases of substrate for a multilayer micro-electromechanical system apparatus. In general, the MEMS apparatuses may comprise one or more cavities that may be arranged as an array, for example. Figs 5A to 5D show a stack 500 of layers from side and illustrate the phases of creating a trench 108 of a trench pattern 300. As shown in Fig. 5A, the trench 108 of the trench pattern 300 is formed to the stack 500 of layers.

[0060] In an embodiment, the stack 500 of layers comprises the sacrificial layer 106 comprising sacrificial material between the first layer arrangement 502 and the second layer arrangement 504. The first layer arrangement 502 and the second layer arrangement 504 may comprise the etchant resistive layers 104, 506 and potentially other layers. The sacrificial layer 106 may be, for example, amorphous silicon and / or polysilicon. The layers of the first and second layer arrangements 502, 504 may vary during the fabrication phases. A substrate 102 is included in the second layer arrangement 504. The material of the substrate 102 may be freely chosen taking into account the process conditions and the knowledge of a person skilled in the art.

[0061] The trench 108 can be considered a groove. The trench 108 of the trench pattern 300 extends in a direction of a normal N of a surface of the sacrificial layer 106 through the sacrificial layer 106 that is inside the stack 500. The trench 108 forms a pattern to the sacrificial layer 106 in lateral directions i.e. the pattern can be observed from above of the stack 500. The trench pattern 300 of the trench 108 may laterally confine a desired section of the sacrificial layer 106 and it may be circular or conical, for example. The trench pattern 300 defines a boundary that may enclose a cavity area of a micro-electromechanical system apparatus within the trench pattern 300 as already explained in association with Figs. 1A-1K.

[0062] Fig. 5B shows an example of how the barrier structure 116 of the trench 108 may be formed. The barrier structure comprises wall arrangement 506 that is resistive and / or immune to an etching process that is directed material of the sacrificial layer 106 at least part of which is removed by the etching process of the manufacturing process. The wall arrangement 506 may be formed by modifying a surface structure of the sacrificial layer 106 of the trench 108. Alternatively, an etchant resistive wall arrangement 506 may be added to the trench 108. The adding may be performed by deposition, for example. In an embodiment, the resistive wall arrangement may be thin, with a thickness of be 50- 200 nm, for example.As shown in Fig. 5C, a refill layer 111 of polysilicon or the like may be deposited on the stack 500. In that manner, the trench 108 may be refilled as already explained in association with Fig. 1C.

[0063] As shown in Fig. 5D, the refill layer 111 that refills the trench 108 may be planarized. The planarization may be performed by a chemical mechanical polishing (CMP), for example, which the person skilled in the art is familiar with.

[0064] In an embodiment, the planarization may be performed by an etch-back procedure which refers to etching a certain depth in a controlled manner. However, the etch-back procedure may produce a shallow recess at the trench 108 depending upon the over-etch process. The CMP process is preferred for its characteristic negligible recess but may not always be required.

[0065] Relating to Figs. 6A and 6B, a cross section of the trench 108 may be rectangular or conical in a view from side. The rectangular cross section means the diameter of the trench is at least approximately constant as a function of depth of the trench 108. The conical cross section means the diameter of the trench 108 may vary linearly or non-linearly as function of the depth. In other words, the profile of the trench 108 may be etched as either a vertical trench such that the cross section is rectangular or a tapered trench such that the cross section varies as a function of the depth. The tapered trench may be more easily filled with polysilicon but does involve some geometric constraints (the trench width, taper, and polysilicon thickness are all inter-related).

[0066] Figure 7A is a flowchart illustrating an embodiment. The flowchart illustrates a first part of a method of fabricating a piezoelectric micromachined ultrasonic transducer.

[0067] In step 700, a first etch stop layer is deposited on a substrate. In step 702, depositing a sacrificial layer on the first etch stop layer to form a layered structure;

[0068] In step 704, forming a trench pattern, a trench 108 of the trench pattern 300 extending through a sacrificial layer 106, to the first etch stop layer and the trench pattern 300 defining a boundary to at least one cavity area 110 of microelectromechanical system apparatus;

[0069] In step 706, depositing a refill 111 in the trench 108 of the trench pattern 300, the refill forming a barrier structure to the trench, the barrier structure being resistive to an etching process of sacrificial material of the layer;

[0070] In step 708, depositing a second etch stop layer on the sacrificial layer and trench pattern.In step 710, etching an opening 114 on the second etch stop layer inside the at least one cavity area.

[0071] In step 712, depositing a layer of sacrificial layer material as a number of horizontal lines each covering the opening 114 and the other end of the horizontal line being outside the at least one cavity area 106.

[0072] In step 714, depositing an third etch stop layer on the second etch stop layer and the horizontal sacrificial layer material lines.

[0073] In step 716, forming at least one hole 120 through the third etch stop layer to horizontal sacrificial layer material line outside the at least one cavity area.

[0074] In step 718, removing sacrificial material of the sacrificial layer from the at least one cavity area through the at least one hole 120 by a process of etching for forming at least one cavity 122 within the layered structure, each of the at least one cavity being laterally confined by the barrier structure.

[0075] In step 720, sealing the cavity by depositing a fourth layer 124 on top of the third etch stop layer.

[0076] Figure 7B is a flowchart illustrating an embodiment. The flowchart illustrates a second part of some further steps of fabricating piezoelectric micromachined ultrasonic transducer.

[0077] In step 722, a first metal electrode is deposited on the fourth layer. In step 724, piezo layer is deposited on top of the first metal electrode. In step 726, the piezo layer is patterned, and a hole is etched through the piezo layer to provide access to the first metal electrode.

[0078] In step 728, a second metal electrode is deposited and patterned on top of the piezo layer.

[0079] In step 730, a protection layer is deposited and patterned on top of the metal electrodes and piezo layer.

[0080] Fig. 8 illustrates an example with a set of membranes, with trench patterns 300. Further, a set of openings 114, holes 120 and horizontal lines connecting the openings and holes are shown (not all marked). As Fig.8 shows, the at least one hole 120 may be connected to more than one opening 114 via more than one horizontal stripes.

[0081] The proposed solution has many advantages over prior art. The cavities are defined with precise dimensions using confined barriers. PMUTs can be constructed with a fourth layer thickness that is both minimal or several micrometers, adjustable, and with improved thickness uniformity (< 50 nm). The spacing between PMUT membranes within an array can be reduced to 2 pm andintersecting cavities can be fabricated. It is also possible to customize the depth of the cavity. A thin layer of materials (about 50 nm) can be used as a sacrificial layer material 116.

[0082] The proposed solution offers a cost-effective method with high yield for fabricating vacuum-sealed cavities, eliminating the need for the wafer bonding process. This approach allows for the creation of PMUTs with cavity dimensions ranging from small to large on a single wafer. Additionally, cavities of various shapes and sizes can be fabricated, partly due to the sub-micron narrow barrier. In an embodiment, the method can be scaled to four to six to eight to twelve inch wafers. Using a low-temperature fabrication method enables the fabrication of PMUTs within application-specific integrated circuit (ASIC) wafers.

[0083] The steps and related functions described in the above and attached figures are in no absolute chronological order, and some of the steps may be performed simultaneously or in an order differing from the given one. Other functions can also be executed between the steps or within the steps. Some of the steps can also be left out or replaced with a corresponding step.

[0084] It will be obvious to a person skilled in the art that, as the technology advances, the inventive concept can be implemented in various ways. The invention and its embodiments are not limited to the examples described above but may vary within the scope of the claims.

Claims

Claims1. A method of fabricating a piezoelectric micromachined ultrasonic transducer, comprisingdepositing (700) a first etch stop layer (104) on a substrate (102); depositing (702) a sacrificial layer (106) on the first etch stop layer (104) to form a layered structure;forming (704) a trench pattern (300), a trench (108) of the trench pattern extending through the sacrificial layer (106), to the first etch stop layer (104) and the trench pattern (300) defining a boundary to at least one cavity area (110) of micro-electromechanical system apparatus;depositing (706) a refill (111) in the trench (108) of the trench pattern (300), the refill forming a barrier structure to the trench, the barrier structure being resistive to an etching process of sacrificial material of the layer;depositing (708) a second etch stop layer (112) on the sacrificial layer and trench pattern;etching (710) an opening (114) on the second etch stop layer (112) above the at least one cavity;depositing (712) a layer of sacrificial layer material (116) as a number of horizontal lines each covering the opening (114) and the other end of the horizontal line not being above the at least one cavity area (110);depositing (714) a third etch stop layer n (118) on the second etch stop layer (112) and the horizontal sacrificial layer material lines (116);forming (716) at least one hole (120) through the third etch stop layer (118) to horizontal sacrificial layer material line (118) not being above the at least one cavity area;removing (718) sacrificial material of the sacrificial layer (116) from the at least one cavity area (110) through the at least one hole (124) by a process of etching for forming at least one cavity (122) within the layered structure, each of the at least one cavity (122) being laterally confined by the barrier structure, sealing (720) the cavity (122) by depositing a fourth layer (124) on top of the third etch stop layer;depositing (722) a first metal electrode on the fourth layer; depositing (724) piezo layer on top of the first metal electrode; pattern (726) the piezo layer and etch a hole through the piezo layer to provide access to the first metal electrode;deposit and pattern (728) a second metal electrode on top of the piezo layer anddeposit and pattern (730) a protection layer on top of the metal electrodes and piezo layer.

2. The method of claim 1, further comprising: performing at least the sealing process in vacuum to create a vacuum in the cavity.

3. The method of claim 1, further comprising:depositing a layer of sacrificial layer material as a number of horizontal lines each having one end at an opening and the other end connected to one or more corresponding horizontal lines.

4. The method of claim 3, further comprising: forming the at least one hole at a point where more than one horizontal line is connected.

5. The method of any preceding claim, further comprising: forming the barrier structure (116) by a thermal oxidation or a deposition process.

6. The method of any preceding claim, wherein the material of the fourth layer is crystalline silicon, poly-crystalline or amorphous silicon, oxides, nitrides, or metals etc. or combination of these.

7. The method of any preceding claim, wherein the material of the sacrificial layer is one of crystalline, amorphous or poly-crystalline silicon, metals like: molybdenum, titanium, Titanium Tungsten or metals that are etched by xenon difluoride.

8. The method of any preceding claim, wherein etching agent utilises in process of etching to remove the sacrificial material includes xenon difluoride.

9. The method of any preceding claim, further comprising: planarizing the filled trench by chemical mechanical polishing after filling the trench with second etch stop layer.

10. The method of any preceding claim, further comprising: the separation of the trenches being at the narrowest 2 pm11. A piezoelectric micromachined ultrasonic transducer, wherein the piezoelectric micromachined ultrasonic transducer is fabricated by the method steps of claim 1.

12. The piezoelectric micromachined ultrasonic transducer of claim 10, wherein the piezoelectric micromachined ultrasonic transducer is additionally fabricated by any of the method steps of claim 2 to 10.

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