Monitoring of integrity of logic components

Abstract

The present invention relates to an electronic device (100) comprising: - one or more logic components (102-1); - for each logic component (102-1), a test interface (106-1) designed to: receive input data (TDI1), transmit the input data (TDM) to the logic component (102-1) so that the latter delivers output data (TDO1), and deliver an output physical signal (S[TDO1]), such as a square-wave electrical signal for example, transporting the output data (TDO1). The electronic device (100) further comprises, for each test interface (106-1), a monitoring module (108-1) designed to: - receive the output physical signal (S[TDO1]) delivered by the test interface (106-1), and - deliver a response (R1) dependent on physical characteristics of the received output physical signal (S[TDO1]).

Description

Description TDTRE: INTEGRITY MONITORING OF LOGIC COMPONENTS Technical field of the invention

[0001] The present invention relates to the integrity monitoring of logic components. More specifically, the present invention relates to an electronic device and an aircraft comprising such an electronic device. Technological background

[0002] An electronic device of the type comprising: is known from the prior art. one or more logical components; an electronic circuit to which the logic component(s) are connected, to exchange digital data; For each logic component, a test interface designed to: "interrupt the communication between the logic component and the electronic circuit," "receiving digital input data, » transmit the digital input data to the logic component so that the latter provides digital output data, and ® provide a physical output signal, such as an electrical square wave signal, carrying the digital output data; in which, in the case of multiple test interfaces, the test interfaces are connected one after the other in a chain.

[0003] In particular, the test interface(s) may conform to the JTAG standard (Joint Test Action Group). The JTAG standard specifically requires that, in the case of multiple logic components, the test interfaces be connected one after the other in a chain.

[0004] The digital input data can, for example, be software intended to be loaded into one of the logic components, or a configuration in the case of an FPGA logic component (from the English "Field-Programmable Gate Array").

[0005] Another use of JTAG test interfaces is to observe internal states of logic components during their operation.

[0006] JTAG test interfaces can also be used for their primary function: testing the internal and external connections of logic components to detect electrical faults such as short circuits or open circuits. This connection test thus verifies the physical integrity of the logic components. This test is typically performed by sending initial digital data, often generated during the design phase of the electronic device, to the first test interface in the chain. The output data of each logic component is then used as input data for the next interface. The output data at the end of the chain is then compared to a reference to detect a faulty connection if there is a difference.

[0007] Furthermore, tests of the internal and external connections of the logic components can also be carried out by radiographic analysis of these connections.

[0008] Thus, the connection test performed through JTAG test interfaces could be used to detect an attack intentionally modifying the response of one of the logical components to the input digital data provided to it. Indeed, in this case, the output digital data at the end of the chain would differ from the expected reference.

[0009] However, this would be ineffective in detecting attacks that do not alter the operation of the logical components, and therefore the responses to the input numerical data provided to them.

[0010] It may therefore be desirable to provide an electronic device that makes it possible to overcome at least some of the aforementioned problems and constraints. Summary of the invention

[0011] Therefore, an electronic device is proposed comprising: one or more logical components; an electronic circuit to which the logic component(s) are connected, for exchanging digital data; for each logic component, a test interface designed to: • interrupt the exchanges of the logic component with the electronic circuit, • receive digital input data, • transmit the digital input data to the logic component so that the latter provides digital output data, and • provide a physical output signal, such as an electrical square wave signal, carrying the digital output data; wherein, in the case of more than one test interface, the test interfaces are connected one after the other in a chain; characterized in that it comprises, for each test interface, a monitoring module designed to: • receive the physical output signal provided by the test interface, and • provide a response dependent on physical characteristics of the received physical output signal undetectable in the transported digital output data; and in that, in the case of several logic components, the digital input data received by each test interface after the first test interface, are derived from the response of the monitoring module of the previous test interface, for example taken equal to that response.

[0012] Undetectable physical characteristics are those present in the physical signal but lost in the transmitted digital data. In other words, two signals can have different physical characteristics but still carry the same digital data. Thus, thanks to the invention, it is possible to detect attacks that would not modify the digital output data of each logic component, but would modify the physical signal carrying this digital output data.

[0013] This is the case, for example, with an attack that would involve altering the temperature of logic components, such as heating them to such an extent that they deviate from their nominal operating point, thus leading to a failure of logic component integrity. Indeed, this temperature change would modify the physical characteristics of the physical signal (such as a voltage variation, an increase in leakage currents, a timing problem, etc.), which can be detected by the monitoring module, even if the encoded bits remain unchanged.

[0014] Another example of an attack could be the replacement of one of the logic components with a compromised logic component that performs the same operations, but also malicious actions, such as transmitting digital data outside the electronic device. This attack would not be detectable by simply analyzing the digital output data, but could be detected due to a change in the physical signal carrying this digital output data, resulting from the compromised logic component having different physical characteristics than the original logic component.

[0015] The invention may further include one or more of the following optional features, in any technically feasible combination.

[0016] Optionally, each monitoring module includes an element designed to implement a physically non-reproducible function.

[0017] Optionally, each monitoring module also includes a digital filter designed to remove one or more predefined bits from a digital response of the element designed to implement the physically non-reproducible function, in order to provide the response of the monitoring module.

[0018] Optionally, the response provided by each monitoring module also depends on the digital output data carried by the physical output signal.

[0019] Optionally, the electronic device also includes, for each test interface, a hash module designed to: - receive the response provided by the identification module, and - provide a fingerprint of the response; and, in the case of several logic components, the digital input data of each test interface after the first test interface, is the fingerprint of the hash module of the previous test interface.

[0020] Optionally, the electronic device also includes a test module with a memory in which initial digital data and, for at least one test interface, a reference are stored, the test module being designed to: - provide the initial digital data to the test interface or, in the case of several logic components, to the first test interface; and - for each test interface for which a reference is stored: receive an integrity measurement from the digital response provided by the monitoring module of the test interface in question, and compare each received integrity measurement to the corresponding digital reference.

[0021] Optionally, for each test interface for which a reference is recorded, each integrity measure is formed from the fingerprint provided by the monitoring module of the test interface in question.

[0022] Optionally, the electronic device also includes a printed circuit board bearing: the logic component(s), the electronic circuit and the test interface(s).

[0023] Optionally, the printed circuit board also carries the test module, or the printed circuit board also carries an interface to which the test module, separate from the printed circuit board, is designed to be connected, in order to provide the initial digital data and receive the integrity measurement(s) through the interface.

[0024] Optionally, the electronic device also includes an interface carried by the printed circuit board, and the test module is separate from the printed circuit board and designed to be connected to the interface to provide the initial digital data and receive the integrity measurement(s) through the interface.

[0025] An aircraft incorporating an electronic device according to the invention is also proposed. Brief description of the figures

[0026] The invention will be better understood with the aid of the following description, given solely by way of example and made with reference to the accompanying drawings in which: Figure 1 is a schematic view of a first electronic device according to the invention, Figure 2 is a schematic view of a second electronic device according to the invention. Figure 3 is a schematic view of a third electronic device according to the invention. Figure 4 is a schematic view of a third electronic device according to the invention, and Figure 5 is a block diagram of an example implementation of the invention. Detailed description of the invention

[0027] With reference to figure 1, a first electronic device 100 according to the invention will now be described.

[0028] The first electronic device 100 includes first of all a logic component 102-1, for example one of: a system-on-chip (SoC), a general-purpose processor (GPP), and a field-programmable gate array (FPGA).

[0029] The first electronic device 100 further includes an electronic circuit 104 to which the logic component 102-1 is connected for exchanging digital data. The electronic circuit 104 may include conductive traces and possibly other electronic components.

[0030] The first electronic device 100 also includes a test interface 106-1 for the logic component 102-1. The test interface 106-1 is, for example, compliant with the JTAG standard (from the English "Joint Test Action Group").

[0031] The test interface 106-1 is primarily designed to interrupt communication between the logic component 102-1 and the electronic circuit 104. For example, in the case of a JTAG test interface 106-1, it can be placed in boundary-scan mode. With communication interrupted, the test interface 106-1 is further designed to receive digital input data TDI1 and to transmit this input data to the logic component 102-1 so that the latter can provide digital output data TDO1 in response. The test interface 106-1 is then designed to provide a physical output signal S[TDO1] carrying the digital output data TDO1.

[0032] The physical output signal S[TDO1] is, for example, an electrical signal, typically a square wave to carry a binary train. Thus, the physical output signal S[TDO1] has physical characteristics that depend on one or more environmental parameters of the logic component 102-1, for example, the ambient temperature of the logic component 102-1, these environmental parameters being variable.

[0033] Such physical characteristics include, for example, in the case where the physical output signal S[TDO1] is square: a high value, a low value, a rising edge duration to go from the low value to the high value, and a falling edge duration to go from the high value to the low value.

[0034] The first electronic device 100 further includes a monitoring module 108-1 designed to receive the physical output signal S[TDO1] and, in response, provide a response R1, preferably digital, depending in particular on physical characteristics of the physical output signal S[TDO1] that are undetectable in the digital output data TDO1. Indeed, the same digital output data TDO1 can be represented by slightly different physical output signals. Thus, the monitoring module 108-1 is designed so that the response R1 depends, for example, on one or more of the physical characteristics listed above in the case where the physical output signal S[TDO1] is square wave. The response R1 may also depend on the transmitted digital output data TDO1.

[0035] The 108-1 monitoring module preferably includes a 108'-1 element designed to implement a physically unclonable function (PUF). As is known, the PUF is achieved by incorporating a unique physical structure into the 108'-1 element, for example, by exploiting random and unpredictable physical variations in this structure to generate deterministic and unique digital responses. These variations are introduced during the manufacturing process and are therefore difficult to reproduce exactly, even between physical structures manufactured under identical conditions. Thus, this physical structure is capable of generating unique and unpredictable digital outputs.The implementation of the PUF allows obtaining the following essential properties: - uniqueness of digital outputs thanks to the specificity of the physical structure; - inclonability of the physical structure, of which an exactly identical copy is impossible to reproduce; - repeatability under normal environmental conditions.

[0036] Preferably, the monitoring module 108-1 also includes a digital filter 108”-1 designed to filter a digital output R'1 from the element 108'-1. This is because the digital output R'1 consists of a sequence of bits. However, due to the very design of the element 108'-1, some bits may be highly unstable because they are sensitive to even minor natural variations in the physical output signal S[TDO1]. By "natural," we mean "that which are not the result of an attack." The digital filter 108”-1 is thus designed to remove these unstable bits from the digital output R'1, in order to provide the response R1.An identification of unstable bits can thus, for example, be carried out beforehand, during a design phase of the electronic device 100, by operating the electrical device 100 normally (in particular, in ranges of variation of the characteristics of the physical output signal S[TDO1 considered to be normal) and by identifying the bit or bits of the digital output R'1 which are unstable.

[0037] In one embodiment, the first electronic device 100 comprises a printed circuit board 110 carrying the logic component 102-1, the electronic circuit 104 and the test interface 106-1.

[0038] The R1 response provided by the monitoring module 108-1 can be used to obtain a digital integrity measure MU of the logic component 102-1. For example, as in the illustrated example, the R1 response can itself constitute the integrity measure MH.

[0039] It is thus possible to monitor the logic component 02-1 by providing, as digital input data TD11 of the test interface INT1, predefined initial digital data TDI, and by verifying that the integrity measurement MI1 obtained from the response R1 is identical to an expected reference MH*.

[0040] For this purpose, the first electronic device 100 preferably includes a test module 112 with a memory 114 in which the initial digital data TDI and the reference MI1* are stored. The test module 112 is then designed to first provide the initial digital data TDI to the test interface 106-1. The test module 112 is further designed to receive the integrity measurement MI1 and to compare the integrity measurement MH with the corresponding reference MH*.

[0041] A difference between the MH integrity measurement and the MH* reference therefore indicates that the integrity of the logic component 102-1 is compromised.

[0042] The test module 112 can be, as in the illustrated example, separated from the printed circuit board 110. In this case, the printed circuit board 110 may have an external interface 116 to which the test module 112 is designed to be connected.

[0043] An example of the operation of the first device 100 will now be detailed.

[0044] In this operating example, the physical output signal S[TDO1] is a square wave alternating between a high and a low value. The high value represents a bit with a value of 1 and is generally considered to be a value of the physical output signal S[TDO1] between 0.9 V and 1.2 V. The low value represents a bit with a value of 1 and is generally considered to be a value of the physical output signal S[TDO1] between 0 V and 0.5 V.

[0045] The 108-1 monitoring module is designed so that the response R1 depends on the high value of the output physical signal S[TDO1]. For example, the response R1 takes the following numerical values: R1 =

[0000] when the high value is 0.9 V, R1 =

[0010] when the high value is 1 V, R1 =

[0110] when the high value is 1.1 V, and R1 =

[0001] when the high value is 1.2 V.

[0046] During normal operation of the logic component 102-1, particularly when the logic component 102-1 is operating at a normal operating temperature, it has been found that the high value is 0.9 V. Thus, the expected MH* reference is

[0000] .

[0047] One known possible attack involves increasing the temperature of logic component 102-1. In this case, the high value of the physical output signal S[TDO1] increases slightly, for example to 1.1 V. This increase would be undetectable in the digital output data of TDO1, since the two values ​​0.9 V and 1.1 V would represent the same binary value. However, this change is detected by the monitoring module 108-1, which then provides an R1 response of

[0110] .

[0048] The test module 112 then detects that the integrity measurement Mil (equal to the response R1 in this example) is different from the response MI1* and therefore a possible compromise of the integrity of the logic component 102-1.

[0049] With reference to figure 2, a second electronic device 200 according to the invention will now be described.

[0050] The second electronic device 200 is similar to the first electronic device 100, except that it also includes a hash module 202-1 output from the monitoring module 108-1. The hash module 202-1 is designed to receive the response R1 and to provide a hash E1 of that response R1. For example, the hash module 202-1 is designed to implement one of the secure hashing algorithms SHA-1, SHA-2, or SHA-3. The hash module 202-1 enhances security by strengthening the authenticity of the response R1.

[0051] With reference to figure 3, a third electronic device 300 according to the invention will now be described.

[0052] The third electronic device 300 is similar to the second electronic device 100, except that several logic components 102-1, 102-2 are monitored, all connected to the electronic circuit 104 to exchange digital data.

[0053] In addition, a test interface 106-1, 106-2 like those in Figures 1 and 2 is associated with each of the logic components 102-1, 102-2. Thus, each test interface 106-1, 106-2 is first designed to interrupt the communication of the logic component 102-1, 102-2 associated with the electronic circuit 104. With the communication interrupted, each test interface 106-1, 106-2 is further designed to receive digital input data TDI, TDI2 and to transmit the digital input data TDI1, TDI2 to the associated logic component 102-1, 102-2 so that the latter provides in response digital output data TDO1, TDO2. The test interface 106-1, 106-2 is then designed to provide a physical output signal S[TDO1], S[TDO2] carrying the digital output data TDO1, TDO2. As before, each physical output signal S[TDO1], S[TDO2] is, for example, an electrical signal, typically a square wave to carry a binary stream.

[0054] The test interfaces 106-1, 106-2 are also connected one after the other in a chain.

[0055] In addition, a monitoring module 108-1, 108-2, preferably with an element 108-1, 108'-2 designed to implement a physically non-reproducible function and optionally a digital filter 108'-1, 108'-2, is associated with each test interface 106-1, 106-2, at the latter's output in the chain. Each monitoring module 108-1, 108-2 is thus designed to receive the physical output signal S[TDO1], S[TDO2] from the associated test interface 106-1, 106-2 and, in response, provide the response R1, R2.

[0056] As explained previously, each response R1, R2 depends on physical characteristics of the physical output signal S[TDO1], S[TDO2] and, possibly, the digital output data TDO1, TDO2 carried.

[0057] Furthermore, the TDI2 input digital data of each test interface 106-2 after the first 106-1 is derived from the R1 response of the monitoring module 108-1 associated with the preceding test interface 106-1. For example, this R1 response forms the TDI2 input digital data. Alternatively, as in the illustrated example, a hash module 202-1, 202-2 is provided as the output of each monitoring module 106-1, 106-2, so the TDI2 input digital data is formed from the E1 hash of the R1 response.

[0058] The R2 response provided by the 108-2 monitoring module associated with the last 106-2 test interface in the chain can thus be used to obtain an MI2 integrity measure. For example, the R2 response itself can constitute the MI2 integrity measure. Alternatively, as in the illustrated example, the E2 fingerprint of this R2 response is used as the MI2 integrity measure.

[0059] In addition, each of the other intermediate R1 responses (i.e., provided by the 108-1 monitoring module associated with a 106-1 test interface before the last one) can also be used to obtain an MI1 integrity measure, for example either directly (MI1 = R1), or by using its fingerprint (MI1 = E1) as in the illustrated example.

[0060] With reference to figure 4, a fourth electronic device 300 according to the invention will now be described.

[0061] The fourth electronic device 400 is similar to the third electronic device 300, except that the test module 112 is carried by the printed circuit board 110.

[0062] The presence of the test module 112 on the printed circuit board 110, or more generally in the electronic device 400, allows for the implementation at any time of a verification of the physical integrity of the logic components 102-1, 102-2, in particular at the start-up of the printed circuit board 110 and on demand when the printed circuit board 110 is in operational operation.

[0063] In some embodiments, the test module 112 can be designed to disable the monitoring module(s) 108-1, 108-2 and the hashing module(s) 202-1, 202-2 if present, so that these modules do not modify the digital output data of each test interface 106-1, 106-2.

[0064] Thus, it is possible to use the test interface(s) to load software into one of the logic components (or a configuration in the case of an FPGA logic component), and / or observe internal states of the logic components during their operation, and / or to test internal and external connections of the logic component(s) 102-1, 102-2.

[0065] To perform these operations, the test module 112 then includes an external interface, for example an external JTAG interface, through which external digital input data can be provided to the first test interface 106-1 and through which the digital data provided by the last test interface 106-2 can be exported.

[0066] With reference to Figure 5, an example of implementation of the invention will now be described, in particular in the case where the test module 112 is part of the electrical device 104, for example when the test module 112 is carried by the printed circuit board 110.

[0067] During a manufacturing phase 502, while the electrical component(s) 102-1, 102-2 are in a normal and safe environment, initial digital data (TDI) is provided to the test interface 102-1 or to the first of the test interfaces 102-1, 102-2, and the integrity measurement(s) MH, MI2 are retrieved. The initial digital data (TDI) is stored in memory 114, as is the integrity measurement(s) MH, MI2, as references MH*, MI2*. Furthermore, the digital filters 108”-1, 108”-2 are configured by identifying the unstable bits of the digital outputs R'1, R'2.

[0068] During this manufacturing phase 502, the test module 112 is also, for example, placed in a mode allowing software or FPGA loading, and / or observation of the internal states of the logic components 102-1, 102-2 during their operation, and / or testing of the internal and external connections of the logic components 102-1, 102-2.

[0069] During a 504 logistics phase, the test module 112 is placed in a monitoring mode in which, when the electronic device 400 is powered on (and with it, the test module 112), the test module 112 monitors incoming external digital data to detect if the external digital data is malicious or corresponds to unauthorized operations during that 504 logistics phase, such as the loading of software or an FPGA. In this case, the test module 112 is designed, for example, to block the electronic device 400, for example, by performing a reset, which puts the electronic device 400 into a non-operating mode (i.e., for example, where no services or functions can be activated). This helps to reduce the risk to the integrity of the logic components during the 504 logistics phase.

[0070] During an operational phase 506 or maintenance phase 508, at at least some start-ups of the electronic device 400, the test module 112 first performs an integrity test by providing the initial digital TDI recorded data and comparing the integrity measurement(s) MI1, MI2 with the recorded references MI1*, MI2*.

[0071] If no integrity problems are detected, the test module 12 disables the test interface(s) 106-1, 106-2 and allows the electronic device 400 to start up, so that the logic component(s) 102-1, 102-2 can operate normally by exchanging digital data with the electronic circuit 104 for the performance of intended services.

[0072] In the event of detection of an integrity compromise, the test module 112 performs, for example, one or more of the following actions: blocking the electronic device, alerting a maintenance operator of an integrity fault, starting the electronic device in minimal service (degraded operation).

[0073] In conclusion, it is clear that an electronic device such as those described above makes it possible to detect attacks that do not alter the operation of the logic component(s).

[0074] It should also be noted that the invention is not limited to the embodiments described above. Indeed, it will be apparent to those skilled in the art that various modifications can be made to the embodiments described above, in light of the information just disclosed to them.

[0075] For example, the physical output signal could be a light signal. Furthermore, the digital data could be encoded in the physical signal in a way other than by square waves, for example by phase or frequency modulation.

[0076] In the detailed presentation of the invention given above, the terms used shall not be interpreted as limiting the invention to the embodiments set forth in this description, but shall be interpreted as including all equivalents which can be foreseen by a person skilled in the art by applying their general knowledge to the implementation of the teaching which has just been disclosed to them.

Claims

Demands [1] Electronic device (100; 200; 300; 400) comprising: one or more logical components (102-1, 102-2); an electronic circuit (104) to which the logic component(s) (102-1, 102-2) are connected, for exchanging digital data; for each logic component (102-1, 102-2), a test interface (106-1, 106-2) designed to: • interrupt the communication between the logic component (102-1, 102-2) and the electronic circuit (104), "receive digital input data (TDI1, TDI2), • transmit the input digital data (TDM, TDI2) to the logic component (102-1, 102-2) so that the latter provides output digital data (TDO1, TDO2), and » provide a physical output signal (S[TDO1], S[TDO2]), such as an electrical square wave signal, carrying the digital output data (TDO1, TDO2); wherein, in the case of several test interfaces (106-1, 106-2), the test interfaces (106-1, 106-2) are connected one after the other in a chain; the electronic device (100; 200; 300) being characterized in that it comprises: For each test interface (106-1, 106-2), a monitoring module (108-1, 108-2) designed to: • receive the physical output signal (S[TDO1], S[TDO2]) provided by the test interface (106-1, 106-2), and » provide a response (R1, R2) dependent on physical characteristics of the received output physical signal (S[TDO1], S[TDO2]) undetectable in the output digital data (TDO1, TDO2) carried; and in that, in the case of several logic components (102-1, 102-2), the input digital data (TDI2) received by each test interface (106-2) after the first test interface (106-1), are derived from the response (R1) of the monitoring module (108-1) of the previous test interface (106-1), for example taken equal to this response (R1). [2] Electronic device (100; 200; 300; 400) according to claim 1, wherein each monitoring module (108-1, 108-2) comprises an element (108'-1, 108'-2) designed to implement a physically non-reproducible function. [3] Electronic device (100; 200; 300; 400) according to claim 2, wherein each monitoring module (108-1, 108-2) further comprises a digital filter (08'-1, 108'-2) designed to remove one or more predefined bits from a digital output (R'1, R'2) of the element (108'-1, 108-2) designed to implement the physically non-reproducible function, in order to provide the response (R1, R2) of the monitoring module (108-1, 108-2). [4] Electronic device (100; 200; 300; 400) according to any one of claims 1 to 3, wherein the response (R1, R2) provided by each monitoring module (108-1, 108-2) further depends on the digital output data (TDO1, TDO2) carried by the physical output signal (S[TDO1J, S[TDO2j]. [5] Electronic device (200; 300; 400) according to any one of claims 1 to 4, further comprising, for each test interface (106-1, 106-2), a hash module (202-1, 202-2) designed to: receive the response (R1, R2) provided by the identification module (108-1, 108-2), and provide a fingerprint (E1, E2) of the response (R1, R2); and in which, in the case of several logical components (102-1, 102-2), the digital input data (TDI2) of each test interface (106-2) after the first test interface (106-1), are the fingerprint (E1) of the hash module (202-1) of the previous test interface (106-1). [6] Electronic device (200; 300; 400) according to any one of claims 1 to 5, further comprising a test module (112) having a memory (114) in which initial digital data (TDi) are stored and, for at least one test interface (106-1, 106-2), a reference (MH*, MI2*), the test module (112) being designed to: provide the initial digital data (TDI) to the test interface (106-1) or, in the case of multiple logic components (102-1, 102-2), to the first test interface (106-1); and for each test interface (106-1, 106-2) for which a reference (E1*, E2*) is registered: "receive an integrity measure (MI1, MI2) from the response (R1, R2) provided by the monitoring module (108-1, 108-2) of the test interface (106-1, 106-2) under consideration, and compare each integrity measure (MI1, MI2) received to the corresponding reference (MH*, MI2*). [7] Electronic device (200; 300; 400) according to claims 5 and 6, wherein, for each test interface (106-1, 106-2) of which a reference (E1*, E2*) is recorded, each integrity measure (MH, MI2) is formed from the fingerprint (E1, E2) provided by the monitoring module (108-1, 108-2) of the test interface (106-1, 106-2) considered. [8] Electronic device (100; 200; 300; 400) according to any one of claims 1 to 7, further comprising a printed circuit board (110) carrying: the logic component(s) (102-1, 102-2), the electronic circuit (104) and the test interface(s) (06-1, 106-2). [9] Electronic device (400) according to claims 6 and 8 sockets together, wherein the printed circuit board (110) further carries the test module (112), or wherein the printed circuit board (110) further carries an interface (116) to which the test module (112), separate from the printed circuit board (110), is designed to be connected, in order to provide the initial digital data (TDI) and receive the integrity measurement(s) (MH, MI2) through the interface (116). [10] Aircraft comprising an electronic device (100; 200; 300; 400) according to any one of claims 1 to 9.

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