Method for forming metal oxide layer, metal oxide layer, and semiconductor device

Abstract

Provided is a metal oxide layer having high carrier mobility. This method for forming a metal oxide layer comprises: a first step for forming a seed layer on an insulating layer; a second step for forming a metal oxide layer containing indium on the seed layer; and a third step for performing a microwave plasma treatment so that the concentration of hydrogen increases from the top surface to the bottom surface of the metal oxide layer. In the third step, a first crystal growth occurs from the top surface toward the bottom surface of the metal oxide layer in a region of the metal oxide layer not overlapping the seed layer, and a second crystal growth occurs from the bottom surface toward the top surface of the metal oxide layer in a region of the metal oxide layer overlapping the seed layer.

Description

Method for forming a metal oxide layer, metal oxide layer, semiconductor device

[0001] One aspect of the present invention relates to a metal oxide layer and a method for forming a metal oxide layer. Another aspect of the present invention relates to a semiconductor device, a memory device, a display device, and an electronic device having a metal oxide layer.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. Examples of technical fields of one aspect of the present invention disclosed herein include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, methods for driving them, or methods for manufacturing them. A semiconductor device refers to any device that can function by utilizing semiconductor properties.

[0003] In recent years, the development of semiconductor devices has progressed, and these devices are mainly used in LSIs (Large Scale Integration), CPUs (Central Processing Units), and memory. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (circuits with at least transistors) formed on chips by processing semiconductor wafers, and electrodes that serve as connection terminals are formed on them.

[0004] Semiconductor circuits (IC chips) such as LSIs, CPUs, and memory are mounted on circuit boards, such as printed circuit boards, and used as components in various electronic devices.

[0005] Furthermore, the technology of constructing transistors using semiconductor thin films formed on substrates with insulating surfaces is attracting attention. These transistors are widely applied in electronic devices such as integrated circuits and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors are attracting attention as other materials.

[0006] Transistors using oxide semiconductors are known to have extremely low leakage current in the non-conductive state. For example, Patent Document 1 discloses a low-power CPU that utilizes the characteristic of low leakage current of transistors using oxide semiconductors. Patent Document 2 also discloses a memory device that uses oxide semiconductors and can retain stored data for a long period of time.

[0007] Non-patent document 1 states In ２ O ３ Its use in thin-film transistors has been reported.

[0008] Japanese Patent Publication No. 2012-257187 Japanese Patent Publication No. 2011-151383

[0009] Dhananjay and C. W. Chu, “Realization of In2O3 thin film transistors through reactive evaporation process,” Appl. Phys. Lett. 91, 132111 (2007). Takashi Koida, “High-mobility transparent conductive film,” National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Presentation Meeting 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0010] One aspect of the present invention aims to provide a metal oxide layer with high carrier mobility. Another aspect of the present invention aims to provide a novel metal oxide layer. Another aspect of the present invention aims to provide a transistor, semiconductor device, or memory device to which a metal oxide layer is applied.

[0011] One aspect of the present invention aims to provide a transistor with good electrical characteristics. One aspect of the present invention aims to provide a transistor with a large on-current. One aspect of the present invention aims to provide a transistor with low parasitic capacitance. One aspect of the present invention aims to provide a semiconductor device having a transistor with excellent characteristics. One aspect of the present invention aims to provide a semiconductor device with excellent characteristics. One aspect of the present invention aims to provide a highly reliable transistor, semiconductor device, display device, or memory device. One aspect of the present invention aims to provide a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated. One aspect of the present invention aims to provide a semiconductor device, display device, or memory device with low power consumption. One aspect of the present invention aims to provide a memory device with a fast operating speed. One aspect of the present invention aims to provide a semiconductor device with a high degree of freedom in transistor arrangement.

[0012] One aspect of the present invention aims to provide a semiconductor device having a novel configuration. Another aspect of the present invention aims to mitigate at least one of the problems of the prior art.

[0013] Furthermore, the description of these problems does not preclude the existence of other problems. Moreover, one aspect of the present invention does not need to solve all of these problems. Other problems can be identified from the description in the specification, drawings, claims, etc.

[0014] One aspect of the present invention is a method for forming a metal oxide layer, comprising: a first step of forming a seed layer on an insulating layer; a second step of forming a metal oxide layer containing indium on the seed layer; and a third step of performing microwave plasma treatment so that the hydrogen concentration increases from the upper surface to the lower surface of the metal oxide layer.

[0015] Furthermore, one aspect of the present invention is a method for forming a metal oxide layer, comprising the first step of forming a seed layer on an insulating layer, the second step of forming a metal oxide layer on the seed layer, and the third step of performing microwave plasma treatment, wherein in the second step, a first metal oxide layer, a second metal oxide layer, and a third metal oxide layer, each containing indium, are stacked in this order to form a metal oxide layer, and microwave plasma treatment is performed such that the hydrogen concentration of the third metal oxide layer is lower than the hydrogen concentration of the first metal oxide layer.

[0016] In the above-described method for forming a metal oxide layer, it is preferable to introduce hydrogen gas, oxygen gas, and argon gas when performing microwave plasma treatment.

[0017] In the above method for forming the metal oxide layer, the insulating layer is provided on a substrate, and it is preferable that the temperature of the substrate during microwave plasma treatment be 150°C or higher and 180°C or lower.

[0018] In the above-described method for forming a metal oxide layer, in the second step, a metal oxide layer is formed on the insulating layer, covering the seed layer, and in the third step, it is preferable that first crystal growth occurs in the region of the metal oxide layer that does not overlap with the seed layer, moving from the top surface to the bottom surface of the metal oxide layer.

[0019] In the above method for forming a metal oxide layer, in the third step, it is preferable that a second crystal growth occurs in the region of the metal oxide layer that overlaps with the seed layer, moving from the bottom surface to the top surface of the metal oxide layer.

[0020] In the above method for forming a metal oxide layer, it is preferable that the seed layer has a hexagonal or trigonal crystal structure, and the metal oxide layer has a bixbite-type crystal structure.

[0021] In the above method for forming the metal oxide layer, it is preferable that the upper surface of the seed layer is the {001} plane.

[0022] In the above method for forming the metal oxide layer, it is preferable that the first crystal growth direction and the second crystal growth direction each coincide with the <001> orientation of the seed layer.

[0023] In the above method for forming a metal oxide layer, it is preferable that the seed layer contains indium, gallium, zinc, and oxygen.

[0024] In the above method for forming the metal oxide layer, it is preferable that the seed layer and the metal oxide layer each have a bixbite-type crystal structure.

[0025] In the above method for forming the metal oxide layer, it is preferable that the upper surface of the seed layer is a {111} plane.

[0026] In the above method for forming the metal oxide layer, it is preferable that the first crystal growth direction and the second crystal growth direction each coincide with the <111> orientation of the seed layer.

[0027] Another aspect of the present invention is a metal oxide layer containing indium. The metal oxide layer has a concentration gradient in which the hydrogen concentration increases from the top surface to the bottom surface. The metal oxide layer has crystal grains whose crystal structure is of the bixbite type. The top surface of the crystal grains is a {111} plane.

[0028] Another aspect of the present invention is a metal oxide layer having a first metal oxide layer, a second metal oxide layer on the first metal oxide layer, and a third metal oxide layer on the second metal oxide layer. Each of the first to third metal oxide layers contains indium. The third metal oxide layer has a region with a lower hydrogen concentration than the first metal oxide layer. The metal oxide layer has crystal grains with a bixbite crystal structure. The upper surface of the crystal grains is a {111} plane.

[0029] In the above-mentioned metal oxide layer, it is preferable that the crystal grains include a part of the first metal oxide layer, a part of the second metal oxide layer, and a part of the third metal oxide layer.

[0030] Another aspect of the present invention is a semiconductor device having the above-mentioned metal oxide layer, a conductive layer, and an insulating layer having a portion located between the metal oxide layer and the conductive layer.

[0031] According to one aspect of the present invention, a metal oxide layer with high carrier mobility can be provided. According to one aspect of the present invention, a novel metal oxide layer can be provided. According to one aspect of the present invention, a transistor, semiconductor device, or memory device to which a metal oxide layer is applied can be provided.

[0032] According to one aspect of the present invention, a transistor with good electrical characteristics can be provided. According to one aspect of the present invention, a transistor with a large on-current can be provided. According to one aspect of the present invention, a transistor with low parasitic capacitance can be provided. According to one aspect of the present invention, a semiconductor device having a transistor with excellent characteristics can be provided. According to one aspect of the present invention, a semiconductor device having excellent characteristics can be provided. According to one aspect of the present invention, a highly reliable transistor, semiconductor device, display device, or memory device can be provided. According to one aspect of the present invention, a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated can be provided. According to one aspect of the present invention, a semiconductor device, display device, or memory device with low power consumption can be provided. According to one aspect of the present invention, a memory device with a fast operating speed can be provided. According to one aspect of the present invention, a semiconductor device with a high degree of freedom in transistor arrangement can be provided.

[0033] According to one aspect of the present invention, a semiconductor device having a novel configuration can be provided. According to one aspect of the present invention, at least one of the problems of the prior art can be mitigated.

[0034] Furthermore, the description of these effects does not preclude the existence of other effects. Moreover, one aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description in the specification, drawings, claims, etc.

[0035] Figures 1A, 1B, 1C, 1D, and 1E show examples of methods for forming a metal oxide layer. Figures 2A, 2B, 2C, and 2D show examples of methods for forming a metal oxide layer. Figures 3A, 3B, and 3C show examples of methods for forming a metal oxide layer. Figures 4A and 4B show examples of methods for forming a metal oxide layer. Figure 5 is a top view illustrating a microwave plasma processing apparatus. Figure 6 is a cross-sectional view illustrating a microwave plasma processing apparatus. Figure 7 is a cross-sectional view illustrating a microwave plasma processing apparatus. Figure 8 is a cross-sectional view illustrating a microwave plasma processing apparatus. Figures 9A, 9B, and 9C show examples of semiconductor device configurations. Figures 10A and 10B show examples of semiconductor device configurations. Figures 11A and 11B show examples of semiconductor device configurations. Figures 12A, 12B, and 12C show examples of semiconductor device configurations. Figures 13A and 13B show examples of semiconductor device configurations. Figures 14A, 14B, and 14C show examples of semiconductor device configurations. Figure 15 is a diagram showing an example of the configuration of a semiconductor device. Figures 16A and 16B are diagrams showing an example of the configuration of a semiconductor device. Figures 17A and 17B are diagrams showing an example of the configuration of a semiconductor device. Figures 18A, 18B, and 18C are diagrams showing an example of the configuration of a semiconductor device. Figures 19A, 19B, and 19C are diagrams showing an example of the configuration of a semiconductor device. Figures 20A, 20B, 20C, 20D, and 20E are diagrams showing an example of the configuration of a semiconductor device. Figures 21A, 21B, 21C, 21D, 21E, and 21F are diagrams showing an example of the configuration of a semiconductor device. Figures 22A and 22B are diagrams showing an example of the configuration of a semiconductor device. Figure 23 is a diagram showing an example of the configuration of a semiconductor device. Figures 24A and 24B are diagrams illustrating the carrier concentration dependence of hole mobility. Figure 24C is a cross-sectional view illustrating an indium oxide film. Figure 25 is a diagram showing an example of the configuration of a memory device. Figures 26A and 26B are diagrams showing an example of the configuration of a memory device. Figures 27A, 27B, 27C, and 27D show examples of storage device configurations. Figure 28 shows an example of storage device configuration. Figures 29A and 29B show examples of display device configurations. Figure 30 shows an example of display device configuration.Figures 31A, 31B, 31C, and 31D show examples of the configuration of electronic equipment. Figures 32A, 32B, 32C, 32D, 32E, and 32F show examples of the configuration of electronic equipment. Figures 33A, 33B, 33C, 33D, 33E, 33F, and 33G show examples of the configuration of electronic equipment. Figures 34A and 34B show examples of the configuration of electronic components. Figures 35A, 35B, and 35C show examples of the configuration of a large computer. Figures 36A and 36B are perspective views of semiconductor equipment. Figure 37 is a perspective view of semiconductor equipment. Figures 38A and 38B show the models used in the calculations. Figure 38C is a diagram illustrating the temperature conditions in the calculations. Figures 39A, 39B, 39C, 39D, 39E, and 39F show the calculation results. Figures 40A, 40B, 40C, 40D, and 40E show the calculation results. Figure 41 shows the hydrogen concentration dependence of the similarity.

[0036] The embodiments will be described below with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different ways, and their form and details can be modified in various ways without departing from the spirit and scope thereof. Accordingly, the present invention shall not be construed as being limited to the contents of the following embodiments.

[0037] In the invention described below, the same reference numerals are used in common across different drawings for identical parts or parts having similar functions, and repeated explanations are omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used, and reference numerals may not be assigned.

[0038] In the figures described herein, the size of each component, the thickness of the layers, or the area may be exaggerated for clarity. Therefore, the scale is not necessarily limited to those figures.

[0039] Furthermore, ordinal numbers such as "first," "second," etc., used in this specification are added to avoid confusion of constituent elements and do not limit them numerically. In addition, the ordinal numbers used for constituent elements in one part of this specification may not be the same as the ordinal numbers used for those constituent elements in other parts of this specification or in the claims.

[0040] A transistor is a type of semiconductor device that can perform functions such as amplifying current or voltage, and switching operations that control conduction or non-conductivity. Transistors as used herein include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs).

[0041] Furthermore, the functions of "source" and "drain" may be reversed when transistors with different polarities are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" may be used interchangeably.

[0042] Furthermore, in this specification, "electrically connected" includes cases where a connection is made via "something that has some kind of electrical function." Here, "something that has some kind of electrical function" is not particularly limited as long as it enables the exchange of electrical signals between the connected objects. For example, "something that has some kind of electrical function" includes electrodes or wiring, switching elements such as transistors, resistive elements, coils, and other elements with various functions.

[0043] In this specification, cases where two nodes are connected via an insulator, such as the dielectric of a capacitive element, the gate insulating film of a transistor, or an interlayer insulating film, are not included in the definition of "electrical connection."

[0044] In this specification, "heights match" refers to a configuration in which the heights from a reference surface (for example, a flat surface such as the substrate surface) are equal in a cross-sectional view. For example, if there are two layers with different heights (here referred to as layer A and layer B) with respect to the reference surface, the heights also match if the difference between the height of the top surface of layer A and the height of the top surface of layer B is 10 nm or less.

[0045] In this specification, "side edges coincide" means that, in a plan view, at least a portion of the contours of the stacked layers overlap. For example, in the case of two stacked layers (here referred to as layer A and layer B), if the shortest distance from the side edge of layer A to the side edge of layer B in a plan view is 10 nm or less, then the side edges also coincide.

[0046] In general, it can be difficult to clearly distinguish between "exact match" and "approximate match." Therefore, in this specification, "match" may include both exact matches and approximate matches.

[0047] In this specification, the top surface shape of a component refers to the contour shape of that component in a plan view. A plan view refers to a view from the direction normal to the surface on which the component is formed, or to the surface of the support (e.g., substrate) on which the component is formed.

[0048] In the following, expressions indicating direction, such as "up" and "down," will generally be used in accordance with the orientation shown in the drawings. However, for the purpose of simplifying explanations, the direction referred to as "up" or "down" in the specification may not always coincide with that of the drawings. For example, when explaining the stacking order (or formation order) of a laminate, even if the side on which the laminate is provided (the surface to be formed, the support surface, the adhesive surface, the flat surface, etc.) is located above the laminate in the drawing, the surface to be formed may be described as "down" and the laminate side as "up."

[0049] Furthermore, in this specification, the terms "film" and "layer" are interchangeable. For example, the term "insulating layer" may be interchangeable with the term "insulating film."

[0050] Furthermore, unless otherwise specified in this specification, off-current refers to the drain current when the transistor is in the off state (also called the non-conducting state or cutoff state). Unless otherwise specified, the off state refers to the state in an n-channel transistor where the voltage Vgs between the gate and source is lower than the threshold voltage Vth (in a p-channel transistor, it is higher than Vth).

[0051] In this specification, space groups are expressed using international notation (or Hermann-Mauguin notation) in short notation. Crystal planes and crystal orientations are expressed using Miller indices. In crystallography, space groups, crystal planes, and crystal orientations are expressed by superscripting numbers, but in this specification, due to formatting constraints, a minus sign (-) may be placed before the number instead of a superscript. Individual orientations within a crystal are represented by [ ], collective orientations representing all equivalent orientations are represented by < >, individual crystal planes are represented by ( ), and collective planes with equivalent symmetry are represented by {}.

[0052] (Embodiment 1) In this embodiment, a metal oxide according to one aspect of the present invention and a method for forming a layer having the metal oxide (also called a metal oxide layer) will be described with reference to Figures 1A to 4B.

[0053] A metal oxide according to one aspect of the present invention can be used, for example, in the semiconductor layer of a transistor. In this case, since the metal oxide functions as a semiconductor, it can be referred to as an oxide semiconductor. Furthermore, depending on the type, combination, and composition of the elements constituting the metal oxide, the metal oxide according to one aspect of the present invention can also be used as a conductive material, a semiconductor material, or an insulating material.

[0054] The metal oxide layer is preferably crystalline. For example, the metal oxide layer is preferably crystalline. The grain size of the crystal grains in the metal oxide layer is preferably, for example, 10 nm to 1 μm, 10 nm to 0.5 μm, or 10 nm to 100 nm. Alternatively, it is preferably 50 nm to 1 μm, 50 nm to 0.5 μm, or 50 nm to 100 nm. By forming the semiconductor layer of a transistor using a crystalline metal oxide layer, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved. The grain size of the crystal grains can be calculated, for example, by calculating the area of ​​the crystal grains and assuming a perfect circle corresponding to the calculated area. This diameter is sometimes called the area circle equivalent diameter.

[0055] One embodiment of the present invention provides a metal oxide containing indium. The higher the indium content in the metal oxide, the more impurity scattering or ion scattering can be reduced, thereby increasing the field-effect mobility of a transistor having the metal oxide in its semiconductor layer. As a result, the transistor can achieve a large on-current and high frequency characteristics.

[0056] The crystal grains of the metal oxide layer contain indium and oxygen. By increasing the indium content in the crystal grains, the crystal structure of the crystal grains becomes cubic, specifically bixbite type. For the metal oxide layer to have crystal grains with a cubic crystal structure, the indium content in the crystal grains should be 70% to 100%, preferably 80% to 100%, more preferably 90% to 100%, and even more preferably 95% to 100%.

[0057] In this specification, the content of a metal element in a metal oxide refers to the ratio of the number of atoms of that element to the total number of atoms of that metal element contained in the metal oxide. For example, if a metal oxide contains metal elements X, Y, and Z, then the number of atoms of each of metal elements X, Y, and Z contained in the metal oxide is A. Ｘ A Ｙ A Ｚ In this case, the content of metal element X is A Ｘ / (AＸ +A Ｙ +A Ｚ It can be represented by). Further, the atomic ratio (atomic number ratio) of each of the metal elements X, Y, and Z in the metal oxide is B Ｘ :B Ｙ :B Ｚ When represented by, the content of the metal element X is B Ｘ / (B Ｘ +B Ｙ +B Ｚ ).

[0058] In addition, the metal oxide layer can contain other elements as long as the crystal structure of the crystal grains retains the cubic system. For example, the metal oxide layer can contain a first element in addition to indium. Examples of the first element include one or more selected from tin, zinc, antimony, copper, cobalt, and gallium. The content of the first element in the crystal grains is preferably 0.1% or more and less than 30%, more preferably 0.1% or more and less than 20%, still more preferably 0.1% or more and less than 10%, and even more preferably 0.1% or more and less than 5%. When element Mx1 and element Mx2 are selected as the first element, the content of the first element in the crystal grains can be calculated as the sum of the content of element Mx1 and the content of element Mx in the crystal grains. By adding an element (for example, tin, antimony, and cobalt) that can become a cation of tetravalent or higher to indium oxide, the atoms of the added element are substituted for indium atoms and one or more electrons remain, and the carrier concentration of the metal oxide layer can be increased. Further, by adding an element (for example, zinc and copper) that can become a cation of divalent or lower to indium oxide, the atoms of the added element are substituted for indium atoms and one or more electrons are lacking, and the carrier concentration of the metal oxide layer can be reduced. Further, by adding an atom (for example, gallium) that can become a trivalent cation to indium oxide, it is possible to suppress the formation of oxygen deficiency in the metal oxide layer while maintaining the carrier concentration of the metal oxide layer.

[0059] The metal oxide layer according to one aspect of the present invention may have a single-layer structure or a laminated structure of two or more layers. For example, the metal oxide layer may have a three-layer structure comprising a first metal oxide layer, a second metal oxide layer on the first metal oxide layer, and a third metal oxide layer on the second metal oxide layer.

[0060] Preferably, each of the first to third metal oxide layers contains indium.

[0061] As the second metal oxide layer, an oxide containing the aforementioned first element can also be used in addition to indium.

[0062] The first metal oxide layer may contain a second element, in addition to indium, which has a stronger bonding force with oxygen than indium. By containing the second element in the first metal oxide layer, oxygen vacancies (V) are created in the first metal oxide layer. Ｏ ) and defects in which hydrogen enters the oxygen vacancy (V Ｏ This can suppress the formation of H.

[0063] As the second element, one or more selected from, for example, gallium, aluminum, yttrium, scandium, titanium, tungsten, molybdenum, tin, zirconium, hafnium, and tantalum can be used. The second element is preferably one or more selected from gallium, aluminum, scandium, and yttrium, more preferably gallium or aluminum, and even more preferably gallium.

[0064] Gallium, aluminum, yttrium, and scandium primarily exist as trivalent cations, similar to indium atoms. Therefore, by using gallium, aluminum, yttrium, or scandium as the second element, the carrier concentration of the first metal oxide layer can be kept low.

[0065] Gallium is preferred because it has a strong bonding affinity with oxygen, and the bond length with oxygen is close to that of indium. Scandium and yttrium are also preferred because their oxides can take the same bixbite form as indium oxide, making it easier to maintain crystal structure even when increasing their content.

[0066] Furthermore, titanium and tungsten have a stronger bonding force with oxygen compared to molybdenum and tin. Therefore, when titanium or tungsten is used as the second element, the amount of V in the first metal oxide layer is greater than when molybdenum or tin is used. Ｏ and V Ｏ The formation of H can be suppressed. On the other hand, molybdenum and tin have bond lengths with oxygen that are closer to the bond length between indium and oxygen compared to titanium and tungsten. Therefore, when molybdenum or tin is used as the second element, it is easier to maintain the crystal structure of the first metal oxide layer even if the content of the second element in the first metal oxide layer is higher than when titanium or tungsten is used.

[0067] When the first metal oxide layer contains a second element, the content of the second element in the first metal oxide layer is preferably 0.1% or more and 5% or less. For example, when indium oxide containing gallium is used as the first metal oxide layer, the gallium content is preferably 0.1% or more and 5% or less. This allows V to be present in the metal oxide layer. Ｏ and V Ｏ This makes it possible to suppress the formation of H and easily realize a normally-off transistor.

[0068] The third metal oxide layer may contain a second element in addition to indium. Specific examples of the second element can be found in the description above.

[0069] The metal oxide layer may have a two-layer structure consisting of a first metal oxide layer and a second metal oxide layer on the first metal oxide layer, or it may have a two-layer structure consisting of a second metal oxide layer and a third metal oxide layer on the second metal oxide layer.

[0070] In order to form a crystalline metal oxide layer, one aspect of the present invention provides a seed layer in contact with the metal oxide layer. This configuration allows the crystallinity of the metal oxide layer to be enhanced by utilizing the seed layer. Furthermore, it is possible to form a metal oxide layer having large crystal grains. Since the seed layer functions as a seed or nucleus for enhancing the crystallinity of the metal oxide layer, it can be called a seed crystal or crystal nucleus.

[0071] A method for forming a metal oxide layer using a seed layer will be explained with reference to Figures 1A to 2D and Figure 4A.

[0072] A substrate 10 is prepared, and an insulating layer 20 is formed on the substrate 10 (see Figure 1A). The insulating layer 20 can be formed using sputtering, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), atomic layer deposition (ALD), or pulsed laser deposition (PLD).

[0073] As the substrate 10, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there are semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, or conductive resin substrates. Alternatively, there are substrates having metal nitrides, substrates having metal oxides, etc. Furthermore, there are substrates in which a conductor or semiconductor is provided on an insulating substrate, substrates in which a conductor or insulator is provided on a semiconductor substrate, and substrates in which a semiconductor or insulator is provided on a conductive substrate. Alternatively, substrates with elements mounted on them may be used. Examples of elements mounted on the substrate include capacitive elements, resistive elements, switch elements, light-emitting elements, or memory elements.

[0074] The insulating layer 20 preferably has an amorphous structure. If the insulating layer 20 has a polycrystalline or single-crystal structure, when the metal oxide layer 30 is formed later, the metal oxide layer 30 may crystallize in accordance with the crystal structure of the insulating layer 20, potentially resulting in the formation of a polycrystalline structure with small crystal grains. Therefore, by having an amorphous structure for the insulating layer 20, unintended crystallization of the metal oxide layer 30 can be suppressed, making it possible to obtain a metal oxide layer 30 with large crystal grains.

[0075] The upper surface of the insulating layer 20 is preferably flat. This configuration suppresses nucleation caused by irregularities on the upper surface of the insulating layer 20 and promotes crystal growth in the metal oxide layer.

[0076] In this specification, a layer is considered flat if its average surface roughness (Ra) is less than 3 nm. Average surface roughness (Ra) is a three-dimensional extension of the arithmetic mean roughness defined in JIS B 0601:2001 (ISO 4287:1997) to curved surfaces. Average surface roughness (Ra) can be evaluated using an atomic force microscope (AFM). For example, average surface roughness (Ra) can be calculated over a 1 mm square area. If the layer is island-like and does not have a 1 mm square area in plan view, it may be calculated over the entire area of ​​the layer in plan view. The average surface roughness (Ra) described in this specification may also be referred to as root mean square roughness (Rq or RMS) or maximum height roughness (Rz).

[0077] Furthermore, the flatness of the upper surface of a layer can also be evaluated by performing image analysis of a transmission electron microscope (TEM) image. For example, the contrast observed in the TEM image is assumed to be the interface between the first layer and the second layer, and the shape of this interface is assumed to be the roughness curve of the first layer. Then, the arithmetic mean roughness can be calculated from the assumed roughness curve. The reference length may be the length of the upper surface of the first layer observed in the TEM image, or the length of the region where the first layer and the second layer overlap. The reference length is, for example, 100 nm. In this case, it is preferable that the observation range of the TEM image is 100 nm or more in either the vertical or horizontal direction. If the arithmetic mean roughness of the upper surface of the first layer calculated using this method is less than 3 nm, the upper surface of the first layer can also be said to be flat.

[0078] The average surface roughness (Ra) or arithmetic mean roughness of the upper surface of the insulating layer 20 is preferably 0 nm or more and less than 3 nm, more preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, more preferably 0 nm or more and 0.5 nm or less, more preferably 0 nm or more and 0.3 nm or less, and even more preferably 0 nm or more and 0.2 nm or less.

[0079] For example, the flatness of the upper surface of the insulating layer 20 can be improved by performing a chemical mechanical polishing (CMP) treatment. When the insulating layer 20 has a laminated structure of n layers (where n is an integer greater than or equal to 2), the CMP treatment can be applied to the uppermost layer (the nth layer) of the insulating layer 20. Alternatively, the CMP treatment can be applied to a layer other than the uppermost layer of the insulating layer 20 (the kth layer (where k is an integer greater than or equal to 1 or less than or equal to n-1)), and the k+1th to nth layers can be formed on the flattened kth layer.

[0080] The insulating layer 20 may have grooves, recesses, openings, trenches, or slits, for example, or it may have protrusions, projections, etc. Even in such cases, a crystalline metal oxide layer 30 can be formed.

[0081] When the metal oxide layer 30 is used as a semiconductor layer in a transistor, it is preferable that defects such as oxygen vacancies are sufficiently reduced in the metal oxide layer 30.

[0082] The insulating layer 20 preferably has a function to supply oxygen. This supplies oxygen to the metal oxide layer 30, thereby reducing oxygen deficiency. An insulating layer having an oxygen-supplying function is, for example, an insulating layer having a region containing oxygen that is desorbed by heating (hereinafter sometimes referred to as excess oxygen). In the semiconductor device manufacturing process, when heating is performed, oxygen can be supplied from the insulating layer. Examples of insulating layers having an oxygen-supplying function include silicon oxide layers or silicon oxynitride layers.

[0083] Furthermore, it is preferable that the insulating layer 20 has barrier properties against oxygen. This suppresses the detachment of oxygen from the metal oxide layer 30 and the formation of oxygen deficiencies. Examples of insulating layers having barrier properties against oxygen include a gallium oxide layer or an aluminum oxide layer.

[0084] It is particularly preferable to use gallium oxide as the insulating layer 20. Compared to aluminum, the ionic radius of gallium is close to that of indium. Therefore, when indium oxide is used as the metal oxide layer 30, using gallium oxide as the insulating layer 20 makes it possible to bring the surface density of metal atoms in the metal oxide layer 30 closer to the surface density of metal atoms in the insulating layer 20. As a result, the frequency of bonding between indium atoms in the metal oxide layer 30 and gallium atoms in the insulating layer 20 via oxygen atoms increases, and the occurrence of oxygen vacancies or oxygen with dangling bonds at the interface between the metal oxide layer 30 and the insulating layer 20 can be suppressed.

[0085] Furthermore, as the insulating layer 20, gallium oxide or aluminum oxide to which the metal elements contained in the metal oxide layer 30 have been added can also be used. For example, if the metal oxide layer 30 contains indium, gallium oxide containing indium or aluminum oxide containing indium can also be used as the insulating layer 20. In this case, the insulating layer 20 has gallium or aluminum, indium, and oxygen. Even in this case, it is possible to suppress the occurrence of oxygen vacancies or oxygen with dangling bonds at the interface between the metal oxide layer 30 and the insulating layer 20. In addition, gallium atoms and aluminum atoms in oxides tend to exist in tetrahedral coordination positions, while indium atoms in oxides tend to exist in octahedral coordination positions. In other words, in gallium oxide containing indium and aluminum oxide containing indium, tetrahedral and octahedral coordination are mixed, and it is presumed that the crystallinity will be low. Therefore, by using gallium oxide containing indium or aluminum oxide containing indium as the insulating layer 20, the crystallinity of the insulating layer 20 can be reduced. Furthermore, the insulating layer 20 can have an amorphous structure.

[0086] In gallium oxide containing indium, the indium content is preferably 0.5% to 5%, and more preferably 0.5% to 2%. This allows the insulating properties of the insulating layer 20 to be maintained. Similarly, in aluminum oxide containing indium, the indium content is preferably 0.5% to 5%, and more preferably 0.5% to 2%.

[0087] Furthermore, if the insulating layer 20 has a laminated structure of two or more layers, it is preferable to use an insulating layer that has the function of supplying oxygen or an insulating layer that has barrier properties against oxygen in the layer in contact with the metal oxide layer 30.

[0088] Next, it is preferable to perform a hydrogen addition treatment after the formation of the insulating layer 20 (see Figure 1B). The hydrogen addition treatment can be carried out using an ion implantation device, an ion doping device, or a plasma treatment device. Alternatively, as a hydrogen addition treatment, microwave plasma treatment can be performed in a hydrogen-containing atmosphere. The arrows shown in Figure 1B indicate hydrogen. Here, hydrogen includes ionic states and plasma states. The insulating layer 20 corresponds to the underlayer film of the metal oxide layer 30 that will be formed later. Nucleation may occur due to minute debris at the interface between the underlayer film and the metal oxide layer 30, or due to protrusions or depressions in the underlayer film. Therefore, by performing a hydrogen addition treatment on the underlayer film, such nucleation can be suppressed, and crystal growth from near the interface between the underlayer film and the metal oxide layer 30 can be suppressed.

[0089] Furthermore, since it is sufficient to suppress nucleation occurring near the upper surface of the insulating layer 20, it is preferable to add hydrogen to the region near the upper surface of the insulating layer 20, as shown in the hatching pattern of Figure 1B. The region near the upper surface of the insulating layer 20 refers, for example, to the region within 5 nm, preferably within 2 nm, from the interface between the insulating layer 20 and the metal oxide layer 30 to be formed later toward the interior of the insulating layer 20. Before the formation of the metal oxide layer 30, the hydrogen concentration in this region of the insulating layer 20 is preferably 0.1 atomic% or more and 10 atomic% or less. If the hydrogen concentration in this region is less than 0.1 atomic%, there is a risk that nucleation will not be sufficiently suppressed. On the other hand, if the hydrogen concentration in this region exceeds 10 atomic%, hydrogen will remain in this region, and the remaining hydrogen will cause V Ｏ and V Ｏ This could lead to the formation of H, potentially causing the transistor to become normally-on, or reducing the reliability of the transistor.

[0090] Furthermore, since it is sufficient for the insulating layer 20 to contain hydrogen, an insulating layer 20 containing hydrogen may be formed. The insulating layer 20 containing hydrogen can be formed in a hydrogen-containing atmosphere, or it can be formed using a hydrogen-containing raw material gas. By adding hydrogen during the formation of the insulating layer 20, an insulating layer 20 with low crystallinity, for example, an insulating layer 20 having an amorphous structure, can be formed. In this case, the hydrogen addition process described above may be omitted.

[0091] Next, a seed layer 31 is formed on the insulating layer 20 (see Figure 1C). As the seed layer 31, an oxide containing indium (typically indium oxide), an oxide containing one or both of yttrium and zirconium, erbium oxide, etc., can be used. Examples of oxides containing one or both of yttrium and zirconium include yttrium oxide, zirconium oxide, and oxides containing both yttrium and zirconium. In addition, an oxide containing indium and the first element mentioned above can be used as the seed layer 31. An example of such an oxide is indium tin oxide (In-Sn oxide, also called ITO). These oxides have a cubic crystal structure.

[0092] The thickness of the seed layer 31 is preferably thin. The thickness of the seed layer 31 is 0.1 nm or more and 3 nm or less, preferably 0.3 nm or more and 2.5 nm or less, and more preferably 0.5 nm or more and 2 nm or less. It is preferable that the seed layer 31 has a region with the above-mentioned thickness in at least a part of it. By making the thickness of the seed layer 31 thin, the step difference that occurs between the seed layer 31 and the insulating layer 20 is reduced. Therefore, the coverage of the metal oxide layer that is formed later is improved and defects such as porosity can be reduced. In addition, crystal growth of the metal oxide layer can be promoted.

[0093] Furthermore, the thickness of the seed layer 31 can be increased. The thickness of the seed layer 31 can be, for example, 0.3 nm to 15 nm, preferably 1 nm to 10 nm, and more preferably 2 nm to 10 nm. By increasing the thickness of the seed layer 31, a highly crystalline seed layer 31 can be formed. A highly crystalline seed layer 31 is a single-crystal seed layer 31 or a seed layer 31 containing large crystal grains.

[0094] Here, we will describe an example of a method for forming the seed layer 31.

[0095] First, an oxide layer 31f, which will serve as the seed layer 31, is formed on the insulating layer 20 (see Figure 2A). The oxide layer 31f can be formed using sputtering, CVD, MBE, ALD, or PLD. For details on how to form the oxide layer 31f, please refer to the description of the method for forming the metal oxide layer 30, which will be written later.

[0096] Next, it is preferable to perform a treatment to enhance the crystallinity of the oxide layer 31f (see Figure 2B). Oxides with a cubic crystal structure (typically indium oxide) are presumed to grow while maximizing the surface area of ​​the {111} plane. In other words, they are presumed to preferentially orient themselves to the {111} plane. Therefore, by performing a treatment to enhance crystallinity, crystal grains oriented in the oxide layer 31f with the <111> orientation parallel to the thickness direction of the substrate 10 (also called <111> oriented crystal grains) can be formed.

[0097] Examples of treatments to enhance the crystallinity of the oxide layer include heat treatment, plasma treatment, microwave treatment (including microwave plasma treatment), and light (e.g., ultraviolet light) irradiation. Multiple of these treatments can be performed simultaneously or sequentially. The arrows in Figure 2B indicate heat, plasma, microwave, radical, or light, respectively.

[0098] As a treatment to enhance the crystallinity of the oxide layer 31f, microwave plasma treatment is preferred, and microwave plasma treatment in an oxygen-containing atmosphere is particularly preferred.

[0099] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less. Microwave plasma processing refers to processing using a device that has a power supply that generates high-density plasma using microwaves, for example. Microwave plasma processing can also be called microwave-excited high-density plasma processing.

[0100] Microwave plasma treatment is preferably carried out under reduced pressure, with a pressure of 10 Pa to 1000 Pa being preferred, more preferably 50 Pa to 700 Pa, and even more preferably 100 Pa to 400 Pa. The treatment temperature is preferably room temperature (25°C) to 750°C, more preferably 300°C to 500°C, and can be 400°C to 450°C.

[0101] When performing microwave plasma treatment, it is preferable to heat the substrate. For example, it is preferable to heat the substrate to a temperature of room temperature (e.g., 25°C) or higher and 500°C or lower, more preferably 100°C or higher and 450°C or lower, more preferably 200°C or higher and 450°C or lower, more preferably 300°C or higher and 450°C or lower, and even more preferably 400°C or higher and 450°C or lower.

[0102] Microwave plasma treatment can be performed using, for example, oxygen gas and argon gas. Note that the oxygen flow rate ratio (O) in microwave plasma treatment is important. ２ / ( O ２ If the oxygen flow rate ratio (O) is too high, the discharge becomes unstable. Therefore, for example, the oxygen flow rate ratio (O) ２ / ( O ２ The value of +Ar) is preferably greater than 0% and 50% or less, more preferably greater than 0% and 40% or less, and even more preferably greater than 0% and 30% or less.

[0103] In microwave plasma processing using oxygen and argon gases, the main oxygen radicals are triplet oxygen (O( ３ P ２ )), singlet oxygen (O( １ D ２ )), and oxygen ions (O ２ ＋It can take on three states. In the reduction of hydrogen concentration in oxide films by microwave plasma treatment, oxygen ions play an effective role. Also, the amount of oxygen radicals in each state changes depending on the oxygen flow rate ratio or pressure in microwave plasma treatment. For example, under conditions where the oxygen flow rate ratio is low and the pressure is low, the amount of oxygen ions tends to increase. On the other hand, if the oxygen flow rate ratio or pressure is set too low, there are concerns that the control of the oxygen flow rate will become unstable, the discharge will not be stable, and the oxide film may be etched. For example, the oxygen flow rate ratio (O ２ / ( O ２ The value of +Ar) is preferably greater than 0% and 10% or less, preferably between 0.5% and 5%, more preferably between 0.5% and 3%, and typically 1%.

[0104] The shorter the processing time for microwave plasma treatment, the higher the productivity. For example, the processing time for microwave plasma treatment is preferably 1 minute or more and 60 minutes or less, more preferably 1 minute or more and 30 minutes or less, and even more preferably 1 minute or more and 10 minutes or less.

[0105] Next, the oxide layer 31f is processed using photolithography or the like to form a seed layer 31 (see Figure 2C). The shape of the seed layer 31 in plan view can be island-like or striped. The sides of the seed layer 31 may also have a tapered shape. The upper end of the seed layer 31 may also have a curved shape. The number of seed layers 31 provided on the insulating layer 20 may be one or multiple.

[0106] There are two main methods of photolithography. One method involves forming a resist mask on the thin film to be processed, then processing the thin film by etching or other means, and removing the resist mask. The other method involves forming a photosensitive thin film, then exposing and developing it to process the thin film into the desired shape. Dry etching and wet etching methods can be used for etching.

[0107] In this embodiment, a resist mask is formed on the oxide layer 31f, and the oxide layer 31f is processed using a wet etching method to form a seed layer 31. After the seed layer 31 is formed, the resist mask is removed. By using a wet etching method, damage to the insulating layer 20 can be reduced compared to when a dry etching method is used. In addition, the flatness of the upper surface of the insulating layer 20 can be maintained.

[0108] After the formation of the seed layer 31, the aforementioned treatment to enhance the crystallinity of the oxide layer may be performed. This further enhances the crystallinity of the seed layer 31. In addition, the surface state or film quality of the portion of the insulating layer 20 that does not overlap with the seed layer 31 can be modified. Microwave plasma treatment is particularly preferred as a treatment to enhance the crystallinity of the oxide layer (see Figure 2D). This, in addition to the above effects, can remove impurities adhering to the upper surface of the seed layer 31.

[0109] Furthermore, the process of increasing the crystallinity of the oxide layer, which is performed before processing the oxide layer 31f, may be omitted. For example, the oxide layer 31f can be formed, then the oxide layer 31f can be processed to form the seed layer 31, and then the process of increasing the crystallinity of the oxide layer can be performed. This increases the crystallinity of the seed layer 31 and also modifies the surface state or film quality of the portion of the insulating layer 20 that does not overlap with the seed layer 31.

[0110] The above is an explanation of an example of a method for forming the seed layer 31.

[0111] Furthermore, if the sputtering target has multiple crystal grains, and these crystal grains have a layered structure, and there is an interface that is easily cleaved on the crystal grains, then by colliding ions with the sputtering target, the crystal grains may cleave, and plate-shaped or pellet-shaped sputtering particles may be obtained. Plate-shaped or pellet-shaped sputtering particles deposited on the insulating layer 20 can also be used as a seed layer 31. The thickness (length in the c-axis direction) of the plate-shaped or pellet-shaped sputtering particles is, for example, 0.5 nm or more and less than 1 nm, typically 0.7 nm, for a sputtering target with a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or close to that, or In:Ga:Zn = 1:3:2 [atomic ratio] or close to that. This thickness is suitable because it is within the range of suitable film thickness for the seed layer 31.

[0112] To replenish the hydrogen on the surface of the insulating layer 20 that was removed during the seed layer 31 formation process, a hydrogen addition treatment may be performed after the formation of the seed layer 31. For example, microwave plasma treatment may be performed in a hydrogen-containing atmosphere. This may add hydrogen to the upper surface of the portion of the insulating layer 20 that does not overlap with the seed layer 31, thereby suppressing nucleation near the insulating layer 20.

[0113] The process of adding hydrogen to the upper surface of the insulating layer 20 will hereafter be referred to as the first process. As mentioned above, the first process may be performed after the formation of the insulating layer 20, after the formation of the seed layer 31, or after the formation of the insulating layer 20 and after the formation of the seed layer 31, respectively.

[0114] Next, a metal oxide layer 30 is formed on the seed layer 31. For example, the metal oxide layer 30 is formed on the insulating layer 20, covering the seed layer 31 (see Figure 1D). As the metal oxide layer 30, an oxide containing indium (typically indium oxide) can be used. The metal oxide layer 30 can be formed using sputtering, CVD, MBE, ALD, or PLD.

[0115] The metal oxide layer 30 is preferably formed using a sputtering method. Hydrogen (H) is used as the sputtering gas. ２It is preferable to use a gas containing ). By introducing hydrogen when forming the metal oxide layer 30 using the sputtering method, a metal oxide layer 30 with low crystallinity, for example, an amorphous metal oxide layer 30, can be formed. In addition, nucleation can be suppressed or crystal nuclei other than the seed layer 31 can be promoted during the formation of the metal oxide layer 30. As the sputtering gas, hydrogen, noble gas (typically argon), and oxygen (O) can be used. ２ A mixed gas of ) can be used. In addition, water (H) can be used as the sputtering gas. ２ O), or nitrogen (N ２ Using gases containing ) etc. may produce the same effect as described above.

[0116] Furthermore, a sputtering gas that does not contain hydrogen may be used. As the sputtering gas, for example, a noble gas or oxygen as a single gas, or a mixture of a noble gas and oxygen, may be used.

[0117] Furthermore, when forming the metal oxide layer 30 using the sputtering method, the substrate temperature during film formation of the metal oxide layer 30 is preferably between room temperature (25°C) and 250°C, more preferably between room temperature and 200°C, and even more preferably between room temperature and 140°C. For example, setting the substrate temperature to between room temperature and 140°C is preferable because it increases productivity. It is also preferable because it suppresses nucleation. In addition, the metal oxide layer can be formed at room temperature or without heating the substrate.

[0118] The metal oxide layer 30 can also be formed using the ALD method. By using the ALD method, which deposits atoms individually during film formation, nucleation in the film can be suppressed compared to the sputtering method, which impacts the surface to be formed with particles. For example, a precursor and an oxidizing agent can be used to form the metal oxide layer 30. If the precursor contains indium, a film containing indium and oxygen will be formed as the metal oxide layer 30. When the precursor contains indium, the thermal ALD method can be used as the ALD method.

[0119] Examples of precursors containing indium include trimethylindium, triethylindium, ethyldimethylindium, tris(1-methylethyl)indium, tris(2,2,6,6-tetramethyl-3,5-heptanedionic acid)indium, cyclopentadienylindium, indium(III) acetylacetonate, (3-(dimethylamino)propyl)dimethylindium, (diethylphosphino)dimethylindium, chlorodimethylindium, bromodimethylindium, and dimethyl(2-propanolat)indium.

[0120] Furthermore, inorganic precursors that do not contain hydrocarbons may be used as indium precursors. As inorganic precursors containing indium, halogenated indium compounds such as trifluoroindium (indium(III) fluoride), indium trichloride (indium(III) chloride), indium tribromide (indium(III) bromide), and indium triiodide (indium(III) iodide) can be used.

[0121] In the method for forming the metal oxide layer 30, it is preferable to use a precursor with a low impurity concentration, i.e., a high purity precursor. For example, by using a precursor with a purity of 3N (99.9%) or higher, preferably 4N (99.99%) or higher, more preferably 5N (99.999%) or higher, and even more preferably 6N (99.9999%) or higher, the amount of impurities in the metal oxide layer 30 can be reduced.

[0122] The aluminum content in the precursor is preferably 1000 ppm or less, more preferably 500 ppm or less, even more preferably 100 ppm or less, even more preferably 50 ppm or less, even more preferably 10 ppm or less, and even more preferably 1 ppm or less. By using a precursor with a low aluminum content, the concentration of aluminum in the metal oxide layer 30 can be reduced, and the crystallinity of the metal oxide layer 30 can be improved.

[0123] Furthermore, it is preferable that the precursor is purified by two or more distillations (also called rectification or precision distillation). Using such a precursor makes it easier to form metal oxide films with fewer impurities, which is preferable. Performing distillation multiple times is preferable because it further suppresses the retention of impurities in the precursor that originate from the starting materials used in the manufacture of the precursor. However, the present invention is not limited to the above, and a precursor purified by one distillation, i.e., simple distillation, may also be used. Using simple distillation is preferable because it can reduce manufacturing costs. By performing one or more distillations, the aluminum content in the precursor can be set to 100 ppm or less, 1 ppm or less, or 1 ppb (0.001 ppm) or less.

[0124] As an oxidizing agent, ozone (O ３ ), oxygen (O ２ ), water (H ２ O), hydrogen peroxide (H ２ O ２ ) and the like can be used. Preferably, the oxidizing agent contains at least one of ozone and oxygen. By using ozone, oxygen, etc., which do not contain hydrogen, as the oxidizing agent, the amount of hydrogen mixed into the metal oxide layer 30 can be reduced. Furthermore, by using water, hydrogen peroxide, etc., which contain hydrogen, as the oxidizing agent, a metal oxide layer 30 with low crystallinity can be formed. In addition, nucleation can be suppressed or crystal nuclei other than the seed layer 31 can be eliminated during the formation of the metal oxide layer 30.

[0125] Unless otherwise specified in this specification, when ozone, oxygen, water, or hydrogen peroxide are used as oxidizing agents, these shall include not only gaseous or molecular states, but also plasma states, radical states, or ionic states.

[0126] When introducing the precursor into the reaction chamber, the substrate heating temperature is preferably set to a temperature corresponding to the decomposition temperature of the precursor. In the case of a thermal ALD method using triethylindium as the indium-containing precursor, for example, the substrate heating temperature can be 100°C to 350°C, preferably 150°C to 300°C. When a seed layer 31 is provided, the substrate heating temperature can be room temperature (25°C) to 300°C, preferably room temperature to 200°C, and more preferably room temperature to 150°C. Lowering the substrate heating temperature can reduce the crystallinity of the metal oxide layer 30 during film formation.

[0127] Next, microwave plasma treatment is preferably performed. In particular, microwave plasma treatment in a hydrogen-containing atmosphere is preferred. Microwave plasma treatment can remove impurities such as hydrogen and carbon from the upper surface and nearby regions of the metal oxide layer 30. For example, hydrogen in the metal oxide layer 30 can be removed as water molecules (dehydrated) by the reaction of hydrogen and oxygen. This reduces the hydrogen concentration in the metal oxide layer 30. At this time, the metal oxide layer 30 has a concentration gradient in which the hydrogen concentration increases from the upper surface to the lower surface. Also, the hydrogen concentration is lower in the upper surface and nearby regions of the metal oxide layer 30 than in the lower surface and nearby regions of the metal oxide layer 30. Alternatively, for example, carbon in the metal oxide layer 30 can be removed as carbon dioxide (CO2) by the reaction of carbon and oxygen. ２ It can be removed (decarbonized) as a result. This reduces the carbon concentration in the metal oxide layer 30.

[0128] When performing microwave plasma treatment in a hydrogen-containing atmosphere, for example, hydrogen gas, oxygen gas, and argon gas can be used. Here, the ratio of the hydrogen gas flow rate to the total gas flow rate is defined as the hydrogen flow rate ratio. For example, when using hydrogen gas, oxygen gas, and argon gas, the hydrogen flow rate ratio represents the ratio of the hydrogen gas flow rate to the sum of the hydrogen gas flow rate, oxygen gas flow rate, and argon gas flow rate. For example, the hydrogen flow rate ratio is preferably greater than 0% and 15% or less, more preferably greater than 0% and 10% or less, and even more preferably greater than 0% and 7.5% or less. By setting the hydrogen flow rate ratio within the above range, the number of active species such as OH radicals or OH ions during microwave plasma treatment increases, which may promote the above reaction. On the other hand, by increasing the amount of hydrogen above the above range, H ２ The proportion of active species decreases due to an increase in inactive species such as O, H ２ There is a risk that hydrogen in the metal oxide layer 30 may not be sufficiently removed due to reduction of the metal oxide layer 30 by the above method.

[0129] In addition, hydrogen (H) is used as the sputtering gas. ２ Indium oxide films deposited by sputtering using a gas containing ) have low crystallinity and, for example, an amorphous structure, but microcrystals may remain in the film. Therefore, by performing the microwave plasma treatment, it may be possible to further reduce the crystallinity of the metal oxide layer 30 and promote amorphous formation.

[0130] Furthermore, it is presumed that the dehydration, decarbonization, and amorphous transformation accelerated by microwave plasma treatment occur simultaneously.

[0131] When performing the above microwave plasma treatment, the substrate temperature is set to 100°C to 300°C, preferably 120°C to 250°C, more preferably 150°C to 200°C, more preferably 150°C to 180°C, and even more preferably 155°C to 175°C. This allows for the suppression of nucleation in the metal oxide layer 30 while promoting crystal growth from the seed layer 31.

[0132] The microwave plasma treatment performed after the formation of the metal oxide layer 30 will be referred to as the second treatment from now on.

[0133] Here, we will explain crystal growth in indium oxide films.

[0134] As mentioned above, by adding hydrogen to the interface between the insulating layer 20 and the metal oxide layer 30, nucleation and crystal growth near the interface are suppressed. Therefore, crystal growth (lateral growth) from the seed layer 31 along the surface of the insulating layer 20 is suppressed. While lateral growth is suppressed, crystal growth occurs from the upper surface of the seed layer 31 perpendicular to the surface of the substrate 10, using the seed layer 31 as a seed or nucleus. This crystal growth is called the first growth. The first growth can be said to occur in the region of the metal oxide layer 30 that overlaps with the seed layer 31, from the lower surface to the upper surface of the metal oxide layer 30. In Figure 4A, the direction of the first growth is shown by a solid arrow. Note that the direction perpendicular to the surface of the substrate 10 can also be said to be the direction parallel to the thickness direction of the substrate 10. Also, if the upper surface of the seed layer 31 is the {111} plane, the direction of the first growth coincides with the <111> orientation of the seed layer 31.

[0135] Microwave plasma treatment reduces the concentration of impurities such as hydrogen and carbon in the upper surface and vicinity of the metal oxide layer 30, meaning that this region is in a state where crystallization is easily achieved. Therefore, if the first growth reaches the upper surface of the metal oxide layer 30 before crystallization begins in the upper surface and vicinity of the metal oxide layer 30, crystal growth can be generated along the upper surface of the metal oxide layer 30 from the region crystallized by the first growth. This crystal growth is called the second growth. In Figure 4A, the direction of the second growth is shown by a dashed arrow. In particular, if the upper surface of the seed layer 31 is a {111} plane, the direction of the second growth is parallel to the {111} plane of the seed layer 31. As mentioned above, oxides with a cubic crystal structure (typically indium oxide) are presumed to grow while maximizing the surface area of ​​the {111} plane. Therefore, the rate of the second growth is faster than the rate of the first growth. Therefore, the area of ​​the crystalline region in a plan view can be increased before nucleation occurs on the upper surface and nearby regions of the metal oxide layer 30. The upper surface and nearby regions of the metal oxide layer 30, which have crystallized through the second growth, can be made to function substantially as a seed layer.

[0136] Using the above region as a seed layer, crystal growth occurs from the top surface to the bottom surface of the metal oxide layer 30. This crystal growth is called the third growth. The third growth can be said to occur in the region of the metal oxide layer 30 that does not overlap with the seed layer 31. In Figure 4A, the direction of the third growth is shown by a dotted arrow. In particular, if the top surface of the seed layer 31 is a {111} plane, the direction of the third growth coincides with the <111> orientation of the seed layer 31. Note that the third growth is more likely to occur in oxide films containing indium (for example, indium oxide films, In-Ga-Zn oxide films, etc.).

[0137] The first to third growth processes described above can improve the crystallinity of the metal oxide layer 30, for example, by achieving single crystal formation of the metal oxide layer 30. It should be noted that the first to third growth processes are not limited to occurring sequentially, but may also occur in combination.

[0138] From the above, a highly crystalline metal oxide layer 30 (typically a single-crystal metal oxide layer 30) can be formed (see Figure 1E). Due to the first to third growth processes, the crystal growth in the metal oxide layer 30 occurs along the upper surface of the metal oxide layer 30 or the upper surface of the insulating layer 20, and therefore this crystal growth can be called lateral growth.

[0139] As crystal grains grow using the seed layer 31 as a seed or nucleus, the crystal grains of the metal oxide layer 30 have a first portion in contact with the upper surface of the seed layer 31 and a second portion in contact with the upper surface of the insulating layer 20, and the surface orientation of the upper surface of the first portion and the surface orientation of the upper surface of the second portion coincide. If the seed layer 31 has crystal grains with a <111> orientation, the surface orientation of the upper surface of the first portion and the surface orientation of the upper surface of the second portion become {111} planes. Furthermore, no grain boundaries are observed in the crystal grains.

[0140] Furthermore, a heat treatment may be performed following the microwave plasma treatment described above. This heat treatment will be referred to as the third treatment hereafter. This heat treatment can be performed, for example, at a temperature of 250°C to 650°C, preferably 300°C to 500°C, and more preferably 320°C to 450°C. By performing this heat treatment, the crystal grains in the metal oxide layer 30 can be made larger. In addition, the film density of the metal oxide layer 30 can be increased. In addition, excess hydrogen in the metal oxide layer 30 can be reduced.

[0141] By setting the temperature of the above heat treatment to, for example, 450°C or lower, preferably 400°C or lower, a transistor having a metal oxide layer 30 on a layer containing copper wiring can be fabricated. However, if the temperature is below 250°C, the density of the metal oxide layer 30 may not be sufficiently increased, making it difficult to achieve a large on-current.

[0142] The above heat treatment is preferably carried out under reduced pressure. The above heat treatment can also be carried out in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm (0.001%) or more, 1% or more, or 10% or more of an oxidizing gas. For example, when heat treatment is carried out in a mixed atmosphere of nitrogen gas and oxygen gas, it is preferable to have about 20% oxygen gas. Alternatively, after heat treatment in an atmosphere of nitrogen gas or an inert gas, heat treatment can be carried out in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the oxygen that has been removed.

[0143] Furthermore, it is preferable that the gas used in the above heat treatment is highly purified. For example, the amount of water contained in the gas used in the above heat treatment should be 1 ppb (1 × 10⁻¹⁶). −３ Preferably less than ppm, and 0.1 ppb (1 × 10⁻¹⁰ −４ It is more preferable to have a ppm or less, and 0.05 ppb (5 × 10) −５ A concentration of ppm or less is even more preferable. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and other substances from being incorporated into the metal oxide layer 30 as much as possible.

[0144] There are no special limitations on the heating device used for the heat treatment; it may be a device that heats the object to be treated by heat conduction or thermal radiation from a heat source such as a resistance heating element. For example, an electric furnace or an RTA (Rapid Thermal Anneal) device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. An LRTA device is a device that heats the object to be treated by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp. A GRTA device is a device that performs heat treatment using high-temperature gas.

[0145] By using an RTA (Real-Time Attenuation) device, the heat treatment time can be shortened. The treatment time is preferably 1 minute or more and 10 minutes or less, more preferably 3 minutes or more and 10 minutes or less, and even more preferably 5 minutes or more and 10 minutes or less. When using an RTA device to shorten the heat treatment time, the heating temperature can be set to be above the strain point of the substrate. This further shortens the heat treatment time. The heating temperature is preferably 400°C or more and 750°C or less, and more preferably 450°C or more and 700°C or less.

[0146] From the above, a crystalline metal oxide layer 30 can be formed. Furthermore, a metal oxide layer 30 having crystal grains can be formed. Moreover, by using the above method, the crystal grains of the metal oxide layer 30 can be enlarged and the crystal grain boundaries within the metal oxide layer 30 can be reduced. Therefore, a metal oxide layer 30 can be made in which grain boundary scattering is reduced and carrier mobility is high.

[0147] Furthermore, the metal oxide layer 30 can be processed using photolithography or the like to form island-shaped or striped metal oxide layers 30 in a plan view. The number of metal oxide layers 30 provided on the insulating layer 20 may be one or multiple. In addition, the metal oxide layer 30 in areas that do not overlap with the seed layer 31 and the metal oxide layer 30 in the vicinity thereof may be removed so that the seed layer 31 does not remain, or at least a part of the seed layer 31 may remain and a metal oxide layer 30 having an overlapping area with the seed layer 31 may be formed.

[0148] If the metal oxide layer 30 has a polycrystalline structure, it is also possible to form an island-like or striped single-crystal metal oxide layer 30 by processing the metal oxide layer 30 so as not to include grain boundaries.

[0149] Furthermore, the metal oxide layer 30 can also be processed after forming a conductive layer, an insulating layer, or a laminate including both a conductive layer and an insulating layer on the metal oxide layer 30.

[0150] When forming the metal oxide layer 30 using an oxide containing indium, the crystal structure of the seed layer 31 is not limited to cubic. For example, a seed layer 31 with a hexagonal or trigonal crystal structure can also be used. For example, by making the upper surface of the seed layer 31 a (001) plane and the lower surface of the metal oxide layer 30 a (111) plane, the requirements related to crystal orientation necessary for epitaxial growth can be satisfied. Examples of seed layer 31 that can be used include zinc oxide, indium gallium oxide (In-Ga oxide), gallium zinc oxide (Ga-Zn oxide, also written as GZO), aluminum zinc oxide (Al-Zn oxide, also written as AZO), indium gallium zinc oxide (In-Ga-Zn oxide, also written as IGZO), indium aluminum zinc oxide (In-Al-Zn oxide, also written as IAZO), or indium tin zinc oxide (In-Sn-Zn oxide, also written as ITZO®). It is preferable to use an In-Ga-Zn oxide as the seed layer 31. In this case, the seed layer 31 contains indium, gallium, zinc, and oxygen. More specifically, it is preferable to have a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or close to that, or a composition of In:Ga:Zn = 1:3:2 [atomic ratio] or close to that.

[0151] In-Ga-Zn oxides and In-Sn-Zn oxides, etc., tend to have a CAAC (c-axis aligned crystalline) structure. When an oxide having a CAAC structure is used as the seed layer 31, the c-axis direction of the seed layer 31 is parallel or approximately parallel to the thickness direction of the substrate 10. Therefore, by using an oxide that tends to have a CAAC structure as the seed layer 31, the controllability of the crystal plane of the crystal grains in the metal oxide layer 30 can be improved.

[0152] When an oxide having a CAAC structure is used as the seed layer 31, and the upper surface of the seed layer 31 is the {001} plane, the first growth direction coincides with the <001> orientation of the seed layer 31, the second growth direction is parallel to the {001} plane of the seed layer 31, and the third growth direction coincides with the <001> orientation of the seed layer 31. The crystal grains of the metal oxide layer 30, whose crystal structure is bixbite type, are oriented with the <111> orientation parallel to the thickness direction of the substrate 10. The oxide having a CAAC structure has crystal grains with a hexagonal or trigonal crystal structure.

[0153] Figures 1A to 1E show a configuration in which the metal oxide layer 30 is a single layer. However, the present invention is not limited to this. The metal oxide layer 30 can also be a laminated structure of two or more layers.

[0154] An example of a method for forming a metal oxide layer having a three-layer structure using a seed layer will be explained with reference to Figures 3A to 3C and Figure 4B.

[0155] A substrate 10 is prepared, an insulating layer 20 is formed on the substrate 10, and a seed layer 31 is formed on the insulating layer 20 (see Figure 3A). The structure and formation methods of the substrate 10, insulating layer 20, and seed layer 31 can be found in the description above. Furthermore, the first treatment described above is performed on either or both of the insulating layer 20 and the seed layer 31 after their formation. The first treatment method can be found in the description above.

[0156] Next, a metal oxide layer 30 is formed on the insulating layer 20, covering the seed layer 31 (see Figure 3B). In Figure 3B, metal oxide layers 30_1, 30_2, and 30_3 are stacked in this order to form the metal oxide layer 30. Indium-containing oxides can be used for each of the metal oxide layers 30_1 to 30_3. In addition, metal oxide layers 30_1 to 30_3 can be indium-containing oxides that have different constituent elements or compositions from each other.

[0157] The composition and formation methods of each of the metal oxide layers 30_1 to 30_3 can be found by referring to the composition and formation methods of the metal oxide layer 30 described above. When the metal oxide layers 30 form a laminated structure, different methods can be used for each layer. For example, metal oxide layers 30_1 and 30_3 can be formed using the ALD method, and metal oxide layer 30_2 can be formed using the sputtering method. Alternatively, metal oxide layers 30_1 and 30_3 can be formed using the sputtering method, and metal oxide layer 30_2 can be formed using the ALD method.

[0158] The metal oxide layer 30_1 preferably contains hydrogen. For example, after the formation of the metal oxide layer 30_2, the hydrogen concentration of the metal oxide layer 30_1 is preferably higher than the hydrogen concentration of the metal oxide layer 30_2. Specifically, after the formation of the metal oxide layer 30_2, the hydrogen concentration of the metal oxide layer 30_1 is preferably 0.1 atomic% or more and less than 20 atomic%, more preferably 0.1 atomic% or more and 15 atomic%, and even more preferably 0.1 atomic% or more and 10 atomic%. Alternatively, it is preferably greater than 2.7 atomic% and less than 20 atomic%, more preferably greater than 2.7 atomic% and 15 atomic%, more preferably 3 atomic% or more and 15 atomic%, and even more preferably 3 atomic% or more and 10 atomic%. This suppresses nucleation in the metal oxide layer 30_1. It also suppresses lateral growth from the seed layer 31. Therefore, it is possible to promote crystal growth from the seed layer 31 in the direction perpendicular to the surface of the substrate 10 (the first growth described above).

[0159] The hydrogen concentration of the metal oxide layer can be evaluated, for example, using secondary ion mass spectrometry (SIMS). Alternatively, the evaluation can be performed by combining the SIMS measurement results with the film density of the metal oxide layer. Theoretical values ​​may also be used as the film density of the metal oxide layer.

[0160] As the metal oxide layer 30_1, indium oxide or indium oxide containing gallium can be used. For example, when silicon oxide is used as the insulating layer 20, a gallium-containing indium oxide film can be formed as the metal oxide layer 30_1. Also, for example, when gallium oxide or aluminum oxide is used as the insulating layer 20, an indium oxide film can be formed as the metal oxide layer 30_1 using a sputtering method. By forming an indium oxide film as the metal oxide layer 30_1 using a sputtering method, a mixed layer with the insulating layer 20 is formed between the insulating layer 20 and the metal oxide layer 30_1, or within the metal oxide layer 30_1. When gallium oxide is used as the insulating layer 20, gallium is mixed into the indium oxide, so the mixed layer can also be called gallium-containing indium oxide. Furthermore, the mixed layer is formed with a thickness of 0.1 to 1.0 nm. In this way, by providing the metal oxide layer 30_1 or the mixed layer below the metal oxide layer 30_2, V is formed in the metal oxide layer 30_1 or near the interface between the metal oxide layer 30_1 and the metal oxide layer 30_2. Ｏ and V Ｏ This can suppress the formation of H.

[0161] As described above, by having the metal oxide layer 30_1 contain hydrogen, and by having at least one of the metal oxide layer 30_1 and the insulating layer 20 contain gallium, it is easy to realize a transistor with high crystallinity in the channel formation region and normal off operation.

[0162] Before forming the metal oxide layer 30_3, it is preferable that the metal oxide layer 30_2 be a less dense film compared to the metal oxide layer 30_1. Here, a less dense film is a film with a lower film density or a faster wet etching rate than the film being compared. A less dense film can also be described as a softer film. By making the metal oxide layer 30_2 a less dense film, impurities such as carbon and hydrogen in the metal oxide layer 30_2 become relatively easier to diffuse. Therefore, by performing a subsequent treatment (specifically the second treatment), it is possible to reduce impurities such as carbon and hydrogen in the metal oxide layer 30_2 and promote crystal growth.

[0163] For example, indium oxide films deposited using the ALD method may contain impurities such as carbon and hydrogen derived from the precursor. Furthermore, indium oxide films deposited using the ALD method are presumed to have an amorphous structure and be sparse films.

[0164] Before forming the metal oxide layer 30_3, it is preferable that the hydrogen concentration of the metal oxide layer 30_2 is lower than the hydrogen concentration of the metal oxide layer 30_1. This promotes crystal growth.

[0165] It is preferable that the metal oxide layer 30_3 be a denser film compared to the metal oxide layer 30_2. Here, a dense film is a film with a higher film density or a slower wet etching rate than the film being compared. A dense film can also be described as a hard film. With this configuration, the diffusion of impurities from the upper layer into the metal oxide layer 30_2 can be blocked by the metal oxide layer 30_3.

[0166] It is preferable to continuously deposit the metal oxide layers 30_1 to 30_3 without exposure to the atmosphere. For example, a multi-chamber type deposition apparatus can be used. This allows for the deposition of metal oxide layers 30_1 to 30_3 with reduced hydrogen content in the film, and further reduces the incorporation of hydrogen into the film between each deposition process.

[0167] One or both of the metal oxide layers 30_1 and 30_3 may contain a second element in addition to indium. In this case, one or both of the metal oxide layers 30_1 and 30_3 can be formed using the ALD method with an indium precursor, a second element precursor, and an oxidizing agent.

[0168] When gallium is used as the second element, for example, triethylgallium, trimethylgallium, gallium trichloride, tris(dimethylamide)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionic acid)gallium, dimethylchlorogallium, or diethylchlorogallium can be used as precursors having the second element.

[0169] When aluminum is used as the second element, for example, aluminum trichloride, trimethylaluminum, triethylaluminum, triisobutylaluminum, dimethylaluminum hydride, tris(dimethylamino)aluminum, or tris(diethylamino)aluminum can be used as the precursor having the second element.

[0170] Next, it is preferable to perform the second treatment described above. By performing the second treatment, impurities such as hydrogen and carbon can be removed from the upper surface of the metal oxide layer 30 and the surrounding region. At this time, the metal oxide layer 30 has a concentration gradient in which the hydrogen concentration increases from the upper surface to the lower surface. Also, the metal oxide layer 30_3 has a region with a lower hydrogen concentration than the metal oxide layer 30_1. Furthermore, by performing the second treatment, the first to third growth described above occurs, and the crystallinity of the metal oxide layer 30 can be improved, for example, the metal oxide layer 30 can be made into a single crystal. In Figure 4B, the direction of the first growth is shown by a solid arrow, the direction of the second growth is shown by a dashed arrow, and the direction of the third growth is shown by a dotted arrow.

[0171] As described above, crystal grains are formed from metal oxide layer 30_1 to metal oxide layer 30_3. When metal oxide layers 30_1 to 30_3 each contain indium, the crystal structure of the crystal grain is bixbite type. The crystal grain includes at least a part of metal oxide layer 30_1, at least a part of metal oxide layer 30_2, and at least a part of metal oxide layer 30_3. When seed layer 31 has crystal grains with a <111> orientation, the upper surface of the crystal grain formed from metal oxide layer 30_1 to metal oxide layer 30_3 is a {111} plane.

[0172] Next, it is preferable to perform the third treatment described above. This can increase the film density of the metal oxide layer 30. In particular, since the metal oxide layer 30_2 is a sparse film, it is preferable to perform the third treatment.

[0173] Based on the above, a layered structure and a crystalline metal oxide layer 30 can be formed. Metal oxide layers 30_1 to 30_3 correspond to the first to third metal oxide layers described above, respectively.

[0174] The metal oxide layer 30 may also be processed using photolithography or the like.

[0175] The above is a description of the method for forming a metal oxide layer using a seed layer.

[0176] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0177] (Embodiment 2) This embodiment describes a microwave plasma processing apparatus that can be used in the above-mentioned method for forming the metal oxide layer. The microwave plasma processing apparatus described in this embodiment can also be used in the semiconductor device manufacturing method described later.

[0178] First, we will explain the configuration of a manufacturing apparatus that can reduce the inclusion of impurities during the manufacturing of semiconductor devices and other equipment, using Figures 5 to 7.

[0179] Figure 5 schematically shows a top view of a single-wafer multi-chamber manufacturing apparatus 600. The manufacturing apparatus 600 includes an atmospheric substrate supply chamber 601, an atmospheric substrate transport chamber 602, a load lock chamber 603a, an unload lock chamber 603b, a transport chamber 604, chambers 606a, 606b, 606c, and 606d. The atmospheric substrate supply chamber 601 includes a cassette port 607 for accommodating substrates and an alignment port 608 for aligning substrates. The atmospheric substrate transport chamber 602 has a mechanism for transporting substrates from the atmospheric substrate supply chamber 601. The load lock chamber 603a loads substrates in, and the unload lock chamber 603b unloads substrates out. The load lock chamber 603a and the unload lock chamber 603b have a mechanism for switching the pressure inside the chamber between atmospheric pressure and a reduced pressure state.

[0180] Furthermore, the atmospheric substrate transport chamber 602 is connected to the load lock chamber 603a and the unload lock chamber 603b, the load lock chamber 603a and the unload lock chamber 603b are connected to the transport chamber 604, and the transport chamber 604 is connected to chambers 606a, 606b, 606c and 606d.

[0181] Furthermore, gate valves GV are provided at the connection points of each chamber, and each chamber can be independently maintained in a reduced pressure state, except for the atmospheric substrate supply chamber 601 and the atmospheric substrate transport chamber 602. In addition, a transport robot 609a is provided in the atmospheric substrate transport chamber 602, and a transport robot 609b is provided in the transport chamber 604. Transport robots 609a and 609b can transport substrates within the manufacturing apparatus 600.

[0182] The back pressure (total pressure) of the transport chamber 604 and each chamber is, for example, 1 × 10⁻⁶. −４ Pa or less, preferably 3 × 10 −５ Pa or less, more preferably 1 × 10 −５ The pressure shall be less than or equal to Pa. Furthermore, the partial pressures of gas molecules (or atoms) with a mass-to-charge ratio (m / z) of 18, gas molecules (or atoms) with a mass-to-charge ratio (m / z) of 28, and gas molecules (or atoms) with a mass-to-charge ratio (m / z) of 44 in the transport chamber 604 and each chamber shall be, for example, 3 × 10⁻⁶.−５ Pa or less, preferably 1 × 10 −５ Pa or less, more preferably 3 × 10 −６ The pressure should be below Pa. By lowering the partial pressure of gas molecules (or atoms) with a mass-to-charge ratio (m / z) of 18, the addition of hydrogen can be suppressed. Similarly, by lowering the partial pressure of gas molecules (or atoms) with a mass-to-charge ratio (m / z) of 28, the addition of nitrogen can be suppressed. Furthermore, by lowering the partial pressure of gas molecules (or atoms) with a mass-to-charge ratio (m / z) of 44, the addition of carbon can be suppressed.

[0183] The total pressure and partial pressure in the transport chamber 604 and each chamber can be measured using a mass spectrometer. For example, a quadrupole mass spectrometer (also known as Q-mass) can be used as the mass spectrometer.

[0184] Furthermore, it is desirable that the transport chamber 604 and each chamber be configured to minimize external or internal leaks. For example, the leak rate of the transport chamber 604 and each chamber should be 3 × 10 −６ Pa・m ３ / s or less, preferably 1 × 10 −６ Pa・m ３ The pressure should be less than or equal to / s. The leak rate can be derived from the total pressure and partial pressure measured using the mass spectrometer described above.

[0185] The leak rate depends on both external and internal leaks. To keep the leak rate below the aforementioned values, measures must be taken to address both external and internal leaks. For example, it is preferable to seal the opening and closing parts of the conveying chamber 604 and each chamber with metal or alloy gaskets.

[0186] Furthermore, aluminum, chromium, titanium, zirconium, nickel, or vanadium, which emit less impurity-containing gas, may be used as components of the manufacturing apparatus 600. Alternatively, the aforementioned metals that emit less impurity-containing gas may be used as a coating on an alloy containing iron, chromium, and nickel. Alloys containing iron, chromium, and nickel are rigid, heat-resistant, and suitable for processing. Here, reducing the surface area by reducing surface irregularities of the components through polishing or other means can reduce the emission of gas.

[0187] The components of the manufacturing apparatus 600 are preferably made of metal as much as possible. For example, when installing a viewing window made of quartz or the like, it is preferable to thinly coat the surface with iron fluoride, aluminum oxide, chromium oxide, or the like to suppress the release of gas.

[0188] Adsorbent material present in the transport chamber 604 and each chamber can cause gas release. Therefore, it is preferable to remove as much of the adsorbent material as possible using a pump with high exhaust capacity and to evacuate the chamber beforehand. Furthermore, it is preferable to bake the transport chamber 604 and each chamber to promote the removal of adsorbent material. Baking can be performed at a temperature of 100°C to 450°C. At this time, if the adsorbent material is removed while introducing an inert gas into the transport chamber 604 and each chamber, the removal rate of the adsorbent material can be further increased. It is preferable to use a noble gas as the inert gas.

[0189] Alternatively, it is preferable to increase the pressure in the transport chamber 604 and each chamber by introducing an inert gas such as a heated noble gas or oxygen, and then exhaust the transport chamber 604 and each chamber again after a certain period of time. This process is effective when repeated between 2 and 30 times, preferably between 5 and 15 times.

[0190] Next, chambers 606b and 606c will be explained using the schematic cross-sectional diagram shown in Figure 6.

[0191] Chambers 606b and 606c are chambers capable of performing microwave plasma treatment on an object to be processed, for example. Note that chambers 606b and 606c differ in their atmosphere during microwave plasma treatment. Since many other components are common to both chambers, they will be described together below.

[0192] Chambers 606b and 606c each have a slot antenna plate 628, a dielectric plate 629, a substrate holder 632, and an exhaust port 639. Outside chambers 606b and 606c, a gas supply source 621, a valve 622, a high-frequency generator 623, a waveguide 624, a mode converter 625, a gas pipe 626, a waveguide 627, a matching box 635, a high-frequency power supply 636, a vacuum pump 637, and a valve 638.

[0193] The high-frequency generator 623 is connected to the mode converter 625 via a waveguide 624. The mode converter 625 is connected to the slot antenna plate 628 via a waveguide 627. The slot antenna plate 628 is positioned in contact with the dielectric plate 629. The gas supply source 621 is connected to the mode converter 625 via a valve 622. Gas is then supplied to chamber 606b or chamber 606c through a gas pipe 626 that passes through the mode converter 625, waveguide 627, and dielectric plate 629. The vacuum pump 637 has the function of exhausting gas and other substances from chambers 606b and 606c via a valve 638 and an exhaust port 639. The high-frequency power supply 636 is connected to the substrate holder 632 via a matching box 635.

[0194] The substrate holder 632 has the function of holding the substrate 631. For example, it has the function of electrostatically or mechanically chucking the substrate 631. It also has the function of being an electrode to which power is supplied from the high-frequency power supply 636. It also has a heating mechanism 633 inside and has the function of heating the substrate 631.

[0195] As the vacuum pump 637, for example, a dry pump, a mechanical booster pump, an ion pump, a titanium sublimation pump, a cryopump, or a turbomolecular pump can be used. In addition to the vacuum pump 637, a cryotrap may also be used. Using a cryopump and cryotrap is particularly preferable because it allows for efficient water exhaust.

[0196] Furthermore, the heating mechanism 633 can be, for example, a mechanism that uses a resistance heating element to heat. Alternatively, it may be a mechanism that heats by heat conduction or thermal radiation from a heated medium such as gas.

[0197] Furthermore, the gas supply source 621 may be connected to the purifier via a mass flow controller. It is preferable to use a gas with a dew point of -80°C or lower, preferably -100°C or lower. For example, oxygen gas, nitrogen gas, and noble gases (such as argon) may be used.

[0198] For example, silicon oxide (quartz), aluminum oxide (alumina), or yttrium oxide (yttria) may be used as the dielectric plate 629. Furthermore, another protective layer may be formed on the surface of the dielectric plate 629. For the protective layer, magnesium oxide, titanium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silicon oxide, aluminum oxide, or yttrium oxide may be used. Since the dielectric plate 629 will be exposed to particularly high-density regions of the high-density plasma 630, providing a protective layer can mitigate damage. As a result, an increase in particles during processing can be suppressed.

[0199] The high-frequency generator 623 has the function of generating microwaves in the range of 0.3 GHz to 3.0 GHz, 0.7 GHz to 1.1 GHz, or 2.2 GHz to 2.8 GHz. The microwaves generated by the high-frequency generator 623 are transmitted to the mode converter 625 via the waveguide 624. In the mode converter 625, the microwaves transmitted as TE (Transverse Electric) mode are converted to TEM (Transverse Electric and Magnetic) mode. The microwaves are then transmitted to the slot antenna plate 628 via the waveguide 627. The slot antenna plate 628 is provided with a plurality of slot holes, and the microwaves pass through these slot holes and the dielectric plate 629. This generates an electric field below the dielectric plate 629, and a high-density plasma 630 can be generated. The high-density plasma 630 contains ions and radicals corresponding to the type of gas supplied from the gas supply source 621. For example, oxygen radicals are present.

[0200] At this time, the ions and radicals generated by the high-density plasma 630 can modify the film quality and surface state of the film on the substrate 631. Furthermore, the crystallinity of the film on the substrate 631 can be improved. It is preferable to apply a bias to the substrate 631 using a high-frequency power supply 636. For example, an RF power supply with frequencies such as 13.56 MHz or 27.12 MHz can be used for the high-frequency power supply 636. If recesses are formed in the film on the substrate 631, applying a bias to the substrate side allows ions in the high-density plasma 630 to efficiently reach deep into the recesses.

[0201] For example, oxygen radical treatment using high-density plasma 630 can be performed by introducing oxygen gas from gas supply source 621 in chamber 606b or chamber 606c. Similarly, hydrogen radical treatment using high-density plasma 630 can be performed by introducing hydrogen gas.

[0202] Figure 6 shows one gas supply source 621 and one valve 622, but it is preferable to provide multiple of each. For example, when configuring a system that can supply three types of gases, such as a noble gas (e.g., argon), oxygen gas, and hydrogen gas, it is preferable to have a configuration with three gas supply sources 621 and three valves 622 that control the flow rates of each of the three gases. For example, by applying this configuration to chamber 606b and introducing the noble gas and oxygen gas, oxygen radical treatment using high-density plasma 630 can be performed. Alternatively, by applying this configuration to chamber 606c and introducing the noble gas, oxygen gas, and hydrogen gas, radical treatment using high-density plasma 630 can be performed. In this way, the atmosphere can be made different in chamber 606b and chamber 606c.

[0203] Next, chambers 606a and 606d will be described using the schematic cross-sectional diagram shown in Figure 7.

[0204] Chambers 606a and 606d are chambers capable of irradiating the workpiece with electromagnetic waves, for example. Note that chambers 606a and 606d differ in the type of electromagnetic waves they emit. However, many other components are common to both chambers, and will be described together below.

[0205] Chambers 606a and 606d each have one or more lamps 640, a substrate holder 645, a gas inlet 643, and an exhaust port 650. A gas supply source 641, a valve 642, a vacuum pump 648, and a valve 649 are provided outside chambers 606a and 606d.

[0206] The gas supply source 641 is connected to the gas inlet 643 via a valve 642. The vacuum pump 648 is connected to the exhaust port 650 via a valve 649. The lamp 640 is positioned opposite the substrate holder 645. The substrate holder 645 has the function of holding the substrate 644. The substrate holder 645 also has a heating mechanism 646 inside that has the function of heating the substrate 644.

[0207] For example, the lamp 640 can be a light source that has the function of emitting electromagnetic waves such as visible light or ultraviolet light. For example, a light source that has the function of emitting electromagnetic waves with peaks at wavelengths of 10 nm to 2500 nm, 500 nm to 2000 nm, or 40 nm to 340 nm can be used.

[0208] For example, the lamp 640 can be a light source such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp. For example, a halogen lamp can be used as the lamp 640 in chamber 606a, and a light source other than a halogen lamp can be used as the lamp 640 in chamber 606d. In this way, the type of electromagnetic wave can be different in chamber 606a and chamber 606b.

[0209] For example, electromagnetic waves emitted from the lamp 640 can be partially or entirely absorbed by the substrate 644 or a film on the substrate, thereby modifying the film quality and surface condition of the film on the substrate 644. For example, defects can be generated or reduced, or impurities can be removed. Furthermore, if the substrate 644 is heated during the process, the generation or reduction of defects or the removal of impurities can be performed more efficiently. In addition, the crystallinity of the film on the substrate 631 can be improved.

[0210] Alternatively, for example, the substrate holder 645 may be heated by electromagnetic waves emitted from the lamp 640, thereby heating the substrate 644. In this case, the substrate holder 645 does not need to have a heating mechanism 646 inside.

[0211] For the vacuum pump 648, refer to the description of the vacuum pump 637. For the heating mechanism 646, refer to the description of the heating mechanism 633. For the gas supply source 641, refer to the description of the gas supply source 621.

[0212] The microwave plasma processing apparatus that can be used in this embodiment is not limited to the one described above. Figure 8 shows a microwave plasma processing apparatus 660 having a different configuration from the one described above. The microwave plasma processing apparatus 660 has a quartz tube 661, a gas supply source 621, a valve 622, a high-frequency generator 623, a waveguide 624, a gas pipe 626, a vacuum pump 637, a valve 638, and an exhaust port 639. The microwave plasma processing apparatus 660 also has a substrate holder 662 inside the quartz tube 661 that holds a plurality of substrates 631 (631_1 to 631_n, where n is an integer of 2 or more). In Figure 8, substrates 631_1 to 631_4 and substrates 631_n-3 to 631_n are shown with n as an integer of 8 or more. The microwave plasma processing apparatus 660 may also have a heating means 663 on the outside of the quartz tube 661.

[0213] Microwaves generated by the high-frequency generator 623 are irradiated onto a substrate placed inside the quartz tube 661 via the waveguide 624. The vacuum pump 637 is connected to the exhaust port 639 via the valve 638, and the pressure inside the quartz tube 661 can be adjusted. The gas supply source 621 is connected to the gas pipe 626 via the valve 622, and a desired gas can be introduced into the quartz tube 661. The heating means 663 can heat the substrate 631 inside the quartz tube 661 to a desired temperature. Alternatively, the heating means 663 may heat the gas supplied from the gas supply source 621. The microwave plasma processing apparatus 660 can perform heating treatment and microwave plasma treatment on the substrate 631 simultaneously. Alternatively, the substrate 631 can be heated first, followed by microwave plasma treatment, and then heated.

[0214] Substrates 631_1 to 631_n can all be processing substrates for forming semiconductor devices or memory devices. Some of the substrates may be dummy substrates. Using dummy substrates is preferable because it allows multiple processing substrates to be processed uniformly during microwave plasma processing or heat processing, and reduces variations between processing substrates. For example, it is preferable to place a dummy substrate on the processing substrate closest to the high-frequency generator 623 and waveguide 624 so that the processing substrate is not directly exposed to microwaves.

[0215] This microwave plasma processing apparatus can be used to perform oxygen radical treatment or hydrogen radical treatment. It allows for film modification while suppressing the incorporation of impurities into the treated material.

[0216] This embodiment can be implemented in appropriate combination with other embodiments or examples described herein, at least in part.

[0217] (Embodiment 3) This embodiment describes an example of the configuration of a semiconductor device according to one aspect of the present invention. The semiconductor device according to one aspect of the present invention has a transistor. The transistor has a semiconductor layer, a conductive layer that functions as a gate electrode, and an insulating layer that functions as a gate insulating layer. The insulating layer has a portion located between the semiconductor layer and the conductive layer. The semiconductor layer of the transistor exemplified below can be the metal oxide layer exemplified in Embodiment 1.

[0218] [Example of Semiconductor Device Configuration] Figure 9A is a top view of a semiconductor device having a transistor 200, and Figures 9B and 9C are cross-sectional views corresponding to the cutting lines A1-A2 and A3-A4 in Figure 9A, respectively. Figure 9B corresponds to a cross-section in the channel length direction of the transistor 200, and Figure 9C corresponds to a cross-section in the channel width direction. Figures 11A and 11B are enlarged views of Figure 9B. Note that some components are omitted in Figure 9A.

[0219] The semiconductor device shown in Figures 9A to 9C comprises a substrate 210, an insulating layer 201 provided on the substrate 210, and a transistor 200 provided on the insulating layer 201. The transistor 200 comprises a semiconductor layer 230, a conductive layer 242a, a conductive layer 242b, and an insulating layer 250 on the semiconductor layer 230, and a conductive layer 260 on the insulating layer 250.

[0220] An insulating layer 275 is provided covering the semiconductor layer 230, the conductive layer 242a, and the conductive layer 242b, and an insulating layer 280 is provided on the insulating layer 275. The insulating layer 280 and the insulating layer 275 are provided with openings (also called grooves) that reach the semiconductor layer 230. The insulating layer 250 is provided inside the openings along the surfaces of the insulating layer 280, the insulating layer 275, the conductive layer 242a, the conductive layer 242b, the semiconductor layer 230, and the insulating layer 201. The conductive layer 260 is provided so as to fill the openings. An insulating layer 282 is provided covering the insulating layer 280, the insulating layer 250, and the conductive layer 260, and an insulating layer 283 and an insulating layer 285 are provided on the insulating layer 282 in that order.

[0221] In transistor 200, the conductive layer 260 functions as a gate electrode, and the insulating layer 250 functions as a gate insulating layer. Furthermore, the conductive layer 242a functions as either a source electrode or a drain electrode, and the conductive layer 242b functions as the other.

[0222] The semiconductor layer 230 has a channel formation region in the transistor 200, and a source region and a drain region provided so as to sandwich the channel formation region. At least a part of the channel formation region overlaps with the conductive layer 260. The source region overlaps with the conductive layer 242a, and the drain region overlaps with the conductive layer 242b. The source region and the drain region can be swapped with each other. The source region and the drain region are n-type regions (low-resistance regions) with a higher carrier concentration compared to the channel formation region.

[0223] The substrate 210, insulating layer 201, and semiconductor layer 230 can be made using the substrate 10, insulating layer 20, and metal oxide layer 30 exemplified in Embodiment 1, respectively.

[0224] Crystal grain boundaries can act as recombination centers, potentially trapping carriers and causing a decrease in transistor on-current and field-effect mobility. There is also concern that they may increase the off-current. Therefore, it is preferable to avoid the formation of crystal grain boundaries in the channel formation region of a transistor as much as possible. This is particularly important in nm-level VLSIs, where the presence of crystal grain boundaries in the transistor's channel formation region impairs its electrical properties, potentially rendering the entire chip defective. For example, by using a single-crystal metal oxide layer in an island or stripe pattern, as exemplified in Embodiment 1, as the semiconductor layer of the transistor, it is possible to achieve a configuration where the channel formation region is single-crystal, or where no crystal grain boundaries are formed in the channel formation region. This suppresses variations in the transistor's electrical properties across the substrate surface.

[0225] Furthermore, a seed layer 231, corresponding to the seed layer 31 exemplified in Embodiment 1, may be provided between the semiconductor layer 230 and the insulating layer 201. In Figures 10A and 10B, the seed layer 231 is provided so as to overlap with the conductive layer 242b. By providing the seed layer 231 so as to overlap with only one of the conductive layers 242a or 242b, the crystallinity of the channel formation region can be improved, for example, by achieving single crystallization of the channel formation region. This can increase the field-effect mobility and on-current of the transistor.

[0226] Figure 11A shows a configuration in which the semiconductor layer 230 is a single layer. However, the semiconductor layer 230 can be a stacked structure. In the configuration example shown in Figure 11B, the semiconductor layer 230 has semiconductor layer 230_1, semiconductor layer 230_2 on semiconductor layer 230_1, and semiconductor layer 230_3 on semiconductor layer 230_2. The metal oxide layers 30_1 to 30_3 exemplified in Embodiment 1 can be applied to semiconductor layers 230_1 to 230_3, respectively.

[0227] It is preferable that semiconductor layers 230_1 to 230_3 contain indium oxide. Alternatively, semiconductor layers 230_1 and 230_3 may contain indium oxide containing the second element described in Embodiment 1. Oxides containing the second element have a larger band gap than indium oxide. Therefore, the band gap of indium oxide containing the second element may be larger than the band gap of indium oxide. Also, the electron affinity of indium oxide containing the second element may be smaller than the electron affinity of indium oxide. By making the electron affinity of semiconductor layer 230_1 and semiconductor layer 230_3 smaller than the electron affinity of semiconductor layer 230_2, the carrier flow path can be moved away from the interface between the insulating layer 250 and the semiconductor layer 230, and the effects of surface scattering can be reduced. As a result, it may be possible to increase the on-current or improve reliability. With such a configuration, the transistor can be made into an embedded channel structure.

[0228] The semiconductor layer 230_2 may use indium oxide containing the first element described in Embodiment 1. However, using indium oxide containing gallium in the semiconductor layer 230_2 may cause a decrease in the on-current of the transistor 200 due to impurity scattering, etc. Therefore, it is preferable that the semiconductor layer 230_2 be of high purity. For example, the concentration of one or more elements selected from carbon, nitrogen, and gallium in the semiconductor layer 230_2 is 1 × 10⁻⁶. ２０ atoms / cm ３ The following is preferable: 5 × 10 １９ atoms / cm ３ The following is more preferable: 1 × 10 １９ atoms / cm ３ The following is more preferable: 5 × 10 １８ atoms / cm ３ This is even more preferable. These concentrations are calculated as the average value of the concentrations within the valid range of the SIMS measurement results.

[0229] It is preferable that the film thickness of semiconductor layer 230_1 and semiconductor layer 230_3 be thin. The film thickness of semiconductor layer 230_1 and semiconductor layer 230_3 are each 0.1 nm to 3 nm, preferably 0.1 nm to 2.5 nm, more preferably 0.1 nm to 2 nm, and even more preferably 0.5 nm to 2 nm. It is preferable that semiconductor layer 230_1 and semiconductor layer 230_3 each have at least a portion of the above-mentioned film thickness region.

[0230] To achieve a large on-current of the transistor, a thicker semiconductor layer 230_2 is preferable. On the other hand, if the thickness of the semiconductor layer 230_2 is made too thick, the density of grain boundaries increases due to self-crystallization, and the on-current of the transistor may decrease due to the effect of carrier scattering at the grain boundaries. Therefore, it is preferable that the thickness of the semiconductor layer 230_2 is the same as the channel length of the transistor 200, or thinner than the channel length. For example, the thickness of the semiconductor layer 230_2 is 2 nm or more and 50 nm or less. It is preferable that the semiconductor layer 230_2 has a region with the above-mentioned thickness in at least a part of it. As will be described later, the transistor using the indium oxide film is a storage-type transistor with electrons as the majority carrier. In this case, the higher the surface density of donors in the channel formation region, that is, the larger the product of the donor concentration in the channel formation region and the thickness of the semiconductor layer 230, the lower the threshold voltage becomes, and the transistor may become normally-on. By reducing the surface density of donors in the channel formation region, for example by thinning the film thickness of semiconductor layer 230_2, it is possible to suppress the decrease in threshold voltage and create a normally-off transistor. Channels may be formed in one or both of semiconductor layers 230_1 and 230_3. In this case, it is preferable that the film thickness of semiconductor layer 230, that is, the total film thickness of semiconductor layers 230_1 to 230_3, be the same as the channel length or thinner than the channel length.

[0231] It is preferable that the conductive layer 242a and the conductive layer 242b each have a laminated structure. For example, as shown in Figure 11A, the conductive layer 242a may have a conductive layer 242a1 on the semiconductor layer 230 and a conductive layer 242a2 on the conductive layer 242a1. The conductive layer 242b may have a conductive layer 242b1 on the semiconductor layer 230 and a conductive layer 242b2 on the conductive layer 242b1.

[0232] The conductive layers 242a1 and 242b1 can be made of conductive materials that are resistant to oxidation, conductive materials that maintain low electrical resistance even when oxidized, conductive metal oxides (also called oxide conductors), or conductive materials that have the function of suppressing oxygen diffusion. This allows conductive layers 242a and 242b to maintain conductivity even if they absorb oxygen. Each of the conductive layers 242a1 and 242b1 contains, for example, indium, a third element, and oxygen. The third element is preferably one or more selected from tin, zinc, tungsten, titanium, and zirconium. Specifically, the conductive layers 242a1 and 242b1 can be made from metal oxides such as indium tin oxide (In-Sn oxide, also known as ITO), silicon-containing indium tin oxide (also known as ITSO), indium zinc oxide (In-Zn oxide, also known as IZO®), tungsten-containing indium tin oxide (In-Sn-W oxide, also known as ITWO), indium titanium oxide (In-Ti oxide), and indium zirconium oxide (In-Zr oxide).

[0233] If the main components of the source electrode and drain electrode are the same as the main components of the semiconductor layer, the work functions of the source electrode and drain electrode can be made to approximately match the lower edge of the conduction band of the semiconductor layer. This reduces the energy barrier between the source electrode and drain electrode and the semiconductor layer. Therefore, the contact resistance between the source electrode and the semiconductor layer, and the contact resistance between the drain electrode and the semiconductor layer can be reduced. For example, the main components of the source electrode and drain electrode, and the main component of the semiconductor layer, can be indium.

[0234] By making the main component of semiconductor layer 230 the same as the main components of conductive layer 242a1 and conductive layer 242b1, a reduction in the thickness of semiconductor layer 230 may occur when processing the conductive films that become conductive layer 242a1 and conductive layer 242b1. In this case, the film thickness of the portion of semiconductor layer 230 that overlaps with conductive layer 260 becomes thinner than the film thickness of the portion of semiconductor layer 230 that overlaps with conductive layer 242a1 or conductive layer 242b1 (see Figure 12A).

[0235] Furthermore, the same reduction in the thickness of the semiconductor layer 230 described above also occurs when the semiconductor layer 230 has a stacked structure. For example, when the semiconductor layer 230 has a three-layer structure consisting of semiconductor layers 230_1 to 230_3, the film thickness of the portion of semiconductor layer 230_3 that overlaps with the conductive layer 260 may become thinner than the film thickness of the portion of semiconductor layer 230_3 that overlaps with the conductive layer 242a1 or conductive layer 242b1 (see Figure 12B). Alternatively, the portion of semiconductor layer 230_3 that overlaps with the insulating layer 250 may be removed (see Figure 12C).

[0236] Conductive layers 242a1 and 242b1 may also be made of conductive materials such as tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide, which have the function of suppressing the permeation of impurities such as water and hydrogen. Furthermore, the conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or in a laminated form. By providing conductive layers 242a1 and 242b1, the diffusion of impurities such as water and hydrogen into the semiconductor layer 230 through conductive layers 242a2 and 242b2 can be suppressed.

[0237] It is preferable to use a metal or alloy with higher conductivity than conductive layers 242a1 and 242b1 for conductive layers 242a2 and 242b2. For example, it is preferable to use a low-resistance conductive material such as tungsten, copper, or aluminum. This can improve the conductivity of conductive layers 242a and 242b.

[0238] Furthermore, materials containing metallic elements such as gold, platinum, palladium, silver, ruthenium, copper, bismuth, lead, tin, nickel, cobalt, cadmium, and iron are conductive materials that are resistant to oxidation, and therefore these materials can also be used for conductive layers 242a1 and 242b1. In addition, since these materials tend to have low resistivity, they can also be used for conductive layers 242a2 and 242b2.

[0239] For example, ITO can be used as conductive layer 242a1 and conductive layer 242b1, and tungsten can be used as conductive layer 242a2 and conductive layer 242b2.

[0240] The conductive layers 242a and 242b can also be single-layer structures. In this case, the above-mentioned metal oxides such as ITO or ITSO can be used as the conductive layers 242a and 242b.

[0241] As shown in Figure 13A, an insulating layer 271a can be provided between the conductive layer 242a and the insulating layer 275, and an insulating layer 271b can be provided between the conductive layer 242b and the insulating layer 275. The insulating layers 271a and 271b each function as etching stoppers during processing of the conductive layers 242a and 242b. In other words, the insulating layers 271a and 271b each have the function of protecting the conductive layers 242a and 242b. Furthermore, since the insulating layers 271a and 271b are in contact with the conductive layers 242a and 242b, respectively, it is preferable that they be inorganic insulators that do not easily oxidize the conductive layers 242a and 242b. For example, the insulating layer 271a can be a laminated structure of a silicon nitride film in contact with the conductive layer 242a and a silicon oxide film on the silicon nitride film. The laminated structure of the insulating layer 271b is similar.

[0242] Furthermore, as shown in Figure 13A, it is possible to provide an insulating layer 255 between the conductive layer 242a2 and the insulating layer 250, and between the conductive layer 242b2 and the insulating layer 250. Since the insulating layer 255 is in contact with the conductive layers 242a2 and 242b2, it is preferable that the insulating layer 255 is an inorganic insulator that does not easily oxidize the conductive layers 242a2 and 242b2. This prevents excessive oxidation of the conductive layers 242a2 and 242b2 by heat treatment, even if a relatively easily oxidized tungsten film or the like is used for the conductive layers 242a2 and 242b2. For example, a silicon nitride film can be used as the insulating layer 255.

[0243] The insulating layer 255 can be formed by creating openings in the insulating layers 280 and 275, removing the portions of the insulating film that will become insulating layers 271a and 271b, and the conductive film that will become conductive layers 242a2 and 242b2 that overlap with the openings, forming the insulating film that will become the insulating layer 255, and processing the insulating film using anisotropic etching. In other words, the insulating layer 255 is formed in a sidewall shape, in contact with the side wall of the opening.

[0244] Figure 13B shows an example configuration in which a three-layer structure of semiconductor layers 230_1 to 230_3 is applied as the semiconductor layer 230 in the configuration shown in Figure 13A.

[0245] The conductive layer 260 is preferably provided extending in the channel width direction, as shown in Figures 9A and 9C. With this configuration, when multiple transistors are provided, the conductive layer 260 functions as wiring.

[0246] The conductive layer 260 may have a laminated structure. Figure 11A shows an example in which the conductive layer 260 has a conductive layer 260a located on the side in contact with the insulating layer 250 and a conductive layer 260b on the conductive layer 260a. In this case, it is preferable to use a conductive material that is resistant to oxidation, such as titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide, or a conductive material that has the function of suppressing oxygen diffusion, for the conductive layer 260a. It is also preferable to use a low-resistance conductive material such as tungsten, copper, or aluminum for the conductive layer 260b.

[0247] As shown in Figure 14A, the transistor may have a conductive layer 205 that functions as a transistor back gate. The transistor 200 shown in Figure 14A differs from the transistor shown in Figure 11A mainly in that it has a conductive layer 205 and an insulating layer 202.

[0248] The conductive layer 205 is provided so as to be embedded in the insulating layer 202. The height of the upper surface of the conductive layer 205 and the height of the upper surface of the insulating layer 202 are the same. The insulating layer 201 is provided covering the insulating layer 202 and the conductive layer 205. By providing the insulating layer 201 on top of the conductive layer 205 and the insulating layer 202, whose upper surface heights are the same, the flatness of the upper surface of the insulating layer 201 can be improved.

[0249] The conductive layer 205 functions as the second gate (back gate) of the transistor 200. The conductive layer 205 is provided in a region that overlaps with the conductive layer 260 via the semiconductor layer 230. The conductive layer 260 is sometimes referred to as the first gate (front gate).

[0250] The conductive layer 205 can be made of a material that can be used for the conductive layer 260. Furthermore, the conductive layer 205 may have a laminated structure. For example, it may have a laminated structure of an insulating layer 202, a titanium nitride film in contact with the substrate 210, and a tungsten film on the titanium nitride film.

[0251] Furthermore, the conductive layer 205 can also be made of an oxide conductor. Compared to materials composed of metal elements (also called metallic materials), this oxide conductor is more likely to maintain its conductivity even when absorbing oxygen. For example, even when an oxide insulating film is used for the insulating layer 202, the conductive layer 205 can maintain its conductivity, making it suitable. Examples of such oxide conductors include metal oxides such as ITO, ITSO, In-Zn oxide, and In-Ti oxide.

[0252] When the conductive layer 205 functions as the second gate of the transistor 200, the insulating layer 201 functions as the second gate insulating layer.

[0253] The insulating layer 202 can be made of a silicon oxide film. Alternatively, an insulating film having an oxygen barrier can be provided between the insulating layer 202 and the conductive layer 205. This can suppress oxidation of the conductive layer 205.

[0254] The insulating layer 250 can be a laminated structure of two or more layers. Figure 14B is an enlarged view of the cross-section in the channel width direction of the transistor 200 shown in Figure 14A. For example, Figure 14B shows an example in which the insulating layer 250 has a laminated structure consisting of an insulating layer 250_1 in contact with the semiconductor layer 230, an insulating layer 250_2 on insulating layer 250_1, and an insulating layer 250_3 on insulating layer 250_2.

[0255] The insulating layer 201 can have a laminated structure of two or more layers. For example, Figure 14B shows an example in which the insulating layer 201 has a laminated structure consisting of an insulating layer 201_1 in contact with the semiconductor layer 230, an insulating layer 201_2 below insulating layer 201_1, and an insulating layer 201_3 below insulating layer 201_2.

[0256] The insulating layer 250 is preferably formed from two or more films. By using two or more films for the insulating layer 250, multiple functions can be imparted to the insulating layer 250. Examples of functions that the insulating layer 250 may have include supplying oxygen to the semiconductor layer 230, extracting excess oxygen contained in the semiconductor layer 230, extracting hydrogen contained in the semiconductor layer 230, and suppressing the diffusion of hydrogen into the semiconductor layer 230. The same applies to the insulating layer 201.

[0257] For example, it is preferable that insulating layer 250_1 and insulating layer 201_1 have insulating layers that have the function of supplying oxygen. It is preferable that insulating layer 250_2 and insulating layer 201_2 have insulating layers that have the function of capturing and fixing hydrogen. It is preferable that insulating layer 250_3 and insulating layer 201_3 have insulating layers that have high barrier properties against hydrogen.

[0258] Examples of insulating layers that have the function of supplying oxygen include silicon oxide layers or silicon oxynitride layers. Silicon oxide and silicon oxynitride are also materials with high dielectric breakdown voltage. Therefore, by using silicon oxide or silicon oxynitride, the dielectric breakdown voltage of transistor 200 can be improved.

[0259] It is preferable to use metal oxides such as magnesium oxide, aluminum oxide, hafnium oxide, aluminum, and hafnium-containing oxides (hafnium aluminate) as insulators that have the function of capturing and fixing hydrogen.

[0260] Furthermore, in addition to its function of capturing and fixing hydrogen, hafnium oxide also has the function of capturing and fixing oxygen. Because insulating layers 250_2 and 201_2 contain hafnium oxide, excess oxygen contained in the semiconductor layer 230 can be captured and fixed. Also, since hafnium oxide is a high-k material, its use can reduce gate leakage in transistors.

[0261] Examples of insulators that have barrier properties against hydrogen include nitrides such as silicon nitride and oxides such as tantalum oxide. Silicon nitride is suitable for insulating layer 250_3 and insulating layer 201_3 because of its high barrier properties against hydrogen.

[0262] The above film configuration can also be understood as a layered structure consisting of a film that can supply oxygen to a film adjacent to the indium oxide film (e.g., a silicon oxide film), a film that can getter hydrogen (e.g., a hafnium oxide film) on its outer periphery, and a film that suppresses the intrusion of oxygen and hydrogen (e.g., a silicon nitride film) on its outer periphery. With this configuration, oxygen deficiencies in the indium oxide film are compensated for by oxygen in the silicon oxide film. In addition, hydrogen in the indium oxide film is captured by the hafnium oxide film through heat treatment or other means. Furthermore, the presence of the silicon nitride film results in a film configuration that minimizes the intrusion of oxygen and hydrogen from the outside. In other words, with the above film configuration, the indium oxide film becomes more i-type. Therefore, transistors having the above-described indium oxide film have high field-effect mobility and high reliability.

[0263] By arranging the insulating layer 201 and the insulating layer 250 in a symmetrical structure in the vertical direction (stacking direction) with respect to the semiconductor layer 230, it may be possible to appropriately control the hydrogen concentration distribution and oxygen concentration distribution in and around the semiconductor layer 230. This may result in good electrical characteristics and high reliability in the transistor.

[0264] The insulating layer 250_1, insulating layer 250_2, and insulating layer 250_3 can be, for example, a silicon oxide film with a thickness of 1.5 nm to 2.0 nm, a hafnium oxide film with a thickness of 1.5 nm to 3.0 nm, and a silicon nitride film with a thickness of 1.0 nm to 3.0 nm.

[0265] Furthermore, the insulating layer 250 may have an insulating film that provides a barrier to oxygen. For example, in the configuration shown in Figure 14B, an insulating film that provides a barrier to oxygen may be provided between the semiconductor layer 230 and the insulating layer 250_1. Examples of insulators that provide a barrier to oxygen include aluminum oxide and gallium oxide. By providing an insulating layer 250 that provides a barrier to oxygen between the channel-forming region of the semiconductor layer 230 and the conductive layer 260, it is possible to suppress the diffusion of oxygen contained in the channel-forming region into the conductive layer 260 and the formation of oxygen vacancies in the channel-forming region. In addition, it is possible to suppress the diffusion of oxygen contained in the semiconductor layer 230 into the conductive layer 260 and the oxidation of the conductive layer 260.

[0266] In particular, by providing a gallium oxide film or an aluminum oxide film between the semiconductor layer 230 and the insulating layer 250_1, hydrogen in the semiconductor layer 230 can permeate through the gallium oxide film or aluminum oxide film and the insulating layer 250_1, be captured and fixed in the insulating layer 250_2, and reduce the hydrogen concentration in the semiconductor layer 230. Furthermore, this is preferable because it suppresses the formation of oxygen vacancies at the interface between the semiconductor layer 230 and the gallium oxide film or aluminum oxide film. For hydrogen to permeate through the gallium oxide film or aluminum oxide film, the film thickness of the gallium oxide film or aluminum oxide film provided between the semiconductor layer 230 and the insulating layer 250_1 should be 0.1 nm or more and 3 nm or less, preferably 0.5 nm or more and 1.5 nm or less.

[0267] Furthermore, an insulating film having barrier properties against oxygen may be provided between the semiconductor layer 230 and the insulating layer 201_1. This prevents oxygen contained in the channel-forming region from diffusing into the conductive layer 205 and suppresses the formation of oxygen vacancies in the channel-forming region. It also prevents oxygen contained in the semiconductor layer 230 from diffusing into the conductive layer 205 and suppresses oxidation of the conductive layer 205.

[0268] In the manufacturing process of semiconductor devices, oxygen can be supplied from the insulating layer 250 and insulating layer 201 to the semiconductor layer 230 by heat treatment. In this case, by providing the insulating layer having the function of supplying oxygen by heating only on the insulating layer 250 side, oxygen can be selectively supplied to the channel formation region of the semiconductor layer 230. Therefore, it may not be necessary to provide an insulating layer having the function of supplying oxygen by heating on the insulating layer 201 side.

[0269] For example, the insulating layer 250 may have an insulating layer 250_1 that has the function of supplying oxygen, while the insulating layer 201 may not have an insulating layer 201_1 that has the function of supplying oxygen. Alternatively, for example, the thickness of the insulating layer 201_1 may be greater than that of the insulating layer 250_1.

[0270] When processing the semiconductor layer 230 into an island shape, portions of the insulating layer 201_1 that do not overlap with the semiconductor layer 230 may be removed. Figure 14C shows an example of a configuration in which the insulating layer 201_1 has an island shape in a plan view. Figure 14C is an enlarged view of the cross-section in the channel width direction of the transistor 200 shown in Figure 14A.

[0271] By setting the thickness of the insulating layer 250 and the insulating layer 201 to 1 nm to 20 nm, preferably 3 nm to 10 nm, the subthreshold swing value (also called the S value), which is one of the transistor characteristics, can be reduced. The S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude while the drain voltage is constant in the subthreshold region.

[0272] Furthermore, the film thickness of each layer constituting the insulating layer 250 and the insulating layer 201 is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm. Note that each layer constituting the insulating layer 250 and the insulating layer 201 only needs to have a region with the above-mentioned film thickness in at least a portion of it.

[0273] If the materials used as insulating layer 250 and insulating layer 201 are ferroelectric materials, the transistor can function as, for example, an FeFET (Ferroelectric Field Effect Transistor).

[0274] Examples of materials that may possess ferroelectric properties include oxides containing one or both hafnium and zirconium. Examples of such oxides include metal oxides such as hafnium oxide, zirconium oxide, and hafnium-zirconium oxide. Alternatively, as a material that may possess ferroelectric properties, a material may be used in which element J1 (where element J1 is one or more selected from the other of hafnium and zirconium, silicon, aluminum, scandium, yttrium, lanthanum, strontium, gadolinium, etc.) is added to a metal oxide containing one of hafnium and zirconium.

[0275] Incidentally, the crystal structure (properties) of the materials listed above can change not only depending on the film deposition conditions but also on various processes. Therefore, in this specification, materials that exhibit ferroelectricity are not only called ferroelectrics, but also materials that may possess ferroelectricity.

[0276] The insulating layer 275 preferably has barrier properties against hydrogen. The insulating layer 275 is provided between the insulating layer 280 and the semiconductor layer 230. This configuration suppresses the diffusion of hydrogen contained in the insulating layer 280 into the semiconductor layer 230. Therefore, it is possible to suppress the increase in hydrogen concentration in the semiconductor layer 230, particularly in the channel formation region, due to the hydrogen contained in the insulating layer 280. For example, silicon nitride is preferably used as the insulating layer 275. Since silicon nitride also has barrier properties against oxygen, it can be said to be an insulator that has barrier properties against both hydrogen and oxygen.

[0277] The insulating layer 280 preferably has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance between wirings can be reduced. For example, the insulating layer 280 preferably has one or more of the following: silicon oxide, silicon oxynitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and silicon oxide with vacancies. Silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0278] Furthermore, in this embodiment, it is preferable to configure the semiconductor device to suppress the diffusion of hydrogen into the transistor 200, etc., in addition to the above configuration. For example, it is preferable to provide an insulator having the function of suppressing hydrogen diffusion so as to cover the transistor 200. In the semiconductor device described in this embodiment, the insulator is, for example, an insulating layer 282 and an insulating layer 283.

[0279] It is preferable that one or more of the insulating layers 282 and 283 function as a barrier insulator that suppresses the diffusion of impurities such as water and hydrogen from above the transistor 200 to the transistor 200. Therefore, it is preferable that one or more of the insulating layers 282 and 283 function as a barrier insulator that suppresses the diffusion of impurities such as water and hydrogen to the transistor 200 from above. ２ O, NO, NO ２ It is preferable to have an insulating material that has the function of suppressing the diffusion of impurities such as copper atoms (i.e., the above-mentioned impurities do not easily permeate). Alternatively, it is preferable to have an insulating material that has the function of suppressing the diffusion of oxygen (i.e., at least one such as oxygen atoms and oxygen molecules) (i.e., the above-mentioned oxygen does not easily permeate).

[0280] The insulating layer 282 and insulating layer 283 preferably have an insulator that has the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, or silicon nitride oxide can be used. For example, it is preferable to use silicon nitride, which has higher hydrogen barrier properties, as the insulating layer 283. Also, for example, it is preferable that the insulating layer 282 has aluminum oxide or magnesium oxide, which have high hydrogen capture and hydrogen fixation functions. This makes it possible to suppress the diffusion of impurities such as water and hydrogen from the interlayer insulating film located outside the insulating layer 283 to the transistor 200, etc. Also, it is possible to suppress the diffusion of oxygen contained in the insulating layer 280, etc., upward from the transistor 200, etc. via the insulating layer 282, etc. Furthermore, by providing a film similar to one or both of the insulating layers 282 and 283 below the transistor 200, it is possible to suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200, etc.

[0281] Openings reaching the conductive layer 242a are formed in insulating layers 285, 283, 282, 280, and 275, and the conductive layer 243a and insulating layer 241a are provided within these openings. The insulating layer 241a is provided in contact with the side wall of the opening, and the conductive layer 243a is provided inside the insulating layer 241a. In addition, openings reaching the conductive layer 242b are formed in insulating layers 285, 283, 282, 280, and 275, and the conductive layer 243b and insulating layer 241b are provided within these openings. The insulating layer 241b is provided in contact with the side wall of the opening, and the conductive layer 243b is provided inside the insulating layer 241b. The conductive layer 243a and conductive layer 243b are provided with a conductive layer 260 in between. The upper surfaces of conductive layer 243a and conductive layer 243b are at the same height as the upper surface of insulating layer 285.

[0282] As insulating layers 241a and 241b, barrier insulators that can be used for insulating layer 275 and the like can be used. For example, silicon nitride can be used as insulating layer 241a and insulating layer 241b. This makes it possible to suppress the mixing of impurities such as water and hydrogen contained in insulating layer 280, etc., into semiconductor layer 230 through conductive layer 243a and conductive layer 243b. In addition, it is possible to prevent oxygen contained in insulating layer 280 from being absorbed by conductive layer 243a and conductive layer 243b.

[0283] Each of the conductive layers 243a and 243b may have a laminated structure. Figure 11A shows an example in which the conductive layer 243a has a two-layer structure consisting of a conductive layer 243a1 in contact with the side surface of the insulating layer 241a and the conductive layer 242a, and a conductive layer 243a2 on top of the conductive layer 243a1, and the conductive layer 243b has a two-layer structure consisting of a conductive layer 243b1 in contact with the side surface of the insulating layer 241b and the conductive layer 242b, and a conductive layer 243b2 on top of the conductive layer 243b1. For example, titanium or titanium nitride can be used for conductive layers 243a1 and 243b1, and tungsten, copper, or aluminum can be used for conductive layers 243a2 and 243b2.

[0284] Furthermore, Figure 15 shows an example configuration in which a conductive layer 205 and an insulating layer 202 are provided in the configuration shown in Figure 13B.

[0285] [Modified Version] The following describes an example with some configuration differences from the above example. Note that the following explanation omits parts that overlap with the above.

[0286] [Modification 1] The above describes a configuration in which the gate electrode is embedded in an insulating layer, but the following describes a transistor with a different configuration.

[0287] Figure 16A shows a cross-sectional view of transistor 200a in the channel length direction. Transistor 200a has a semiconductor layer 230, an insulating layer 250, a conductive layer 260, a conductive layer 242a, and a conductive layer 242b.

[0288] An insulating layer 250 is provided covering the semiconductor layer 230, and a conductive layer 260 is provided on the insulating layer 250 at a position overlapping with the semiconductor layer 230. Furthermore, insulating layers 281 and 280 are laminated and provided covering the insulating layer 250 and the conductive layer 260. A pair of openings reaching the semiconductor layer 230 is provided in the insulating layer 281, insulating layer 280, and insulating layer 250, respectively. Conductive layers 242a and 242b are provided on the insulating layer 280 and are in contact with the semiconductor layer 230 at their respective openings.

[0289] As the insulating layer 281, an insulator having barrier properties against hydrogen and oxygen, similar to that of the insulating layer 275, can be used. This suppresses the diffusion of impurities contained in the insulating layer 280 into the semiconductor layer 230, and the diffusion of oxygen contained in the semiconductor layer 230 towards the insulating layer 280. Furthermore, the insulating layer 281 can also be a laminated structure consisting of an insulating layer having barrier properties against hydrogen and an insulating layer having barrier properties against oxygen.

[0290] The region of the semiconductor layer 230 that overlaps with the conductive layer 260 functions as a channel-forming region. Furthermore, a pair of regions 230n flanking the channel-forming region function as a source region or a drain region. It is preferable that regions 230n have lower resistance than the channel-forming region.

[0291] For example, region 230n preferably contains an element that imparts conductivity to the semiconductor layer 230. Examples of such elements include typical nonmetallic elements other than hydrogen and oxygen, typical metallic elements, and transition elements (transition metals). Specifically, examples include boron, phosphorus, magnesium, aluminum, silicon, etc. These elements can be introduced into a portion of the semiconductor layer 230 by methods such as doping, ion implantation, or thermal diffusion. For example, using the conductive layer 260 as a mask, the above elements can be introduced into a region of the semiconductor layer 230 that does not overlap with the conductive layer 260 via the insulating layer 250 by doping or ion implantation.

[0292] Figure 16B shows an example where the insulating layer 250 is located only in the region overlapping with the conductive layer 260 and is not provided on the region 230n of the semiconductor layer 230. In this case, by using a film containing the above-mentioned elements for the insulating layer 281 in contact with region 230n, the above-mentioned elements can be introduced into region 230n during the formation of the insulating layer 281 or by subsequent heat treatment. For example, it is preferable to use silicon nitride containing hydrogen for the insulating layer 281. Alternatively, an oxide containing a metal element from among the above-mentioned elements may be used.

[0293] [Modification 2] Figure 17A shows an example in which a conductive layer 205, which functions as a second gate electrode, is provided in the configuration shown in Figure 16A.

[0294] The conductive layer 205 is provided on the substrate 210, and the insulating layer 201 is provided so as to cover the conductive layer 205. The structure, materials, etc. of the conductive layer 205 and the insulating layer 201 can be found in the description above.

[0295] Figure 17B shows an example in which the insulating layer 250 is located only in the region overlapping with the conductive layer 260 and is not provided on the region 230n of the semiconductor layer 230.

[0296] [Modification 3] The following describes a transistor in which the conductive layer, which functions as a gate electrode, is located below the semiconductor layer.

[0297] Figure 18A shows a cross-sectional view of transistor 200b in the channel length direction. Transistor 200b has a semiconductor layer 230, an insulating layer 201, a conductive layer 205, a conductive layer 242a, and a conductive layer 242b. The conductive layer 205 functions as the gate electrode of transistor 200b. The insulating layer 201 functions as the gate insulating layer of transistor 200b.

[0298] The composition and materials of the substrate 210, conductive layer 205, insulating layer 201, and semiconductor layer 230 can be found in the information described above.

[0299] Each of the conductive layer 242a and conductive layer 242b has a region in contact with the upper surface of the semiconductor layer 230 and a region in contact with the side surface of the semiconductor layer 230. The insulating layer 280 is provided so as to cover the semiconductor layer 230, the conductive layer 242a, and the conductive layer 242b.

[0300] Figure 18B shows an example in which an insulating layer 284 is provided in the configuration shown in Figure 18A.

[0301] The insulating layer 284 is provided so as to cover the semiconductor layer 230 and has a first opening and a second opening that reach the semiconductor layer 230. Within the first opening, the conductive layer 242a is in contact with the semiconductor layer 230, and within the second opening, the conductive layer 242b is in contact with the semiconductor layer 230.

[0302] The insulating layer 284 functions as a channel protection film that protects the channel formation region when forming the conductive layers 242a and 242b. The insulating layer 284 is formed on the semiconductor layer 230, a first opening and a second opening are formed in the insulating layer 284, conductive films that will become the conductive layers 242a and 242b are deposited on the insulating layer 284, and the conductive layers 242a and 242b can be formed by processing the conductive films. Since the channel formation region is not exposed during the deposition and processing of the conductive films, damage to the channel formation region can be suppressed. Therefore, a transistor with good electrical characteristics can be made.

[0303] As the insulating layer 284, a material that can be used for the insulating layer 280 can be applied.

[0304] Figure 18C shows an example in the configuration shown in Figure 18A where the side surface of the semiconductor layer 230 is located inward from the side surface of the conductive layer 205. It also shows an example where the conductive layer 205 has a region that does not overlap with the semiconductor layer 230. This reduces the occupied area of ​​the transistor 200b.

[0305] Figure 19A shows an example in the configuration shown in Figure 18A where both the conductive layer 242a and the conductive layer 242b have a two-layer structure. Figure 19B shows an example in the configuration shown in Figure 19A where the side edge of the conductive layer 242a1 coincides with the side edge of the semiconductor layer 230, and the side edge of the conductive layer 242b1 coincides with the side edge of the semiconductor layer 230. By using the configuration shown in Figure 19A or Figure 19B, the contact resistance between the source electrode and the semiconductor layer, and the contact resistance between the drain electrode and the semiconductor layer can be reduced while maintaining conductivity as a wiring.

[0306] In the configuration shown in Figure 19A, the conductive layer 242a1 and the conductive layer 242b1 are in contact with a portion of the upper surface and a portion of the side surface of the semiconductor layer 230, respectively. This increases the contact area between the conductive layer 242a1 and the semiconductor layer 230, and the contact area between the conductive layer 242b1 and the semiconductor layer 230.

[0307] The composition and materials of conductive layers 242a1, 242a2, 242b1, and 242b2 can be found in the description above. For example, metal oxides such as ITO or ITSO can be used for conductive layers 242a1 and 242b1, and tungsten, copper, or nickel can be used for conductive layers 242a2 and 242b2.

[0308] In the configuration shown in Figures 19A and 19B, an insulating layer 281 is provided on the insulating layer 280. As the insulating layer 281, an insulator having barrier properties against hydrogen and oxygen, similar to that of the insulating layer 275, can be used. This suppresses the diffusion of impurities such as water and hydrogen from above the transistor 200b into the semiconductor layer 230.

[0309] In the configuration shown in Figures 19A and 19B, the conductive layers 242a1 and 242b1 are formed by creating conductive films that will become the conductive layers 242a1 and 242b1, and then removing a portion of the region of the conductive film that overlaps with the semiconductor layer 230 by etching. If the etching selectivity ratio of the conductive layer to the semiconductor layer 230 is small, when the conductive film is etched, a portion of the exposed region of the semiconductor layer 230 is etched, and grooves are formed in the semiconductor layer 230.

[0310] Figure 19C shows an example in which, in the configuration shown in Figure 19A, a conductive layer 260 that functions as a second gate electrode and an insulating layer 250 that functions as a second gate insulating layer are provided.

[0311] The insulating layer 250 is provided on the semiconductor layer 230, the conductive layer 242a, and the conductive layer 242b. The conductive layer 260 is provided on the insulating layer 250 such that it has a region overlapping with the semiconductor layer 230. The insulating layer 280 is provided so as to cover the conductive layer 260. The composition, materials, etc., of the conductive layer 260 and the insulating layer 250 can be found in the above description.

[0312] By using the conductive layer 260 as a second gate electrode, the on-current can be increased or the threshold voltage can be controlled. For example, by setting the conductive layer 205 and the conductive layer 260 to the same potential and driving them as a double-gate transistor, the on-current can be increased. Alternatively, by applying a different potential to the conductive layer 260 than to the conductive layer 205, the threshold voltage can be controlled. Therefore, by controlling the threshold voltage, it is easy to realize a normally-off transistor.

[0313] [Modification 4] Below, we will describe a vertical transistor in which the source electrode and drain electrode are located at different heights.

[0314] Figure 20A shows a schematic cross-sectional view of transistor 200c. Transistor 200c has a semiconductor layer 230, an insulating layer 250, a conductive layer 260, a conductive layer 245, and a conductive layer 246. Conductive layer 245 functions as either the source electrode or the drain electrode of transistor 200c, and conductive layer 246 functions as the other.

[0315] A conductive layer 245 is provided on an insulating layer 201, and an insulating layer 211 is provided covering the conductive layer 245. A conductive layer 246 is provided on the insulating layer 211. The conductive layer 246 and the insulating layer 211 are provided with openings that reach the conductive layer 245. The semiconductor layer 230 is provided in contact with the upper surface of the conductive layer 246, the side surface of the conductive layer 246 at the opening, the side surface of the insulating layer 211, and the upper surface of the conductive layer 245. The insulating layer 250 is provided covering the semiconductor layer 230 at the opening, and the conductive layer 260 is provided covering the insulating layer 250.

[0316] In transistor 200c, the source electrode and drain electrode are located at different heights, and current flows in the height direction through the semiconductor layer. That is, the channel length direction has a component in the height direction (vertical direction), so transistor 200c can be called a VFET (Vertical Field Effect Transistor), vertical transistor, vertical channel transistor, or vertical channel type transistor. In transistor 200c, two or more of the source electrode, semiconductor, and drain electrode can be stacked, so the occupied area can be significantly reduced compared to a so-called planar type transistor (which can also be called a lateral transistor or LFET (Lateral FET)) in which the semiconductor is arranged on a plane.

[0317] Furthermore, the channel length of transistor 200c can be precisely controlled by the thickness of the insulating layer 211, which functions as a spacer, thus significantly reducing the variation in channel length compared to planar transistors. Moreover, by thinning the insulating layer 211, transistors with extremely short channel lengths can be fabricated. For example, transistors with channel lengths of 2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less, and with channel lengths of 5 nm or more, 7 nm or more, or 10 nm or more can be fabricated. Therefore, transistors with extremely short channel lengths, which were not possible with mass-production exposure equipment, can be realized. Additionally, transistors with channel lengths of less than 10 nm can be realized without using the extremely expensive exposure equipment used in state-of-the-art LSI technology.

[0318] In transistor 200c, the shape of the opening provided in the insulating layer 211 can be of various shapes.

[0319] Figure 20B shows a perspective view with the insulating layer 211 and the semiconductor layer 230 extracted. Here, an example is shown in which a cylindrical opening 290o is provided in the insulating layer 211. In this case, the semiconductor layer 230 has a cylindrical portion along the side wall of the opening 290o and flat portions parallel to the substrate surface at the bottom and top. In the configuration shown in Figure 20B, the channel width of the transistor is approximately equal to the circumference of the cylindrical portion. Therefore, in the configuration shown in Figure 20B, it is easy to make the channel length small and the channel width large, and a transistor capable of carrying extremely large currents can be realized.

[0320] On the other hand, Figure 20C shows an example in which a slit-shaped opening 290s is provided in the insulating layer 211. As shown in Figure 20C, multiple semiconductor layers 230 can be arranged in the opening 290s, making it suitable for high-density arrangement of transistors. Although not shown here, a conductive layer 260 that functions as a gate electrode can be embedded in the opening 290s and used as wiring extending in the direction of extension of the opening 290s.

[0321] The substrate 210, insulating layer 211, and semiconductor layer 230 can be made using the substrate 10, insulating layer 20, and metal oxide layer 30 exemplified in Embodiment 1, respectively.

[0322] A seed layer 231 may be provided between the semiconductor layer 230 and the conductive layer 246. In Figure 20D, the seed layer 231 is provided so as to overlap with the conductive layer 246. By placing the seed layer 231 near the channel formation region, the crystallinity of the channel formation region can be improved, for example, by achieving single crystallization of the channel formation region. This can increase the field-effect mobility and on-current of the transistor.

[0323] The crystal growth in the semiconductor layer 230 when the metal oxide layer 30 exemplified in Embodiment 1 is applied to the semiconductor layer 230 will now be described. As shown in Figure 20E, even if the surface of the semiconductor layer 230 to be formed has a recess, the first to third growth described above will occur, improving the crystallinity of the metal oxide layer 30, for example, achieving single crystal formation of the metal oxide layer 30. In Figure 20E, the direction of the first growth is indicated by a solid arrow, the direction of the second growth is indicated by a dashed arrow, and the direction of the third growth is indicated by a dotted arrow. The seed layer 231 shown in Figure 20E corresponds to the seed layer 31 exemplified in Embodiment 1.

[0324] As mentioned above, when the upper surface of the seed layer 231 is a {111} plane, the third growth direction coincides with the <111> orientation of the seed layer 31. Also, within the cylindrical opening 290o, the third growth direction is parallel to the direction along the side surface of the opening 290o. The same applies within the slit-shaped opening 290s.

[0325] In addition, in the configuration shown in Figures 20A and 20B, a sidewall-shaped insulating layer can be provided between the side wall of the opening 290o and the semiconductor layer 230, and a conductive layer can be provided in contact with the side surface of the insulating layer that faces the semiconductor layer 230.

[0326] A transistor 200c having the above configuration is shown in Figure 21A. The transistor 200c shown in Figure 21A differs from the transistor shown in Figure 20A mainly in that it has an insulating layer 203 and a conductive layer 205. The insulating layer 203 is the sidewall-shaped insulating layer described above, and the conductive layer 205 is the conductive layer described above.

[0327] A conductive layer 205 is provided on an insulating layer 211, and an insulating layer 212 is provided so as to cover the conductive layer 205. A conductive layer 246 is provided on the insulating layer 212. The conductive layer 246, insulating layer 212, conductive layer 205, and insulating layer 211 are provided with openings that reach the conductive layer 245. The insulating layer 203 is provided in contact with the side surface of the conductive layer 246, the side surface of the insulating layer 212, the side surface of the conductive layer 205, the side surface of the insulating layer 211, and a part of the upper surface of the conductive layer 245 at the opening. The semiconductor layer 230 is provided covering the insulating layer 203 at the opening. It is also in contact with the upper surface of the conductive layer 246 and the other upper surface of the conductive layer 245 at the opening. The insulating layer 250 is provided covering the semiconductor layer 230 at the opening, and the conductive layer 260 is provided covering the insulating layer 250.

[0328] In the transistor 200c shown in Figure 21A, the conductive layer 260 functions as a first gate electrode, the insulating layer 250 functions as a first gate insulating layer, the conductive layer 205 functions as a second gate electrode, and the insulating layer 203 functions as a second gate insulating layer.

[0329] The semiconductor layer 230 has a region that overlaps with the conductive layer 205 via the insulating layer 203 and with the conductive layer 260 via the insulating layer 250. At least a portion of this region functions as a channel formation region for the transistor 200c.

[0330] The threshold voltage of transistor 200c can be controlled by applying different potentials to the conductive layer 260 and the conductive layer 205. Therefore, it is easy to realize a normally-off transistor by controlling the threshold voltage.

[0331] In transistor 200c, either the conductive layer 260 or the conductive layer 205 may be used as the gate electrode, and either as the back gate electrode. In particular, transistor 200c may have a structure in which the conductive layer 260 is used as the gate electrode and the conductive layer 205 is used as the back gate electrode. By using the conductive layer 260, which has a larger region facing the semiconductor layer 230 than the conductive layer 205, as the gate electrode, the gate electric field is applied to the semiconductor layer 230 more efficiently, which may improve the electrical characteristics of the transistor.

[0332] It is also possible to apply the same potential to conductive layer 260 and conductive layer 205. This makes it possible to increase the on-current, reduce initial characteristic variations, suppress deterioration of electrical characteristics in negative GBT (Gate Bias-Temperature) stress tests, and suppress DIBL (Drain-Induced Barrier Lowering).

[0333] The conductive layer 205 can use a conductive material applicable to the conductive layer 260. The insulating layer 203 can use an insulating material applicable to the insulating layer 250. The insulating layer 212 can use an insulating material applicable to the insulating layer 211.

[0334] In addition, a seed layer 231 may be provided between the semiconductor layer 230 and the conductive layer 246, similar to the configuration shown in Figure 20D. Figure 21B shows an example of a configuration in which a seed layer 231 is provided between the semiconductor layer 230 and the conductive layer 246 in the configuration shown in Figure 21A.

[0335] In addition, the configuration shown in Figure 21A can also be configured without the conductive layer 260. The transistor 200c shown in Figure 21C differs mainly from the transistor shown in Figure 21A in that it does not have the conductive layer 260. In the transistor 200c shown in Figure 21C, the conductive layer 205 functions as the gate electrode, and the insulating layer 203 functions as the gate insulating layer. Since the conductive layer 260 is not provided at the opening, the width of the opening can be reduced without changing the film thickness of the semiconductor layer 230 and the insulating layer 250, thereby enabling miniaturization or high integration of the transistor. Alternatively, the film thickness of the insulating layer 250 can be increased to enhance the function of the insulating layer 250, enabling the realization of a transistor with high field-effect mobility and high reliability. Alternatively, the film thickness of the semiconductor layer 230 can be increased to realize a transistor with a large on-current and high field-effect mobility.

[0336] In addition, a seed layer 231 may be provided between the semiconductor layer 230 and the conductive layer 246, similar to the configuration shown in Figure 20D. Figure 21D shows an example of a configuration in which a seed layer 231 is provided between the semiconductor layer 230 and the conductive layer 246 in the configuration shown in Figure 21C.

[0337] Furthermore, a configuration in which only the insulating layer 203 and the semiconductor layer 230 are provided in the opening, that is, a configuration in which the semiconductor layer 230 fills the opening. A transistor 200c having this configuration is shown in Figure 21E. By adopting the configuration shown in Figure 21E, it is not necessary to provide at least the conductive layer 260 in the opening, and the width of the opening can be reduced. Therefore, miniaturization or high integration of the transistor can be achieved.

[0338] Furthermore, in the configuration shown in Figure 21E, the conductive layer 246 may be provided between the semiconductor layer 230 and the insulating layer 250. A transistor 200c having this configuration is shown in Figure 21F. By adopting the configuration shown in Figure 21F, it is not necessary to form an opening in the conductive layer 246. Therefore, the processing of the opening becomes easier, and the productivity of semiconductor devices can be increased.

[0339] Furthermore, in the configuration shown in Figure 21F, the semiconductor layer 230 may not be located on the insulating layer 212, that is, the semiconductor layer 230 may be located only in the opening. For example, after forming the semiconductor layer 230, the semiconductor layer 230 can be embedded in the opening by performing CMP processing until the upper surface of the insulating layer 212 is exposed. This suppresses the step breaks in the conductive layer 246 formed on the insulating layer 212 and the semiconductor layer 230.

[0340] [Modification 5] Below, we will describe an example of a transistor in which the gate electrode surrounds the semiconductor layer.

[0341] Figure 22A shows a schematic cross-sectional view of a semiconductor device having a transistor 200d. In Figure 22A, the area to the left of the dashed line corresponds to the cross-section in the channel length direction, and the area to the right corresponds to the cross-section in the channel width direction. The transistor 200d shown in Figure 22A can also be called a transistor having a GAA (Gate All Around) structure, as the gate electrode is provided so as to surround the semiconductor layer.

[0342] The transistor 200d has multiple semiconductor layers arranged to overlap each other. Here, an example is shown in which the transistor 200d has semiconductor layer 230a, semiconductor layer 230b, and semiconductor layer 230c from the bottom. The transistor 200d also has conductive layer 242a, conductive layer 242b, conductive layer 260, and insulating layer 250. An insulating layer 201 is provided between the substrate 210 and the transistor 200d, an insulating layer 286 is provided so as to surround the transistor 200d, and an insulating layer 288 is provided so as to cover the transistor 200d.

[0343] The conductive layer 260, which functions as the gate electrode, has portions located below semiconductor layer 230a, between semiconductor layer 230a and semiconductor layer 230b, between semiconductor layer 230b and semiconductor layer 230c, and above semiconductor layer 230c. The insulating layer 250, which functions as the gate insulating layer, has portions located between the conductive layer 260 and each semiconductor layer. By arranging the gate electrode to surround the semiconductor layers in this way, the gate electric field is applied to surround the semiconductor layers, thereby improving the controllability of the on / off state of the transistor 200d. Specifically, this has the effect of increasing the source-drain current (on current) in the on state and reducing the leakage current (off current) in the off state.

[0344] It is preferable that the semiconductor layers 230a, 230b, and 230c have crystal grains epitaxially grown from a seed layer. In this case, the semiconductor layers 230a to 230c each have a first to third crystal grain. When indium oxide is used as the semiconductor layers 230a to 230c, the first to third crystal grains have a cubic crystal structure. Furthermore, since the first to third crystal grains are formed using the seed layer as a seed or nucleus, at least one crystal orientation of the first to third crystal grains is aligned with each other. For example, the

[111] orientation of the first crystal grain, the

[111] orientation of the second crystal grain, and the

[111] orientation of the third crystal grain are aligned with each other.

[0345] Crystal orientation can be evaluated by the diffraction pattern (also called the nano-beam electron diffraction pattern) observed by nano-beam electron diffraction (NBED). Alternatively, it can be evaluated by the pattern (also called the FFT pattern) obtained by performing a Fast Fourier Transform (FFT) on the TEM image. The FFT pattern reflects reciprocal lattice space information similar to that of the diffraction pattern described above.

[0346] For example, if the difference in angle between the FFT patterns of the first to third crystal grains is -5 degrees or more and 5 degrees or less, preferably -3 degrees or more and 3 degrees or less, and more preferably -2 degrees or more and 2 degrees or less, then the first to third crystal grains can be said to have at least one crystal orientation aligned with each other. For example, the angle of the FFT pattern in the

[111] orientation refers to the acute angle formed between the approximate straight line between one or both of the spots originating from the (222) plane or the spots originating from the (-2-2-2) plane and the central spot, and the reference line (for example, a straight line extending in the vertical direction).

[0347] In the channel length direction, conductive layer 242a and conductive layer 242b are provided so as to sandwich conductive layer 260. Conductive layer 242a and conductive layer 242b are in contact with each semiconductor layer.

[0348] Furthermore, an insulating layer 287, which functions as a spacer, is provided between the conductive layer 242a or conductive layer 242b and the insulating layer 250. The insulating layer 287 reduces the parasitic capacitance between the conductive layer 242a or conductive layer 242b and the conductive layer 260. Note that the insulating layer 287 may be omitted if it is not needed.

[0349] The insulating layer 286 and the insulating layer 288 function as interlayer insulating layers. Furthermore, it is preferable to use an insulating film that functions as a protective insulating layer for the insulating layer 288.

[0350] Here, an example with three semiconductor layers stacked is shown, but the number of semiconductor layers in transistor 200d is not limited to this; it can be one, two, or four or more layers. Fewer semiconductor layers shorten the manufacturing process, improving yield and reducing manufacturing costs. Furthermore, a larger number of semiconductor layers allows for increased on-current.

[0351] Figure 22B shows an example of stacking two transistors having GAA structures. In Figure 22B, transistor 200s is located below transistor 200d.

[0352] The transistor 200s is provided on a substrate 150 and has a plurality of semiconductor layers (semiconductor layer 130a, semiconductor layer 130b, semiconductor layer 130c), a conductive layer 131a, a conductive layer 131b, a conductive layer 260s, and an insulating layer 250s. The conductive layer 131a functions as one of the source electrode and the drain electrode, and the conductive layer 131b functions as the other. The conductive layer 260s functions as the gate electrode, and the insulating layer 250s functions as the gate insulating layer.

[0353] Transistor 200s is preferably a p-channel transistor. A CMOS (Complementary Metal Oxide Semiconductor) circuit can be constructed using transistor 200s, which is a p-channel transistor, and transistor 200d, which is an n-channel transistor. Furthermore, a CFET (Complementary Field Effect Transistor) can be constructed by stacking transistors 200s and 200d in this manner.

[0354] Typically, silicon can be used as the semiconductor layer 130a, semiconductor layer 130b, and semiconductor layer 130c. It is preferable that the semiconductor layers 130a, semiconductor layer 130b, and semiconductor layer 130c have a single-crystal structure epitaxially grown from the substrate 150. For example, the semiconductor layers 130a, semiconductor layer 130b, and semiconductor layer 130c can be formed by alternately forming single-crystal silicon-germanium films and silicon films on a substrate 150 having single-crystal silicon, and then selectively removing the silicon-germanium films.

[0355] The insulating layer 151 is embedded in the substrate 150 and functions as an element isolation layer. In addition, an insulating layer 286s is provided surrounding the transistor 200s and functions as an interlayer insulating layer.

[0356] An insulating layer 289 is provided between the conductive layer 242a and the conductive layer 131a, and between the conductive layer 242b and the conductive layer 131b, to insulate the two conductive layers.

[0357] The conductive layer 260s is provided so as to surround the channel formation regions of semiconductor layers 130a, 130b, and 130c via the insulating layer 250s. Furthermore, a conductive layer 260 is provided in contact with the conductive layer 260s, functioning as the gate electrode of transistor 200d. This configuration allows for the creation of separate gate electrode and gate insulating layers for transistors 200d and 200s. For example, conductive materials exhibiting different work functions can be applied to the conductive layer 260s and conductive layer 260. Additionally, the insulating layer 250s and insulating layer 250 can differ not only in material but also in thickness.

[0358] This configuration makes it possible to stack transistors 200d and 200s, which have high on-current and low off-current, thereby realizing a semiconductor device with high integration density, high-speed operation, and low power consumption.

[0359] Figure 23 shows an example of two transistors having a GAA structure arranged side by side. Figure 23 is a schematic perspective view of a semiconductor device. In Figure 23, transistors 200d and 200s are arranged side by side. In Figure 23, the insulating layers 286 and 288 are shown only by their outlines with solid lines. Also, in Figure 23, conductive layers 131a, 131b, 242a, 242b, and insulating layer 287 are not explicitly shown for the sake of explanation, but their configurations can be seen in Figures 22A and 22B.

[0360] Semiconductor layers 130a, 130b, and 130c are stacked, and in regions that do not overlap with these, semiconductor layers 230a, 230b, and 230c are stacked. The conductive layer 260s is provided so as to surround the channel formation regions of semiconductor layers 130a, 130b, and 130c via an insulating layer 250s. In addition, a conductive layer 260 that functions as the gate electrode of transistor 200d is provided in contact with the conductive layer 260s. With this configuration, the gate electrodes of transistor 200s and transistor 200d can be created separately. Furthermore, since the gate wiring can be shared between the two transistors, higher integration is possible compared to a configuration in which the gate wiring is provided separately.

[0361] The configuration shown in Figure 23 occupies a larger area compared to the configuration shown in Figure 22B, but it offers greater flexibility in the arrangement of the n-channel transistor 200d and the p-channel transistor 200s. Therefore, it is preferable because it can realize various circuit configurations in addition to CMOS circuits, making it highly versatile and easy to replace with conventional LSIs.

[0362] Furthermore, the semiconductor layers 130a to 130c are made of cuprous oxide (Cu ２ O), copper aluminate (CuAlO) ２ ), copper gallium oxide (CuGaO ２ It is also possible to use metal oxides such as stannous oxide (SnO) and tellurium oxide. Furthermore, it is also possible to use a mixture of tellurium oxide and tellurium as semiconductor layers 130a to 130c.

[0363] By using a p-type semiconductor metal oxide for semiconductor layers 130a to 130c and an n-type semiconductor metal oxide for semiconductor layers 230a to 230c, it becomes possible to manufacture semiconductor devices at relatively low process temperatures. Furthermore, since all semiconductor layers are composed of metal oxides, it is possible to use the same material for at least one of the source electrode, drain electrode, gate insulating layer, and gate electrode in transistors 200s and 200d. By using the same material, the equipment used for formation can be common, thereby reducing the manufacturing cost of semiconductor devices.

[0364] Furthermore, the semiconductor layers 130a to 130c are WS ２ , WSe ２ MoS ２ MoSe ２ It is also possible to use transition metal dichalcogenides such as those mentioned above.

[0365] When using a metal oxide or a transition metal dichalcogenide as the semiconductor layer 130a to 130c, it is also possible to use a substrate other than a single-crystal silicon substrate (such as an insulating substrate or conductive substrate as described in Embodiment 1) as the substrate 150. Furthermore, it is also possible to provide an insulating layer between the substrate 150 and the semiconductor layer, and to omit the element isolation layer.

[0366] The above is an explanation of the variations.

[0367] This embodiment can be implemented in appropriate combination with other embodiments or examples described herein, at least in part.

[0368] (Embodiment 4) This embodiment describes an indium oxide film that can be used in the semiconductor layer of a transistor in a semiconductor device according to one aspect of the present invention.

[0369] In this specification, indium oxide having at least a crystalline portion or crystalline region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystal IO or crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0370] Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0371] The carrier concentration dependence of the hole (Hall) mobility of indium oxide, silicon, and IGZO is described. Figure 24A shows silicon (Si) and indium oxide (InO Ｘ Figure 24B is a schematic diagram of the carrier concentration dependence of hole mobility with respect to IGZO.

[0372] First, as indicated by the arrows in Figure 24B, IGZO tends to exhibit higher hole mobility as the carrier concentration increases. On the other hand, as indicated by the arrows in Figure 24A, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases (see Non-Patent Literature 2). This trend is similar to that of silicon, where the lower the concentration of dopants (impurities) in the material, the less impurity scattering occurs and the higher the hole mobility. In other words, the higher the purity and intrinsic nature of indium oxide, the higher its hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to silicon. Note that the properties of indium oxide shown in Figure 24A are assumed to be those of a single crystal. Therefore, when indium oxide is not a single crystal (for example, polycrystalline), the properties may differ from those shown in Figure 24A.

[0373] In Figure 24A, the low carrier concentration range R1 exhibits extremely high hole mobility, making it a suitable carrier concentration range for, for example, the channel formation region of a transistor. For example, in the case of indium oxide, the range R1 has a carrier concentration of 1 × 10⁻⁶. １５ cm −３ This range includes, for example, 1 × 10１４ cm −３ Above, 1 × 10 １８ cm −３ The following range. By sufficiently reducing the carrier concentration, it can be expected that the value of the hole mobility can be increased to about 270 cm ２ / (V·s).

[0374] Incidentally, in indium oxide, the region where the carrier concentration is in the range R1 can contain an element that lowers the carrier concentration. Examples of the element that lowers the carrier concentration include magnesium, calcium, zinc, cadmium, copper, etc. By substituting these elements for indium, the carrier concentration can be lowered. Also, examples of the element that lowers the carrier concentration include nitrogen, phosphorus, arsenic, antimony, etc. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0375] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and it can be said that it is a suitable carrier concentration range for, for example, the source region and drain region of a transistor, or a resistor, or a transparent conductive film. The range R2 is a range including a carrier concentration value of 1 × 10 ２０ cm −３ and, for example, 1 × 10 １９ cm −３ or more and 1 × 10 ２２ cm −３ or less. By sufficiently increasing the carrier concentration, it can be expected that the resistivity can be reduced to 1 × 10 −４ Ω·cm or less.

[0376] In the case of indium oxide, the region where the carrier concentration is in the range R2 may contain elements that increase the carrier concentration. For example, it is preferable to include elements common to the source and drain electrodes of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use elements whose oxides are conductive or semiconducting. As for the supply method of elements that increase the carrier concentration, a method of forming a film containing the element and diffusing it, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. In this specification, unless otherwise specified, the presence or absence of mass separation is not limited. For example, in this specification, a method of supplying ions by mass separation is called ion implantation, and a method of supplying ions without mass separation is called ion doping.

[0377] In this way, indium oxide uses regions with low carrier concentrations for the transistor's channel formation region and regions with high carrier concentrations for the transistor's source and drain regions. In other words, indium oxide can be said to be an oxide in which valence electron control is possible. In IGZO, however, strain can form in the source and drain regions due to stress on the electrodes in contact with the IGZO, and n-type regions may be formed. On the other hand, unlike IGZO, indium oxide allows for valence electron control, so it does not require the formation of strain in the film as in IGZO. Less strain in the film is expected to improve reliability. For example, by creating regions with carrier concentrations in the range R1 and range R2 shown in Figure 24A within the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Valence electron control in silicon transistors is generally known. On the other hand, valence electron control in indium oxide transistors is a novel technological concept that would not normally be conceived.

[0378] By applying the above technical concept, the indium oxide transistor described herein has two or more, preferably three or more, more preferably four or more, and most preferably five of the following features (1) to (5): (1) High on-current (in other words, high mobility). (2) Low off-current. (3) Normally off is possible. (4) High reliability. (5) High cutoff frequency (fT). For example, the indium oxide transistor described herein has high mobility, low off-current, and is normally off. This transistor is different from a transistor that is high mobility and normally on.

[0379] In addition, the i-type nature of a semiconductor means that the Fermi level (Ef) and the intrinsic Fermi level (Ei) are the same (Ef = Ei). As shown in Figure 24B, in IGZO, the lower the carrier concentration, the lower the hole mobility. Therefore, when Ef = Ei is reached, there are no carriers left (in other words, the material has properties similar to an insulator), and it may cease to function as a transistor. On the other hand, in indium oxide, as shown in Figure 24A, the lower the carrier concentration, the higher the hole mobility, and when Ef = Ei is reached, the hole mobility is maximized. That is, transistors containing indium oxide can achieve high field-effect mobility by setting Ef = Ei. Furthermore, because transistors containing indium oxide have a low carrier concentration, they tend to be normally off. Therefore, transistors containing indium oxide can be normally off and achieve high field-effect mobility.

[0380] Note that "normally-off" refers to a state where no current flows through the transistor when no potential is applied to the gate or when the gate-source voltage is 0 V. Also, normally-off can be evaluated by the threshold voltage (Vth) or the shift value (Vsh) of the transistor. Unless otherwise specified, Vth shall be calculated by the constant current method. More specifically, Vth is the gate voltage (Vg) when the value of drain current (Id) × channel length (L) ÷ channel width (W) in the Id-Vg characteristics of the transistor becomes 1 nA (1 × 10 −９ A). Also, Vsh is the gate voltage (Vg) at the intersection of the tangent line with the maximum slope when the drain current (Id) in the Id-Vg characteristics of the transistor is expressed in logarithmic notation and the line of Id = 1 pA (1 × 10 −１２ A), or the Vg at the intersection of the extrapolated line from between two points where the slope is maximum when Id in the Id-Vg characteristics of the transistor is expressed in logarithmic notation and the line of Id = 1 pA. For example, if one or both of Vth and Vsh are zero or positive values, it can be regarded as a normally-off transistor.

[0381] Also, in a transistor having indium oxide, in order to make the semiconductor i-type, that is, to achieve Ef = Ei, the film structure in contact with the indium oxide film is important. For example, in a transistor having indium oxide, a film structure in which a silicon oxide film, a hafnium oxide film, and a silicon nitride film in contact with the indium oxide film are laminated can be cited. By adopting such a film structure, Ef = Ei can be achieved, and a highly reliable semiconductor device can be obtained.

[0382] In the above film structure, instead of the silicon oxide film, an oxygen-containing film such as a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, or a gallium oxide film can also be used. Also, in the above film structure, instead of the silicon nitride film, a silicon nitride oxide film, a silicon oxynitride film, etc. can also be used. Further, the hafnium oxide film located closer to the indium oxide film side than the silicon nitride film functions as a hydrogen gettering site.

[0383] Furthermore, the above film configuration can also be viewed as a layered structure consisting of a film that can supply oxygen to the indium oxide film (e.g., a silicon oxide film), a film that can getter hydrogen (e.g., a hafnium oxide film), and a film that suppresses the intrusion of oxygen and hydrogen (e.g., a silicon nitride film). With this configuration, oxygen deficiencies in the indium oxide film are compensated for by oxygen in the silicon oxide film. Also, hydrogen in the indium oxide film is captured by the hafnium oxide film through heat treatment or other means. In addition, the silicon nitride film provides a film configuration that minimizes the intrusion of oxygen and hydrogen from the outside. In other words, by using the above film configuration, the indium oxide film can be made closer to type i. Therefore, transistors having the above-described indium oxide film have high field-effect mobility and high reliability.

[0384] Next, we will describe indium oxide films applied to transistors. Indium oxide films are preferably crystalline (i.e., they have crystal grains). Examples of films with crystal grains include single-crystal films, polycrystalline films, or amorphous films containing crystal grains (also called microcrystalline films). In particular, polycrystalline films are preferred for indium oxide films, and single-crystal films are more preferred. Single-crystal films do not have crystal grain boundaries. Impurities that inhibit carrier flow (typically insulating impurities, insulating oxides, etc.) tend to segregate at crystal grain boundaries. By using single-crystal films, carrier scattering at crystal grain boundaries can be suppressed, enabling the realization of transistors exhibiting high field-effect mobility. Furthermore, it has the excellent effect of suppressing variations in transistor characteristics caused by these crystal grain boundaries.

[0385] In addition, compared with microcrystalline films or amorphous films, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility. When using a polycrystalline film, it is preferable to use a film with as large crystal grain sizes as possible and few grain boundaries. In a transistor to which a polycrystalline film of indium oxide is applied, when no grain boundaries are present in the channel formation region or no grain boundaries are observed, since the channel formation region is located within the single crystal region contained in the polycrystalline film, it can be regarded as a transistor to which single crystal indium oxide is applied.

[0386] The crystallinity of indium oxide can be analyzed, for example, by X-ray diffraction (XRD: X-Ray Diffraction), transmission electron microscopy (TEM: Transmission Electron Microscope), or electron diffraction (ED: Electron Diffraction). Alternatively, analysis may be performed by combining a plurality of these.

[0387] In this specification and the like, a semiconductor layer in which no grain boundaries are observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the directions of crystal axes are the same in at least two regions within the channel formation region can be referred to as a single crystal film. Also, in the channel formation region, a semiconductor layer in which, within one crystal grain, with a certain crystal axis or a certain crystal orientation as the axis of rotation, the directions of other crystal axes continuously change can be referred to as a single crystal film.

[0388] The channel formation region refers to a region in the semiconductor layer that overlaps (or faces) the gate electrode through the gate insulating layer and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, crystal grains, grain boundaries, crystal axes, crystal orientations, etc. in the channel formation region can be confirmed by cross-sectional observation including the semiconductor layer, the source electrode, and the drain electrode.

[0389] The indium oxide film in the channel-forming region is preferable to have a low impurity concentration. Impurities in the indium oxide film in the channel-forming region can act as a scattering source for carriers, and thus can cause a decrease in field-effect mobility. Furthermore, these impurities can also inhibit crystal growth in the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The concentration of these impurities in the indium oxide film is preferably 0.1% or less, and more preferably 0.01% (100 ppm) or less. Note that elements such as carbon and hydrogen may be present in the deposition gas or precursor during film formation, and may remain in the indium oxide film in higher concentrations than the impurities mentioned above.

[0390] Furthermore, the indium oxide film in the channel-forming region may contain elements that can become trivalent cations like indium, as long as their crystals maintain a cubic (bixbite) crystal structure. Examples include group 13 elements of the periodic table such as gallium and aluminum, and group 3 elements of the periodic table. Since these elements mainly exist as trivalent cations in the oxide, the carrier concentration of indium oxide can be kept low.

[0391] Furthermore, the indium oxide film described herein has a high film density. The theoretical value of the film density of the indium oxide film is 7.18 g / cm³. ３ In this specification, the range of film density for indium oxide films is 6.70 g / cm³. ３ 7.18g / cm or more ３ The following, preferably 6.90 g / cm³ ３ 7.18g / cm or more ３ The following, and more preferably 7.00 g / cm³ ３ 7.18g / cm or more ３ The following applies:

[0392] Furthermore, film density can be evaluated using methods such as Rutherford backscattering (RBS) or X-ray reflectivity (XRR). Differences in film density can sometimes be evaluated using transmission electron microscopy (TEM) images of the cross-section. In TEM observation, a high film density results in a darker (more intense) transmission electron (TE) image, while a low film density results in a fainter (brighter) transmission electron (TE) image.

[0393] By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be increased to 50 cm². ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ It can be set to (V・s) or more.

[0394] One of the characteristics of indium oxide films is that they have higher oxygen permeability (diffusivity) compared to IGZO films. As shown in Figure 24C, indium oxide films (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and oxygen molecules (O) ２ It is released as water molecules (H) by reacting with hydrogen contained in the membrane. ２ It may also be released as O. Furthermore, oxygen deficiencies (V) can form in the membrane. Ｏ If oxygen atoms are present, diffusing oxygen atoms will fill the oxygen deficiency. Indium oxide films allow oxygen to diffuse easily, so they can be said to fill oxygen deficiencies more easily than IGZO films.

[0395] Thus, because indium oxide films are more likely to reduce oxygen vacancies in the film compared to IGZO films, applying such indium oxide films to transistors makes it possible to realize transistors with extremely high reliability.

[0396] Furthermore, as shown in Figure 24C, the indium oxide film diffuses hydrogen. Hydrogen diffusing into the indium oxide film from the outside permeates the film and forms hydrogen molecules (H ２It is released as ) or by reacting with oxygen contained in the film, and released as water molecules. The above-mentioned oxygen and hydrogen diffuse through the indium oxide film by heat treatment. The temperature of the heat treatment is 200°C to 700°C, preferably 350°C to 650°C, and more preferably 400°C to 500°C.

[0397] Transistors using indium oxide films are storage-type transistors that use electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, in a transistor, the on-current or field-effect mobility of the transistor can be increased.

[0398] Table 1 shows single crystal indium oxide (here, In ２ O ３ The effective masses of indium oxide and single-crystal silicon (Si) are shown below. As shown in Table 1, indium oxide is characterized by a small effective electron mass and a large effective hole mass. Furthermore, the effective electron mass of indium oxide is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in transistors, transistors with high field-effect mobility and high frequency characteristics (also called f-characteristics) can be realized. In addition, because the effective hole mass is large, transistors with extremely low off-currents can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width is 1 fA (1 × 10⁻¹⁶) in an environment of 125°C. −１５ A) Less than or equal to, or 1aA (1 × 10 −１８ A) Less than or equal to 1aA (1 × 10) in a room temperature (25°C) environment. −１８ A) Less than or equal to, or 1zA (1 × 10⁻¹⁰ −２１ A) The following is possible. Also, as shown in Table 1, indium oxide has a smaller effective electron mass and a larger effective hole mass than silicon, so it may be possible to realize a transistor with higher field-effect mobility and lower off-current than a Si transistor.

[0399]

[0400] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. It is preferable to use a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with the indium oxide for the seed layer. This improves the crystallinity of the indium oxide film. A substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0401] One method for evaluating the degree of lattice mismatch is to use the following lattice mismatch value. The lattice mismatch Δa [%] of the crystals in the formed film (in this case, the indium oxide film) relative to the crystals in the seed layer is given by Δa = ((L １ -L ２ ) / L ２ It is calculated as ) × 100. Here L １ L is the length of the unit cell vector of the crystals in the formed film, or the lattice constant. ２ This is the length of the unit cell vector of the crystal in the seed layer, or the lattice constant.

[0402] The lattice mismatch Δa between the seed layer and the indium oxide film is preferably small in absolute value, and most preferably zero. For example, Δa can be -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less.

[0403] Here, the indium oxide crystal has a cubic structure (bixbite type). For example, yttria-stabilized zirconia (YSZ) crystals can have a cubic structure (fluorite type). The lattice mismatch of the indium oxide crystal with respect to the cubic YSZ crystal is in the range of -2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on a YSZ substrate.

[0404] Furthermore, the crystal structure of the seed layer and the crystal structure of the indium oxide film do not necessarily have to be the same in terms of crystal system or crystal orientation. For example, a film with a hexagonal or trigonal crystal structure can be used beneath an indium oxide film with a cubic crystal structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to crystal orientation necessary for epitaxial growth can be met. Examples of hexagonal or trigonal crystals include wurtzite-type structures and YbFe. ２ O ４ Type structure, Yb ２ Fe ３ O ７ These include type structures and their modified type structures. YbFe ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal with a crystalline structure is IGZO. Indium oxide single crystal films can be formed not only on YSZ substrates but also on insulating films. On the other hand, it is difficult to form silicon single crystal films on insulating films. Silicon crystals have a diamond structure. Thus, in terms of single crystals, indium oxide and silicon have similar properties. However, when comparing indium oxide and silicon from the perspective of whether single crystals can be formed on insulating films, they have different properties.

[0405] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0406] (Embodiment 5) In this embodiment, a memory device according to one aspect of the present invention will be described with reference to Figures 25 to 28. In this embodiment, an example of the configuration of a memory device in which a layer having memory cells is stacked on a layer on which a drive circuit including a sense amplifier is provided will be described.

[0407] The transistors in the memory cells exemplified below can be the same type of transistor (referred to as an OS transistor) exemplified in Embodiment 3, in which a channel is formed in a single-crystal oxide semiconductor.

[0408] <Example of Storage Device Configuration> Figure 25 shows a block diagram illustrating an example of the configuration of a storage device 480 according to one aspect of the present invention. The storage device 480 shown in Figure 25 has a layer 420 and a stacked layer 470.

[0409] Layer 420 is a layer having Si transistors. In layer 470, element layers 430[1] to 430[m] (where m is an integer of 2 or more) are stacked. Element layers 430[1] to 430[m] are layers having OS transistors. Layer 470, in which layers having OS transistors are stacked, can be stacked on top of layer 420.

[0410] The elements in the element layers 430[1] to 430[m], such as OS transistors and capacitive elements, constitute memory cells. Figure 25 shows an example in which the element layers 430[1] to 430[m] have a plurality of memory cells 432 arranged in a matrix of m rows and n columns (where n is an integer of 2 or more).

[0411] In Figure 25, the memory cell 432 in the first row and first column is shown as memory cell 432[1,1], and the memory cell 432 in the mth row and nth column is shown as memory cell 432[m,n]. In this embodiment, an arbitrary row may be referred to as row i, and an arbitrary column may be referred to as column j. Therefore, i is an integer between 1 and m, and j is an integer between 1 and n. In this embodiment, the memory cell 432 in the ith row and jth column is shown as memory cell 432[i,j]. In this embodiment, when "i + α" (where α is a positive or negative integer) is used, "i + α" is not less than 1 and not greater than m. Similarly, when "j + α" is used, "j + α" is not less than 1 and not greater than n.

[0412] Figure 25 also illustrates, as an example, m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction. In this embodiment, the first wiring WL (first row) is denoted as wiring WL[1], and the mth wiring WL (mth row) is denoted as wiring WL[m]. Similarly, the first wiring PL (first row) is denoted as wiring PL[1], and the mth wiring PL (mth row) is denoted as wiring PL[m]. Similarly, the first wiring BL (first column) is denoted as wiring BL[1], and the nth wiring BL (nth column) is denoted as wiring BL[n]. Note that the number of layers of element layers 430[1] to 430[m] and the number of wirings WL (and wirings PL) do not have to be the same.

[0413] Multiple memory cells 432 located in row i are electrically connected to the wiring WL (wiring WL[i]) and wiring PL (wiring PL[i]) in row i. Multiple memory cells 432 located in column j are electrically connected to the wiring BL (wiring BL[j]) in column j.

[0414] Wiring BL functions as a bit line for writing and reading data. Wiring WL functions as a word line for controlling the on or off state (conductive or non-conductive) of the access transistor, which functions as a switch. Wiring PL functions as a constant potential line connected to the capacitor. A separate wire can be provided to transmit the back gate potential.

[0415] The memory cells 432 respectively included in the element layers 430[1] to 430[m] are connected to the sense amplifier 446 via the wiring BL. The wiring BL can be arranged in the parallel direction and the perpendicular direction on the substrate surface where the layer 420 is provided. By forming the wiring BL extending from the memory cells 432 included in the element layers 430[1] to 430[m] with not only the wiring arranged in the horizontal direction on the substrate surface but also the wiring arranged in the vertical direction, the length of the wiring between the element layer 430 and the sense amplifier 446 can be shortened. Since the signal propagation distance between the memory cell and the sense amplifier can be shortened and the resistance and parasitic capacitance of the bit line are significantly reduced, reduction of power consumption and signal delay can be achieved. Therefore, reduction of power consumption and signal delay of the storage device 480 can be realized. Also, even if the capacitance of the capacitor included in the memory cell 432 is made small, it can be operated. Therefore, miniaturization of the storage device 480 can be realized.

[0416] The layer 420 includes a PSW 471 (power switch), a PSW 472, and a peripheral circuit 422. The peripheral circuit 422 includes a drive circuit 440, a control circuit 473, and a voltage generation circuit 474. Each circuit included in the layer 420 is a circuit having Si transistors.

[0417] In the storage device 480, each circuit, each signal, and each voltage can be appropriately selected and discarded as necessary. Alternatively, other circuits or other signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0418] Also, the signals BW, CE, and GW are control signals. The signal CE is a chip enable signal, the signal GW is a global write enable signal, and the signal BW is a byte write enable signal. The signal ADDR is an address signal. The signal WDA is a write data signal, and the signal RDA is a read data signal. The signals PON1, PON2 are power gating control signals. Note that the signals PON1, PON2 may be generated by the control circuit 473.

[0419] The control circuit 473 is a logic circuit that has the function of controlling the overall operation of the storage device 480. For example, the control circuit performs logical operations on signals CE, GW, and BW to determine the operating mode of the storage device 480 (e.g., write operation, read operation). Alternatively, the control circuit 473 generates a control signal for the drive circuit 440 so that this operating mode is executed.

[0420] The voltage generation circuit 474 has the function of generating a negative voltage. The signal WAKE has the function of controlling the input of the signal CLK to the voltage generation circuit 474. For example, when a high-level signal is applied to the signal WAKE, the signal CLK is input to the voltage generation circuit 474, and the voltage generation circuit 474 generates a negative voltage.

[0421] The drive circuit 440 is a circuit for writing and reading data to and from the memory cell 432. The drive circuit 440 includes a row decoder 442, a column decoder 444, a row driver 443, a column driver 445, an input circuit 447, an output circuit 448, and the aforementioned sense amplifier 446.

[0422] The row decoder 442 and column decoder 444 have the function of decoding the ADDR signal. The row decoder 442 is a circuit for specifying the row to access, and the column decoder 444 is a circuit for specifying the column to access. The row driver 443 has the function of selecting the wiring WL specified by the row decoder 442. The column driver 445 has the function of writing data to the memory cell 432, reading data from the memory cell 432, and holding the read data.

[0423] The input circuit 447 has the function of holding the signal WDA. The data held by the input circuit 447 is output to the column driver 445. The output data of the input circuit 447 is the data (Din) to be written to the memory cell 432. The data (Dout) read by the column driver 445 from the memory cell 432 is output to the output circuit 448. The output circuit 448 has the function of holding Dout. The output circuit 448 also has the function of outputting Dout to the outside of the storage device 480. The data output from the output circuit 448 is the signal RDA.

[0424] PSW 471 has the function of controlling the supply of VDD to the peripheral circuit 422. PSW 472 has the function of controlling the supply of VHM to the row driver 443. Here, the high power supply potential of the storage device 480 is VDD, and the low power supply potential is GND (ground potential). VHM is a high power supply potential used to raise the word line to a high level, and is higher than VDD. The on / off state of PSW 471 is controlled by signal PON1, and the on / off state of PSW 472 is controlled by signal PON2. In Figure 25, the number of power supply domains to which VDD is supplied in the peripheral circuit 422 is set to 1, but it can be multiple. In this case, a power switch can be provided for each power supply domain.

[0425] The element layers 430[1] to 430[m] can be layered on top of layer 420. Figure 26A shows a perspective view of a memory device 480 in which five layers (m=5) of element layers 430[1] to 430[5] are layered on top of layer 420.

[0426] In Figure 26A, the element layer 430 provided as the first layer is shown as element layer 430[1], the element layer 430 provided as the second layer is shown as element layer 430[2], and the element layer 430 provided as the fifth layer is shown as element layer 430[5]. Also in Figure 26A, wiring WL and wiring PL extending in the X direction, and wiring BL and wiring BLB extending in the Y direction and Z direction (directions perpendicular to the substrate surface on which the drive circuit is provided) are shown. Wiring BLB is an inversion bit line. Note that, in order to make the drawing easier to read, some of the wiring WL and wiring PL of each element layer 430 have been omitted from the description.

[0427] Figure 26B shows a schematic diagram illustrating an example configuration of the wiring BL and sense amplifier 446 connected to the wiring BLB shown in Figure 26A, and the memory cells 432 having element layers 430[1] to 430[5] connected to the wiring BL and wiring BLB. A configuration in which multiple memory cells (memory cells 432) are electrically connected to one wiring BL and wiring BLB is also called a "memory string".

[0428] Figure 26B illustrates an example of the circuit configuration of a memory cell 432 connected to wiring BLB. The memory cell 432 has a transistor 437 and a capacitive element 438. The transistor 437, the capacitive element 438, and each wiring (BL, WL, etc.) may also be referred to as wiring BL[1] and wiring WL[1], for example, wiring BL and wiring WL.

[0429] In the memory cell 432, either the source or drain of transistor 437 is connected to wiring BL. The other source or drain of transistor 437 is connected to one electrode of capacitive element 438. The other electrode of capacitive element 438 is connected to wiring PL. The gate of transistor 437 is connected to wiring WL.

[0430] The wiring PL is a wire that provides a constant potential to maintain the potential of the capacitive element 438. By connecting multiple wiring PLs together and using them as a single wire, the number of wires can be reduced.

[0431] In one aspect of the present invention, OS transistors are stacked, and wiring that functions as bit lines is arranged perpendicular to the substrate surface on which layer 420 is provided. In addition, the transistors 437 and capacitive elements 438 of the memory cell 432 are arranged in a parallel direction perpendicular to the substrate surface on which layer 420 is provided. By providing each element and each wiring perpendicular to the substrate surface, the length of the wiring between element layers can be shortened, and the density of elements provided per unit area can be increased. Therefore, a memory device with excellent memory capacity and reduced power consumption can be obtained.

[0432] [Example Configuration of Memory Cell 432 and Sense Amplifier 446] Figures 27A and 27B show the circuit diagram corresponding to the memory cell 432 described above, and the circuit block diagram corresponding to the said circuit diagram. As shown in Figures 27A and 27B, the memory cell 432 may be represented as a block in drawings, etc. Note that the wiring BL shown in Figures 27A and 27B can be similarly represented when replaced with wiring BLB.

[0433] Furthermore, Figures 27C and 27D show the circuit diagram corresponding to the sense amplifier 446 described above, and the circuit block diagram corresponding to said circuit diagram. The sense amplifier 446 is shown to include a switch circuit 482, a precharge circuit 483, a precharge circuit 484, and an amplification circuit 485. In addition to wiring BL and wiring BLB, wiring SA_OUT and wiring SA_OUTB, which output the readout signal, are also shown.

[0434] As shown in Figure 27C, the switch circuit 482 includes, for example, an N-type transistor 482_1 and an N-type transistor 482_2. The N-type transistors 482_1 and 482_2 switch the conduction state of the wiring pair SA_OUT and SA_OUTB and the wiring pair BL and BLB according to the signal CSEL.

[0435] As shown in Figure 27C, the pre-charge circuit 483 is composed of N-type transistors 483_1 to 483_3. The pre-charge circuit 483 is a circuit for pre-charging wiring BL and wiring BLB to an intermediate potential VPRE corresponding to the potential VDD / 2, in accordance with the signal EQ.

[0436] As shown in Figure 27C, the pre-charge circuit 484 is composed of P-type transistors 484_1 to 484_3. The pre-charge circuit 484 is a circuit for pre-charging wiring BL and wiring BLB to an intermediate potential VPRE corresponding to the potential VDD / 2, in accordance with the signal EQB.

[0437] As shown in Figure 27C, the amplification circuit 485 consists of P-type transistors 485_1, 485_2, N-type transistors 485_3, and 485_4, which are connected to wiring SAP or wiring SAN. Wiring SAP or wiring SAN is wiring that has the function of providing VDD or VSS. P-type transistors 485_1, 485_2, 485_3, and 485_4 are transistors that constitute an inverter loop.

[0438] Furthermore, Figure 27D shows a circuit block diagram corresponding to the sense amplifier 446 described in Figure 27C, etc. As shown in Figure 27D, the sense amplifier 446 may be represented as a block in drawings, etc.

[0439] Figure 28 is a circuit diagram of the storage device 480 shown in Figure 25. Figure 28 uses the circuit blocks described in Figures 27A to 27D to illustrate the circuit.

[0440] As shown in Figure 28, the layer 470, which includes the element layer 430 [m], has memory cells 432. The memory cells 432 shown in Figure 28 are connected, for example, to a pair of wiring BL[1] and wiring BLB[1], or wiring BL[2] and wiring BLB[2]. The memory cells 432 connected to wiring BL are memory cells from which data is written or read.

[0441] Wiring BL[1] and wiring BLB[1] are connected to sense amplifier 446[1], and wiring BL[2] and wiring BLB[2] are connected to sense amplifier 446[2]. Sense amplifiers 446[1] and 446[2] can read data according to the various signals described in Figure 27C.

[0442] This embodiment can be implemented in appropriate combination with other embodiments or examples described herein, at least in part.

[0443] (Embodiment 6) This embodiment describes an example of the configuration of a display device to which a transistor according to one aspect of the present invention can be applied.

[0444] Since the transistor according to one aspect of the present invention can be made extremely small, a display device to which the transistor according to one aspect of the present invention is applied can be an extremely high-resolution display device. For example, the display device according to one aspect of the present invention can be used in the display section of information terminals (wearable devices) such as wristwatches and bracelets, and in the display section of head-mounted displays (HMDs) such as virtual reality (VR) devices such as head-mounted displays and augmented reality (AR) devices such as glasses.

[0445] In one embodiment of the present invention, a display device can be provided with a drive circuit and a pixel circuit stacked on top of each other. In this case, the transistors constituting the pixels can be transistors in which channels are formed in a single-crystal oxide semiconductor, as exemplified in Embodiment 3.

[0446] [Display Module] Figure 29A shows a perspective view of the display module 580. The display module 580 includes a display device 500A and an FPC (Flexible Printed Circuit) 590.

[0447] The display module 580 has substrates 591 and 592. The display module 580 has a display unit 581. The display unit 581 is an area for displaying an image.

[0448] Figure 29B shows a schematic perspective view illustrating the configuration of the substrate 591. A circuit section 582, a pixel circuit section 583 on the circuit section 582, and a pixel section 584 on the pixel circuit section 583 are stacked on the substrate 591. A terminal section 585 for connecting to the FPC 590 is provided in a portion of the substrate 591 that does not overlap with the pixel section 584. The terminal section 585 and the circuit section 582 are electrically connected by a wiring section 586, which is composed of multiple wires.

[0449] The pixel section 584 has a plurality of pixels 584a arranged periodically. An enlarged view of one pixel 584a is shown on the right side of Figure 29B. The pixel 584a has a light-emitting element 110R that emits red light, a light-emitting element 110G that emits green light, and a light-emitting element 110B that emits blue light.

[0450] The pixel circuit section 583 has a plurality of periodically arranged pixel circuits 583a. Each pixel circuit 583a is a circuit that controls the light emission of three light-emitting devices that one pixel 584a has. A single pixel circuit 583a may be configured to have three circuits that control the light emission of one light-emitting device. For example, each pixel circuit 583a may have at least one selection transistor, one current control transistor (drive transistor), and a capacitive element. In this case, a gate signal is input to the gate of the selection transistor, and a source signal is input to the source. This realizes an active matrix type display panel.

[0451] The circuit section 582 has circuits for driving each pixel circuit 583a of the pixel circuit section 583. For example, it is preferable to have one or both of a gate line drive circuit and a source line drive circuit. In addition, it may have at least one of the following: an arithmetic circuit, a memory circuit, and a power supply circuit. Furthermore, transistors provided in the circuit section 582 may constitute a part of the pixel circuit 583a. That is, the pixel circuit 583a may be composed of transistors in the pixel circuit section 583 and transistors in the circuit section 582.

[0452] The FPC 590 functions as wiring for supplying video signals and power potential, etc., to the circuit section 582 from an external source. An IC may also be mounted on the FPC 590.

[0453] The display module 580 can be configured such that one or both of the pixel circuit section 583 and the circuit section 582 are superimposed on the lower side of the pixel section 584, thereby making the aperture ratio (effective display area ratio) of the display section 581 extremely high. For example, the aperture ratio of the display section 581 can be 40% or more and less than 100%, preferably 50% or more and 95%, and more preferably 60% or more and 95%. Furthermore, it is possible to arrange the pixels 584a at an extremely high density, making the resolution of the display section 581 extremely high. For example, it is preferable that the pixels 584a in the display section 581 are arranged at a density of 2000 ppi or more, preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 6000 ppi or more, with a resolution of 20000 ppi or less, or 30000 ppi or less.

[0454] Because such a display module 580 is extremely high-resolution, it is suitable for VR devices such as head-mounted displays, or AR devices such as glasses. For example, even in a configuration where the display part of the display module 580 is viewed through lenses, the display module 580 has an extremely high-resolution display part 581, so even when the display part is magnified with lenses, pixels are not visible, and a highly immersive display can be provided. Furthermore, the display module 580 is not limited to this, and is suitable for electronic devices with relatively small display parts. For example, it is suitable for the display part of wearable electronic devices such as wristwatches.

[0455] [Display device 500A] The display device 500A shown in Figure 30 includes a substrate 301, a light-emitting element 110R, a light-emitting element 110G, a light-emitting element 110B, a capacitive element 540, a transistor 310, and a transistor 320.

[0456] Transistor 310 is a transistor in which a channel is formed on a single-crystal substrate. Transistor 320 can be a transistor in which a channel is formed on a single-crystal oxide semiconductor, as exemplified in Embodiment 3.

[0457] The transistor 310 is a transistor having a channel-forming region in the substrate 301. The substrate 301 can be a semiconductor substrate such as a single-crystal silicon substrate. The transistor 310 comprises a portion of the substrate 301, a conductive layer 311, a low-resistance region 312, an insulating layer 313, and an insulating layer 314. The conductive layer 311 functions as a gate electrode. The insulating layer 313 is located between the substrate 301 and the conductive layer 311 and functions as a gate insulating layer. The low-resistance region 312 is a region of the substrate 301 doped with impurities and functions as either a source or a drain. The insulating layer 314 is provided covering the side surface of the conductive layer 311.

[0458] Furthermore, an element isolation layer 315 is provided between two adjacent transistors 310 so as to be embedded in the substrate 301.

[0459] The transistor 320 has a semiconductor layer 351, an insulating layer 353, a conductive layer 354, a pair of conductive layers 355, an insulating layer 356, and a conductive layer 357.

[0460] An insulating layer 352 is provided on the layer on which the transistor 310 is located, via a wiring layer 316 and an interlayer insulating layer. The insulating layer 352 functions as a barrier layer to prevent impurities from diffusing from the substrate 301 side to the transistor 320, and to prevent oxygen from detaching from the semiconductor layer 351 to the insulating layer 352 side. As the insulating layer 352, for example, a film that is less permeable to hydrogen or oxygen than a silicon oxide film, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film, can be used.

[0461] A conductive layer 357 is provided on an insulating layer 352, and an insulating layer 356 is provided covering the conductive layer 357. The conductive layer 357 functions as the second gate electrode of the transistor 320, and a portion of the insulating layer 356 functions as the second gate insulating layer. It is preferable to use an oxide insulating film, such as a silicon oxide film, in at least the region of the insulating layer 356 that is in contact with the semiconductor layer 351. It is preferable that the upper surface of the insulating layer 356 is flattened.

[0462] The semiconductor layer 351 is provided on the insulating layer 356. Preferably, the semiconductor layer 351 has a metal oxide (also called an oxide semiconductor) film that exhibits semiconductor properties. A pair of conductive layers 355 are provided in contact with the semiconductor layer 351 and function as a source electrode and a drain electrode.

[0463] An insulating layer 358 and an insulating layer 350 are provided to cover the top and side surfaces of the pair of conductive layers 355, as well as the side surfaces of the semiconductor layer 351. The insulating layer 358 functions as a barrier layer to prevent impurities such as water or hydrogen from diffusing into the semiconductor layer 351 and to prevent oxygen from detaching from the semiconductor layer 351. An insulating film similar to that used for the insulating layer 352 can be used for the insulating layer 358.

[0464] The insulating layer 358 and the insulating layer 350 are provided with openings that reach the semiconductor layer 351. An insulating layer 353 in contact with the upper surface of the semiconductor layer 351 and a conductive layer 354 are embedded inside these openings. The conductive layer 354 functions as a first gate electrode, and the insulating layer 353 functions as a first gate insulating layer.

[0465] The upper surfaces of the conductive layer 354, the insulating layer 353, and the insulating layer 350 are flattened so that their heights are the same, and an insulating layer 359 is provided covering them. The insulating layer 359 functions as a barrier layer to prevent impurities such as water or hydrogen from diffusing into the transistor 320. An insulating film similar to that used for the insulating layer 352 can be used for the insulating layer 359.

[0466] The transistor 320 employs a configuration in which a semiconductor layer on which a channel is formed is sandwiched between two gates. The transistor may be driven by connecting the two gates and supplying them with the same signal. Alternatively, the threshold voltage of the transistor may be controlled by applying a potential to control the threshold voltage to one of the two gates and a potential to drive the other gate.

[0467] An insulating layer 564 is provided on the insulating layer 359. The insulating layer 564 functions as an interlayer insulating layer.

[0468] The plug 574, which is electrically connected to one side of the conductive layer 355, is provided so as to be embedded in the insulating layer 564, insulating layer 359, insulating layer 350, and insulating layer 358. Here, it is preferable that the plug 574 has a conductive layer 574a that covers the side surface of the opening in the insulating layer 564, etc., and a part of the upper surface of the conductive layer 355, and a conductive layer 574b that is in contact with the upper surface of the conductive layer 574a. In this case, it is preferable to use a conductive material that does not easily allow oxygen to diffuse as the conductive layer 574a.

[0469] Furthermore, a capacitive element 540 is provided on the insulating layer 564. The capacitive element 540 has a conductive layer 541, a conductive layer 545, and an insulating layer 543 located between them. The conductive layer 541 functions as one electrode of the capacitive element 540, the conductive layer 545 functions as the other electrode of the capacitive element 540, and the insulating layer 543 functions as the dielectric of the capacitive element 540.

[0470] The conductive layer 541 is embedded in an insulating layer 554 provided on an insulating layer 564. The conductive layer 541 is electrically connected to the conductive layer 355 of the transistor 320 by a plug 574. The insulating layer 543 is provided covering the conductive layer 541. The conductive layer 545 is provided in the region that overlaps with the conductive layer 541 via the insulating layer 543.

[0471] An insulating layer 555a is provided to cover the capacitive element 540, an insulating layer 555b is provided on the insulating layer 555a, and an insulating layer 555c is provided on the insulating layer 555b.

[0472] Insulating layers 555a, 555b, and 555c can each preferably be made of inorganic insulating films. For example, it is preferable to use silicon oxide films for insulating layers 555a and 555c, and silicon nitride films for insulating layer 555b. This allows insulating layer 555b to function as an etching protective film. In this embodiment, an example is shown in which a part of insulating layer 555c is etched and a recess is formed, but the insulating layer 555c does not necessarily have to have a recess.

[0473] A light-emitting element 110R, a light-emitting element 110G, and a light-emitting element 110B are provided on the insulating layer 555c.

[0474] The light-emitting element 110R has a pixel electrode 111R, an organic layer 112R, a common layer 114, and a common electrode 113. The light-emitting element 110G has a pixel electrode 111G, an organic layer 112G, a common layer 114, and a common electrode 113. The light-emitting element 110B has a pixel electrode 111B, an organic layer 112B, a common layer 114, and a common electrode 113. The common layer 114 and the common electrode 113 are provided in common to the light-emitting elements 110R, 110G, and 110B. Note that the pixel electrode 111R, pixel electrode 111G, and pixel electrode 111B are sometimes collectively referred to as the pixel electrode 111.

[0475] The organic layer 112R of the light-emitting element 110R contains at least a luminescent organic compound that emits red light. The organic layer 112G of the light-emitting element 110G contains at least a luminescent organic compound that emits green light. The organic layer 112B of the light-emitting element 110B contains at least a luminescent organic compound that emits blue light. The organic layers 112R, 112G, and 112B can each also be called EL layers and each contains at least a luminescent substance (luminescent layer).

[0476] The display device 500A has different light-emitting devices for each light-emitting color, resulting in minimal change in chromaticity between low-brightness and high-brightness illumination. Furthermore, because the organic layers 112R, 112G, and 112B are separated, crosstalk between adjacent sub-pixels can be suppressed even in high-resolution display panels. Therefore, a display panel with high resolution and high display quality can be realized.

[0477] An insulating layer 125, a resin layer 126, and a layer 128 are provided in the region between adjacent light-emitting elements.

[0478] The pixel electrodes 111R, 111G, and 111B of the light-emitting element are electrically connected to the conductive layer 355 of the transistor 320 by plugs 556 embedded in insulating layers 555a, 555b, and 555c, a conductive layer 541 embedded in insulating layer 554, and plugs 574. The height of the upper surface of insulating layer 555c and the height of the upper surface of plug 556 are the same. Various conductive materials can be used for the plugs.

[0479] Furthermore, a protective layer 121 is provided on the light-emitting elements 110R, 110G, and 110B. The substrate 170 is bonded to the protective layer 121 by an adhesive layer 171.

[0480] There is no insulating layer covering the upper edge of the pixel electrode 111 between two adjacent pixel electrodes 111. Therefore, the spacing between adjacent light-emitting elements can be made extremely narrow. Consequently, a high-definition or high-resolution display device can be made.

[0481] This embodiment can be implemented in appropriate combination with other embodiments or examples described herein, at least in part.

[0482] (Embodiment 7) In this embodiment, an electronic device according to one aspect of the present invention will be described with reference to Figures 31A to 33G.

[0483] The electronic device of this embodiment has a display panel (display device) to which a transistor according to one aspect of the present invention is applied in the display unit. The display device according to one aspect of the present invention can be easily made high-definition and high-resolution, and can achieve high display quality. Therefore, it can be used in the display unit of various electronic devices.

[0484] Examples of electronic devices include television sets, desktop or laptop computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as other electronic devices with relatively large screens, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, personal digital assistants, and audio playback devices.

[0485] In particular, a display panel according to one embodiment of the present invention is suitable for electronic devices having a relatively small display area because it can increase resolution. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), as well as wearable devices that can be worn on the head, such as VR devices such as head-mounted displays, AR devices such as glasses, and MR devices.

[0486] A display panel according to one embodiment of the present invention preferably has an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels). In particular, a resolution of 4K, 8K, or higher is preferred. Furthermore, the pixel density (resolution) of the display panel according to one embodiment of the present invention is preferably 100 ppi or more, preferably 300 ppi or more, more preferably 500 ppi or more, more preferably 1000 ppi or more, more preferably 2000 ppi or more, more preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 7000 ppi or more. By using a display panel having either high resolution or high detail, or both, it becomes possible to further enhance the sense of presence and depth. Furthermore, there are no particular limitations on the aspect ratio of the display panel in one embodiment of the present invention. For example, the display panel can support various aspect ratios such as 1:1 (square), 4:3, 16:9, and 16:10.

[0487] The electronic device of this embodiment may have sensors (including those with the function of detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation).

[0488] The electronic device of this embodiment can have a variety of functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, a function to execute various software (programs), a wireless communication function, a function to read programs or data recorded on a recording medium, and so on.

[0489] Figures 31A to 31D illustrate an example of a wearable device that can be worn on the head. These wearable devices have one or both functions: the ability to display AR content and / or the ability to display VR content. In addition to AR and VR, these wearable devices may also have the ability to display Substitutional Reality (SR) or Mixed Reality (MR) content. By having an electronic device that has the ability to display at least one of the following content types, such as AR, VR, SR, and MR, it is possible to enhance the user's sense of immersion.

[0490] The electronic device 700A shown in Figure 31A and the electronic device 700B shown in Figure 31B each include a pair of display panels 751, a pair of housings 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical members 753, a frame 757, and a pair of nose pads 758.

[0491] A display panel according to one embodiment of the present invention can be applied to the display panel 751. Therefore, an electronic device capable of displaying extremely high resolution can be created.

[0492] Electronic devices 700A and 700B can project an image displayed on the display panel 751 onto the display area 756 of the optical element 753. Because the optical element 753 is translucent, the user can see the image displayed on the display area superimposed on the transmitted image visible through the optical element 753. Therefore, electronic devices 700A and 700B are electronic devices capable of AR display.

[0493] Electronic devices 700A and 700B may be equipped with cameras capable of capturing images of the area in front of them as imaging units. Furthermore, electronic devices 700A and 700B may each be equipped with acceleration sensors such as gyro sensors to detect the orientation of the user's head and display an image corresponding to that orientation in the display area 756.

[0494] The communications unit has a wireless communication device, which can supply video signals and the like. Alternatively, instead of the wireless communication device, or in addition to the wireless communication device, it may be equipped with a connector to which a cable supplying video signals and power potential can be connected.

[0495] Furthermore, electronic devices 700A and 700B are equipped with batteries (not shown) that can be charged wirelessly, wired, or both.

[0496] The housing 721 may be equipped with a touch sensor module. The touch sensor module has the function of detecting when the outer surface of the housing 721 is touched. The touch sensor module can detect the user's tap or slide operations and perform various processes. For example, a tap operation can be used to pause or resume the video, and a slide operation can be used to fast forward or rewind. Furthermore, by providing a touch sensor module in each of the two housings 721, the range of operations can be expanded.

[0497] Various types of touch sensors can be applied to the touch sensor module. For example, various methods such as capacitive, resistive, infrared, electromagnetic induction, surface acoustic wave, and optical sensors can be used. In particular, it is preferable to apply a capacitive or optical sensor to the touch sensor module.

[0498] When using an optical touch sensor, a photoelectric conversion device (also called a photoelectric element) can be used as the light-receiving device (also called a photoelectric element). The active layer of the photoelectric conversion device can be made of either an inorganic semiconductor or an organic semiconductor, or both.

[0499] The electronic device 800A shown in Figure 31C and the electronic device 800B shown in Figure 31D each include a pair of display units 820, a housing 821, a communication unit 822, a pair of mounting units 823, a control unit 824, a pair of imaging units 825, and a pair of lenses 832.

[0500] A display panel according to one embodiment of the present invention can be applied to the display unit 820. Therefore, an electronic device capable of displaying extremely high resolution can be created. This allows the user to experience a high level of immersion.

[0501] The display unit 820 is located inside the housing 821 in a position visible through the lens 832. Furthermore, by displaying different images on a pair of display units 820, a three-dimensional display using parallax can be achieved.

[0502] Electronic devices 800A and 800B can each be described as electronic devices for VR. A user wearing electronic device 800A or electronic device 800B can view the image displayed on the display unit 820 through the lens 832.

[0503] It is preferable that electronic devices 800A and 800B each have a mechanism that allows adjustment of the left and right positions of the lens 832 and the display unit 820 so that they are in the optimal position according to the user's eye position. It is also preferable that they have a mechanism that adjusts the focus by changing the distance between the lens 832 and the display unit 820.

[0504] The attachment portion 823 allows the user to attach the electronic device 800A or 800B to their head. While the attachment portion 823 is exemplified in Figure 31C and other figures as resembling the temples (or arms) of eyeglasses, it is not limited to this. The attachment portion 823 only needs to be wearable by the user; for example, it may be helmet-shaped or band-shaped.

[0505] The imaging unit 825 has the function of acquiring external information. The data acquired by the imaging unit 825 can be output to the display unit 820. An image sensor can be used in the imaging unit 825. In addition, multiple cameras may be provided to accommodate multiple angles of view, such as telephoto and wide-angle.

[0506] Although an example with an imaging unit 825 is shown here, any distance measuring sensor (hereinafter also referred to as a detection unit) capable of measuring the distance to an object can be provided. In other words, the imaging unit 825 is one form of the detection unit. As the detection unit, for example, an image sensor or a distance image sensor such as LiDAR (Light Detection and Ranging) can be used. By using the image obtained by the camera and the image obtained by the distance image sensor, more information can be acquired, enabling more accurate gesture control.

[0507] The electronic device 800A may have a vibration mechanism that functions as a bone conduction earphone. For example, a configuration having such a vibration mechanism can be applied to one or more of the display unit 820, housing 821, and mounting unit 823. This allows users to enjoy video and audio simply by wearing the electronic device 800A, without needing separate audio equipment such as headphones, earphones, or speakers.

[0508] Electronic devices 800A and 800B may each have input terminals. Cables can be connected to the input terminals to supply video signals from video output devices, etc., and power for charging batteries provided in the electronic devices.

[0509] An electronic device according to one aspect of the present invention may have a function for wireless communication with an earphone 750. The earphone 750 has a communication unit (not shown) and has a wireless communication function. The earphone 750 can receive information (e.g., voice data) from the electronic device through its wireless communication function. For example, the electronic device 700A shown in Figure 31A has a function for transmitting information to the earphone 750 through its wireless communication function. Also, for example, the electronic device 800A shown in Figure 31C has a function for transmitting information to the earphone 750 through its wireless communication function.

[0510] Furthermore, the electronic device may have an earphone section. The electronic device 700B shown in Figure 31B has an earphone section 727. For example, the earphone section 727 and the control unit can be connected to each other by a wire. Part of the wiring connecting the earphone section 727 and the control unit may be located inside the housing 721 or the mounting section 723.

[0511] Similarly, the electronic device 800B shown in Figure 31D has an earphone unit 827. For example, the earphone unit 827 and the control unit 824 can be connected to each other by wire. Part of the wiring connecting the earphone unit 827 and the control unit 824 may be located inside the housing 821 or the mounting unit 823. Also, the earphone unit 827 and the mounting unit 823 may have magnets. This allows the earphone unit 827 to be fixed to the mounting unit 823 by magnetic force, which is preferable as it facilitates storage.

[0512] Furthermore, the electronic device may have an audio output terminal to which earphones or headphones can be connected. The electronic device may also have an audio input terminal and / or an audio input mechanism. For example, a sound-collecting device such as a microphone can be used as the audio input mechanism. By having an audio input mechanism, the electronic device may be given the function of a so-called headset.

[0513] Thus, as one embodiment of the present invention, both eyeglass-type (electronic devices 700A and 700B, etc.) and goggle-type (electronic devices 800A and 800B, etc.) are preferred as electronic devices.

[0514] The electronic device 6500 shown in Figure 32A is a portable information terminal that can be used as a smartphone.

[0515] The electronic device 6500 includes a housing 6501, a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509. The display unit 6502 has a touch panel function. The control device 6509 includes, for example, one or more selected from a CPU, a GPU (Graphics Processing Unit), and a storage device. A semiconductor device according to one aspect of the present invention can be applied to the display unit 6502, the control device 6509, etc. Using a semiconductor device according to one aspect of the present invention as the control device 6509 is preferable because it can reduce power consumption.

[0516] A display panel according to one embodiment of the present invention can be applied to the display unit 6502.

[0517] Figure 32B is a schematic cross-sectional view of the housing 6501 including the end on the microphone 6506 side.

[0518] A light-transmitting protective member 6510 is provided on the display side of the housing 6501, and the display panel 6511, optical member 6512, touch sensor panel 6513, printed circuit board 6517, battery 6518, etc. are arranged in the space enclosed by the housing 6501 and the protective member 6510.

[0519] The protective member 6510 is fixed to the display panel 6511, the optical member 6512, and the touch sensor panel 6513 by an adhesive layer (not shown).

[0520] In the area outside the display unit 6502, a portion of the display panel 6511 is folded back, and the FPC 6515 is connected to this folded portion. IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to terminals provided on the printed circuit board 6517.

[0521] A display device according to one embodiment of the present invention can be applied to the display panel 6511. As a result, an extremely lightweight electronic device can be realized. Furthermore, because the display panel 6511 is extremely thin, a large-capacity battery 6518 can be installed while keeping the thickness of the electronic device low. In addition, by folding back a part of the display panel 6511 and placing the connection part with the FPC 6515 on the back of the pixel section, an electronic device with a narrow bezel can be realized.

[0522] Figure 32C shows an example of a television system. The television system 7100 has a display unit 7000 incorporated into a housing 7101. Here, the housing 7101 is supported by a stand 7103.

[0523] The television device 7100 shown in Figure 32C can be operated using the operation switches on the housing 7101 and a separate remote control unit 7111. Alternatively, the display unit 7000 may be equipped with a touch sensor, and the television device 7100 can be operated by touching the display unit 7000 with a finger or the like. The remote control unit 7111 may have a display unit that displays information output from the remote control unit 7111. Channels and volume can be controlled and the image displayed on the display unit 7000 can be controlled using the operation keys or touch panel on the remote control unit 7111.

[0524] The television system 7100 is configured to include a receiver and a modem. The receiver can receive general television broadcasts. Furthermore, by connecting to a wired or wireless communication network via the modem, it is possible to perform one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.

[0525] Figure 32D shows an example of a notebook computer. The notebook computer 7200 includes a casing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, a control device 7216, etc. A display unit 7000 is incorporated into the casing 7211. The control device 7216 includes, for example, one or more selected from a CPU, a GPU, and a storage device. A semiconductor device according to one aspect of the present invention can be applied to the display unit 7000, the control device 7216, etc. Using a semiconductor device according to one aspect of the present invention as the control device 7216 is preferable because it can reduce power consumption.

[0526] Figures 32E and 32F show examples of digital signage.

[0527] The digital signage 7300 shown in Figure 32E includes a housing 7301, a display unit 7000, and a speaker 7303, etc. Furthermore, it may include LED lamps, operation keys (including a power switch or operation switches), connection terminals, various sensors, a microphone, etc.

[0528] Figure 32F shows a digital signage 7400 mounted on a cylindrical column 7401. The digital signage 7400 has a display unit 7000 that is provided along the curved surface of the column 7401.

[0529] The larger the display area 7000, the more information can be provided at once. Furthermore, a larger display area 7000 is more eye-catching, which can, for example, enhance the effectiveness of advertising.

[0530] Applying a touch panel to the display unit 7000 is preferable because it not only allows images or videos to be displayed on the display unit 7000, but also enables intuitive operation by the user. Furthermore, when used for purposes such as providing route information or traffic information, intuitive operation can enhance usability.

[0531] Furthermore, as shown in Figures 32E and 32F, it is preferable that the digital signage 7300 or digital signage 7400 can be linked wirelessly with an information terminal 7311 or information terminal 7411 such as a smartphone owned by the user. For example, the advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or information terminal 7411. Also, the display on the display unit 7000 can be switched by operating the information terminal 7311 or information terminal 7411.

[0532] Furthermore, the digital signage 7300 or digital signage 7400 can be used to run games using the screen of the information terminal 7311 or information terminal 7411 as the control device (controller). This allows an unspecified number of users to participate in and enjoy the game simultaneously.

[0533] In Figures 32C to 32F, a display panel according to one embodiment of the present invention can be applied to the display unit 7000.

[0534] The electronic device shown in Figures 33A to 33G includes a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or operation switch), connection terminals 9006, a sensor 9007 (including a function to detect, detect, or measure force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation), a microphone 9008, etc.

[0535] The electronic devices shown in Figures 33A to 33G have various functions. For example, they may have functions to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date or time, a function to control processing by various software (programs), a wireless communication function, a function to read and process programs or data recorded on a recording medium, etc. However, the functions of electronic devices are not limited to these and can have various functions. Electronic devices may have multiple display units. Furthermore, electronic devices may be equipped with a camera, etc., and have functions to capture still images or videos and save them on a recording medium (external or built into the camera), a function to display the captured images on a display unit, etc.

[0536] Details of the electronic equipment shown in Figures 33A to 33G will be explained below.

[0537] Figure 33A is a perspective view showing a personal digital information terminal (PDI) 9101. The PDI 9101 can be used, for example, as a smartphone. The PDI 9101 may also be equipped with a speaker 9003, connection terminals 9006, sensors 9007, etc. The PDI 9101 can also display text and image information on multiple surfaces. Figure 33A shows an example where three icons 9050 are displayed. Information 9051, indicated by a dashed rectangle, can also be displayed on other surfaces of the display unit 9001. Examples of information 9051 include notifications of incoming emails, SNS messages, and phone calls, the subject of an email or SNS message, the sender's name, date and time, battery level, and signal strength. Alternatively, icons 9050 or the like may be displayed in the location where the information 9051 is displayed.

[0538] Figure 33B is a perspective view showing the personal digital assistant (PDA) 9102. The PDA 9102 has the function of displaying information on three or more sides of the display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different sides. For example, a user can check information 9053, which is displayed in a position that can be observed from above the PDA 9102, while the PDA 9102 is stored in the breast pocket of their clothing. The user can check the display without taking the PDA 9102 out of their pocket and decide, for example, whether or not to answer a call.

[0539] Figure 33C is a perspective view showing the tablet terminal 9103. The tablet terminal 9103 can run various applications, such as mobile phone calls, email, document viewing and creation, music playback, internet communication, and computer games. The tablet terminal 9103 has a display unit 9001, a camera 9002, a microphone 9008, and a speaker 9003 on the front of the housing 9000. The left side of the housing 9000 has operation keys 9005 as buttons for operation, and the bottom has connection terminals 9006.

[0540] Figure 33D is a perspective view showing a wristwatch-type personal information terminal 9200. The personal information terminal 9200 can be used, for example, as a smartwatch (registered trademark). The display unit 9001 has a curved display surface, allowing it to display information along the curved surface. The personal information terminal 9200 can also make hands-free calls by communicating with, for example, a wireless communication headset. Furthermore, the personal information terminal 9200 can transmit data to other information terminals and be charged via a connection terminal 9006. Charging may be performed by wireless power supply.

[0541] Figures 33E to 33G are perspective views showing a foldable portable information terminal 9201. Figure 33E shows the portable information terminal 9201 in an unfolded state, Figure 33G shows it in a folded state, and Figure 33F shows a perspective view of the state in between, transitioning from one of Figures 33E or 33G to the other. The portable information terminal 9201 offers excellent portability in its folded state and excellent readability of the display due to its seamless, wide display area in its unfolded state. The display unit 9001 of the portable information terminal 9201 is supported by three housings 9000 connected by hinges 9055. For example, the display unit 9001 can be bent with a radius of curvature of 0.1 mm to 150 mm.

[0542] This embodiment can be implemented in appropriate combination with other embodiments or examples described herein, at least in part.

[0543] (Embodiment 8) This embodiment describes an application example of a semiconductor device according to one aspect of the present invention. A semiconductor device according to one aspect of the present invention can be used, for example, in electronic components, electronic equipment, large computers, space equipment, and data centers (also referred to as Data Centers: DCs). Electronic components, electronic equipment, large computers, space equipment, and data centers using a semiconductor device according to one aspect of the present invention are effective in achieving high performance, such as low power consumption.

[0544] Electronic components and the like to which a semiconductor device according to one embodiment of the present invention is applied can be applied to the electronic device exemplified in Embodiment 7.

[0545] [Electronic Components] Figure 34A shows a perspective view of a substrate (mounted substrate 704) on which electronic components 700 are mounted. The electronic component 700 shown in Figure 34A has a semiconductor device 710 inside a mold 711. Some details are omitted in Figure 34A to show the inside of the electronic component 700. The electronic component 700 has a land 712 on the outside of the mold 711. The land 712 is electrically connected to an electrode pad 713, and the electrode pad 713 is electrically connected to the semiconductor device 710 via a wire 714. The electronic component 700 is mounted on, for example, a printed circuit board 702. Multiple such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounted substrate 704.

[0546] Furthermore, the semiconductor device 710 includes a drive circuit layer 715 and a storage layer 716. The storage layer 716 has a configuration in which multiple memory cell arrays are stacked. The configuration in which the drive circuit layer 715 and the storage layer 716 are stacked can be a monolithic stack configuration. In a monolithic stack configuration, the layers can be connected without using through-electrode technologies such as TSV (Through Silicon Via) and bonding technologies such as Cu-Cu direct bonding. By monolithically stacking the drive circuit layer 715 and the storage layer 716, for example, a so-called on-chip memory configuration can be achieved in which memory is directly formed on the processor. By using an on-chip memory configuration, it is possible to speed up the operation of the interface portion between the processor and the memory.

[0547] Furthermore, by using an on-chip memory configuration, the size of connection wiring can be reduced compared to technologies using through-hole electrodes such as TSVs, making it possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which in turn improves the memory bandwidth (also called memory bandwidth).

[0548] Furthermore, it is preferable to form the multiple memory cell arrays in the memory layer 716 using OS transistors and to stack these multiple memory cell arrays monolithically. By configuring the multiple memory cell arrays in a monolithic stack, it is possible to improve either or both of the memory bandwidth and / or the memory access latency. Bandwidth is the amount of data transferred per unit time, and access latency is the time from access to the start of data exchange. In the case of a configuration using Si transistors in the memory layer 716, it is difficult to create a monolithic stack configuration compared to OS transistors. Therefore, in a monolithic stack configuration, OS transistors can be said to have a superior structure compared to Si transistors.

[0549] Furthermore, the semiconductor device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained in the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disc-shaped substrate (also called a wafer) and cutting it into cubes. Examples of semiconductor materials that can be used for dies include silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) is sometimes called a silicon die.

[0550] Next, a perspective view of the electronic component 730 is shown in Figure 34B. The electronic component 730 is an example of a SiP (System in Package) or MCM (Multi-Chip Module). The electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 are provided on the interposer 731.

[0551] Electronic component 730 shows an example of using semiconductor device 710 as a high-bandwidth memory (HBM). Furthermore, semiconductor device 735 can be used in integrated circuits such as CPUs, GPUs, or FPGAs (Field Programmable Gate Arrays).

[0552] The package substrate 732 can be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 can be, for example, a silicon interposer or a resin interposer.

[0553] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "redistribution board" or "intermediate board". In addition, through electrodes may be provided on the interposer 731, and these through electrodes may be used to electrically connect the integrated circuits and the package substrate 732. Furthermore, in silicon interposers, TSVs can also be used as through electrodes.

[0554] In HBMs, many connections are necessary to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted requires fine and high-density wiring. For this reason, it is preferable to use a silicon interposer for mounting the HBM.

[0555] Furthermore, in SiP and MCM using silicon interposers, reliability degradation due to differences in expansion coefficients between the integrated circuit and the interposer is less likely to occur. In addition, because silicon interposers have high surface flatness, connection failures between the integrated circuit and the silicon interposer are less likely to occur. In particular, in 2.5D packages (2.5-dimensional packaging) where multiple integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0556] On the other hand, when electrically connecting multiple integrated circuits with different terminal pitches using silicon interposers and TSVs, space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 730, the width of the terminal pitch becomes a problem, and it may become difficult to provide the many wires necessary to achieve a wide memory bandwidth. For this reason, as mentioned above, a monolithic stacked configuration using OS transistors is preferable. A composite structure combining a memory cell array stacked using TSVs and a monolithic stacked memory cell array may also be used.

[0557] Alternatively, a heat sink (heat dissipation plate) may be provided on top of the electronic component 730. If a heat sink is provided, it is preferable to align the heights of the integrated circuits provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the heights of the semiconductor device 710 and the semiconductor device 735.

[0558] To mount the electronic component 730 onto another substrate, electrodes 733 may be provided at the bottom of the package substrate 732. Figure 34B shows an example in which the electrodes 733 are formed with solder balls. By providing solder balls in a matrix at the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrodes 733 may be formed with conductive pins. By providing conductive pins in a matrix at the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0559] The electronic component 730 can be mounted on other boards using various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0560] [Large-scale computer] Figure 35A shows a perspective view of the large-scale computer 5600. The large-scale computer 5600 houses multiple rack-mount type computers 5620 in rack 5610. The large-scale computer 5600 may also be referred to as a supercomputer.

[0561] Figure 35B shows a perspective view of an example of a computer 5620. The computer 5620 has a motherboard 5630. The motherboard 5630 is provided with multiple slots 5631 and multiple connection terminals. A PC card 5621 is inserted into a slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0562] Figure 35C shows an example of a PC card 5621. The PC card 5621 is a processing board equipped with, for example, a CPU, GPU, and memory device. The PC card 5621 has a board 5622 and connectors 5623, 5624, 5625, electronic components 5626, 5627, 5628, and 5629 mounted on the board 5622. Note that Figure 35C shows components other than electronic components 5626, 5627, and 5628.

[0563] The connector 5629 has a shape that allows it to be inserted into the slot 5631 of the motherboard 5630, and functions as an interface for connecting the PC card 5621 and the motherboard 5630. Examples of standards for the connector 5629 include PCIe.

[0564] Terminals 5623, 5624, and 5625 can serve as interfaces for, for example, power supply and signal input to the PC card 5621. They can also serve as interfaces for, for example, outputting signals calculated by the PC card 5621. Examples of standards for terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). When outputting video signals from terminals 5623, 5624, and 5625, examples of standards include HDMI (registered trademark).

[0565] The electronic component 5626 has terminals (not shown) for inputting and outputting signals, and by inserting these terminals into a socket (not shown) on the board 5622, the electronic component 5626 and the board 5622 can be electrically connected.

[0566] Electronic components 5627 and 5628 have multiple terminals, and these terminals can be mounted to the wiring provided on board 5622 by, for example, reflow soldering. Examples of electronic component 5627 include FPGAs, GPUs, and CPUs. For example, electronic component 730 can be used as electronic component 5627. Examples of electronic component 5628 include memory devices. For example, electronic component 700 can be used as electronic component 5628.

[0567] The 5600 mainframe computer can also function as a parallel computer. By using the 5600 mainframe computer as a parallel computer, it is possible to perform large-scale calculations necessary for, for example, artificial intelligence training and inference.

[0568] This embodiment can be implemented in appropriate combination with other embodiments or examples described herein, at least in part.

[0569] (Embodiment 9) A semiconductor device according to one aspect of the present invention will be described. Figure 36A is a schematic perspective view of a semiconductor device 60 according to one aspect of the present invention. Figure 36B is a schematic perspective view of a part of the semiconductor device 60. Figure 37 is a schematic perspective view illustrating the configuration of the semiconductor device 60.

[0570] In Figures 36A, 36B, and 37, the semiconductor device 60 has an element layer 70 below an element layer 80 which includes a substrate 22 which is a semiconductor substrate, and a support substrate 40 above the element layer 80 via an insulating layer 41. The element layer 80 has a plurality of transistors 21 which constitute a functional circuit 11. The element layer 70 has a plurality of transistors 71 which constitute a switch circuit 15. The transistors 71 function as switches to control the conduction and non-conductivity between an external power supply line and a conductive layer 72 which functions as a power line.

[0571] The transistor exemplified in Embodiment 3 can be used for transistor 71.

[0572] The transistor 21 in the element layer 80 is formed on the front surface (also called the "first surface") of the substrate 22. The element layer 70 is formed on the back surface (the surface opposite to the front surface, also called the "second surface") of the substrate 22. Therefore, the transistor 71 in the element layer 70 is formed on the second surface of the substrate 22.

[0573] Figure 37 illustrates a functional circuit 11 consisting of a CPU 12, a GPU 13, and a memory 14.

[0574] Furthermore, the functional circuit 11 is not limited to the CPU 12, GPU 13, and memory 14, and one or more of these can be used. It is also possible to include circuits with other functions.

[0575] To improve the operating speed, mounting density, and power consumption of the semiconductor device 60, the functional circuit 11 requires miniaturization and thinning of transistors, wiring, etc., and reduction of the power supply potential. The switch circuit 15 can control the supply of voltage supplied from an external source to each circuit of the functional circuit 11, and to stop the supply. This makes it possible to stop the supply of power potential to circuits in standby mode, thereby reducing power consumption.

[0576] Furthermore, the transistors constituting the switch circuit 15 require high dielectric strength. One effective way to increase the dielectric strength of the transistors is to thicken the gate insulating film. Thus, transistors 21 and 71 require different performance characteristics. Therefore, different measures are needed to improve the characteristics of transistors 21 and 71.

[0577] Furthermore, miniaturization and thinning are required for the functional circuit 11. Therefore, if the switch circuit 15 is constructed using the same process node as the functional circuit 11, not only the routing wiring but also the wiring for supplying power (power lines) will become thinner, making it impossible to supply sufficient power to the functional circuit 11. In addition, if the wiring resistance increases due to miniaturization, voltage drop is likely to cause unevenness in the power supply potential within the functional circuit 11. To stably supply power to the functional circuit 11, it is preferable that the wiring constituting the switch circuit 15 has a lower wiring resistance than the wiring constituting the functional circuit 11. In particular, it is preferable that the wiring that functions as a power line has a lower wiring resistance than the wiring constituting the functional circuit 11. One means of reducing wiring resistance is to increase the cross-sectional area of ​​the conductive layer that functions as wiring. However, in order to increase the cross-sectional area of ​​the conductive layer, it is necessary to increase one or both of the width and height of the conductive layer. Thus, it is preferable to use different process nodes for the functional circuit 11 and the switch circuit 15.

[0578] In a semiconductor device 60 according to one aspect of the present invention, by providing the functional circuit 11 and the switch circuit 15 on different element layers, different improvement measures can be implemented in the functional circuit 11 and the switch circuit 15. Furthermore, the functional circuit 11 and the switch circuit 15 can be formed at different process nodes.

[0579] In one aspect of the present invention, a plurality of conductive layers 72 that function as power lines and a switch circuit 15 can be arranged below the functional circuit 11, thereby reducing the occupied area of ​​the semiconductor device 60. Furthermore, it is preferable that the element layer 70, which is superimposed on the element layer 80, is formed using thin-film formation techniques such as CVD or sputtering. Therefore, the transistor 71 included in the element layer 70 is preferably a thin-film transistor.

[0580] At least a portion of the multiple conductive layers 72 of the element layer 70 can function as power lines. Furthermore, if the element layer 70 has a clock signal generation circuit, at least a portion of the multiple conductive layers 72 can function as clock signal lines. It is also possible to supply either or both of the power supply and / or clock signal supplied from an external source to the functional circuit 11 of the element layer 80 via at least a portion of the multiple conductive layers 72.

[0581] For example, it is possible to manufacture a die (semiconductor chip) containing the functional circuit 11 and a die containing the switch circuit 15 separately, and then mechanically bond them together using 3D integration technology. However, with 3D integration technology, improving the alignment accuracy is difficult because the two are bonded together mechanically, and miniaturizing the bumps used to connect them is also difficult, making it difficult to narrow the pitch of the connection points. As a result, there was a challenge in shortening the wiring distance required to supply power to the necessary parts of the functional circuit 11.

[0582] According to one aspect of the present invention, an element layer 70 including a switch circuit 15 is formed on the back side of the substrate 22 using thin-film formation technology, photolithography technology, or the like. Therefore, the semiconductor device 60 according to one aspect of the present invention is a monolithically stacked semiconductor device.

[0583] By forming the element layer 70 using thin-film formation technology, high-precision alignment at the photolithography level can be achieved. Furthermore, conductive layers that function as power lines can be connected to the necessary locations of the functional circuit 11 over extremely short distances. Therefore, the necessary voltage of power can be supplied to the necessary locations of the functional circuit 11. In addition, in the semiconductor device 60 according to one aspect of the present invention, since the connection distance between the switch circuit 15 and the functional circuit 11 is short, power loss related to power transmission is reduced, and power consumption can be reduced.

[0584] This embodiment can be implemented in appropriate combination with other embodiments or examples described herein, at least in part.

[0585] In this example, the relationship between indium oxide crystallization and hydrogen concentration is explained using calculations. Classical molecular dynamics methods were used for these calculations.

[0586] First, Model A was prepared, consisting of single-crystal indium oxide. Model A is a supercell in which the lattice constants of the a-axis, b-axis, and c-axis are tripled, 1x, and tripled, respectively, compared to a unit cell of bixbyte-type indium oxide (ICSD (Inorganic Crystal Structure Database) col.code.14387). Model A contains 288 indium atoms and 432 oxygen atoms. Figure 38A shows Model A viewed from the b-axis direction, and Figure 38B shows Model A viewed from a direction approximately perpendicular to the a-axis. The dashed line in Figure 38A corresponds to the unit cell, and inside this dashed line are 32 indium atoms and 48 oxygen atoms.

[0587] Next, hydrogen atoms were randomly placed in Model A. Specifically, hydrogen atoms were placed outside the dashed line shown in Figure 38A, and at a distance of 0.08 nm or more from the indium and oxygen atoms. By varying the number of hydrogen atoms placed, Models A0 to A10 were created. Table 2 shows the number of atoms (composition) and hydrogen concentration contained in each of Models A0 to A10. Models C0 to C10 shown in Table 2 will be described later.

[0588]

[0589] Next, calculations to relax the positions of hydrogen atoms (hereinafter referred to as the first calculation) were performed for each of models A0 to A10. The conditions for the first calculation are shown in Table 3.

[0590]

[0591] In this example, the open-source software LAMMPS was used. The potential model used was orb-d3-v2, a type of pre-trained model. The time step was set to 0.5 fs.

[0592] The first calculation was performed with the positions of the indium and oxygen atoms fixed, using an ensemble of NVT and a temperature of 10K. The total calculation time was 5 ps.

[0593] Next, for each of models A0 to A10 after the first calculation, a calculation to optimize the cell size (hereinafter referred to as the second calculation) was performed. The conditions for the second calculation can be found in Table 3. The second calculation was performed with the coordinates of atoms located inside the dashed line shown in Figure 38A fixed, with the ensemble set to NPT and the temperature to 10K. The total calculation time was 10 ps.

[0594] Next, using the cell sizes of models A0 to A10 obtained in the second calculation, models corresponding to model A were created for each hydrogen concentration. Specifically, model B0 was created by applying the cell size of model A0 obtained in the second calculation to model A. Models B1 to B10 were created in a similar manner. In each of models B0 to B10, the indium atoms and oxygen atoms refer to the internal coordinates (fractional coordinates) of model A; therefore, each of models B0 to B10 is referred to here as a perfect crystal.

[0595] Next, hydrogen atoms were randomly placed in models B1 to B10. The hydrogen atoms were placed using the method described above. Models C0 to C10 were created by varying the number of hydrogen atoms placed in each model. Specifically, the number of atoms in models C0 to C10 was arranged to match the number of atoms in models A0 to A10. Table 2 shows the number of atoms (composition) and hydrogen concentration in each of models C0 to C10.

[0596] Next, for each of models C0 to C10, a calculation was performed to amorphousize the model and then crystallize it (hereinafter referred to as the third calculation). The conditions for the third calculation can be found in Table 3. The third calculation was performed by fixing the coordinates of atoms located inside the dashed line shown in Figure 38A, setting the ensemble to NVT, and varying the temperature as shown in Figure 38C. The total calculation time was 310 ps. After the third calculation, model C0 is shown in Figure 39A, model C1 in Figure 39B, model C2 in Figure 39C, model C3 in Figure 39D, model C4 in Figure 39E, model C5 in Figure 39F, model C6 in Figure 40A, model C7 in Figure 40B, model C8 in Figure 40C, model C9 in Figure 40D, and model C10 in Figure 40E.

[0597] Next, the similarity between a model containing hydrogen atoms and a perfect crystal (in this case, a model without hydrogen atoms) was calculated. Specifically, the similarity of model C0 was calculated using model C0 and model B0 after the third calculation. In addition, the similarity of model C1 was calculated using the model obtained by removing hydrogen atoms from model C1 after the third calculation and model B1. The method for calculating the similarity of models C2 to C10 can be found by referring to the method for calculating the similarity of model C1. SOAP (Smooth Overlap of Atomic Positions) from the Python library DScribe was used to calculate the similarity. The sigma was set to 0.5 in the similarity calculation. The similarity is expressed as a value from 0.0 to 1.0, with a similarity of 1.0 being used when the same model is used. In this calculation, the closer the similarity is to 1.0, the closer the model is to a crystal.

[0598] The process from the first calculation to calculating the similarity was performed independently twice. In other words, the number of n was 2. The calculated similarity is shown in Figure 41. In Figure 41, the horizontal axis represents hydrogen concentration [atomic %], and the vertical axis represents the similarity to the perfect crystal.

[0599] Figure 41 shows that the similarity of hydrogen-containing indium oxide is lower than that of hydrogen-free indium oxide. Therefore, it is suggested that the presence of hydrogen in indium oxide suppresses crystal growth. Furthermore, Figure 41 shows that the similarity tends to decrease as the hydrogen concentration increases. For example, the similarity of models with a hydrogen concentration greater than 2.7 atomic percent (models C3 to C10) was less than 0.98. Therefore, it is suggested that the higher the hydrogen concentration in the material, the more the crystal growth in indium oxide is suppressed. To suppress crystal growth in indium oxide, it is suggested that it is preferable to increase the hydrogen concentration in the material to more than 2.7 atomic percent, for example, to 3 atomic percent or more.

[0600] Furthermore, in models C6 to C10, the hydrogen concentration in the non-crystallized regions (regions with low similarity) was approximately 20 atomic percent in all cases. From this, it is estimated that the upper limit of hydrogen concentration in indium oxide is approximately 20 atomic percent. Therefore, it is suggested that the hydrogen concentration in indium oxide should be at least less than 20 atomic percent, preferably 15 atomic percent or less, and more preferably 10 atomic percent or less.

[0601] ADDR: signal, BL: wiring, BLB: wiring, BW: signal, CE: signal, CLK: signal, CSEL: signal, EQ: signal, EQB: signal, GV: gate valve, GW: signal, PL: wiring, RDA: signal, SA_OUT: wiring, SA_OUTB: wiring, SAN: wiring, SAP: wiring, VPRE: intermediate potential, WAKE: signal, WDA: signal, WL: wiring, 10: circuit board, 11: functional circuit, 12: CPU, 13: GPU, 14: memory, 15: switch circuit, 20: insulating layer, 21: transistor, 22: circuit board, 30: metal oxide layer, 30_1: metal oxide layer, 30 _2: Metal oxide layer, 30_3: Metal oxide layer, 31: Seed layer, 31f: Oxide layer, 40: Support substrate, 41: Insulating layer, 60: Semiconductor device, 70: Element layer, 71: Transistor, 72: Conductive layer, 80: Element layer, 110B: Light-emitting element, 110G: Light-emitting element, 110R: Light-emitting element, 111: Pixel electrode, 111B: Pixel electrode, 111G: Pixel electrode, 111R: Pixel electrode, 112B: Organic layer, 112G: Organic layer, 112R: Organic layer, 113: Common electrode, 114: Common layer, 121: Protective layer, 125: Insulating layer, 126: Resin layer, 128: Layer, 130a: Semiconductor layer, 13 0b: Semiconductor layer, 130c: Semiconductor layer, 131a: Conductive layer, 131b: Conductive layer, 150: Substrate, 151: Insulating layer, 170: Substrate, 171: Adhesive layer, 200: Transistor, 200a: Transistor, 200b: Transistor, 200c: Transistor, 200d: Transistor, 200s: Transistor, 201: Insulating layer, 201_1: Insulating layer, 201_2: Insulating layer, 201_3: Insulating layer, 202: Insulating layer, 203: Insulating layer, 205: Conductive layer, 210: Substrate, 211: Insulating layer, 212: Insulating layer, 230: Semiconductor layer, 230_1: Semiconductor layer, 230_2: Semiconductor layer, 230_3: Semiconductor layer, 230a: Semiconductor layer, 230b: Semiconductor layer, 230c: Semiconductor layer, 230n: Region, 231: Seed layer, 241a: Insulating layer, 241b: Insulating layer, 242a: Conductive layer, 242b: Conductive layer, 243a: Conductive layer, 243b: Conductive layer, 245: Conductive layer, 246: Conductive layer, 250: Insulating layer, 250_1: Insulating layer, 250_2: Insulating layer, 250_3: Insulating layer, 250s: Insulating layer, 255: Insulating layer, 260: Conductive layer, 260a: Conductive layer, 260b: Conductive layer, 260s: Conductive layer, 271a: Insulating layer, 271b: Insulating layer, 275: Insulating layer,280: insulating layer, 281: insulating layer, 282: insulating layer, 283: insulating layer, 284: insulating layer, 285: insulating layer, 286: insulating layer, 286s: insulating layer, 287: insulating layer, 288: insulating layer, 289: insulating layer, 290o: opening, 290s: opening, 301: substrate, 310: transistor, 311: conductive layer, 312: low resistance region, 313: insulating layer, 314: insulating layer, 315: element isolation layer, 316: wiring layer, 320: transistor, 350: insulating layer, 351: semiconductor layer, 352: insulating layer, 353: insulating layer, 354: conductive layer, 355: conductive layer, 356: insulating layer, 357: conductive Electrode layer, 358: Insulating layer, 359: Insulating layer, 420: Layer, 422: Peripheral circuit, 430: Element layer, 432: Memory cell, 437: Transistor, 438: Capacitive element, 440: Drive circuit, 442: Row decoder, 443: Row driver, 444: Column decoder, 445: Column driver, 446: Sense amplifier, 447: Input circuit, 448: Output circuit, 470: Layer, 471: PSW, 472: PSW, 473: Control circuit, 474: Voltage generation circuit, 480: Memory device, 482: Switch circuit, 482_1: N-type transistor, 482_2: N-type transistor, 483: Precharge circuit, 483_1: N-type transistor, 483_3: N-type transistor, 484: Precharge circuit, 484_1: P-type transistor, 484_3: P-type transistor, 485: Amplifier circuit, 485_1: P-type transistor, 485_2: P-type transistor, 485_3: N-type transistor, 485_4: N-type transistor, 500A: Display device, 540: Capacitive element, 541: Conductive layer, 543: Insulating layer, 545: Conductive layer, 554: Insulating layer, 555a: Insulating layer, 555b: Insulating layer, 555c: Insulating layer, 556: Plug, 564: Insulating layer, 574: P Lug, 574a: conductive layer, 574b: conductive layer, 580: display module, 581: display unit, 582: circuit unit, 583: pixel circuit unit, 583a: pixel circuit, 584: pixel unit, 584a: pixel, 585: terminal unit, 586: wiring unit, 590: FPC, 591: substrate, 592: substrate, 600: manufacturing equipment, 601: atmospheric substrate supply chamber, 602: atmospheric substrate transport chamber, 603a: load lock chamber, 603b: unload lock chamber, 604: transport chamber, 606a: chamber, 606b: chamber, 606c: chamber, 606d: chamber, 607: cassette port,608: Alignment port, 609a: Transport robot, 609b: Transport robot, 621: Gas supply source, 622: Valve, 623: High-frequency generator, 624: Waveguide, 625: Mode converter, 626: Gas tube, 627: Waveguide, 628: Slot antenna plate, 629: Dielectric plate, 630: High-density plasma, 631: Substrate, 632: Substrate holder, 633: Heating mechanism, 635: Matching box, 636: High-frequency power supply, 637: Vacuum pump, 638: Valve, 639: Exhaust port, 640: Lamp, 641: Gas supply source, 642: Valve, 643: Gas inlet, 6 44: Substrate, 645: Substrate holder, 646: Heating mechanism, 648: Vacuum pump, 649: Valve, 650: Exhaust port, 660: Microwave plasma processing device, 661: Quartz tube, 662: Substrate holder, 663: Heating means, 700: Electronic component, 700A: Electronic equipment, 700B: Electronic equipment, 702: Printed circuit board, 704: Mounted board, 710: Semiconductor device, 711: Mold, 712: Land, 713: Electrode pad, 714: Wire, 715: Drive circuit layer, 716: Memory layer, 721: Housing, 723: Mounting part, 727: Earphone part, 730: Electronic component, 731: Inter Poser, 732: Package substrate, 733: Electrode, 735: Semiconductor device, 750: Earphone, 751: Display panel, 753: Optical component, 756: Display area, 757: Frame, 758: Nose pad, 800A: Electronic device, 800B: Electronic device, 820: Display unit, 821: Housing, 822: Communication unit, 823: Mounting unit, 824: Control unit, 825: Imaging unit, 827: Earphone unit, 832: Lens, 5600: Large computer, 5610: Rack, 5620: Computer, 5621: PC card, 5622: Board, 5623: Connection terminal, 5624: Connection terminal, 5625: Connection terminal Child, 5626: Electronic component, 5627: Electronic component, 5628: Electronic component, 5629: Connection terminal, 5630: Motherboard, 5631: Slot, 6500: Electronic device, 6501: Enclosure, 6502: Display unit, 6503: Power button, 6504: Button, 6505: Speaker, 6506: Microphone, 6507: Camera, 6508: Light source, 6509: Control device, 6510: Protective component, 6511: Display panel, 6512: Optical component, 6513: Touch sensor panel, 6515: FPC, 6516: IC, 6517: Printed circuit board, 6518: Battery, 7000: Display unit,7100: Television equipment, 7101: Enclosure, 7103: Stand, 7111: Remote control unit, 7200: Notebook computer, 7211: Enclosure, 7212: Keyboard, 7213: Pointing device, 7214: External connection port, 7216: Control unit, 7300: Digital signage, 7301: Enclosure, 7303: Speaker, 7311: Information terminal, 7400: Digital signage, 7401: Pillar, 7411: Information Terminal, 9000: Housing, 9001: Display unit, 9002: Camera, 9003: Speaker, 9005: Operation keys, 9006: Connection terminal, 9007: Sensor, 9008: Microphone, 9050: Icon, 9051: Information, 9052: Information, 9053: Information, 9054: Information, 9055: Hinge, 9101: Personal Information Terminal, 9102: Personal Information Terminal, 9103: Tablet terminal, 9200: Personal Information Terminal, 9201: Personal Information Terminal,

Claims

1. A method for forming a metal oxide layer, comprising: a first step of forming a seed layer on an insulating layer; a second step of forming a metal oxide layer containing indium on the seed layer; and a third step of performing microwave plasma treatment on the metal oxide layer so that the hydrogen concentration increases from the upper surface to the lower surface.

2. A method for forming a metal oxide layer, comprising: a first step of forming a seed layer on an insulating layer; a second step of forming a metal oxide layer on the seed layer; and a third step of performing microwave plasma processing, wherein in the second step, a first metal oxide layer, a second metal oxide layer, and a third metal oxide layer, each containing indium, are stacked in this order to form the metal oxide layer, and the microwave plasma processing is performed such that the hydrogen concentration of the third metal oxide layer is lower than the hydrogen concentration of the first metal oxide layer.

3. A method for forming a metal oxide layer, wherein, in the microwave plasma treatment according to claim 1 or claim 2, hydrogen gas, oxygen gas, and argon gas are introduced.

4. A method for forming a metal oxide layer according to claim 1 or claim 2, wherein the insulating layer is provided on a substrate, and the temperature of the substrate during the microwave plasma treatment is 150°C or more and 180°C or less.

5. A method for forming a metal oxide layer according to claim 1 or claim 2, wherein in the second step, the metal oxide layer is formed on the insulating layer, covering the seed layer, and in the third step, first crystal growth occurs in the region of the metal oxide layer that does not overlap with the seed layer, from the upper surface to the lower surface of the metal oxide layer.

6. A method for forming a metal oxide layer according to claim 5, wherein in the third step, a second crystal growth occurs in the region of the metal oxide layer that overlaps with the seed layer, from the lower surface to the upper surface of the metal oxide layer.

7. A method for forming a metal oxide layer according to claim 6, wherein the seed layer has a hexagonal or trigonal crystal structure, and the metal oxide layer has a bixbite-type crystal structure.

8. A method for forming a metal oxide layer according to claim 7, wherein the upper surface of the seed layer is a {001} plane.

9. A method for forming a metal oxide layer according to claim 8, wherein the first crystal growth direction and the second crystal growth direction each coincide with the <001> orientation of the seed layer.

10. A method for forming a metal oxide layer according to claim 9, wherein the seed layer comprises indium, gallium, zinc, and oxygen.

11. A method for forming a metal oxide layer, wherein the seed layer and the metal oxide layer each have a bixbite-type crystal structure, according to claim 6.

12. A method for forming a metal oxide layer according to claim 11, wherein the upper surface of the seed layer is a {111} plane.

13. A method for forming a metal oxide layer according to claim 12, wherein the first crystal growth direction and the second crystal growth direction each coincide with the <111> orientation of the seed layer.

14. A metal oxide layer containing indium, wherein the metal oxide layer has a concentration gradient in which the hydrogen concentration increases from the top surface to the bottom surface, the metal oxide layer has crystal grains having a bixbite crystal structure, and the top surface of the crystal grains is a {111} plane.

15. A metal oxide layer comprising a first metal oxide layer, a second metal oxide layer on the first metal oxide layer, and a third metal oxide layer on the second metal oxide layer, wherein each of the first to third metal oxide layers contains indium, the third metal oxide layer has a region with a lower hydrogen concentration than the first metal oxide layer, the metal oxide layer has crystal grains having a bixbite crystal structure, and the upper surface of the crystal grains is a {111} plane.

16. The metal oxide layer according to claim 15, wherein the crystal grains include a part of the first metal oxide layer, a part of the second metal oxide layer, and a part of the third metal oxide layer.

17. A semiconductor device comprising a metal oxide layer according to any one of claims 14 to 16, a conductive layer, and an insulating layer having a portion located between the metal oxide layer and the conductive layer.

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