Semiconductor device

Abstract

Provided is a semiconductor device that can be miniaturized. Provided is a semiconductor device that occupies a small area. A semiconductor device according to the present invention comprises a first transistor and a second transistor that are stacked. The first transistor and the second transistor each have a plurality of stacked semiconductor layers, a source electrode and a drain electrode, a gate insulation layer, and a gate electrode. The gate electrode is provided so as to surround respective upper surfaces, lower surfaces, and side surfaces of the semiconductor layers, and the gate insulation layer is positioned therebetween. At the first transistor, the source electrode and the drain electrode are provided so as to contact the side surfaces of the semiconductor layers. At the second transistor, the source electrode and the drain electrode are provided so as to contact the upper surfaces, the lower surfaces, and the side surfaces of the semiconductor layers. The first transistor is a p-channel transistor, and the second transistor is a n-channel transistor that includes an oxide semiconductor.

Description

Semiconductor equipment

[0001] One aspect of the present invention relates to a semiconductor device. Another aspect of the present invention relates to a transistor.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. Examples of technical fields of one aspect of the present invention disclosed herein include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, methods for driving them, or methods for manufacturing them. A semiconductor device refers to any device that can function by utilizing semiconductor properties.

[0003] In recent years, the development of semiconductor devices has progressed, and CPUs, memory, or other LSIs are mainly used in semiconductor devices. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and memory) formed on chips by processing semiconductor wafers, and electrodes which are connection terminals.

[0004] CPUs, memory, or other LSI semiconductor circuits (IC chips) are mounted on circuit boards, such as printed circuit boards, and used as components in various electronic devices.

[0005] Furthermore, the technology of constructing transistors using semiconductor thin films formed on substrates with insulating surfaces is attracting attention. These transistors are widely applied in integrated circuits and electronic devices such as image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors are attracting attention as other materials.

[0006] Furthermore, transistors using oxide semiconductors are known to have extremely low leakage current in the non-conductive state. For example, Patent Document 1 discloses a low-power CPU that takes advantage of this low leakage current characteristic. Also, for example, Patent Document 2 discloses a memory device that can retain its contents for a long period of time.

[0007] Japanese Patent Publication No. 2012-257187 Japanese Patent Publication No. 2011-151383

[0008] One aspect of the present invention aims to provide a semiconductor device that can be miniaturized. Alternatively, it aims to provide a semiconductor device with a small footprint. Alternatively, it aims to provide a semiconductor device suitable for high integration. Alternatively, it aims to provide a semiconductor device with low power consumption. Alternatively, it aims to provide a semiconductor device with low leakage current. Alternatively, it aims to provide a semiconductor device with good electrical characteristics. Alternatively, it aims to provide a highly reliable semiconductor device.

[0009] One aspect of the present invention aims to provide a semiconductor device, computing device, memory device, or electronic device having a novel configuration. Another aspect of the present invention aims to mitigate at least one of the problems of the prior art.

[0010] Furthermore, the description of these problems does not preclude the existence of other problems. Moreover, one aspect of the present invention does not need to solve all of these problems. Other problems can be identified from the description in the specification, drawings, claims, etc.

[0011] One aspect of the present invention is a semiconductor device having a first transistor and a second transistor on the first transistor. The first transistor includes a first semiconductor layer, a second semiconductor layer on the first semiconductor layer, a first conductive layer, a second conductive layer, a first insulating layer, and a third conductive layer. The second transistor includes a third semiconductor layer, a fourth semiconductor layer on the third semiconductor layer, a first insulating layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer. The first conductive layer and the second conductive layer are separated from each other and are in contact with the side surfaces of the first semiconductor layer and the second semiconductor layer, respectively. The fourth conductive layer and the fifth conductive layer are separated from each other and are in contact with the upper surface, lower surface, and side surfaces of the third semiconductor layer and the upper surface, lower surface, and side surfaces of the fourth semiconductor layer, respectively. The third conductive layer has portions located below the first semiconductor layer, between the first semiconductor layer and the second semiconductor layer, between the second semiconductor layer and the third semiconductor layer, between the third semiconductor layer and the fourth semiconductor layer, and above the fourth semiconductor layer, respectively. The first insulating layer has portions located between the first semiconductor layer and the third conductive layer, between the second semiconductor layer and the third conductive layer, between the third semiconductor layer and the third conductive layer, and between the fourth semiconductor layer and the third conductive layer, respectively. The first transistor is a p-channel transistor, and the second transistor is an n-channel transistor. Also, the third semiconductor layer and the fourth semiconductor layer each contain a metal oxide.

[0012] Also, in the above, it is preferable to have a second insulating layer between the first semiconductor layer and the second semiconductor layer and between the first insulating layer and the first conductive layer. Further, it is preferable to have a third insulating layer on the second semiconductor layer and between the first insulating layer and the first conductive layer.

[0013] Also, in the above, it is preferable that the first insulating layer and the third conductive layer are in contact with each other between the third semiconductor layer and the fourth semiconductor layer.

[0014] Alternatively, in the above, it is preferable to have a fourth insulating layer between the third semiconductor layer and the fourth semiconductor layer and between the first insulating layer and the third conductive layer.

[0015] Also, in the above, it is preferable to further include the first to third plugs. At this time, it is preferable that the first plug is in contact with the first conductive layer, the second plug is in contact with the fourth conductive layer, and the third plug is in contact with each of the second conductive layer and the fifth conductive layer. At this time, it is preferable that the third plug is in contact with the upper surface of the second conductive layer and the side surface of the fifth conductive layer, respectively.

[0016] Also, in the above, it is preferable that the first semiconductor layer and the second semiconductor layer contain silicon, and the third semiconductor layer and the fourth semiconductor layer contain indium. Further, it is preferable that the fourth conductive layer and the fifth conductive layer contain indium.

[0017] According to one aspect of the present invention, a semiconductor device capable of miniaturization can be provided. Or, a semiconductor device with a small occupied area can be provided. Or, a semiconductor device suitable for high integration can be provided. Or, a semiconductor device with low power consumption can be provided. Or, a semiconductor device with a small leakage current can be provided. Or, a semiconductor device with good electrical characteristics can be provided. Or, a highly reliable semiconductor device can be provided.

[0018] According to one aspect of the present invention, a semiconductor device, an arithmetic device, a storage device, or an electronic device having a novel configuration can be provided. According to one aspect of the present invention, at least one of the problems of the prior art can be at least reduced.

[0019] Note that the description of these effects does not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have to have all of these effects. Note that other effects can be extracted from the descriptions in the specification, drawings, claims, etc.

[0020] Figures 1A and 1B illustrate an example of the configuration of a semiconductor device. Figures 2A and 2B illustrate an example of the configuration of a semiconductor device. Figure 3 illustrates an example of the configuration of a semiconductor device. Figure 4 illustrates an example of the configuration of a semiconductor device. Figure 5 illustrates an example of the configuration of a semiconductor device. Figure 6 illustrates an example of the configuration of a semiconductor device. Figures 7A and 7B illustrate an example of the configuration of a semiconductor device. Figures 8A, 8B, and 8C illustrate an example of a method for manufacturing a semiconductor device. Figures 9A, 9B, and 9C illustrate an example of a method for manufacturing a semiconductor device. Figures 10A, 10B, and 10C illustrate an example of a method for manufacturing a semiconductor device. Figures 11A and 11B illustrate an example of a method for manufacturing a semiconductor device. Figures 12A and 12B illustrate an example of a method for manufacturing a semiconductor device. Figures 13A and 13B illustrate an example of a method for manufacturing a semiconductor device. Figures 14A and 14B illustrate an example of a method for manufacturing a semiconductor device. Figure 15A is an equivalent circuit diagram of a logic circuit. Figure 15B is a diagram showing the circuit symbol of a logic circuit. Figure 15C is a timing chart illustrating the operation of a logic circuit. Figures 16A and 16D are equivalent circuit diagrams of logic circuits. Figures 16B, 16C, 16E, and 16F are diagrams showing the circuit symbols of logic circuits. Figure 17A is a diagram showing the circuit symbol of a buffer circuit. Figure 17B is a diagram showing an example configuration of a buffer circuit. Figure 17C is a timing chart illustrating the operation of a buffer circuit. Figure 17D is a diagram showing an example configuration of a ring oscillator. Figure 17E is a diagram illustrating the oscillation of a ring oscillator. Figure 18A is an equivalent circuit diagram of a DFF circuit. Figure 18B is a diagram showing the circuit symbol of a DFF circuit. Figure 19A is a diagram illustrating an example configuration of a shift register circuit. Figure 19B is a timing chart illustrating the operation of a shift register circuit. Figure 20 is a block diagram illustrating an example configuration of a semiconductor device. Figures 21A, 21B, 21C, 21D, 21E, 21F, 21G, and 21H illustrate examples of memory cell circuit configurations. Figures 22A and 22B show examples of electronic components. Figures 23A, 23B, and 23C show examples of large-scale computers. Figure 23D shows an example of space equipment.Figure 23E shows an example of a storage system applicable to a data center.

[0021] The embodiments will be described below with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different ways, and their form and details can be modified in various ways without departing from the spirit and scope thereof. Accordingly, the present invention shall not be construed as being limited to the contents of the following embodiments.

[0022] In the invention described below, the same reference numerals are used in common across different drawings for identical parts or parts having similar functions, and repeated explanations are omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used, and reference numerals may not be assigned.

[0023] In the figures described herein, the size of each component, the thickness of the layers, or the area may be exaggerated for clarity. Therefore, the scale is not necessarily limited to those figures.

[0024] Furthermore, ordinal numbers such as "the first," "the second," etc., used in this specification are added to avoid confusion of constituent elements and do not imply any numerical limitation.

[0025] A transistor is a type of semiconductor device that can perform functions such as amplifying current or voltage, and switching operations that control conduction or non-conductivity. Transistors as used herein include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs).

[0026] Furthermore, the functions of "source" and "drain" may be reversed when transistors with different polarities are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" may be used interchangeably.

[0027] Furthermore, in this specification, either the source or the drain of a transistor may be referred to as the "first electrode," and the other of the source or drain may be referred to as the "second electrode." The gate may also be referred to as the "gate" or "gate electrode."

[0028] In this specification, "approximately matching top surface shapes" means that at least a portion of the contours overlap between stacked layers. For example, this includes cases where the upper and lower layers are processed with the same mask pattern, or partially with the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer; in these cases, it may also be said that the "top surface shapes are approximately matching."

[0029] In this specification, the top surface shape of a component refers to the contour shape of that component in a plan view. A plan view refers to a view from the direction normal to the surface on which the component is formed, or to the surface of the support (e.g., substrate) on which the component is formed.

[0030] In the following, expressions indicating direction, such as "up" and "down," will generally be used in accordance with the orientation shown in the drawings. However, for the purpose of simplifying explanations, the direction referred to as "up" or "down" in the specification may not always coincide with that of the drawings. For example, when explaining the stacking order (or formation order) of a laminate, even if the side on which the laminate is provided (the surface to be formed, the support surface, the adhesive surface, the flat surface, etc.) is located above the laminate in the drawing, the side to be formed may be described as "down," and the direction opposite to the surface to be formed may be described as "up."

[0031] In this specification, the channel length direction of a transistor refers to one of the directions parallel to the straight line connecting the source region and the drain region by the shortest distance. In other words, the channel length direction corresponds to one of the directions of current flowing through the semiconductor layer when the transistor is in the ON state. The channel width direction refers to the direction perpendicular to the channel length direction. Depending on the structure or shape of the transistor, the channel length direction and channel width direction may not be uniquely determined.

[0032] Furthermore, in this specification, the terms "film" and "layer" are interchangeable. For example, the term "insulating layer" may be interchangeable with the term "insulating film."

[0033] Furthermore, unless otherwise specified in this specification, off-current refers to the drain current when the transistor is in the off state (also called the non-conducting state or cutoff state). Unless otherwise specified, the off state refers to the state in an n-channel transistor where the voltage Vgs between the gate and source is lower than the threshold voltage Vth (in a p-channel transistor, it is higher than Vth).

[0034] In this specification, space groups are expressed using international notation (or Hermann-Mauguin notation) in short notation. Crystal planes and crystal orientations are expressed using Miller indices. In crystallography, space groups, crystal planes, and crystal orientations are expressed by superscripting numbers, but in this specification, due to formatting constraints, a minus sign (-) may be placed before the number instead of a superscript. Individual orientations within a crystal are represented by [ ], collective orientations representing all equivalent orientations are represented by < >, individual crystal planes are represented by ( ), and collective planes with equivalent symmetry are represented by {}.

[0035] In this specification, two lines are described as parallel if they are positioned at an angle of -10 degrees or more and 10 degrees or less. Two lines are described as roughly parallel if they are positioned at an angle of -30 degrees or more and 30 degrees or less (including parallel). Two lines are described as perpendicular if they are positioned at an angle of 80 degrees or more and 100 degrees or less. Two lines are described as roughly perpendicular if they are positioned at an angle of 60 degrees or more and 120 degrees or less (including perpendicular).

[0036] In this specification, two surfaces are described as parallel if their interior angle is between -10 degrees and 10 degrees. Two surfaces are described as approximately parallel if their interior angle is between -30 degrees and 30 degrees (including parallel). Two surfaces are described as perpendicular if their interior angle is between 80 degrees and 100 degrees. Two surfaces are described as approximately perpendicular if their interior angle is between 60 degrees and 120 degrees (including perpendicular).

[0037] (Embodiment 1) This embodiment describes an example of the configuration of a semiconductor device according to one aspect of the present invention, and an example of a method for manufacturing the same.

[0038] One aspect of the present invention is a semiconductor device comprising two types of transistors. One transistor (also called the first transistor) is a p-channel type transistor, and the other transistor (also called the second transistor) is an n-channel type transistor. By having a p-channel type first transistor and an n-channel type second transistor, a semiconductor chip can be realized that includes various logic circuits, functional circuits, memory circuits, or drive circuits, including so-called CMOS (Complementary Metal Oxide Semiconductor) circuits.

[0039] The first transistor and the second transistor each have a sheet-like semiconductor layer, a gate electrode provided so as to surround the top, side, and bottom surfaces of the semiconductor layer, a gate insulating layer located between the semiconductor layer and the gate electrode, and a source electrode and a drain electrode in contact with the semiconductor layer, respectively. Since the gate electrodes of the first and second transistors are provided so as to surround the semiconductor layer, they can also be called GAA (Gate All Around) structure transistors.

[0040] The semiconductor layer of the first transistor (also called the first semiconductor layer) is preferably made of a semiconductor material such as silicon, germanium, or silicon-germanium. The first semiconductor layer is preferably made of single-crystal or polycrystalline silicon or silicon-germanium. In addition, oxide semiconductors such as tellurium oxide, which are p-type semiconductors, or compound semiconductors can be used.

[0041] It is preferable to use a metal oxide (also called an oxide semiconductor) that exhibits semiconductor properties for the semiconductor layer of the second transistor (also called the second semiconductor layer). This makes it possible to realize a semiconductor circuit that combines low power consumption and high-speed operation. In particular, it is preferable to use single-crystal or polycrystalline indium oxide as the second semiconductor layer. In addition, an oxide semiconductor such as In-Ga-Zn oxide (IGZO) may be used as the semiconductor applied to the second transistor. Transistors with an oxide semiconductor applied to the semiconductor layer can have a significantly lower off-current than silicon, so by applying them to CMOS circuits, etc., it is possible to dramatically reduce standby power consumption. In particular, indium oxide has a higher hole mobility compared to oxide semiconductors such as IGZO, and can realize transistors with high on-current, making it suitable for CMOS circuits, etc.

[0042] In addition, metal oxides that can be used for the second semiconductor layer include tin oxide, zinc oxide, indium tin oxide, indium titanium oxide, indium gallium oxide, indium tungsten oxide, indium zinc oxide, indium gallium aluminum oxide, indium gallium tin oxide, gallium zinc oxide, aluminum zinc oxide, indium aluminum zinc oxide, indium tin zinc oxide, indium titanium zinc oxide, indium gallium zinc oxide, indium gallium tin zinc oxide, and indium gallium aluminum zinc oxide. Alternatively, silicon-containing indium tin oxide, gallium tin oxide, aluminum tin oxide, etc., can also be used. When using these, it is preferable that the film has at least crystalline properties, and more preferably that it has a single-crystal structure.

[0043] It is preferable to stack the first and second transistors. By stacking the first and second transistors, the occupied area of ​​the semiconductor device can be reduced, enabling high circuit integration.

[0044] In this case, it is preferable to place the second transistor on top of the first transistor. For example, if silicon or silicon-germanium is used for the first transistor and indium oxide is used for the second transistor, the temperature required for the manufacturing process (e.g., the temperature required for crystallization of the semiconductor layer) may be higher for the first transistor. On the other hand, oxide semiconductors such as indium oxide can develop oxygen vacancies when exposed to extremely high temperatures, which can adversely affect their electrical properties and reliability. Therefore, by placing the first transistor, which requires processing at higher temperatures, below the second transistor, a highly reliable semiconductor device can be realized.

[0045] Furthermore, since the semiconductor device according to one aspect of the present invention has a configuration in which a first p-channel transistor and a second n-channel transistor are stacked three-dimensionally and integrated, it can also be called a CFET (Complementary Field Effect Transistor).

[0046] Preferably, the first transistor has a plurality of first semiconductor layers stacked on top of each other. Furthermore, preferably, the second transistor has a plurality of second semiconductor layers stacked on top of each other. This increases the current that each transistor can carry. In this case, among the plurality of semiconductor layers that each transistor has, a stacked structure is provided between two adjacent semiconductor layers in which a gate insulating layer, a gate electrode, and a gate insulating layer are stacked in this order. In the first and second transistors, a plurality of such stacked structures of gate insulating layers and gate electrodes are stacked with each semiconductor layer in between.

[0047] Furthermore, in the second transistor, the source electrode and drain electrode can be provided so as to be in contact with at least the side surface of the second semiconductor layer. In particular, it is preferable that they be in contact with the top, side, and bottom surfaces of the second semiconductor layer. On the other hand, in the first transistor, the source electrode and drain electrode can be configured to be in contact with at least the side surface of the first semiconductor layer. When an oxide semiconductor is used as the second semiconductor layer, the contact resistance between the source electrode and drain electrode and the second semiconductor layer may be greater compared to when silicon or the like is used. Therefore, by making the contact area between the second semiconductor layer and the source electrode and drain electrode larger than the contact area between the first semiconductor layer and the source electrode and drain electrode, the contact resistance can be reduced even when an oxide semiconductor is used as the second semiconductor layer.

[0048] Below, we will explain more specific configuration examples with reference to the diagrams.

[0049] [Configuration Example] Figure 1A is a schematic top view of the semiconductor device 10. Figure 1B shows a cross-sectional view to the left of the dashed line corresponding to the cutting line A-B in Figure 1A, and a cross-sectional view to the right of the dashed line corresponding to the cutting line C-D. In Figure 1B, the area to the left of the dashed line corresponds to the cross-section in the channel length direction, and the area to the right corresponds to the cross-section in the channel width direction.

[0050] Figure 2A shows a schematic perspective view of the semiconductor device. Figure 2B shows a schematic perspective view including the cross-section of Figure 1B. In Figures 2A and 2B, for clarity, some insulating layers (such as insulating layer 51) are made transparent, and only their outlines are shown with dashed lines.

[0051] The semiconductor device 10 is provided on an insulating layer 11 on a substrate (not shown) and has a configuration in which a transistor 20 and a transistor 30 are stacked on top of it. The gate electrodes of transistors 20 and 30 are common. In addition, one of the source electrode and drain electrode of transistor 20 is connected to one of the source electrode and drain electrode of transistor 30. When transistor 20 is a p-channel transistor and transistor 30 is an n-channel transistor, an inverter circuit is formed by transistors 20 and 30.

[0052] The transistor 20 has a plurality of semiconductor layers 21 (semiconductor layers 21a to 21d), an insulating layer 22, a conductive layer 23, a conductive layer 24, and a conductive layer 25. A portion of the insulating layer 22 functions as the gate insulating layer of the transistor 20, and a portion of the conductive layer 23 functions as the gate electrode of the transistor 20. The conductive layer 24 functions as one of the source electrode and drain electrode of the transistor 20, and the conductive layer 25 functions as the other.

[0053] The transistor 30 has a plurality of semiconductor layers 31 (semiconductor layers 31a to 31d), an insulating layer 22, a conductive layer 23, a conductive layer 34, and a conductive layer 35. Another portion of the insulating layer 22 functions as the gate insulating layer of the transistor 30, and another portion of the conductive layer 23 functions as the gate electrode of the transistor 30. The conductive layer 34 functions as one of the source electrode and drain electrode of the transistor 30, and the conductive layer 35 functions as the other.

[0054] In this embodiment, when describing matters common to components distinguished by letters or numbers attached to their reference numerals (such as semiconductor layer 21a and semiconductor layer 21b), the reference numerals (such as semiconductor layer 21) may be used without further explanation.

[0055] The insulating layer 11 functions as an underlayment insulating layer. Alternatively, the transistor 20 may be formed directly on the substrate without providing the insulating layer 11.

[0056] On the insulating layer 11, semiconductor layers 21a, 21b, 21c, and 21d are stacked in this order, spaced apart from each other and overlapping each other. Above semiconductor layer 21d, semiconductor layers 31a, 31b, 31c, and 31d are stacked in this order, spaced apart from each other and overlapping each other. Preferably, each semiconductor layer 21 and each semiconductor layer 31 are arranged to overlap each other. This allows for a larger effective channel width compared to the case where each transistor has one semiconductor layer, enabling the realization of transistors with a large on-current. Furthermore, stacking each semiconductor layer 21 in the height direction reduces the occupied area compared to the case where they are arranged side by side in the horizontal direction. Moreover, stacking each semiconductor layer 21 and each semiconductor layer 31 further significantly reduces the occupied area. This makes it possible to provide a semiconductor device suitable for high integration.

[0057] Furthermore, so-called Fin-type transistors are known as a technique for increasing the effective channel width. Fin-type transistors can increase the effective channel width by increasing the height of the Fin-shaped semiconductor layer. The effective channel width can be further increased by providing multiple Fin-shaped semiconductor layers in a single transistor, and the effective channel width can be discretely increased by increasing the number of Fin-shaped semiconductor layers. However, this increases the space between the Fin-shaped semiconductor layers, thus increasing the occupied area. In contrast, in one embodiment of the present invention, the effective channel width can be increased by stacking sheet-like semiconductor layers in the height direction and increasing the size of the semiconductor layer in the channel width direction. Moreover, when increasing the effective channel width, the space between semiconductor layers that was necessary in Fin-type transistors is not required, so unlike Fin-type transistors, it is possible to increase the channel width continuously. Therefore, in one embodiment of the present invention, a semiconductor device with high on-current can be realized without increasing the occupied area.

[0058] Here, an example is shown with four semiconductor layers 21 and four semiconductor layers 31, but each can be one, two, three, or five or more. The more semiconductor layers 21 there are, the greater the current that the transistor 20 can supply. The same applies to the semiconductor layers 31.

[0059] The conductive layer 23 has portions located below the semiconductor layer 21a (between the insulating layer 11 and the semiconductor layer 21a), between the semiconductor layer 21a and the semiconductor layer 21b, between the semiconductor layer 21b and the semiconductor layer 21c, between the semiconductor layer 21c and the semiconductor layer 21d, and above the semiconductor layer 21d (between the semiconductor layer 21d and the semiconductor layer 31a). The conductive layer 23 also has portions located between the semiconductor layer 31a and the semiconductor layer 31b, between the semiconductor layer 31b and the semiconductor layer 31c, between the semiconductor layer 31c and the semiconductor layer 31d, and above the semiconductor layer 31d.

[0060] Furthermore, the insulating layer 22 has portions located between each semiconductor layer 21 and each semiconductor layer 31 and the conductive layer 23. As shown on the right side of Figure 1B, the conductive layer 23 is provided so as to surround the semiconductor layers 21 and 31 via the insulating layer 22. With this configuration, the gate electric field can be applied uniformly to the semiconductor layer 21 or the semiconductor layer 31, thereby improving the gate controllability of transistors 20 and 30, increasing the on-current, and further reducing the off-current. As a result, a high-performance semiconductor device with low power consumption can be realized.

[0061] Alternatively, instead of the insulating layer 22, the gate insulating layers for transistors 20 and 30 may be made differently. For example, transistors 20 and 30 may use insulating layers with different materials and / or thicknesses as their respective gate insulating layers.

[0062] The conductive layer 24 and the conductive layer 25 are provided on the insulating layer 11. The conductive layer 24 is provided in contact with one of a pair of sides of the semiconductor layer 21 that intersect the channel length direction. The conductive layer 25 is provided in contact with the other side. Note that if the same material (e.g., silicon) is used for both the semiconductor layer 21 and the conductive layer 24 (or conductive layer 25), it may be difficult to observe their boundary.

[0063] Between two adjacent semiconductor layers 21, an insulating layer 41 is provided between the side surface of the insulating layer 22 intersecting the channel length direction and the side surface of the conductive layer 24, functioning as a spacer. Similarly, an insulating layer 41 is also provided between the insulating layer 22 and the conductive layer 25. By providing the insulating layer 41, parasitic capacitance between the conductive layer 23 and the conductive layer 24, and between the conductive layer 23 and the conductive layer 25 can be reduced, thereby enabling a semiconductor device 10 capable of high-speed operation.

[0064] The insulating layer 41 is also provided below the semiconductor layer 21a and above the semiconductor layer 21d. Furthermore, an insulating layer 42 is provided on the uppermost insulating layer 41. The insulating layer 42 functions as a mask when processing the insulating layer 41 and also functions as a spacer to reduce parasitic capacitance, similar to the insulating layer 41.

[0065] The transistor 20 is preferably a p-channel transistor. The semiconductor layer 21 is preferably made of an inorganic material that can be a p-type semiconductor, such as silicon or silicon germanium. In particular, the semiconductor layer 21 is preferably made of single crystal or polycrystalline silicon or silicon germanium. In addition, other semiconductor materials that can be p-type semiconductors, such as oxide semiconductors, compound semiconductors, or organic semiconductors, can be used. For example, as an oxide semiconductor, an oxide containing one or more metal elements from Ni, Cu, Nd, Sr, La, Te, and Sn can be used. ２ , WSe ２ MoS ２ MoSe ２ Transition metal dichalcogenides such as those mentioned above can be used. Below, we will describe the case in which silicon is used as the semiconductor layer 21.

[0066] The conductive layer 24 and conductive layer 25 preferably contain silicon or silicon germanium to which p-type conductivity has been imparted. Elements from Group 13 of the periodic table, such as boron, aluminum, and gallium, can be used as the elements to impart p-type conductivity. However, this is not limited to cases where a semiconductor material other than silicon or silicon germanium is used for the semiconductor layer 21; conductive materials suitable for the semiconductor material used in the semiconductor layer 21 can be selected and used for the conductive layer 24 and conductive layer 25 from metals, alloys, conductive oxides, conductive nitrides, etc.

[0067] The transistor 20 can also be an n-channel transistor. In this case, the conductive layer 24 and the conductive layer 25 can be made of silicon or silicon germanium to which n-type conductivity has been imparted. As elements to impart n-type conductivity, elements of Group 15 of the periodic table, such as phosphorus and arsenic, can be used.

[0068] Here, we show an example in which conductive layers 24 and 25 are formed by epitaxial growth from the side surface of semiconductor layer 21. In this case, the ends of conductive layers 24 and 25 opposite to semiconductor layer 21 may have specific crystal planes (e.g., (100) plane, (110) plane, (111) plane, etc.) exposed, and may have an uneven shape as shown in Figure 1B.

[0069] An insulating layer 51 is provided covering the conductive layer 24 and the conductive layer 25, and an insulating layer 52 is provided on the insulating layer 51. The insulating layer 51 and the insulating layer 52 function as interlayer insulating films. Preferably, the insulating layer 51 and the insulating layer 52 have one or more of the following: silicon oxide, silicon oxynitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and silicon oxide with vacancies. Silicon oxide and silicon oxynitride are preferred because they are thermally stable. TEOS (Tetra-Ethyl-Ortho-Silicate, chemical formula: Si(OC) ２ H ５ ) ４ A silicon oxide film formed by plasma CVD using ) may also be used.

[0070] When silicon is used for the semiconductor layer 21 of transistor 20, reliability can be improved by terminating the dangling bond with hydrogen. On the other hand, if hydrogen diffuses into the semiconductor layer 31 of transistor 30, carriers are generated, and there is a risk that the channel formation region of the semiconductor layer 31 will become n-type. For this reason, it is preferable to use a film that has barrier properties against hydrogen and oxygen for the insulating layer 52. This prevents hydrogen from diffusing into the semiconductor layer 31 from below the insulating layer 52, thus preventing the semiconductor layer 31 from becoming n-type. Furthermore, oxygen contained in the semiconductor layer 31 and its vicinity diffuses below the insulating layer 52, preventing oxygen vacancies from occurring in the semiconductor layer 31.

[0071] It is preferable to use a silicon nitride film, silicon oxide nitride film, aluminum oxide film, magnesium oxide film, hafnium oxide film, gallium oxide film, etc., as the insulating layer 52.

[0072] In this specification, the term "oxide-nitride" refers to a material in which the oxygen atom content is greater than the nitrogen atom content, and the term "nitride oxide" refers to a material in which the nitrogen atom content is greater than the oxygen atom content. For example, when "silicon oxynitride" is written, it refers to a material in which the oxygen atom content is greater than the nitrogen atom content, and when "silicon nitride oxide" is written, it refers to a material in which the nitrogen atom content is greater than the oxygen atom content.

[0073] Each semiconductor layer 31 is provided on the insulating layer 52. A conductive layer 34 and a conductive layer 35 are also provided on the insulating layer 52.

[0074] In a cross-section along the channel length, the conductive layer 34 and the conductive layer 35 are provided so as to be in contact with the upper surface, lower surface, and side surface of the semiconductor layer 31, respectively. This increases the contact area between the semiconductor layer 31 and the conductive layer 34 or conductive layer 35, reduces the contact resistance between them, and increases the on-current of the transistor 30.

[0075] An insulating layer 43 is provided on the conductive layer 34 and the conductive layer 35, respectively. The insulating layer 43 functions as a mask when processing the semiconductor layer 31. The insulating layer 43 may be removed if it is not needed.

[0076] The transistor 30 is preferably an n-channel type transistor. The semiconductor layer 31 is preferably made of an inorganic material that can be an n-type semiconductor, and is particularly preferably made of a metal oxide (oxide semiconductor) that exhibits semiconductor properties. This makes it possible to realize a semiconductor circuit that combines low power consumption and high-speed operation.

[0077] In particular, it is preferable to use single-crystal or polycrystalline indium oxide as the semiconductor layer 31. The semiconductor layer 31 may also contain other elements (e.g., tungsten, gallium, germanium, etc.) as long as the crystal structure of indium oxide is maintained. Alternatively, an oxide semiconductor such as In-Ga-Zn oxide (IGZO) may be used as the semiconductor layer 31. Transistors using an oxide semiconductor as the semiconductor layer can have significantly lower off-currents than silicon transistors, and by applying them to CMOS circuits, etc., it is possible to dramatically reduce standby power consumption. In particular, indium oxide has a higher Hall effect mobility compared to oxide semiconductors such as IGZO, enabling the realization of transistors with high on-currents, making it suitable for CMOS circuits and the like.

[0078] Furthermore, it is preferable that the conductive layer 34 and conductive layer 35 contain a metal oxide containing the same metal element as the semiconductor layer 31. In particular, it is preferable that both the conductive layer 34 and conductive layer 35 and the semiconductor layer 31 contain a metal oxide containing indium. This reduces the contact resistance between the semiconductor layer 31 and the conductive layer 34 or conductive layer 35. It is preferable to use a metal oxide containing indium and tin for the conductive layer 34 and conductive layer 35 in particular, as this can enhance conductivity. Note that the conductive material is not limited to a metal oxide as long as it can be electrically connected to the semiconductor layer 31. For example, a conductive material suitable for the semiconductor layer 31 can be selected and used, such as a metal, alloy, or nitride conductive material.

[0079] An insulating layer 53 is provided covering the conductive layer 34, conductive layer 35, insulating layer 43, etc. The insulating layer 53 functions as an interlayer insulating layer. Refer to the description of insulating layer 51, etc. for details on the insulating layer 53.

[0080] The insulating layer 53 is provided with slits (grooves) into which the conductive layer 23 and the insulating layer 22 are embedded. These slits extend in the direction of the channel width.

[0081] The insulating layer 22 is in contact with the insulating layer 53, the conductive layer 34, the conductive layer 35, the insulating layer 43, each semiconductor layer 31, the insulating layer 52, the insulating layer 42, the insulating layer 41, each semiconductor layer 21, and the insulating layer 11, and is provided between these and the conductive layer 23.

[0082] An insulating layer 54 is provided in contact with the upper surfaces of the insulating layer 53, the insulating layer 22, and the conductive layer 23. The insulating layer 54 functions as an interlayer insulating layer. The insulating layer 54 may also function as a protective layer to prevent hydrogen from diffusing from the outside. The description of insulating layer 54 can be found in reference to the description of insulating layer 51 or insulating layer 52.

[0083] Openings reaching the conductive layer 25 are provided in insulating layer 54, insulating layer 53, insulating layer 52, and insulating layer 51, and plugs 61 are provided to fill these openings. Openings reaching the conductive layer 35 and insulating layer 52 are also provided in insulating layer 54 and insulating layer 53, and plugs 62 are provided to fill these openings. Openings reaching the conductive layer 34 and conductive layer 24 are also provided in insulating layer 54, insulating layer 53, insulating layer 52, and insulating layer 51, and plugs 63 are provided to fill these openings. Plugs 61 are connected to the conductive layer 25, plugs 62 are connected to the conductive layer 35, and plugs 63 are connected to the conductive layer 34 and conductive layer 24.

[0084] Since the semiconductor device 10 has transistors 20 and 30 stacked on top of each other, the occupied area can be significantly reduced compared to a configuration in which these are provided separately. Furthermore, the gate, source, and drain of transistors 20 and 30 can be connected via wiring and plugs provided above or below transistor 30. Figure 1B shows an example of an inverter circuit configured with transistors 20 and 30, but various circuits can be configured by changing the wiring connections.

[0085] [Modified Versions] The following describes examples with some configuration differences from the above example. Unless otherwise specified, parts that overlap with the above example will be referred to and explained in more detail below.

[0086] [Modification 1] Figure 3 shows a schematic cross-sectional view of the configuration illustrated below. For the top view, please refer to Figure 1A. The configuration shown in Figure 3 differs from the above configuration example mainly in that it has an insulating layer 44.

[0087] The insulating layer 44, like the insulating layer 41, functions as a spacer. The insulating layer 44 is provided between two adjacent semiconductor layers 31, specifically between the insulating layer 22 and the conductive layer 34, or between the insulating layer 22 and the conductive layer 35. It is also preferable that the insulating layer 44 be provided between the semiconductor layer 31a and the insulating layer 52, and on the semiconductor layer 31d.

[0088] The presence of the insulating layer 44 reduces parasitic capacitance between the conductive layer 23 and the conductive layer 34, and between the conductive layer 23 and the conductive layer 35, thereby enabling the realization of a semiconductor device capable of higher-speed operation.

[0089] [Modification 2] The configuration shown in Figure 4 differs from the above configuration example mainly in that it does not have insulating layers 41 and 42.

[0090] By omitting the insulating layers 41 and 42, the width of the transistor 20 in the channel length direction can be reduced, which may reduce the occupied area of ​​the semiconductor device. Furthermore, since the process of forming the insulating layers 41 and 42 can be omitted, manufacturing costs can be reduced.

[0091] [Modification 3] The configuration shown in Figure 5 differs from the above configuration example mainly in the shapes of the conductive layer 24 and conductive layer 25, and the shapes of the conductive layer 34 and conductive layer 35.

[0092] In Figure 1B, the plug 61 is in contact with the upper surface of the conductive layer 25, whereas in Figure 5, the plug 61 is in contact with the side surface of the conductive layer 25. This increases the contact area between the plug 61 and the conductive layer 25, thereby reducing the contact resistance between them. Furthermore, since the width of the conductive layer 25 and the conductive layer 24 in the channel length direction can be reduced, the occupied area of ​​the semiconductor device can be further reduced.

[0093] In Figure 1B, the conductive layers 34 and 35 protrude outward from the portion where the insulating layer 43 is provided, and the protruding portion contacts the plug 63 or plug 62. On the other hand, Figure 5 shows an example where there are no steps between the side surface of the insulating layer 43 and the side surface of the conductive layer 34, and between the side surface of the insulating layer 43 and the conductive layer 35, and the surfaces are generally flat. In Figure 5, the plugs 62 and 63 differ from Figure 1B in that they have portions that contact the upper surface and side surface of the insulating layer 43. This configuration makes it possible to reduce the width of the transistor 30 in the channel width direction.

[0094] [Modification 4] The configuration shown in Figure 6 differs from the above configuration example mainly in that it has a substrate 12 instead of an insulating layer 11.

[0095] A single-crystal semiconductor substrate can be used as the substrate 12. In particular, when silicon or silicon-germanium is used for the semiconductor layer 21, it is preferable to use a single-crystal silicon substrate for the substrate 12. By using a single-crystal substrate made of the same material as the semiconductor layer 21 for the substrate 12, a single-crystal semiconductor film formed by an epitaxial method using the substrate 12 as the base material can be used for the semiconductor layer 21. Therefore, a transistor 20 with extremely high electrical characteristics and reliability can be realized compared to cases where a polycrystalline film, microcrystalline film, or amorphous film is used.

[0096] A recess is formed in a part of the substrate 12, and an element isolation layer 13 is provided to fill the recess. The element isolation layer 13 contains an insulating inorganic material and is a layer for electrically isolating adjacent transistors. The semiconductor layer 21 is provided on the region of the substrate 12 where the element isolation layer 13 is not provided. The conductive layer 24 and the conductive layer 25 are provided on the element isolation layer 13.

[0097] For example, a single-crystal silicon-germanium film and a single-crystal silicon film can be alternately epitaxially grown on a surface of the substrate 12 where the element isolation layer 13 is not provided. Furthermore, by selectively etching the silicon-germanium film, multiple semiconductor layers 21 made of single-crystal silicon that overlap each other can be formed.

[0098] [Modification 5] The above example shows the case in which transistors 20 and 30 are stacked and used, but transistors 20 and 30 may be manufactured and used individually. Figures 7A and 7B show an example in which transistor 30 is formed on the insulating layer 11.

[0099] A conductive layer 34, a conductive layer 35, an insulating layer 22, a plug 62, a plug 63, and an insulating layer 53 are provided in contact with the upper surface of the insulating layer 11. The rest of the configuration is the same as that of the transistor 30 in Figure 1B. The transistor 30 is a transistor with a large on-current and a small footprint.

[0100] Furthermore, a film having the same hydrogen and oxygen barrier properties as the insulating layer 52 may be provided in contact with the upper surface of the insulating layer 11. Alternatively, the insulating layer 11 may use the film having said barrier properties. This prevents hydrogen from diffusing into each semiconductor layer 31 from the outside and prevents the semiconductor layer 31 from becoming n-type. In addition, it prevents oxygen from diffusing from each semiconductor layer 31 and its vicinity to the outside and prevents oxygen vacancies from occurring in the semiconductor layer 31.

[0101] [Example of Manufacturing Method] Below, an example of a method for manufacturing a semiconductor device according to one aspect of the present invention will be described. Here, a semiconductor device 10 having transistors 20 and 30 as exemplified in the above configuration example will be used as an example.

[0102] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed using methods such as sputtering, chemical vapor deposition (CVD), vacuum deposition, pulsed laser deposition (PLD), and atomic layer deposition (ALD).

[0103] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by methods such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife coating, slit coating, roll coating, curtain coating, and knife coating.

[0104] Sputtering methods include RF sputtering, which uses a high-frequency power supply for sputtering; DC sputtering, which uses a DC power supply; and pulsed DC sputtering, which changes the voltage applied to the electrodes in pulses. For film deposition using insulating targets, RF sputtering is preferable. DC sputtering is mainly used when depositing films using conductive targets. In addition to forming conductive films, DC sputtering can also be used to form insulating films by reactive sputtering using pulsed DC sputtering. Specifically, pulsed DC sputtering can be used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0105] CVD methods can be classified into plasma-enhanced CVD (PECVD), which utilizes plasma; thermal CVD (TCD), which utilizes heat; and photo-CVD (Photo-CVD), which utilizes light. Furthermore, depending on the source gas used, they can be divided into metal CVD (MCCVD) and metal-organic CVD (MOCVD) methods.

[0106] Plasma CVD allows for the production of high-quality films at relatively low temperatures. Thermal CVD, on the other hand, does not use plasma, thus minimizing plasma damage to the workpiece. Furthermore, thermal CVD avoids plasma damage during film formation, resulting in films with fewer defects.

[0107] As ALD methods, thermal ALD, which carries out the reaction of the precursor and reactant using only thermal energy, and PEALD, which uses plasma-excited reactants, can be used.

[0108] Unlike sputtering, CVD and ALD are film deposition methods that are less affected by the shape of the workpiece and provide good step-level coverage. In particular, the ALD method is suitable for coating the surface of openings with high aspect ratios due to its excellent step-level coverage and excellent thickness uniformity. However, since the ALD method has a relatively slow deposition rate, it is sometimes preferable to use it in combination with other film deposition methods that have a faster deposition rate, such as the CVD method.

[0109] In CVD (Chemical Vapor Deposition), films of any composition can be deposited by changing the flow rate ratio of the raw material gases. For example, in CVD, by changing the flow rate ratio of the raw material gases while the film is being deposited, films with continuously changing compositions can be deposited. When depositing films while changing the flow rate ratio of the raw material gases, the time required for film deposition can be shortened compared to depositing films using multiple deposition chambers, because time spent on transport or pressure adjustment is eliminated. Therefore, it may be possible to increase the productivity of semiconductor devices.

[0110] In the ALD method, films of any composition can be deposited by using multiple different types of precursors. Alternatively, when multiple different types of precursors are introduced, films of any composition can be deposited by controlling the number of cycles for each precursor. Furthermore, similar to the CVD method, films with continuously changing compositions can be deposited.

[0111] Furthermore, the thin films constituting the semiconductor device can be processed using photolithography or other methods. Alternatively, the thin films may be processed by nanoimprint lithography, sandblasting, lift-off methods, etc. Island-like thin films may also be directly formed using a deposition method with a shielding mask such as a metal mask. Induced self-assembly (DSA) methods may also be used.

[0112] There are two main methods of photolithography. One method involves forming a resist mask on the thin film to be processed, then processing the thin film by etching or other means, and removing the resist mask. The other method involves forming a photosensitive thin film, then exposing and developing it to process the thin film into the desired shape.

[0113] Another method, as an alternative, involves placing a hard mask between the resist mask and the workpiece. Furthermore, microfabrication techniques include multi-patterning technologies such as LELE (Litho-etch Litho-etch), SADP (Self-Aligned Double Patterning), and SAQP (Self-Aligned Quadrable Patterning).

[0114] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture thereof. Other light sources such as ultraviolet light, KrF laser light, or ArF laser light can also be used. Exposure may also be performed using immersion lithography. Furthermore, extreme ultraviolet (EUV) light or X-rays may be used as the light source for exposure. An electron beam can also be used instead of the light source for exposure. Using extreme ultraviolet light, X-rays, or an electron beam is preferable because it enables extremely fine processing. Note that a photomask is not required when exposure is performed by scanning a beam such as the above-mentioned light or an electron beam.

[0115] Thin films can be etched using methods such as dry etching, wet etching, and sandblasting. Dry etching allows for isotropic or anisotropic etching by controlling the conditions. Wet etching allows for isotropic etching.

[0116] Figures 8A to 14B correspond to Figure 1B, respectively, and are schematic cross-sectional views of each stage in the manufacturing process of the semiconductor device 10.

[0117] First, a substrate (not shown) is prepared, and an insulating layer 11 is formed on the substrate. Note that the insulating layer 11 may be omitted if it is not needed.

[0118] As the insulating layer 11, an inorganic insulating film such as a silicon oxide film or a silicon oxynitride film can be used. The insulating layer 11 can be formed using sputtering, CVD, MBE, PLD, ALD, etc. If the surface on which the insulating layer 11 is formed is not flat, a planarization treatment may be performed after the insulating layer 11 is formed so that the upper surface of the insulating layer 11 becomes flat.

[0119] Next, a sacrificial layer 71a is formed on the insulating layer 11, and a semiconductor film 21af is formed thereon. Preferably, the semiconductor film 21af is a film having a single-crystal structure or a polycrystalline structure.

[0120] Since the sacrificial layer 71a is a layer that will be removed later, it is preferable to use a material that allows for a large selectivity ratio between the semiconductor film 21af and the etching rate. For example, a silicon germanium film can be used for the sacrificial layer 71a and a silicon film can be used for the semiconductor film 21af. In addition, the material of the sacrificial layer 71a can be appropriately selected depending on the material of the semiconductor film 21af.

[0121] Furthermore, using a film having a single-crystal structure as the sacrificial layer 71a is preferable because it can enhance the crystallinity of the semiconductor film 21af formed thereon. For example, a single-crystal silicon film can be obtained by using a single-crystal silicon-germanium film as the sacrificial layer 71a and epitaxially growing a silicon film on it as the semiconductor film 21af. In particular, it is preferable to use a single-crystal insulating film that can serve as a base material for the epitaxial growth of the sacrificial layer 71a as the insulating layer 11, or to use a single-crystal silicon substrate or single-crystal film instead of the insulating layer 11, because this facilitates the single-crystallization of the sacrificial layer 71a. As a substrate having a single-crystal film, an SOI (Silicon on Insulator) substrate or the like can be used.

[0122] The sacrificial layer 71a and the semiconductor film 21af can be deposited using sputtering, CVD, MBE, PLD, ALD, or the like. The ALD or CVD method is particularly preferred.

[0123] Next, a sacrificial layer 71b, a semiconductor film 21bf, a sacrificial layer 71c, a semiconductor film 21cf, a sacrificial layer 71d, a semiconductor film 21df, and a sacrificial layer 71e are formed sequentially on the semiconductor film 21af. These can be formed by the same method as the semiconductor film 21af and the sacrificial layer 71a.

[0124] Next, a portion of the laminate of each semiconductor film 21f and each sacrificial layer 71 is removed by etching, thereby processing the laminate into a stripe-like (band-like) shape extending in the channel length direction (Figure 8A). It is preferable to use an anisotropic dry etching method for etching the laminate.

[0125] Next, a thin film is deposited to cover the laminate of each semiconductor film 21f and each sacrificial layer 71, forming a sacrificial layer 72. Unnecessary portions are removed by etching to form a strip-shaped sacrificial layer 72 that covers a portion of the laminate and extends in the channel width direction. The thin film can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. Since the sacrificial layer 72 will be removed later, it is preferable to use a material that allows for a large selectivity ratio of etching rate with each semiconductor layer 21 and insulating layer 11, etc. The conductivity of the sacrificial layer 72 is not limited; insulating material, semiconductor material, or conductive material may be used. For example, amorphous or polycrystalline silicon can be used as the sacrificial layer 72.

[0126] Next, an insulating film is formed covering the laminate of each semiconductor film and each sacrificial layer, and the sacrificial layer 72. Then, an anisotropic etching is performed to form an insulating layer 42 that is in contact with the side surface of the sacrificial layer 72 (Figure 8B). The insulating film that becomes the insulating layer 42 is preferably formed using a film formation method with high coverage, for example, by the ALD method or the CVD method.

[0127] Next, the laminate of each semiconductor film and each sacrificial layer is etched using the sacrificial layer 72 and the insulating layer 42 as masks (Figure 8C). This forms island-shaped sacrificial layers 71a, semiconductor layer 21a, sacrificial layer 71b, semiconductor layer 21b, sacrificial layer 71c, semiconductor layer 21c, sacrificial layer 71d, semiconductor layer 21d, and sacrificial layer 71e, respectively. It is preferable to use anisotropic dry etching. At this time, a portion of the exposed insulating layer 11 may be etched, which may form a protrusion in the portion in contact with the sacrificial layer 71a. In particular, when a semiconductor film or semiconductor substrate containing the same element as the sacrificial layer 71a (e.g., silicon) is used instead of the insulating layer 11, such protrusions are likely to form.

[0128] Next, isotropic etching is performed on the exposed sides of each sacrificial layer 71 (Figure 9A). This causes the sides of each sacrificial layer 71 to recede inward, forming protrusions on each semiconductor layer 21. The protrusions on the semiconductor layer 21 are the exposed portions of its top, bottom, and sides.

[0129] Next, an insulating film 41f is formed by covering the surfaces of the insulating layer 11, each sacrificial layer 71, each semiconductor layer 21, the sacrificial layer 72, and the insulating layer 42 (Figure 9B). It is preferable to use a film formation method that provides high coverage for the insulating film 41f, and it is particularly preferable to use the ALD method or the CVD method.

[0130] Next, the insulating film 41f is etched by anisotropic etching to form multiple insulating layers 41 (Figure 9C). Each insulating layer 41 is provided in a region that overlaps with an insulating layer 42, and is located between adjacent semiconductor layers 21, between semiconductor layer 21a and insulating layer 11, and between insulating layer 42 and semiconductor layer 21d. At this time, the insulating film 41f is separated into multiple parts by etching, and the side surfaces of each semiconductor layer 21 are exposed.

[0131] Next, conductive layers 24 and 25 are formed (Figure 10A). Conductive layers 24 and 25 can be formed by epitaxial growth from the exposed sides of each semiconductor layer 21. For example, silicon germanium containing an element that imparts p-type conductivity can be formed as conductive layers 24 and 25 by a film deposition method such as CVD. At this time, by growing the conductive layers 24 and 25 so that specific crystal planes are exposed, an uneven shape can be formed on the sides of conductive layers 24 and 25 as shown in Figure 10A, etc. Conductive layers 24 and 25 are formed in contact not only with the sides of the semiconductor layer 21, but also with the sides of the insulating layer 42, the sides of each insulating layer 41, and the upper surface of the insulating layer 11. Here, it is preferable to grow conductive layers 24 and 25 to the extent that they reach the region where the plug 61 will be formed later.

[0132] Next, an insulating film is formed by covering the conductive layer 24, the conductive layer 25, the insulating layer 42, and the sacrificial layer 72. Then, the upper part of the insulating film is planarized until the sacrificial layer 72 is exposed to form the insulating layer 51 (Figure 10B). The insulating layer 51 can be formed using sputtering, CVD, MBE, PLD, ALD, etc. CVD is particularly preferred. For the planarization process, chemical mechanical polishing (CMP) or etching can be used.

[0133] Next, an insulating layer 52 is formed on the insulating layer 51, insulating layer 42, and sacrificial layer 72. The insulating layer 52 can be formed using sputtering, CVD, MBE, PLD, ALD, or the like.

[0134] Next, a sacrificial layer 73a, a semiconductor film 31af, a sacrificial layer 73b, a semiconductor film 31bf, a sacrificial layer 73c, a semiconductor film 31cf, a sacrificial layer 73d, a semiconductor film 31df, and a sacrificial layer 73e are formed in order on the insulating layer 52 (Figure 10C).

[0135] First, a sacrificial layer 73a is formed on the insulating layer 52. It is preferable to use a material for the sacrificial layer 73a that has a high selectivity ratio for etching rate with respect to the semiconductor layer 31, insulating layer 41, conductive layer 24, and conductive layer 25, which are formed later. For example, the sacrificial layer 73a can be a film that differs from each of the semiconductor layer 31, insulating layer 41, conductive layer 24, and conductive layer 25 in at least one of its constituent elements, composition, density, or crystallinity. Various materials can be used for the sacrificial layer 73a, including metals, alloys, semiconductors, insulators, oxides, nitrides, fluorides, or organic materials.

[0136] For example, when a crystalline indium oxide film is used for the semiconductor layer 31, it is preferable to use an indium-gallium-zinc oxide (also called IGZO) film for the sacrificial layer 73a. In this case, since indium oxide has a property that makes it easier to crystallize compared to IGZO, it becomes easy to make it different not only in terms of constituent elements and composition but also in terms of crystallinity.

[0137] Furthermore, when an IGZO (CAAC-IGZO (CAAC: c-axis aligned crystal)) film having c-axis oriented crystalline regions is used as the sacrificial layer 73a, the orientation of the crystalline regions of the indium oxide film formed thereon can be controlled. More specifically, the indium oxide film formed on the CAAC-IGZO film tends to be oriented in the

[111] direction perpendicular to the surface on which it is formed. Therefore, a uniaxially oriented crystalline indium oxide film or an indium oxide film having a single-crystal structure can be obtained.

[0138] For the sacrificial layer 73a, various formation methods described above can be selected depending on the material used. In particular, when IGZO is used for the sacrificial layer 73a, it can be formed by sputtering or ALD. When a metal oxide film is used for the sacrificial layer 73a, refer to the description of the method for forming the semiconductor film that will become the semiconductor layer 31a, which will be explained later.

[0139] Here, when a metal oxide film is used for the sacrificial layer 73a, it is preferable that the film be crystalline. When an IGZO film is formed as the sacrificial layer 73a by sputtering, a film with higher crystallinity can be formed by increasing the proportion of oxygen gas in the deposition gas and increasing the substrate temperature during deposition. The film that becomes the sacrificial layer 73a is preferably formed to have a CAAC structure, a polycrystalline structure, a single-crystal structure, or a microcrystalline structure, and a CAAC structure is particularly preferred.

[0140] Next, a semiconductor film 31af is deposited on the sacrificial layer 73a.

[0141] As the semiconductor film 31af, a metal oxide (oxide semiconductor) film having semiconductor properties can be used. The metal oxide film can be deposited using sputtering, CVD, MBE, PLD, ALD, or other methods as appropriate.

[0142] The metal oxide film preferably has crystalline properties. In particular, the metal oxide film of one aspect of the present invention preferably has a metal oxide having a single-crystal structure, a polycrystalline structure, or a CAAC structure.

[0143] Furthermore, it is preferable to perform a treatment to enhance the crystallinity of the metal oxide film during or after its formation. Examples of treatments to enhance the crystallinity of the metal oxide film include heat treatment, plasma treatment, microwave (typically 2.45 GHz) treatment, microwave plasma treatment, and light (e.g., ultraviolet light) irradiation treatment. Multiple of these treatments may be performed simultaneously or sequentially. For example, heat treatment and microwave plasma treatment can be performed simultaneously. Alternatively, heat treatment can be performed first, followed by microwave plasma treatment.

[0144] Here, microwave treatment includes treatments in which microwaves themselves are applied to the film to be formed (in this case, a metal oxide film), microwave plasma treatment, and both. Microwave plasma treatment refers to a treatment in which ions, radicals, etc., excited by microwave plasma are applied to the film to be formed.

[0145] Furthermore, it is preferable to perform the process of increasing the crystallinity of the metal oxide film multiple times during the formation of the metal oxide film. For example, when forming a metal oxide film by the ALD method, it is preferable to perform microwave plasma treatment each time an atomic layer is formed. Alternatively, it is preferable to perform the crystallinity-enhancing treatment each time a metal oxide film of a predetermined thickness is formed, as this can increase productivity. Specifically, it is preferable to form a first metal oxide film of 1 nm to 10 nm thickness, perform a first microwave plasma treatment, and then form a second metal oxide film of 1 nm to 10 nm thickness and perform a second microwave plasma treatment.

[0146] There are no particular limitations on the method for forming the first and second metal oxide films; ALD (Advanced Laser Deposition) or sputtering can be used, respectively. Forming the first metal oxide film using the ALD method is particularly preferable because it prevents the mixing (also known as contamination) of elements from the layers constituting the surface to be formed into the first and second metal oxide films. This is especially preferable when the elements contained in the layers constituting the surface to be formed inhibit the crystallization of the metal oxide (for example, when silicon, carbon, etc. are included). Furthermore, the first and second metal oxide films may have different compositions. While a laminated structure of the first and second metal oxide films is illustrated here, the method is not limited to this. The same treatment can be applied to single-layer or multi-layered metal oxide films of three or more layers.

[0147] Furthermore, treatments to enhance the crystallinity of the metal oxide film may be performed after the metal oxide film has been formed. Specifically, this treatment may be performed directly on the metal oxide film after formation, or it may be performed via another film, such as an insulating film formed on the metal oxide film. For example, microwave plasma treatment may be performed after the metal oxide film has been formed, or an insulating film (e.g., silicon nitride film, silicon oxide film, aluminum oxide film, etc.) may be formed after the metal oxide film has been formed, and then heat treatment or microwave plasma treatment may be performed on the metal oxide film via the insulating film.

[0148] Furthermore, the above-mentioned treatment to enhance the crystallinity of the metal oxide film can also serve as a treatment to remove impurities contained in the metal oxide film. For example, impurities such as hydrogen contained in the metal oxide film can be suitably removed. Alternatively, by performing the treatment to enhance the crystallinity of the metal oxide film in an oxygen gas atmosphere, oxygen deficiencies in the metal oxide film can be reduced.

[0149] When performing a treatment to improve the crystallinity of a metal oxide film, it is preferable to set the heat treatment temperature (or substrate temperature) to room temperature (e.g., 25°C) or higher, 100°C to 700°C, 100°C to 600°C, or 300°C to 450°C.

[0150] By improving the crystallinity of metal oxide films, it is possible to realize transistors with good reliability.

[0151] Metal oxide films can be formed, for example, by a sputtering method using a metal oxide target.

[0152] It is preferable that the metal oxide film be a dense film with as few defects as possible. Furthermore, it is preferable that the metal oxide film be a high-purity film with impurities such as hydrogen and water reduced as much as possible. In particular, it is preferable to use a crystalline metal oxide film as the metal oxide film.

[0153] Furthermore, when forming a metal oxide film, oxygen gas may be mixed with an inert gas (for example, helium gas, argon gas, xenon gas, etc.). The higher the proportion of oxygen gas in the total deposition gas (hereinafter also referred to as the oxygen flow rate ratio) when forming the metal oxide film, the higher the crystallinity of the metal oxide film can be, resulting in a more reliable transistor. Conversely, a lower oxygen flow rate ratio results in lower crystallinity of the metal oxide film, allowing for a transistor with a higher on-current.

[0154] When forming a metal oxide film, higher substrate temperatures result in a more crystalline and dense metal oxide film. Conversely, lower substrate temperatures result in a less crystalline and more electrically conductive metal oxide film.

[0155] For metal oxide film formation, the substrate temperature should be between room temperature and 250°C, preferably between room temperature and 200°C, and more preferably between room temperature and 140°C. For example, setting the substrate temperature between room temperature and 140°C is preferable as it increases productivity. Furthermore, crystallinity can be reduced by forming the metal oxide film at room temperature or without intentional heating.

[0156] When using the ALD method, it is preferable to use a film deposition method such as the thermal ALD method or the PEALD (Plasma Enhanced ALD) method. The thermal ALD method is preferred because it exhibits extremely high step coverage. The PEALD method is also preferred because, in addition to exhibiting high step coverage, it allows for low-temperature film deposition.

[0157] For example, when a metal oxide is used for the semiconductor film 31f, the film can be formed by the ALD method using a precursor containing the constituent metal elements and an oxidizing agent.

[0158] For example, when depositing an indium oxide film, an indium-containing precursor can be used.

[0159] For example, when forming an In-Ga-Zn oxide film, three precursors, i.e., a precursor containing indium, a precursor containing gallium, and a precursor containing zinc, can be used. Alternatively, two precursors, i.e., a precursor containing indium and a precursor containing gallium and zinc, may be used.

[0160] As the precursor containing indium, trimethylindium, triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionato)indium, cyclopentadienylindium, indium(III) chloride, (3-(dimethylamino)propyl)dimethylindium, etc. can be used.

[0161] Also, as the precursor containing gallium, trimethylgallium, triethylgallium, tris(dimethylamide)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionato)gallium, dimethylchlorogallium, diethylchlorogallium, gallium(III) chloride, etc. can be used.

[0162] Also, as the precursor containing zinc, dimethylzinc, diethylzinc, bis(2,2,6,6-tetramethyl-3,5-heptanedionato)zinc, zinc chloride, etc. can be used.

[0163] As the oxidizing agent, for example, ozone (O ３ ), oxygen (O ２ ), water (H ２ O), nitrogen dioxide (NO ２ ), nitrous oxide (N ２ O), hydrogen peroxide (H ２ O ２ ), etc. can be used, and two or more of these may be used.

[0164] To reduce the hydrogen concentration and nitrogen concentration in the film, it is preferable to use O ２ or O ３ as the oxidizing agent, and particularly O ３It is more preferable to use [a specific type of oxidizing agent]. On the other hand, when forming single crystals or polycrystalline materials with large grain sizes, it is preferable to use an oxidizing agent containing hydrogen in order to suppress the formation of crystal nuclei in the initial stages of film formation. For example, H ２ O, or H ２ O ２ It is preferable to use this method. After forming a film with few crystal nuclei, crystal growth can be induced by the heat applied during film formation or by heat treatment after film formation, thereby forming a single crystal film or a polycrystalline film with a large grain size.

[0165] Methods for controlling the composition of the resulting film include adjusting the flow rate ratio of the source gases, the duration of the source gas flow, and the order in which the source gases are flowed. By adjusting these factors, it is also possible to deposit films with continuously changing compositions. Furthermore, it becomes possible to deposit two or more films with different compositions in succession.

[0166] It is preferable to perform a heat treatment after the formation of the metal oxide film. The heat treatment is preferably performed within a temperature range in which the metal oxide film does not undergo polycrystallization, and is preferably performed between 250°C and 650°C, more preferably between 400°C and 600°C. The heat treatment is performed in an inert gas atmosphere, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when performing the heat treatment in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas should be about 20%. The heat treatment may also be performed under reduced pressure. Nitrogen gas is an example of an inert gas. Alternatively, after heat treatment in an inert gas atmosphere, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the desorbed oxygen.

[0167] Furthermore, it is preferable that the gas used in the above heat treatment is highly purified. For example, the amount of water contained in the gas used in the above heat treatment should be 1 ppb (0.001 ppm) or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent as much as possible from the incorporation of water and other substances into the metal oxide film, etc.

[0168] In the following drawings, the semiconductor layer is shown as a single layer, but it may also be a multilayer structure. For example, it can be a two-layer structure formed by the ALD method, a three-layer structure formed by the ALD method, a two-layer structure in which the first layer is formed by the ALD method and the second layer by the sputtering method, or a three-layer structure in which the first layer is formed by the ALD method, the second layer by the sputtering method and the third layer by either the ALD method or the sputtering method. Forming the first layer by the ALD method is preferable because it can suppress mixing, but it is also possible to form the first layer by the sputtering method and the second layer by the ALD method. The semiconductor layer may also be a multilayer structure of four or more layers.

[0169] During the deposition of the semiconductor film 31af, the crystals present in the sacrificial layer 73a can be used as seed crystals to form a semiconductor film 31af having a single-crystal or polycrystalline structure. If the sacrificial layer 73a has uniaxial orientation, such as a CAAC structure, a semiconductor film 31af can be formed that reflects its crystal structure and has a crystal structure with specific orientations aligned. In particular, the ALD method is preferable because it makes it easier to form a highly crystalline semiconductor film 31af that reflects the crystal structure of the sacrificial layer 73a.

[0170] Alternatively, crystal growth may be induced by heat treatment after the deposition of the semiconductor film 31af, thereby forming a semiconductor film 31af having a single-crystal or polycrystalline structure. The heat treatment can be performed at, for example, 120°C to 300°C, preferably 120°C to 250°C, and more preferably 120°C to 200°C. In some cases, the heat treatment may be performed at a temperature exceeding 300°C (for example, higher than 300°C but 600°C or lower). The heat treatment may be performed after each semiconductor film layer is formed, after all semiconductor films have been formed, or thereafter. Furthermore, other processes involving substrate heating (such as the film deposition process) may be combined with the heat treatment.

[0171] Next, a sacrificial layer 73b, a semiconductor film 31bf, a sacrificial layer 73c, a semiconductor film 31cf, a sacrificial layer 73d, a semiconductor film 31df, and a sacrificial layer 73e are formed sequentially on the semiconductor film 31af. Each semiconductor film 31f and each sacrificial layer 73 can be formed in the same manner as the semiconductor film 31af and the sacrificial layer 73a, respectively.

[0172] When the semiconductor film 31af has a single-crystal or polycrystalline structure, the sacrificial layer 73b deposited on it can be a highly crystalline film that reflects the crystal structure of the semiconductor film 31af. In this case, the sacrificial layer 73b can be formed such that the crystal orientation of the crystals in the sacrificial layer 73b aligns with the crystal orientation of the semiconductor film 31af. By stacking each semiconductor film and each sacrificial layer in this manner, the semiconductor films 31af, 31bf, 31cf, and 31df can be made into films having a single-crystal or polycrystalline structure with aligned crystal orientations. This reduces variations in the characteristics of the transistor 30, and enables the manufacture of highly reliable semiconductor devices 10 with a high yield.

[0173] Next, an insulating layer 43 is formed on the sacrificial layer 73e, and the unnecessary portions of the insulating layer 43 are etched to create island-like structures. The insulating layer 43 is formed in a position that overlaps with at least the sacrificial layer 72. At this time, it is preferable that the insulating layer 43 is formed to be wider than the sacrificial layer 72 in the channel length direction. After that, using the insulating layer 43 as a mask, portions of each semiconductor film 31f and each sacrificial layer 73 that are not covered by the insulating layer 43 are removed by etching. This forms island-like sacrificial layers 73a to 73e and semiconductor layers 31a to 31d (Figure 11A).

[0174] The insulating layer 43 can be made of the same insulating material as the insulating layer 52 or insulating layer 51. Furthermore, the insulating layer 43 may be removed after the formation of the semiconductor layer 31a, etc.

[0175] Next, a film is formed to cover the insulating layer 52, sacrificial layers 73a to 73e, semiconductor layers 31a to 31d, and insulating layer 43, forming a sacrificial layer 74. Unnecessary portions are then removed by etching to form the sacrificial layer 74 (Figure 11B). The same material as that used for the sacrificial layer 72 can be used for the sacrificial layer 74. The sacrificial layer 74 can be formed in the region where the conductive layer 23 will later be embedded. Here, an example is shown in which the width of the sacrificial layer 74 is greater than the width of the sacrificial layer 72 in the cross-section in the channel length direction, but it may also be formed to be the same as or smaller than the width of the sacrificial layer 72.

[0176] Next, isotropic etching is performed on the sacrificial layers 73a to 73e to recede the sides in the channel length direction (Figure 12A). As a result, the semiconductor layers 31a to 31d have their top, bottom, and sides exposed at their ends in the channel length direction, respectively. At this time, in the channel width direction, the sides of the sacrificial layers 73a to 73e are covered by the sacrificial layer 74 and are therefore not etched. Here, since the loss of even one of the sacrificial layers 73a to 73e would result in a defect, it is preferable to perform the processing under conditions with the slowest possible etching rate. It is preferable that the sacrificial layers 73a to 73e are processed such that, for example, the width in the channel length direction after processing remains at least 50%, preferably at least 60%, of the original width.

[0177] Next, a conductive film 34f, which will later become the conductive layer 34 and the conductive layer 35, is formed (Figure 12B). The conductive film 34f is preferably formed by a film deposition method that provides as much coverage as possible, and is particularly preferably formed by the ALD method. The conductive film 34f is formed in contact with the side surfaces of each sacrificial layer 73, and the exposed upper, lower, and side surfaces of each semiconductor layer 31.

[0178] Next, the conductive film 34f is subjected to anisotropic etching to expose the insulating layer 52, the sacrificial layer 74, and the insulating layer 43. This etching divides the conductive film 34f, forming a pair of conductive layers 34 and 35 (Figure 13A). Preferably, the conductive layers 34 and 35 are processed so that they have portions located outside the region that overlaps with the insulating layer 43 or the sacrificial layer 74.

[0179] Next, after forming the insulating layer 53, the insulating layer 53 is planarized until the upper surface of the sacrificial layer 74 is exposed. The insulating layer 53 can be made of the same insulating material as the insulating layer 51. After that, the sacrificial layer 74 is removed (Figure 13B). By removing the sacrificial layer 74, the sides of each semiconductor layer 31 and each sacrificial layer 73 are exposed in the channel width direction.

[0180] Next, each sacrificial layer 73, insulating layer 52, sacrificial layer 72, and each sacrificial layer 71 are removed by etching (Figure 14A). At this time, the portion of the insulating layer 52 that is covered by the insulating layer 53, conductive layer 34, or conductive layer 35 remains. As a result, the top, bottom, and side surfaces of each semiconductor layer 31, the side surfaces of the conductive layer 34, the side surfaces of the conductive layer 35, the side surfaces of the insulating layer 52, the side surfaces of each insulating layer 41, the top, bottom, and side surfaces of each semiconductor layer 21, and the top surface of the insulating layer 11 are exposed.

[0181] Next, an insulating layer 22 is formed. The insulating layer 22 is preferably formed by a film formation method that provides as much coverage as possible, and is particularly preferably formed by the ALD method. The insulating layer 22 is formed in contact with the exposed surface described above.

[0182] Next, a conductive film to become the conductive layer 23 is formed, and the conductive layer 23 is formed by planarizing the film until the upper surface of the insulating layer 53 is exposed (Figure 14B). The conductive film to become the conductive layer 23 is preferably formed using a highly embedding film deposition method such as CVD. This makes it possible to form the conductive layer 23 so as to surround each semiconductor layer 31 and each semiconductor layer 21.

[0183] At this stage, transistors 20 and 30 can be formed.

[0184] Next, an insulating layer 54 is formed on the insulating layer 53 and the conductive layer 23. The insulating layer 54 can be formed in the same way as the insulating layer 52 or the insulating layer 51.

[0185] Next, openings reaching the conductive layer 25 and openings reaching the conductive layer 34 and conductive layer 24 are formed in the insulating layer 54, insulating layer 53, insulating layer 52, and insulating layer 51, respectively. After forming a conductive film to fill these openings, the material is planarized until the upper surface of the insulating layer 54 is exposed, thereby forming plugs 61 and 63. After forming openings reaching the conductive layer 35 and insulating layer 52, plug 62 is formed in the same manner as described above (see Figure 1B). In this way, it is preferable to form plugs 61 and 63 in the same process, and plug 62 in a separate process. By following these steps, the semiconductor device 10 can be manufactured.

[0186] The above is an explanation of an example of the manufacturing method.

[0187] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0188] (Embodiment 2) This embodiment describes an indium oxide film that can be used in the semiconductor layer of a transistor in a semiconductor device according to one aspect of the present invention.

[0189] In this specification, indium oxide having at least a crystalline portion or crystalline region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystal IO or crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0190] Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0191] This paper describes the carrier concentration dependence of the hole mobility of indium oxide, silicon, and IGZO.

[0192] IGZO tends to exhibit higher hole mobility as the carrier concentration increases. On the other hand, single-crystal indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases. This trend is similar to that of silicon, where lower dopant (impurity) concentrations in the material reduce impurity scattering and increase hole mobility. In other words, the higher the purity and intrinsic nature of single-crystal indium oxide, the higher its hole mobility. From these results, it can be said that single-crystal indium oxide, unlike IGZO, is a material with physical properties similar to silicon. Note that when indium oxide is not single-crystal (e.g., polycrystalline), the trend may differ from that of single crystals.

[0193] The range of carrier concentrations suitable for the channel formation region of a transistor is 1 × 10⁻⁶. １５ cm −３ This range includes, for example, 1 × 10 １４ cm −３ The above is 1 x 10 １８ cm −３ The range is as follows: By sufficiently reducing the carrier concentration, the hole mobility value can be increased to 270 cm⁻¹. ２ It can be expected to be raised to the level of / (V・s).

[0194] Indium oxide can contain elements that lower the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. These elements can lower the carrier concentration by substituting for indium. Other examples include nitrogen, phosphorus, arsenic, and antimony. These elements can lower the carrier concentration by substituting for oxygen.

[0195] On the other hand, electrical resistance can be reduced by increasing the carrier concentration. For example, the suitable carrier concentration range for the source and drain regions of a transistor, or for a resistor or transparent conductive film, is when the carrier concentration value is 1 × 10⁻⁶ ２０ cm −３ This range includes, for example, 1 × 10 １９ cm −３ The above is 1 x 10 ２２ cm −３The range is as follows: By making the carrier concentration sufficiently high, the resistivity can be increased to 1 × 10⁻⁶. −４ It is expected that the level can be reduced to below Ω·cm.

[0196] Indium oxide may contain elements that increase the carrier concentration. For example, it is preferable to include elements common to the source and drain electrodes of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use elements in which the oxide is conductive or semiconducting.

[0197] Because indium oxide is an oxide whose valence electrons can be controlled, the region with a low carrier concentration can be used for the channel formation region of the transistor, and the region with a high carrier concentration can be used for the source and drain regions of the transistor. This makes it possible to create a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region). Valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technological concept that would not normally be conceived. By using this technological concept, it is possible to realize a transistor with high mobility, low off-current, normally-off capability, and high reliability.

[0198] The indium oxide film is preferably crystalline. In particular, the indium oxide film is preferably polycrystalline, and more preferably single-crystal. A single-crystal film does not have grain boundaries. By using a single-crystal film, carrier scattering at grain boundaries can be suppressed, enabling the realization of transistors that exhibit high field-effect mobility. Furthermore, it has the excellent effect of suppressing variations in transistor characteristics caused by these grain boundaries.

[0199] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using polycrystalline films, it is preferable to use films with the largest possible grain size and few grain boundaries. In a transistor to which a polycrystalline film is applied, if there are no grain boundaries in the channel formation region, or if no grain boundaries are observed, the channel formation region is located within the single-crystal region contained in the polycrystalline film, and therefore it can be considered a transistor to which a single-crystal film is applied.

[0200] The crystallinity of indium oxide can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0201] Furthermore, in this specification, a semiconductor layer in which no grain boundaries are observed in the channel formation region, a semiconductor layer in which the channel formation region is contained within a single crystal grain, or a semiconductor layer in which the crystal axis directions are the same in at least two regions within the channel formation region can be considered as a single crystal film.

[0202] The channel formation region refers to the region of the semiconductor layer that overlaps with (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The crystal grains, grain boundaries, crystal axes, and crystal orientation in the channel formation region can be confirmed by cross-sectional observation including the semiconductor layer, source electrode, and drain electrode.

[0203] Impurities in the indium oxide film can act as a source of carrier scattering, thus potentially causing a decrease in field-effect mobility and inhibiting crystal growth. Examples of impurities in the indium oxide film include boron and silicon. In the channel-forming region of the indium oxide film, lower concentrations of these impurities are preferable. For example, the concentration of each of the above impurity elements should be 0.1% or less, more preferably 0.01% (100 ppm) or less. Note that elements such as carbon and hydrogen may be present in the deposition gas or precursor during film formation, and may remain in the indium oxide film in higher concentrations than the above impurities.

[0204] Furthermore, the indium oxide film may contain elements that can become trivalent cations like indium, as long as their crystals maintain a cubic crystal structure (Bixbite type). Examples include Group 13 elements of the periodic table such as gallium and aluminum, and Group 3 elements of the periodic table. Since these elements mainly exist as trivalent cations in the oxide, the carrier concentration of indium oxide can be kept low.

[0205] By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be increased to 50 cm². ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ It can be set to (V・s) or more.

[0206] One of the characteristics of indium oxide films is their higher oxygen permeability (diffusivity) compared to IGZO films. For example, oxygen diffusing into an indium oxide film permeates the film and is released as oxygen molecules. In some cases, it may also be released as water molecules by reacting with hydrogen contained in the film. Furthermore, if there is an oxygen deficiency in the film, diffusing oxygen atoms will fill the deficiency. Because oxygen diffuses easily through indium oxide films, it can be said that oxygen deficiencies are more easily filled in compared to IGZO films.

[0207] Thus, because indium oxide films are more likely to reduce oxygen vacancies in the film compared to IGZO films, applying such indium oxide films to transistors makes it possible to realize transistors with extremely high reliability.

[0208] Furthermore, the indium oxide film diffuses hydrogen. Hydrogen diffusing into the indium oxide film from the outside permeates the film and is released as hydrogen molecules. Alternatively, it reacts with oxygen contained in the film and is released as water molecules.

[0209] Indium oxide is characterized by a small effective electron mass and a large effective hole mass. Furthermore, the effective electron mass of indium oxide is largely independent of the crystal orientation. Therefore, using crystalline indium oxide in transistors allows for the realization of transistors with high field-effect mobility and high frequency characteristics (also known as f-response). Moreover, due to the large effective hole mass, transistors with extremely low off-currents can be realized. For example, by applying an indium oxide film to a transistor, the off-current per 1 μm of channel width is 1 fA (1 × 10⁻¹⁶) at 125°C. −１５ A) Less than or equal to, or 1aA (1 × 10 −１８ A) is less than or equal to 1aA (1 × 10) under room temperature (25°C) conditions. −１８ A) Less than or equal to, or 1zA (1 × 10⁻¹⁰ −２１ A) The following is possible. Furthermore, because indium oxide has a smaller effective electron mass and a larger effective hole mass than silicon, it may be possible to realize transistors with higher field-effect mobility and lower off-current than Si transistors.

[0210] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. It is preferable to use a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with the indium oxide for the seed layer. This improves the crystallinity of the indium oxide film. A substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0211] One method for evaluating the degree of lattice mismatch is to use the following lattice mismatch value. The lattice mismatch Δa [%] of the crystals in the formed film (in this case, the indium oxide film) relative to the crystals in the seed layer is given by Δa = ((L １ -L ２ ) / L ２ It is calculated as ) × 100. Here L １ L is the length of the unit cell vector of the crystals in the formed film, or the lattice constant. ２ This is the length of the unit cell vector of the crystal in the seed layer, or the lattice constant.

[0212] The lattice mismatch Δa between the seed layer and the indium oxide film is preferably small in absolute value, and most preferably zero. For example, Δa can be -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less.

[0213] Here, the indium oxide crystal has a cubic structure (bixbite type). For example, yttria-stabilized zirconia (YSZ) crystals can have a cubic structure (fluorite type). The lattice mismatch of the indium oxide crystal with respect to the cubic YSZ crystal is in the range of -2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on a YSZ substrate.

[0214] Furthermore, the crystal structure of the seed layer and the crystal structure of the indium oxide film do not necessarily have to be the same in terms of crystal system or crystal orientation. For example, a film with a hexagonal or trigonal crystal structure can be used beneath an indium oxide film with a cubic crystal structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to crystal orientation necessary for epitaxial growth can be met. Examples of hexagonal or trigonal crystals include wurtzite-type structures and YbFe. ２ O ４ Type structure, Yb ２ Fe ３ O ７ These include type structures and their modified type structures. YbFe ２ O４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a type structure is IGZO.

[0215] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0216] (Embodiment 3) In this embodiment, an example of a CMOS type circuit configuration using Si transistors and OS transistors will be described.

[0217] Si transistors have higher field-effect mobility and faster operating speeds than OS transistors. Furthermore, OS transistors have significantly lower off-currents than Si transistors. In particular, OS transistors using indium oxide (also called indium oxide) in the semiconductor layer where the channel is formed achieve extremely low off-currents and high field-effect mobility comparable to Si transistors. By combining OS and Si transistors, a low-power, high-speed CMOS-type circuit can be realized.

[0218] In this embodiment, as an example of a circuit using Si transistors and OS transistors, configuration examples of logic circuits such as NOT circuits, NOR circuits, and NAND circuits will be described. In addition, configuration examples of buffer circuits, ring oscillators, DFF circuits (DFF: Delay Flip Flop), shift register circuits using DFF circuits, selectors, and analog switches will be described.

[0219] [NOT Circuit] Figure 15A is a circuit diagram showing an example of a NOT circuit (NOT). A NOT circuit is also called an inverting circuit or inverter circuit. Figure 15B shows the circuit symbol for a NOT circuit. Figure 15C is a timing chart explaining the operation of a NOT circuit.

[0220] The NOT gate shown in Figure 15A has transistors Tr11 and Tr12. Transistor Tr11 is a Si transistor that functions as a p-channel transistor, and transistor Tr12 is an OS transistor that functions as an n-channel transistor. A potential H (e.g., high power supply potential VDD) is supplied to either the source or drain of transistor Tr11. The other source or drain of transistor Tr11 is connected to either the source or drain of transistor Tr12 and to terminal Y. A potential L (e.g., low power supply potential VSS) is supplied to the other source or drain of transistor Tr12. The gates of transistor Tr11 and transistor Tr12 are connected to terminal A.

[0221] In the NOT gate shown in Figure 15A, terminal A functions as the input terminal and terminal Y functions as the output terminal. When a potential H is input to terminal A, a potential L is output from terminal Y, and when a potential L is input to terminal A, a potential H is output from terminal Y (see Figure 15C).

[0222] Furthermore, as shown in Figure 15C, the NOT circuit has the function of correcting an input signal that has been degraded by wiring resistance, parasitic capacitance, noise, etc., into a signal that is undegraded or has reduced degradation (also called the "waveform shaping function"). The NOT circuit also has the function of amplifying the voltage amplitude of the input signal and outputting it. The output of the NOT circuit is supplied to a load such as a capacitive element Cx or a transistor Trx. Since power is supplied to the output of the NOT circuit via transistor Tr11 or transistor Tr12, the ability to drive the load connected to the output can be increased. The NOT circuit has the function of increasing the ability to drive the load (also called the "driving force improvement function").

[0223] [NOR Circuit] Figure 16A is a circuit diagram showing an example configuration of a 2-input, 1-output NOR circuit (NOR). Figure 16B shows the circuit symbol for the NOR circuit. The NOR circuit shown in Figure 16A has transistors Tr21, Tr22, Tr23, and Tr24. Si transistors functioning as p-channel transistors can be used for transistors Tr21 and Tr22, and OS transistors functioning as n-channel transistors can be used for transistors Tr23 and Tr24.

[0224] In Figure 16A, a potential H is supplied to either the source or drain of transistor Tr21. The other source or drain of transistor Tr21 is connected to either the source or drain of transistor Tr22. The other source or drain of transistor Tr22 is connected to either the source or drain of transistor Tr23, either the source or drain of transistor Tr24, and terminal Y. A potential L is supplied to either the source or drain of transistor Tr23 and the other source or drain of transistor Tr24.

[0225] Furthermore, the gate of transistor Tr21 is connected to the gate and terminal A of transistor Tr23. Also, the gate of transistor Tr22 is connected to the gate and terminal B of transistor Tr24.

[0226] The NOR circuit shown in Figures 16A and 16B has the function of outputting a potential H from terminal Y when a potential L is input to both terminals A and B. It also has the function of outputting a potential L from terminal Y when a potential H is input to one or both terminals A and B.

[0227] Furthermore, as shown in Figure 16C, an OR gate can be realized by connecting the input of a NOT gate to the output of a NOR gate.

[0228] [NAND Circuit] Figure 16D is a circuit diagram showing an example configuration of a 2-input, 1-output NAND circuit (NAND). Figure 16E shows the circuit symbol for the NAND circuit. The NAND circuit shown in Figure 16D has transistors Tr31, Tr32, Tr33, and Tr34. Si transistors functioning as p-channel transistors can be used for transistors Tr31 and Tr32, and OS transistors functioning as n-channel transistors can be used for transistors Tr33 and Tr34.

[0229] In Figure 16D, a potential H is supplied to one of the sources or drains of transistor Tr31 and one of the sources or drains of transistor Tr32. The other source or drain of transistor Tr31 and the other source or drain of transistor Tr32 are connected to one of the sources or drains of transistor Tr33 and terminal Y. The other source or drain of transistor Tr33 is connected to one of the sources or drains of transistor Tr34. A potential L is supplied to the other source or drain of transistor Tr34.

[0230] The gate of transistor Tr31 is connected to the gate and terminal B of transistor Tr34. The gate of transistor Tr32 is connected to the gate and terminal A of transistor Tr33.

[0231] The NAND circuits shown in Figures 16D and 16E have the function of outputting a potential L from terminal Y when a potential H is input to both terminals A and B. Furthermore, they have the function of outputting a potential H from terminal Y when a potential L is input to either or both terminals A and B.

[0232] Furthermore, as shown in Figure 16F, an AND gate can be realized by combining a NOT gate with a NAND gate.

[0233] [Buffer Circuit] Figure 17A shows the circuit symbol for a buffer circuit. A buffer circuit (BF) can be realized by connecting an even number of NOT gates in series. Figure 17B shows an example of a buffer circuit configuration consisting of two NOT gates. Figure 17C is a timing chart that explains the operation of the buffer circuit.

[0234] In a buffer circuit, no logical operations are performed; instead, the same value as the input logical value is output. Specifically, if a potential H is input, a potential H is output, and if a potential L is input, a potential L is output. In addition, like a NOT gate, a buffer circuit has waveform shaping functions (see Figure 17C) and driving force improvement functions. By using a buffer circuit, it is possible to correct signals that have become distorted and improve the driving force for the load without inverting the signal.

[0235] [Ring Oscillator] A ring oscillator (also called an "oscillating circuit") can be realized by connecting an odd number of NOT gates in a ring. Figure 17D shows an example of a ring oscillator (RO) configuration made up of NOT gates. Figure 17D shows a ring oscillator made up of five NOT gates. A ring oscillator has the function of generating an AC signal (oscillating) when power is supplied. Figure 17E is a diagram illustrating the oscillation of a ring oscillator.

[0236] Generally, in a ring oscillator, the first of the n NOT gates (where n is an odd number greater than or equal to 3) that make up the ring oscillator is sometimes called the "first stage," and the nth gate is sometimes called the "nth stage." A ring oscillator composed of NOT gates has a configuration where the output of each stage's NOT gate is connected to the input of the next stage's NOT gate. Also, the output of the nth stage's NOT gate is connected to the input of the first stage's NOT gate.

[0237] Furthermore, in a NOT gate, a certain delay time occurs before the inverted signal of the input signal is output. Since n is an odd number, the output signal of the first stage is input to the first stage with a delay of n stages. This causes the ring oscillator to oscillate. That is, an AC signal is supplied to terminal Y shown in Figure 17C. By using a ring oscillator, for example, a clock signal can be generated within the circuit. Also, by measuring the oscillation frequency of the ring oscillator, the delay time of the NOT gate can be determined.

[0238] [DFF Circuit] Figure 18A is a circuit diagram showing an example configuration of a D flip-flop circuit (DFF). Figure 18B shows the circuit symbol for a D flip-flop circuit. A DFF has a clock signal input terminal CK, an input terminal D, and an output terminal Q.

[0239] The D flip-flop circuit shown in Figure 18A includes transistors Tr41 to Tr49, Tr51 to Tr59, Tr61, Tr62, Tr71, and Tr72. Si transistors functioning as p-channel transistors can be used for transistors Tr41 to Tr49, Tr61, and Tr62, while OS transistors functioning as n-channel transistors can be used for transistors Tr51 to Tr59, Tr71, and Tr72.

[0240] A potential of H is supplied to either the source or drain of transistor Tr41, either the source or drain of transistor Tr42, either the source or drain of transistor Tr44, either the source or drain of transistor Tr46, either the source or drain of transistor Tr48, either the source or drain of transistor Tr61, and either the source or drain of transistor Tr62.

[0241] The source or drain of transistor Tr41 is connected to either the source or drain of transistor Tr51, the gate of transistor Tr44, the gate of transistor Tr46, the gate of transistor Tr53, and the gate of transistor Tr59. The gate of transistor Tr41 is connected to the clock signal input terminal CK, the gate of transistor Tr51, the gate of transistor Tr42, the gate of transistor Tr48, the gate of transistor Tr55, and the gate of transistor Tr57.

[0242] The other source or drain of transistor Tr42 is connected to one source or drain of transistor Tr43. The other source or drain of transistor Tr44 is connected to one source or drain of transistor Tr45. The other source or drain of transistor Tr43 is connected to the other source or drain of transistor Tr45, one source or drain of transistor Tr52, one source or drain of transistor Tr54, the gate of transistor Tr61, and the gate of transistor Tr71. The gate of transistor Tr43 is connected to the gate of transistor Tr52 and input terminal D.

[0243] The other source or drain of transistor Tr52 is connected to one source or drain of transistor Tr53. The other source or drain of transistor Tr54 is connected to one source or drain of transistor Tr55. The gate of transistor Tr45 is connected to the gate of transistor Tr54, the other source or drain of transistor Tr61, one source or drain of transistor Tr71, the gate of transistor Tr47, and the gate of transistor Tr56. The other source or drain of transistor Tr46 is connected to one source or drain of transistor Tr47. The other source or drain of transistor Tr48 is connected to one source or drain of transistor Tr49.

[0244] The other source or drain of transistor Tr47 is connected to one source or drain of transistor Tr56, the other source or drain of transistor Tr49, one source or drain of transistor Tr58, the gate of transistor Tr62, and the gate of transistor Tr72. The other source or drain of transistor Tr62 is connected to one source or drain of transistor Tr72, the gate of transistor Tr49, the gate of transistor Tr58, and the output terminal Q.

[0245] The other source or drain of transistor Tr56 is connected to one source or drain of transistor Tr57. The other source or drain of transistor Tr58 is connected to one source or drain of transistor Tr59. A potential L is supplied to the other source or drain of transistor Tr51, the other source or drain of transistor Tr53, the other source or drain of transistor Tr55, the other source or drain of transistor Tr71, the other source or drain of transistor Tr57, the other source or drain of transistor Tr59, and the other source or drain of transistor Tr72.

[0246] The DFF shown in Figures 18A and 18B has the function of writing information (potential) supplied to input terminal D to the DFF when the signal input to clock signal input terminal CK changes from potential L to potential H, and retaining this information until the next time the signal input to clock signal input terminal CK changes from potential L to potential H. In addition, a signal (potential H or potential L) based on the information held by the DFF is always output from output terminal Q.

[0247] Figure 19A is a block diagram showing an example configuration of a shift register circuit (SR). The SR includes multiple DFFs. In this specification, the first stage (first) DFF is indicated as "DFF[1]", and the potential (data) output from the output terminal Q of DFF[1] is indicated as "Data OUT[1]". Figure 19A shows a block diagram of an SR including four stages (four) DFFs (DFF[1] to DFF[4]). In Figure 19A, the data output from the output terminal Q of each of DFF[1] to DFF[4] is indicated as Data OUT[1] to Data OUT[4].

[0248] Figure 19B is a timing chart illustrating the operation of the SR. The clock signal CLK is input to the clock signal input terminal CK of the odd-numbered stage DFFs. The inverted signal of CLK is input to the clock signal input terminal CK of the even-numbered stage DFFs.

[0249] The input terminal D of DFF[1] receives the pulse signal SPL. DFF[1] holds a signal corresponding to the input signal SPL in synchronization with the signal CLK and outputs it as dataOUT[1]. The value of dataOUT[1] will be a value corresponding to the data held by DFF[1].

[0250] Furthermore, data OUT[1] is input to input terminal D of DFF[2]. DFF[2] holds a signal corresponding to the input data OUT[1] in synchronization with the signal CLK and outputs it as data OUT[2]. Similarly, data OUT[2] is input to input terminal D of DFF[3], and data OUT[3] is input to input terminal D of DFF[4].

[0251] Thus, the SR has the function of sequentially transferring the input signal SPL to the subsequent DFF in synchronization with the signal CLK. In addition, the SR has the function of sequentially switching the potential of the data OUT output from multiple DFFs in synchronization with the signal CLK.

[0252] Furthermore, it is preferable to stack the Si transistor and the OS transistor. Stacking the Si transistor and the OS transistor allows for the realization of a circuit with a small footprint. In addition, the OS transistor operates stably even in high-temperature environments and exhibits minimal characteristic fluctuations. Therefore, the OS transistor is less affected by the heat generated by the Si transistor and can operate stably. Moreover, stacking the Si transistor and the OS transistor allows for extremely short connection distances between them. As a result, wiring resistance and parasitic capacitance are reduced, enabling high-speed operation of the circuit. In addition, the power consumption of the circuit is reduced.

[0253] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0254] (Embodiment 4) In this embodiment, a semiconductor device 900 according to one aspect of the present invention will be described. The semiconductor device 900 can function as a storage device.

[0255] Figure 20 shows a block diagram illustrating an example configuration of a semiconductor device 900. The semiconductor device 900 shown in Figure 20 includes a drive circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Figure 20 shows an example in which the memory array 920 has multiple memory cells 950 arranged in a matrix.

[0256] The transistor exemplified in Embodiment 1 can be applied to the memory cell 950. By using the above transistor, the operating speed of the memory device can be improved. Furthermore, miniaturization and high integration of the memory device can be achieved. In addition, the capacity per unit area of ​​the memory device can be increased.

[0257] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912 (Control Circuit), and a voltage generation circuit 928.

[0258] The transistors exemplified in Embodiment 1 can also be applied to each circuit constituting the drive circuit 910. This makes it possible to reduce the circuit area and power consumption.

[0259] In the semiconductor device 900, each circuit, each signal, and each voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or other signals may be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are external input signals, and signal RDA is an external output signal. Signal CLK is a clock signal.

[0260] Furthermore, signals BW, CE, and GW are control signals. Signal CE is the chip enable signal, signal GW is the global write enable signal, and signal BW is the byte write enable signal. Signal ADDR is the address signal. Signal WDA is the write data signal, and signal RDA is the read data signal. Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may be generated by the control circuit 912.

[0261] The control circuit 912 is a logic circuit that has the function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs logical operations on signals CE, GW, and BW to determine the operating mode of the semiconductor device 900 (e.g., write operation, read operation). Alternatively, the control circuit 912 generates control signals for the peripheral circuit 911 so that this operating mode is executed.

[0262] The voltage generation circuit 928 has the function of generating voltage. The signal WAKE has the function of controlling the input of the signal CLK to the voltage generation circuit 928. For example, when a high-level signal is given as the signal WAKE, the signal CLK is input to the voltage generation circuit 928, and the voltage generation circuit 928 generates voltage.

[0263] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cell 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0264] The row decoder 941 and column decoder 942 have the function of decoding the ADDR signal. The row decoder 941 is a circuit for specifying the row to access, and the column decoder 942 is a circuit for specifying the column to access. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cell 950, reading data from the memory cell 950, and holding the read data.

[0265] The input circuit 925 has the function of holding the signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is the data (Din) to be written to the memory cell 950. The data (Dout) read by the column driver 924 from the memory cell 950 is output to the output circuit 926. The output circuit 926 has the function of holding Dout. The output circuit 926 also has the function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is the signal RDA.

[0266] PSW931 provides V to peripheral circuit 915 ＤＤ It has the function of controlling the supply. PSW932 has the function of V to line driver 923 ＨＭ It has a function to control the supply. Here, the high power supply potential of the semiconductor device 900 is V ＤＤ Therefore, the low power supply potential is GND (ground potential). Also, V ＨＭ This is a high power supply potential used to raise the word line to a high level, V ＤＤIt is higher than that. The on / off state of PSW931 is controlled by signal PON1, and the on / off state of PSW932 is controlled by signal PON2. In Figure 20, in peripheral circuit 915, V ＤＤ The number of power domains supplied is set to one, but it can be multiple. In this case, a power switch should be provided for each power domain.

[0267] Using Figures 21A to 21H, other examples of memory cell configurations applicable to the memory cell 950 will be described.

[0268] [DOSRAM] Figure 21A shows an example of the circuit configuration of a DRAM memory cell. In this specification and elsewhere, a DRAM using an OS transistor is called DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 951 has a transistor M1 and a capacitive element CA.

[0269] Transistor M1 may have a front gate (sometimes simply called a gate) and a back gate. In this case, the back gate may be connected to a wire to which a constant potential or signal is supplied, or the front gate and back gate may be connected.

[0270] The first terminal of transistor M1 is connected to the first terminal of capacitive element CA, the second terminal of transistor M1 is connected to wiring BIL, and the gate of transistor M1 is connected to wiring WOL. The second terminal of capacitive element CA is connected to wiring CAL.

[0271] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitive element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to the wiring CAL.

[0272] Data writing and reading are performed by applying a high-level potential to the wiring WOL, making transistor M1 conductive, and connecting the wiring BIL to the first terminal of the capacitive element CA.

[0273] Furthermore, the memory cell that can be used in memory cell 950 is not limited to memory cell 951, and the circuit configuration can be changed. For example, the configuration of memory cell 952 as shown in Figure 21B is also acceptable. Memory cell 952 is an example in which there is no capacitive element CA and wiring CAL. The first terminal of transistor M1 is electrically floating.

[0274] In the memory cell 952, the potential written via transistor M1 is held in the capacitance (also called parasitic capacitance) between the first terminal and the gate, indicated by the dashed line. This configuration significantly simplifies the structure of the memory cell.

[0275] Furthermore, it is preferable to use the OS transistor described in Embodiment 1 as transistor M1. By using the OS transistor described in Embodiment 1, the operating speed of the memory device can be improved. In addition, the occupied area of ​​the memory cell can be reduced. OS transistors also have the characteristic of having an extremely small off-current. By using an OS transistor as transistor M1, the leakage current of transistor M1 can be made very low. In other words, since the written data can be held by transistor M1 for a long time, the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be made unnecessary. In addition, because the leakage current is very low, multi-level data or analog data can be held in memory cells 951 and 952.

[0276] [NOSRAM] Figure 21C shows an example of a circuit configuration for a gain cell type memory cell with two transistors and one capacitance element. The memory cell 953 has a transistor M2, a transistor M3, and a capacitance element CB. In this specification and elsewhere, a memory device having a gain cell type memory cell using an OS transistor for transistor M2 is called NOSRAM (Nonvolatil Oxide Semiconductor RAM).

[0277] The first terminal of transistor M2 is connected to the first terminal of capacitive element CB, the second terminal of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL. The second terminal of capacitive element CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring RL, and the gate of transistor M3 is connected to the first terminal of capacitive element CB.

[0278] Wiring WBL functions as a write bit line, wiring RBL functions as a read bit line, and wiring WOL functions as a word line. Wiring CAL functions as wiring for applying a predetermined potential to the second terminal of the capacitive element CB. When writing data, during data retention, and when reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to wiring CAL.

[0279] Data writing is performed by applying a high-level potential to the wiring WOL, making transistor M2 conductive, and connecting the wiring WBL to the first terminal of the capacitive element CB. Specifically, when transistor M2 is conductive, a potential corresponding to the information to be recorded in wiring WBL is applied, and this potential is written to the first terminal of the capacitive element CB and the gate of transistor M3. Subsequently, a low-level potential is applied to the wiring WOL, making transistor M2 non-conductive, thereby maintaining the potential of the first terminal of the capacitive element CB and the potential of the gate of transistor M3.

[0280] Data is read by applying a predetermined potential to the wiring RL. The current flowing between the source and drain of transistor M3, and the potential of the first terminal of transistor M3, are determined by the potential of the gate and the potential of the second terminal of transistor M3. Therefore, by reading the potential of the wiring RBL connected to the first terminal of transistor M3, the potential held at the first terminal of the capacitive element CB (or the gate of transistor M3) can be read. In other words, the information written to this memory cell can be read from the potential held at the first terminal of the capacitive element CB (or the gate of transistor M3).

[0281] Alternatively, for example, the wiring WBL and wiring RBL may be combined into a single wiring BIL. An example of the circuit configuration of such a memory cell is shown in Figure 21D. Memory cell 954 is configured such that the wiring WBL and wiring RBL of memory cell 953 are combined into a single wiring BIL, and the second terminal of transistor M2 and the first terminal of transistor M3 are connected to the wiring BIL. In other words, memory cell 954 is configured to operate with the write bit line and the read bit line as a single wiring BIL.

[0282] The memory cell 955 shown in Figure 21E is an example where the capacitive element CB and wiring CAL in memory cell 953 are omitted. Similarly, the memory cell 956 shown in Figure 21F is an example where the capacitive element CB and wiring CAL in memory cell 954 are omitted. By using such a configuration, the integration density of memory cells can be increased.

[0283] Furthermore, it is preferable to use the OS transistor described in Embodiment 1 for at least transistor M2. For example, it is preferable to use the transistors exemplified in Embodiment 1 for one or both of transistors M2 and M3 of memory cells 953 and 954. By using the OS transistor described in Embodiment 1, the operating speed of the memory device can be improved. In addition, the occupied area of ​​the memory cell can be reduced.

[0284] Because the OS transistor has the characteristic of having an extremely low off-current, the written data can be held by transistor M2 for a long time, thus reducing the frequency of memory cell refreshes. Alternatively, it may be possible to eliminate the need for memory cell refresh operations altogether. Furthermore, because the leakage current is very low, multi-level data or analog data can be held in memory cells 953, 954, 955, and 956.

[0285] Memory cells 953, 954, 955, and 956, which use an OS transistor as transistor M2, represent one form of NOSRAM.

[0286] Furthermore, a Si transistor may be used as transistor M3. Si transistors can increase field-effect mobility and can also be made into p-channel transistors, thus increasing the flexibility of circuit design.

[0287] Furthermore, if an OS transistor is used as transistor M3, the memory cell can be constructed using only n-channel transistors.

[0288] Figure 21G also shows a gain cell type memory cell 957 with three transistors and one capacitance element. The memory cell 957 has transistors M4 to M6 and a capacitance element CC.

[0289] The first terminal of transistor M4 is connected to the first terminal of capacitive element CC, the second terminal of transistor M4 is connected to wiring BIL, and the gate of transistor M4 is connected to wiring WOL. The second terminal of capacitive element CC is connected to the first terminal of transistor M5 and to wiring GNDL. The second terminal of transistor M5 is connected to the first terminal of transistor M6, and the gate of transistor M5 is connected to the first terminal of capacitive element CC. The second terminal of transistor M6 is connected to wiring BIL, and the gate of transistor M6 is connected to wiring RWL.

[0290] Wiring BIL functions as a bit line, wiring WOL functions as a write word line, and wiring RWL functions as a read word line. Wiring GNDL is a wire that provides a low level potential.

[0291] Data writing is performed by applying a high-level potential to the wiring WOL, making transistor M4 conductive, and connecting the wiring BIL to the first terminal of the capacitive element CC. Specifically, when transistor M4 is conductive, a potential corresponding to the information to be recorded in wiring BIL is applied, and this potential is written to the first terminal of the capacitive element CC and the gate of transistor M5. Subsequently, a low-level potential is applied to the wiring WOL, making transistor M4 non-conductive, thereby maintaining the potential of the first terminal of the capacitive element CC and the potential of the gate of transistor M5.

[0292] Data is read by precharging the wiring BIL to a predetermined potential, then electrically freezing the wiring BIL, and applying a high-level potential to the wiring RWL. As the wiring RWL reaches a high-level potential, transistor M6 becomes conductive, and the wiring BIL and the second terminal of transistor M5 become connected. At this time, the potential of the wiring BIL is applied to the second terminal of transistor M5, but the potential of the second terminal of transistor M5 and the potential of the wiring BIL change depending on the potential held at the first terminal of the capacitive element CC (or the gate of transistor M5). By reading the potential of the wiring BIL, the potential held at the first terminal of the capacitive element CC (or the gate of transistor M5) can be read. In other words, the information written to this memory cell can be read from the potential held at the first terminal of the capacitive element CC (or the gate of transistor M5).

[0293] Furthermore, it is preferable to use the OS transistor described in Embodiment 1 for at least transistor M4. By using the OS transistor described in Embodiment 1, the occupied area of ​​the memory cell can be reduced.

[0294] Note that Si transistors may be used as transistors M5 and M6. As mentioned above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystal state of the silicon used in the semiconductor layer.

[0295] Furthermore, if OS transistors are used as transistors M5 and M6, the memory cell can be constructed using only n-channel transistors.

[0296] [OS-SRAM] Figure 21H shows an example of SRAM (Static Random Access Memory) using an OS transistor. In this specification and elsewhere, SRAM using an OS transistor is called OS-SRAM (Oxide Semiconductor-SRAM). The memory cell 958 shown in Figure 21H is a memory cell of a backup-capable SRAM.

[0297] The memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, and capacitive elements CD1 and CD2. Transistors MS1 and MS2 are p-channel transistors, while transistors MS3 and MS4 are n-channel transistors.

[0298] The first terminal of transistor M7 is connected to wiring BIL, and the second terminal of transistor M7 is connected to the first terminal of transistor MS1, the first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and the first terminal of transistor M10. The gate of transistor M7 is connected to wiring WOL. The first terminal of transistor M8 is connected to wiring BILB, and the second terminal of transistor M8 is connected to the first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and the first terminal of transistor M9. The gate of transistor M8 is connected to wiring WOL.

[0299] The second terminal of transistor MS1 is connected to wiring VDL. The second terminal of transistor MS2 is connected to wiring VDL. The second terminal of transistor MS3 is connected to wiring GNDL. The second terminal of transistor MS4 is connected to wiring GNDL.

[0300] The second terminal of transistor M9 is connected to the first terminal of capacitive element CD1, and the gate of transistor M9 is connected to wiring BRL. The second terminal of transistor M10 is connected to the first terminal of capacitive element CD2, and the gate of transistor M10 is connected to wiring BRL.

[0301] The second terminal of capacitive element CD1 is connected to wiring GNDL, and the second terminal of capacitive element CD2 is connected to wiring GNDL.

[0302] Wiring BIL and BILB function as bit lines, wiring WOL functions as a word line, and wiring BRL controls the conduction and non-conduction states of transistors M9 and M10.

[0303] Wiring VDL is a wiring that provides a high-level potential, and wiring GNDL is a wiring that provides a low-level potential.

[0304] Data is written by applying a high-level potential to wiring WOL and wiring BRL. Specifically, when transistor M10 is conducting, a potential corresponding to the information to be recorded in wiring BIL is applied, and this potential is written to the second terminal side of transistor M10.

[0305] Incidentally, since the memory cell 958 is configured with an inverter loop by transistors MS1 to MS4, an inverted signal of the data signal corresponding to the potential is input to the second terminal of transistor M8. Because transistor M8 is conducting, the potential applied to wiring BIL, i.e., the inverted signal of the signal input to wiring BIL, is output to wiring BILB. Also, because transistors M9 and M10 are conducting, the potential of the second terminal of transistor M7 and the potential of the second terminal of transistor M8 are held at the first terminal of capacitive element CD2 and the first terminal of capacitive element CD1, respectively. Subsequently, by applying a low-level potential to wiring WOL and wiring BRL, and making transistors M7 to M10 non-conductive, the potentials of the first terminal of capacitive element CD1 and the first terminal of capacitive element CD2 are maintained.

[0306] The data reading process is described below. First, wiring BIL and wiring BILB are precharged to a predetermined potential. Next, a high-level potential is applied to wiring WOL and wiring BRL. At this time, the potential of the first terminal of capacitive element CD1 is refreshed by the inverter loop of memory cell 958 and output to wiring BILB. Also, the potential of the first terminal of capacitive element CD2 is refreshed by the inverter loop of memory cell 958 and output to wiring BIL. In wiring BIL and wiring BILB, the potential changes from the precharged potential to the potential of the first terminal of capacitive element CD2 and the potential of the first terminal of capacitive element CD1, respectively. Therefore, the potential held in the memory cell can be read from the potential of wiring BIL or wiring BILB.

[0307] Furthermore, it is preferable to use the OS transistors exemplified in Embodiment 1 as transistors M7 to M10. This allows the written data to be retained for a long time by transistors M7 to M10, thereby reducing the frequency of memory cell refreshes. Alternatively, it may be possible to eliminate the need for memory cell refresh operations. In addition, the operating speed of the storage device can be improved. Furthermore, the occupied area of ​​the memory cell can be reduced.

[0308] Furthermore, Si transistors may be used as transistors MS1 to MS4.

[0309] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0310] (Embodiment 5) In this embodiment, an application example of a semiconductor device according to one aspect of the present invention will be described with reference to Figures 22A to 23E.

[0311] A semiconductor device according to one aspect of the present invention can be used, for example, in electronic components, large computers, space equipment, data centers (also referred to as DCs), and various electronic devices. By using a semiconductor device according to one aspect of the present invention, lower power consumption and higher performance can be achieved in electronic components, large computers, space equipment, data centers, and various electronic devices.

[0312] Examples of electronic devices include television sets, desktop or laptop computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as other electronic devices with relatively large screens, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, personal digital assistants, and audio playback devices.

[0313] The electronic device of this embodiment may have sensors (including those with the function of detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation).

[0314] The electronic device of this embodiment can have a variety of functions. For example, it can have a function to display various information (still images, videos, or text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, a function to execute various software (programs), a wireless communication function, a function to read programs or data recorded on a recording medium, and so on.

[0315] [Electronic Components] Figure 22A shows a perspective view of a substrate (mounted substrate 989) on which electronic components 980 are mounted. The electronic component 980 shown in Figure 22A has a semiconductor device 981 inside a mold 984. Some details are omitted in Figure 22A to show the inside of the electronic component 980. The electronic component 980 has a land 985 on the outside of the mold 984. The land 985 is connected to an electrode pad 986, and the electrode pad 986 is connected to the semiconductor device 981 via a wire 987. The electronic component 980 is mounted on a printed circuit board 988, for example. Multiple such electronic components are combined and connected on the printed circuit board 988 to complete the mounted substrate 989.

[0316] Furthermore, the semiconductor device 981 has a drive circuit layer 982 and a storage layer 983. The storage layer 983 has a configuration in which multiple memory cell arrays are stacked. The configuration in which the drive circuit layer 982 and the storage layer 983 are stacked can be a monolithic stack configuration. In a monolithic stack configuration, the layers can be connected without using through-electrode technologies such as TSV (Through Silicon Via) and bonding technologies such as Cu-Cu direct bonding. By monolithically stacking the drive circuit layer 982 and the storage layer 983, for example, a so-called on-chip memory configuration can be achieved in which memory is directly formed on the processor. By using an on-chip memory configuration, it is possible to speed up the operation of the interface portion between the processor and the memory.

[0317] Furthermore, by using an on-chip memory configuration, the size of connection wiring can be reduced compared to technologies using through-hole electrodes such as TSVs, making it possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which in turn improves the memory bandwidth (also called memory bandwidth).

[0318] Furthermore, it is preferable to form the multiple memory cell arrays of the memory layer 983 using OS transistors and to stack these multiple memory cell arrays monolithically. By configuring the multiple memory cell arrays in a monolithic stack, it is possible to improve either or both of the memory bandwidth and / or memory access latency. Bandwidth is the amount of data transferred per unit time, and access latency is the time from access to the start of data exchange. In the case of a configuration using Si transistors in the memory layer 983, it is difficult to create a monolithic stack configuration compared to OS transistors. Therefore, in a monolithic stack configuration, OS transistors can be said to have a superior structure compared to Si transistors.

[0319] Furthermore, the drive circuit layer 982 can also be configured to use an OS transistor. The OS transistor shown in the above embodiment is capable of carrying a large current. This makes it possible to operate the semiconductor device 994 at high speed.

[0320] The semiconductor device 981 may also be referred to as a die. In this specification, a die refers to a chip piece obtained in the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disc-shaped substrate (also called a wafer) and cutting it into cubes. Examples of semiconductor materials that can be used for dies include silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) is sometimes called a silicon die.

[0321] In the above, an example of the semiconductor device 981 functioning as a memory device was shown, but the present invention is not limited to this. For example, the semiconductor device 981 can also function as a processor such as a CPU, GPU, or FPGA (Field Programmable Gate Array). In this case, it is preferable to use an OS transistor in the semiconductor device 981. The OS transistor shown in the above embodiment is capable of supplying a large current. This makes it possible to operate the semiconductor device 981 at high speed.

[0322] Next, a perspective view of the electronic component 990 is shown in Figure 22B. The electronic component 990 is an example of a SiP (System in Package) or MCM (Multi-Chip Module). The electronic component 990 has an interposer 991 provided on a package substrate 992 (printed circuit board), and a semiconductor device 994 and a plurality of semiconductor devices 981 are provided on the interposer 991.

[0323] Electronic component 990 shows an example where semiconductor device 981 is used as a high-bandwidth memory (HBM). Furthermore, semiconductor device 994 can be used in integrated circuits such as CPUs, GPUs, or FPGAs.

[0324] Furthermore, it is preferable to use an OS transistor in the semiconductor device 994. The OS transistor shown in the above embodiment is capable of supplying a large current. This makes it possible to operate the semiconductor device 994 at high speed.

[0325] The package substrate 992 can be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 991 can be, for example, a silicon interposer or a resin interposer.

[0326] The interposer 991 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 991 also has the function of connecting integrated circuits provided on the interposer 991 to electrodes provided on the package substrate 992. For these reasons, the interposer is sometimes called a "redistribution substrate" or "intermediate substrate". In addition, through electrodes may be provided on the interposer 991, and these through electrodes may be used to connect the integrated circuits and the package substrate 992. Furthermore, in silicon interposers, TSVs can also be used as through electrodes.

[0327] In HBMs, many connections are necessary to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted requires fine and high-density wiring. For this reason, it is preferable to use a silicon interposer for mounting the HBM.

[0328] Furthermore, in SiP and MCM using silicon interposers, reliability degradation due to differences in expansion coefficients between the integrated circuit and the interposer is less likely to occur. In addition, because silicon interposers have high surface flatness, connection failures between the integrated circuit and the silicon interposer are less likely to occur. In particular, in 2.5D packages (2.5-dimensional packaging) where multiple integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0329] On the other hand, when connecting multiple integrated circuits with different terminal pitches using silicon interposers and TSVs, space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 990, the width of the terminal pitch becomes a problem, and it may become difficult to provide the many wires necessary to achieve a wide memory bandwidth. For this reason, as mentioned above, a monolithic stacked configuration using OS transistors is preferable. A composite structure combining a memory cell array stacked using TSVs and a monolithic stacked memory cell array may also be used.

[0330] Alternatively, a heat sink (heat dissipation plate) may be provided on top of the electronic component 990. If a heat sink is provided, it is preferable to align the heights of the integrated circuits provided on the interposer 991. For example, in the electronic component 990 shown in this embodiment, it is preferable to align the heights of the semiconductor device 981 and the semiconductor device 994.

[0331] To mount the electronic component 990 onto another substrate, electrodes 993 may be provided at the bottom of the package substrate 992. Figure 22B shows an example in which the electrodes 993 are formed with solder balls. By providing solder balls in a matrix at the bottom of the package substrate 992, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrodes 993 may be formed with conductive pins. By providing conductive pins in a matrix at the bottom of the package substrate 992, PGA (Pin Grid Array) mounting can be achieved.

[0332] The electronic component 990 can be mounted on other boards using various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0333] [Large-scale computer] Next, a perspective view of the large-scale computer 5600 is shown in Figure 23A. The large-scale computer 5600 shown in Figure 23A has multiple rack-mount type computers 5620 housed in rack 5610. The large-scale computer 5600 may also be called a supercomputer.

[0334] The computer 5620 can have the configuration shown in the perspective view in Figure 23B, for example. In Figure 23B, the computer 5620 has a motherboard 5630, which has multiple slots 5631 and multiple connection terminals. A PC card 5621 is inserted into a slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0335] The PC card 5621 shown in Figure 23C is an example of a processing board equipped with a CPU, GPU, storage device, etc. The PC card 5621 has a board 5622. The board 5622 also has connection terminals 5623, 5624, 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629. Although Figure 23C shows semiconductor devices other than semiconductor devices 5626, 5627, and 5628, you can refer to the descriptions of semiconductor devices 5626, 5627, and 5628 below for details on these semiconductor devices.

[0336] The connector 5629 has a shape that allows it to be inserted into the slot 5631 of the motherboard 5630, and functions as an interface for connecting the PC card 5621 and the motherboard 5630. Examples of standards for the connector 5629 include PCIe.

[0337] Terminals 5623, 5624, and 5625 can serve as interfaces for, for example, power supply and signal input to the PC card 5621. They can also serve as interfaces for, for example, outputting signals calculated by the PC card 5621. Examples of standards for terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). When outputting video signals from terminals 5623, 5624, and 5625, examples of standards include HDMI (registered trademark).

[0338] The semiconductor device 5626 has terminals (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be connected by inserting these terminals into sockets (not shown) provided on the board 5622.

[0339] The semiconductor device 5627 has multiple terminals, and the semiconductor device 5627 and the board 5622 can be connected by soldering these terminals to the wiring provided on the board 5622, for example, using a reflow soldering method. Examples of semiconductor devices 5627 include FPGAs, GPUs, and CPUs. For example, an electronic component 990 can be used as the semiconductor device 5627.

[0340] The semiconductor device 5628 has multiple terminals, and the semiconductor device 5628 and the board 5622 can be connected by soldering these terminals to the wiring provided on the board 5622, for example, using a reflow soldering method. Examples of the semiconductor device 5628 include a memory device. For example, an electronic component 990 can be used as the semiconductor device 5628.

[0341] The 5600 mainframe computer can also function as a parallel computer. By using the 5600 mainframe computer as a parallel computer, it is possible to perform large-scale calculations necessary for, for example, artificial intelligence training and inference.

[0342] [Space Equipment] A semiconductor device according to one aspect of the present invention can be suitably used in space equipment.

[0343] One embodiment of the present invention includes an OS transistor. Compared to Si transistors, OS transistors exhibit smaller fluctuations in electrical properties due to radiation exposure. In other words, they have high resistance to radiation, making them highly reliable and suitable for use in environments where radiation may be incident. For example, OS transistors are suitable for use in outer space. Specifically, OS transistors can be used as transistors constituting semiconductor devices installed in space shuttles, artificial satellites, or space probes. Examples of radiation include X-rays and neutrons. Outer space refers, for example, to an altitude of 100 km or higher, but outer space as described herein may include one or more of the thermosphere, mesosphere, and stratosphere.

[0344] Figure 23D shows an example of space equipment, specifically a satellite 6800. The satellite 6800 comprises a body 6801, solar panels 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In Figure 23D, a planet 6804 is shown as an example in outer space.

[0345] Furthermore, although not shown in Figure 23D, a battery management system (also known as a BMS) or a battery control circuit may be provided with the secondary battery 6805. Using an OS transistor in the aforementioned battery management system or battery control circuit is preferable because it consumes little power and has high reliability even in outer space.

[0346] Furthermore, outer space is an environment with radiation levels more than 100 times higher than those on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0347] When sunlight shines on the solar panel 6802, the power necessary for the satellite 6800 to operate is generated. However, if, for example, the solar panel is not exposed to sunlight, or if the amount of sunlight hitting the solar panel is low, the amount of power generated will decrease. Therefore, there is a possibility that the power necessary for the satellite 6800 to operate may not be generated. To operate the satellite 6800 even under conditions of low power generation, it is advisable to equip the satellite 6800 with a secondary battery 6805. Note that solar panels are sometimes called solar cell modules.

[0348] The satellite 6800 can generate a signal. This signal is transmitted via antenna 6803, and can be received by, for example, a receiver on the ground or another satellite. By receiving the signal transmitted by satellite 6800, the position of the receiver that received the signal can be measured. Thus, satellite 6800 can constitute a satellite positioning system.

[0349] Furthermore, the control device 6807 has the function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a memory device. It is preferable to use a semiconductor device including an OS transistor, which is one embodiment of the present invention, for the control device 6807.

[0350] Furthermore, the satellite 6800 can be configured to include sensors. For example, by configuring it to include a visible light sensor, the satellite 6800 can have the function of detecting sunlight reflected off objects on the ground. Alternatively, by configuring it to include a thermal infrared sensor, the satellite 6800 can have the function of detecting thermal infrared radiation emitted from the Earth's surface. Thus, the satellite 6800 can function, for example, as an Earth observation satellite.

[0351] In this embodiment, an artificial satellite was used as an example of space equipment, but the invention is not limited to this. For example, a semiconductor device according to one aspect of the present invention can be suitably used in space equipment such as spacecraft, space capsules, and space probes.

[0352] As explained above, OS transistors have superior advantages compared to Si transistors, such as the ability to achieve a wider memory bandwidth and higher radiation resistance.

[0353] [Data Center] One embodiment of the present invention is suitably used in storage systems applied to data centers, for example. Data centers are required to manage data over the long term, such as by ensuring the immutability of the data. Managing data over the long term requires the installation of storage and servers to store vast amounts of data, securing a stable power supply to hold the data, or securing cooling equipment required for data storage, which necessitates the construction of larger buildings.

[0354] By using a semiconductor device according to one aspect of the present invention in a storage system applied to a data center, it is possible to reduce the power required for data retention and miniaturize the semiconductor device that holds the data. Therefore, it is possible to miniaturize the storage system, the power supply for data retention, and the cooling equipment. This, in turn, contributes to space savings in the data center.

[0355] Furthermore, because the semiconductor device according to one aspect of the present invention has low power consumption, heat generation from the circuit can be reduced. Therefore, adverse effects on the circuit itself, peripheral circuits, and modules due to such heat generation can be reduced. In addition, by using the semiconductor device according to one aspect of the present invention, a data center that operates stably even in high-temperature environments can be realized. Therefore, the reliability of the data center can be improved.

[0356] Figure 23E shows a storage system applicable to a data center. The storage system 7010 shown in Figure 23E has multiple servers 7001sb as hosts 7001 (indicated as Host Computer) and multiple storage devices 7003md as storage 7003 (indicated as Storage). The host 7001 and storage 7003 are connected via a storage area network 7004 (SAN: Storage Area Network) and a storage control circuit 7002 (indicated as Storage Controller).

[0357] Host 7001 corresponds to a computer that accesses data stored in storage 7003. The hosts 7001 may be connected to each other via a network.

[0358] Although storage 7003 uses flash memory to shorten data access speed, that is, the time required for data storage and retrieval, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In storage systems, cache memory is usually provided within the storage to shorten the time required for data storage and retrieval in order to solve the problem of the long access speed of storage 7003.

[0359] The aforementioned cache memory is used within the storage control circuit 7002 and storage 7003. Data exchanged between the host 7001 and storage 7003 is stored in the cache memory within the storage control circuit 7002 and storage 7003, and then output to the host 7001 or storage 7003.

[0360] By using OS transistors as the transistors for storing the aforementioned cache memory data, and configuring them to maintain a potential corresponding to the data, the frequency of refresh can be reduced, thereby lowering power consumption. Furthermore, miniaturization is possible by stacking the memory cell arrays.

[0361] Furthermore, by applying a semiconductor device according to one aspect of the present invention to one or more selected from electronic components, large computers, space equipment, data centers, and electronic devices, power consumption can be reduced. Therefore, as energy demand is expected to increase with the performance or integration of semiconductor devices, using a semiconductor device according to one aspect of the present invention can reduce carbon dioxide (CO2) emissions. ２ It is also possible to reduce greenhouse gas emissions, such as those represented by [specific examples of greenhouse gas emissions]. Furthermore, because the semiconductor device according to one aspect of the present invention consumes little power, it is also effective as a measure against global warming.

[0362] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0363] 10: Semiconductor device, 11: Insulating layer, 12: Substrate, 13: Element isolation layer, 20: Transistor, 21: Semiconductor layer, 21a: Semiconductor layer, 21b: Semiconductor layer, 21c: Semiconductor layer, 21d: Semiconductor layer, 21f: Semiconductor film, 21af: Semiconductor film, 21bf: Semiconductor film, 21cf: Semiconductor film, 21df: Semiconductor film, 22: Insulating layer, 23: Conductive layer, 24: Conductive layer, 25: Conductive layer, 30: Transistor, 31: Semiconductor layer, 31a: Semiconductor layer, 31b: Semiconductor layer, 31c: Semiconductor layer, 31d: Semiconductor layer, 31af: Semiconductor film, 31bf: Semiconductor film, 31cf: Semiconductor film, 3 1df: semiconductor film, 31f: semiconductor film, 34: conductive layer, 34f: conductive film, 35: conductive layer, 41: insulating layer, 41f: insulating film, 42: insulating layer, 43: insulating layer, 44: insulating layer, 51: insulating layer, 52: insulating layer, 53: insulating layer, 54: insulating layer, 61: plug, 62: plug, 63: plug, 71: sacrificial layer, 71a: sacrificial layer, 71b: sacrificial layer, 71c: sacrificial layer, 71d: sacrificial layer, 71e: sacrificial layer, 72: sacrificial layer, 73: sacrificial layer, 73a: sacrificial layer, 73b: sacrificial layer, 73c: sacrificial layer, 73d: sacrificial layer, 73e: sacrificial layer, 74: sacrificial layer, 900: semiconductor device, 910: drive 911: Dynamic circuit, 912: Peripheral circuit, 915: Peripheral circuit, 920: Memory array, 923: Row driver, 924: Column driver, 925: Input circuit, 926: Output circuit, 927: Sense amplifier, 928: Voltage generation circuit, 931: PSW, 932: PSW, 941: Row decoder, 942: Column decoder, 950: Memory cell, 951: Memory cell, 952: Memory cell, 953: Memory cell, 954: Memory cell, 955: Memory cell, 956: Memory cell, 957: Memory cell, 958: Memory cell, 980: Electronic component, 981: Semiconductor Device, 982: drive circuit layer, 983: memory layer, 984: mold, 985: land, 986: electrode pad, 987: wire, 988: printed circuit board, 989: mounted board, 990: electronic component, 991: interposer, 992: package board, 993: electrode, 994: semiconductor device, 5600: mainframe computer, 5610: rack, 5620: computer, 5621: PC card, 5622: board, 5623: connection terminal, 5624: connection terminal, 5625: connection terminal, 5626: semiconductor device, 5627: semiconductor device, 5628: semiconductor device, 5629: connection terminal,5630: Motherboard, 5631: Slot, 6800: Satellite, 6801: Aircraft, 6802: Solar Panel, 6803: Antenna, 6804: Planet, 6805: Rechargeable Battery, 6807: Control Unit, 7001: Host, 7001sb: Server, 7002: Storage Control Circuit, 7003: Storage, 7003md: Memory Device, 7010: Storage System

Claims

It comprises a first transistor and a second transistor on the first transistor, The first transistor comprises a first semiconductor layer, a second semiconductor layer on the first semiconductor layer, a first conductive layer, a second conductive layer, a first insulating layer, and a third conductive layer. The second transistor comprises a third semiconductor layer, a fourth semiconductor layer on the third semiconductor layer, a first insulating layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer. The first conductive layer and the second conductive layer are separated from each other and are in contact with the side surface of the first semiconductor layer and the side surface of the second semiconductor layer, respectively. The fourth conductive layer and the fifth conductive layer are separated from each other and are in contact with the upper, lower, and side surfaces of the third semiconductor layer and the upper, lower, and side surfaces of the fourth semiconductor layer, respectively. The third conductive layer has portions located below the first semiconductor layer, between the first and second semiconductor layers, between the second and third semiconductor layers, between the third and fourth semiconductor layers, and above the fourth semiconductor layer, respectively. The first insulating layer has portions located between the first semiconductor layer and the third conductive layer, between the second semiconductor layer and the third conductive layer, between the third semiconductor layer and the third conductive layer, and between the fourth semiconductor layer and the third conductive layer, The first transistor described above is a p-channel transistor, The second transistor is an n-channel transistor, The third semiconductor layer and the fourth semiconductor layer each contain a metal oxide. Semiconductor equipment. 　 In claim 1, Between the first semiconductor layer and the second semiconductor layer, there is a second insulating layer between the first insulating layer and the first conductive layer. On the second semiconductor layer, a third insulating layer is provided between the first insulating layer and the first conductive layer. Semiconductor equipment. 　 In claim 1, Between the third semiconductor layer and the fourth semiconductor layer, the first insulating layer and the third conductive layer are in contact. Semiconductor equipment. 　 In claim 1, Between the third semiconductor layer and the fourth semiconductor layer, and between the first insulating layer and the third conductive layer, the fourth insulating layer is provided. Semiconductor equipment. 　 In claim 1, It further has first to third plugs, The first plug is in contact with the first conductive layer, The second plug is in contact with the fourth conductive layer, The third plug is in contact with the second conductive layer and the fifth conductive layer, Semiconductor equipment. 　 In claim 5, The third plug is in contact with the upper surface of the second conductive layer and the side surface of the fifth conductive layer, Semiconductor equipment. 　 In claim 1, The first semiconductor layer and the second semiconductor layer include silicon. The third semiconductor layer and the fourth semiconductor layer contain indium. The fourth conductive layer and the fifth conductive layer contain indium. Semiconductor equipment.

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