Electronic device

Abstract

Provided is a novel electronic device. This electronic device comprises a housing and a display device. The display device includes a first layer, a second layer, and a third layer. The first layer is provided with a drive circuit unit, a weight switching unit, and a peripheral arithmetic circuit unit. The second layer is provided with a first pixel circuit unit, a second pixel circuit unit, a storage circuit unit, and a multiply-accumulate circuit unit. The third layer is provided with a light-receiving element and a light-emitting element. The storage circuit unit has a function of holding a weight value to be set in the multiply-accumulate circuit unit. The multiply-accumulate circuit unit has a function of performing a multiply-accumulate operation on a weight value set by a current signal of an analog value and an input value based on a signal obtained by the light-receiving element, and outputting an output current corresponding to the multiply-accumulate operation. The peripheral arithmetic circuit unit has a function of performing an arithmetic operation using the output current and outputting an output signal corresponding to the arithmetic operation. The weight switching unit has a function of controlling the storage circuit unit according to the output signal and updating the weight value set in the multiply-accumulate circuit unit.

Description

electronic equipment

[0001] One aspect of the present invention relates to an electronic device. Another aspect of the present invention relates to a wearable electronic device equipped with a display device.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. Examples of technical fields of one aspect of the present invention disclosed herein include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, methods for driving them, or methods for manufacturing them.

[0003] In recent years, Head-Mounted Display (HMD) type electronic devices suitable for applications such as virtual reality (VR) and augmented reality (AR) have become widespread. HMDs can display images in a 360-degree field of view around the observer in response to the user's head movements, gaze, or actions, allowing users to experience a high level of immersion and realism.

[0004] In order to provide a more advanced user experience, it is desirable that the display device provided in the HMD be configured to include not only display functions but also sensing functions. For example, Patent Document 1 discloses a configuration in which a display device provided in the HMD has sensing functions in addition to display functions.

[0005] Furthermore, signals obtained by the sensing function are treated as time-series information or continuous information. Time-series information or continuous information can be processed using neural network techniques such as reservoir computing (RC). For example, Patent Document 2 discloses a semiconductor device capable of performing reservoir computing by implementing a multiply-accumulate circuit between the input layer and the reservoir layer in hardware, and configuring the reservoir layer and output layer in software.

[0006] International Publication No. 2022 / 180481, International Publication No. 2022 / 248963

[0007] In HMDs, when signals obtained from sensing functions are processed using a semiconductor device capable of reservoir computing, a configuration that switches the output layer weight data (sometimes simply called weights) for each function, such as blink detection or goggle attachment / detachment detection, is preferable for improving performance. However, when switching the output layer weights in software, the dynamic weight switching takes time, which impairs usability.

[0008] Furthermore, switching the output layer weights via software requires hardware to control the software. Additionally, switching video displays based on sensing functions requires external hardware for feedback, resulting in a time-consuming process.

[0009] One aspect of the present invention aims to provide an electronic device having a sensing function and a display device with excellent resolution. Alternatively, one aspect of the present invention aims to provide an electronic device having a display device that can reduce power consumption associated with computational processing. Alternatively, one aspect of the present invention aims to provide a novel electronic device that takes into consideration safety and security.

[0010] Furthermore, the description of these problems does not preclude the existence of other problems. Moreover, one aspect of the present invention does not need to solve all of these problems. Other problems can be identified from the description in the specification, drawings, claims, etc.

[0011] One aspect of the present invention is an electronic device comprising a housing and a display device provided inside the housing, wherein the display device is provided in the order of a first layer, a second layer, and a third layer, the first layer being provided with a weight switching unit and a peripheral calculation circuit unit, the second layer being provided with a first pixel circuit unit, a second pixel circuit unit, a memory circuit unit, and a sum-of-accumulate calculation circuit unit, the third layer being provided with a light-receiving element and a light-emitting element, the first pixel circuit unit having a function to control the light-emitting element, the second pixel circuit unit having a function to control the light-receiving element, the memory circuit unit having a function to hold the weight values ​​set in the sum-of-accumulate calculation circuit unit, the sum-of-accumulate calculation circuit unit having a function to perform a sum-of-accumulate calculation on the weight values ​​set by the analog current signal and the input value based on the signal obtained by the light-receiving element, and outputting an output current corresponding to the sum-of-accumulate calculation, the peripheral calculation circuit unit having a function to perform calculations using the output current and outputting an output signal corresponding to the calculation, and the weight switching unit having a function to control the memory circuit unit according to the output signal and update the weight values ​​set in the sum-of-accumulate calculation circuit unit.

[0012] In one embodiment of the present invention, an electronic device is preferred in which the light-emitting element is provided on the display section of the display device, and the light-receiving element is provided in an area outside the display section.

[0013] In one embodiment of the present invention, the first layer is further provided with a drive circuit section, and the weight switching section has the function of outputting a signal to control the drive circuit section in accordance with the signal output from the peripheral calculation circuit section, which is preferable for an electronic device.

[0014] In one embodiment of the present invention, an electronic device is preferred in which the first layer has a first transistor having a semiconductor layer with silicon in the channel formation region, and the second layer has a second transistor having a semiconductor layer with a metal oxide in the channel formation region.

[0015] In one embodiment of the present invention, electronic devices are preferred in which the metal oxide is an oxide containing at least one of indium, element M (where M is Al, Ga, Y, or Sn), or zinc.

[0016] In one embodiment of the present invention, an electronic device is preferred in which the light-receiving element is an organic photodiode and the light-emitting element is an organic electroluminescent element.

[0017] In one embodiment of the present invention, the housing is preferably an electronic device that includes a mounting portion and an optical member.

[0018] Further embodiments of the present invention are described in the following descriptions of embodiments and in the drawings.

[0019] One aspect of the present invention can provide an electronic device having a sensing function and a display device with excellent resolution. Alternatively, one aspect of the present invention can provide an electronic device having a display device that can reduce power consumption associated with computation processing. Alternatively, one aspect of the present invention can provide a novel electronic device that takes into consideration safety and security.

[0020] Furthermore, the description of these effects does not preclude the existence of other effects. Moreover, one aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description in the specification, drawings, claims, etc.

[0021] Figures 1A, 1B, and 1C illustrate examples of display device configurations and electronic device configurations. Figures 2A, 2B, 2C, and 2D illustrate examples of display device configurations. Figures 3A, 3B, and 3C illustrate examples of display device configurations. Figure 4 is a flowchart illustrating a display device. Figure 5 is an example of a display device configuration. Figures 6A and 6B illustrate examples of display device configurations. Figures 7A and 7B illustrate examples of display device configurations. Figure 8 is an example of a display device configuration. Figures 9A and 9B illustrate examples of display device configurations. Figures 10A and 10B illustrate examples of display device configurations. Figure 11 is an example of a display device configuration. Figures 12A, 12B, and 12C illustrate examples of display device configurations. Figure 13 is an example of a display device configuration. Figures 14A and 14B illustrate examples of display device configurations. Figures 15A and 15B illustrate examples of display device configurations. Figures 16A, 16B, 16C, and 16D illustrate examples of display device configurations. Figures 17A, 17B, 17C, and 17D illustrate examples of display device configurations. Figures 18A, 18B, 18C, and 18D illustrate examples of display device configurations. Figures 19A and 19B illustrate examples of display device configurations. Figures 20A and 20B illustrate examples of display device configurations. Figures 21A, 21B, 21C, and 21D illustrate examples of display device configurations. Figure 22 illustrates an example of display device configuration. Figures 23A, 23B, and 23C illustrate examples of display device configurations. Figures 24A and 24B illustrate examples of display device configurations. Figures 25A and 25B illustrate examples of display device configurations. Figure 26 illustrates an example of display device configuration.

[0022] The embodiments will be described below with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different forms, and their form and details can be modified in various ways without departing from the spirit and scope thereof. Accordingly, the present invention shall not be construed as being limited to the contents of the following embodiments.

[0023] Furthermore, in the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings.

[0024] In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion of constituent elements. Therefore, they do not limit the number of constituent elements, nor do they limit the order of the constituent elements. For example, a constituent element referred to as "first" in one embodiment of this specification may be referred to as "second" in another embodiment or in the claims. For example, a constituent element referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0025] (Embodiment 1) This embodiment describes an electronic device according to one aspect of the present invention. The electronic device according to one aspect of the present invention can be suitably used as a wearable electronic device for VR and AR applications.

[0026] <Example of Electronic Device Configuration> Figure 1A is a perspective view of the electronic device 100. The electronic device 100 is a wearable electronic device, and examples include goggles and eyeglasses. For illustrative purposes, Figure 1A shows an eyeglasses-type electronic device with the parts that fit snugly against the face on the sides to protect the eyes omitted.

[0027] The electronic device 100 shown in Figure 1A includes a pair of display devices 10_L and 10_R within a housing 101. Figure 1A also illustrates the user's eyes 102 (eyeballs) when the electronic device 100 is worn.

[0028] The housing 101 has the function of positioning a pair of display devices 10_L and 10_R around the user's eye 102 so that it can capture images of the user's eye 102 and / or the area around the eye 102. For example, as shown in Figure 1A, the pair of display devices 10_L and 10_R are positioned within the housing 101 in a location that overlaps with the eye 102. The housing 101 is also equipped with an acceleration sensor such as a gyro sensor so that it can detect the orientation of the user's head and display an image corresponding to that orientation.

[0029] In this specification, when describing matters common to, for example, display devices 10_L and 10_R, or when there is no need to distinguish between them, the term "display device 10" may be used.

[0030] Figure 1B is a schematic perspective view of a display device 10 applicable to the display devices 10_L and 10_R shown in Figure 1A.

[0031] The display device 10 has a substrate 11 and a substrate 12. The display device 10 has a display unit 13 provided between the substrate 11 and the substrate 12.

[0032] The display unit 13 is the area in the display device 10 that displays images. The display unit 13 is provided with a plurality of pixels 16. Each pixel 16 is provided with a light-emitting element 61 whose light intensity is controlled by a pixel circuit, and a light-receiving element 62 that outputs an electric current (photocurrent) corresponding to the light intensity. The display unit 13, which is provided with pixels 16 having the light-emitting element 61 and the light-receiving element 62, also functions as a light-receiving unit. The light-receiving unit is the area that captures images of the area around the display device 10. The light-receiving element 62 is an element that converts light energy into electrical energy, and is sometimes called a photoelectric conversion element.

[0033] In this specification, the term "element" may sometimes be replaced with "device." For example, display elements, light-emitting elements, and light-receiving elements may be replaced with display devices, light-emitting devices, and light-receiving devices.

[0034] The display device 10 receives various signals and power potentials from the outside via the terminal section 15, and can perform display and imaging on the display unit 13. Between the substrate 11 and the substrate 12, in addition to the layer on which the above-mentioned light-receiving element 62 and light-emitting element 61 are provided, there is a layer on which transistors for performing circuit operation are provided. The layer on which the transistors are provided is provided with a pixel circuit section (also called the first pixel circuit section) that has the function of controlling the light-emitting element 61, a pixel circuit section (also called the second pixel circuit section) that has the function of controlling the light-receiving element 62, a drive circuit section that has the function of controlling each pixel circuit section, a multiply-accumulate operation circuit section and peripheral operation circuit section that have the function of processing the signals generated by the light-receiving element 62, a storage circuit section that stores data for calculations performed by the multiply-accumulate operation circuit section, a weight switching section that switches the weights (also called weight values ​​or weight data) held in the multiply-accumulate operation circuit section, and so on.

[0035] Controlling the light-emitting element means controlling the pixel circuit of the first pixel circuit section to control the emission of light by flowing a current to the light-emitting element according to the image data. Controlling the light-receiving element means controlling the pixel circuit of the second pixel circuit section to control the output of a signal according to the current flowing through the light-receiving element upon receiving light.

[0036] Figure 1C is a schematic diagram illustrating a case where a display device 10, which includes a display unit 13 for displaying and capturing images, is installed in a position close to the user's eye 102.

[0037] The user's eye 102 can see the image through the light 13A from the light-emitting element 61 in the display unit 13. The light 13A may include not only visible light but also infrared light and other types of light.

[0038] Furthermore, the reflected light 14A from the user's eye 102 and / or its surroundings is converted into an electrical signal by a light-receiving element 62 in the display unit 13. The information acquired by the light-receiving element 62 can be imaging data of the eyeball (or the state of the pupil) and / or imaging data of the movement around the eyeball (e.g., eyelids, glabella, inner corner of the eye, outer corner of the eye, etc.).

[0039] <Examples of arrangement of display unit and light receiving unit> In Figure 1B, the display device 10 is described as having a display unit 13 that performs both display and imaging. However, it is also possible to arrange the display unit that performs the display and the light receiving unit that performs imaging in separate areas. Figures 2A to 2D are schematic diagrams illustrating examples of the arrangement of the display unit 13 that performs the display and the light receiving unit 14 that performs imaging.

[0040] By arranging the display area 13 and the light-receiving area 14 in separate locations, the layout density of the light-emitting element 61 and the light-receiving element 62 can be made different. As a result, the light-receiving area 14 can be positioned without compromising the resolution of the display area 13. In addition, fragmented information about the area around the eye (including the eye) can be acquired.

[0041] In the example shown in Figure 2A, a configuration is illustrated in which the area of ​​the display unit 13 and the area of ​​the light-receiving unit 14 are located in separate positions. In Figure 2A, the light-receiving unit 14 is arranged in a line, touching both ends of the display unit 13. If the image captures an up-and-down movement of the eyelids, such as blinking, it can be detected by the line-shaped light-receiving unit 14. By detecting the movement of the eyelids in this way, the calculation circuit connected to the light-receiving unit 14 can perform inference operations according to whether or not blinking has occurred. Note that the light-receiving unit 14, which can be arranged in a line, can also be configured to be touching one side of the display unit 13, as shown in Figure 2B.

[0042] Furthermore, in the example shown in Figure 2C, a configuration is illustrated in which the light-receiving unit 14 is arranged to surround the display unit 13. In Figure 2C, the light-receiving unit 14 is arranged in a ring shape outside the display unit 13. In this configuration in which the light-receiving unit 14 is arranged in a ring shape, it is possible to detect movements around the eyeball, such as the eyelids, the space between the eyebrows, the inner corner of the eye, and the outer corner of the eye. Therefore, for example, the arithmetic circuit connected to the light-receiving unit 14 can perform gaze direction inference without capturing images of eyeball movement. Thus, in one embodiment of the present invention, even if the acquired information around the eyes is fragmentary, it is possible to infer the user's state.

[0043] Furthermore, the light-receiving section 14, which can be arranged in an annular shape, is preferably configured as a display section 13 larger than the size of the eye 102, and is provided around it, as shown in Figure 2D. In this case, the panel size L of the display device 10 Ｄ By setting the diagonal size to 0.1 inches to 5 inches, preferably 0.5 inches to 3 inches, more preferably 1 inch to 2 inches, more preferably 1.3 inches to 1.7 inches, and even more preferably 1.5 inches to 1.6 inches, a configuration can be made in which a display unit 13 and a light-receiving unit 14 corresponding to the size of the eye 102 can be provided. With this configuration, when the display device 10 is brought close to the user's eye 102, information about the user's eye 102 and its surroundings can be acquired by the light-receiving unit 14, and the field of view of the image displayed on the display unit 13 can be enlarged.

[0044] <Example of Display Device Configuration> The configuration of the display device 10 shown in Figure 1B will be explained with reference to Figures 3A to 7B. The display devices applicable to display devices 10_L and 10_R have an RC calculation circuit section that can perform calculation processing based on an algorithm used in reservoir computing (also called the "RC model"). The RC calculation circuit section can switch functions such as blink detection and goggle attachment / detachment detection depending on the switching of weight values ​​(hereinafter referred to as weights).

[0045] Here, we will explain RC models. Known RC models include LSM (Liquid State Machine), ESN (Echo State Network), and FORCE (First Order Reduced and Controlled Error).

[0046] Figure 3A shows an example configuration of an ESN as the RC model 190. The RC model 190 consists of an input layer 191, a reservoir layer 192, and an output layer 193. The reservoir layer 192 corresponds to a hidden layer.

[0047] The input layer 191 includes a node 194. The data u(t) represents the value of node 194 at time t. Although Figure 3A shows one node 194, the input layer 191 may have multiple nodes 194. For example, the input layer 191 may have M nodes 194 (where M is an integer greater than or equal to 1).

[0048] The reservoir layer 192 comprises multiple nodes 195. The data x(t) represents the value of node 195 at time t. Although Figure 3A shows six nodes 195, the number of nodes 195 is not limited to these. For example, the reservoir layer 192 may comprise N nodes 195 (where N is an integer greater than or equal to 2).

[0049] The output layer 193 includes a node 196. The data z(t) represents the value of node 196 at time t. Although Figure 3A shows one node 196, the output layer 193 may have multiple nodes 196. For example, the output layer 193 may have K nodes 196 (where K is an integer greater than or equal to 1).

[0050] Furthermore, in Figure 3A, the weight of the connection between node 194 and node 195 is "weight W". ｉ It also indicates that the weight of the connection between node 195 and node 196 is "weight W". ｏ It is shown that the N nodes 195 of the reservoir layer 192 are irregularly connected to each other. In Figure 3A, the weight of the connections between the nodes 195 is shown as "weight W". ｒ This indicates that...

[0051] Node 194 is connected to multiple nodes 195. In this case, in the RC model 190 shown in Figure 3A, each has a weight W. ｉ The values ​​are determined and fixed to irregular positive and negative values. Also, the data u(t) and the weight W ｉ The sum of these values ​​is supplied to node 195.

[0052] Furthermore, in the reservoir layer 192, the weight W of the connections between the nodes 195 ｒis determined and fixed to irregular positive and negative values. Therefore, the data supplied from the reservoir layer 192 to the output layer 193 becomes non-linear data. In the connection between nodes 195, the value obtained by integrating the weight W ｒ with the data x(t) of the node 195 on the side supplying the data is supplied to the node 195 on the side to which the data is supplied.

[0053] In a recurrent neural network (RNN: Recurrent Neural Network) that handles time-series data in the same way as the RC model, a large amount of teacher data and a long learning time are required to determine the weights W ｉ the weights W ｒ and the weights W ｏ . Therefore, the RNN has a high computational cost. On the other hand, in the RC model, the weights W ｉ and the weights W ｒ are fixed, and only the learning (optimization) of the weights W ｏ is performed. Therefore, the optimization of the weights W ｏ can be completed with less teacher data and less learning time. Therefore, the RC model consumes less power during learning than the RNN. Also, the RC model has a lower computational cost than the RNN.

[0054] The RC model 190 shown in FIG. 3A can be represented by equations (1) to (3). Equation (1) is a mathematical formula for the data x(t). Equation (2) is a mathematical formula for obtaining the weight W ｏ . Equation (3) is a mathematical formula for obtaining the data z(t).

[0055]

[0056]

[0057]

[0058] X represents a matrix of x(t). f represents an activation function. δ represents a leakage rate. T represents a transposed matrix. I represents an identity matrix. Y ｔａｒｇｅｔ represents teacher data. <0000​For example, when analyzing time-series changes in images captured by an image sensor, such as detecting the putting on or taking off of goggles or detecting eye blinking, RNNs are computationally expensive and difficult to implement in hardware due to their complex layer structure. By incorporating the algorithm of an RC model into an image sensor or processor, computational processing can be performed with low power consumption.

[0060] In the RC model described above, for example, the weight W ｏ By switching this, the output data z(t) can be switched according to the input data u(t). In other words, the weight W changes according to the data being captured. ｏ By switching this setting, you can change the object being detected.

[0061] For example, Figure 3B schematically represents an RC model for detecting the putting on or taking off of goggles. The light-receiving element 62 located in the display unit 13 can amplify the current obtained by imaging the user's eye 102 and input it to the input layer 191. The input layer 191 has a weight W ｉ The weights are fixed and can output data corresponding to the sum-of-products operation with the input data. The reservoir layer 192 has weights W ｒ The weight W is fixed and can output data corresponding to the sum-of-products operation with the input data. The output layer 193 has a weight W ｏ W ｏ１ By switching to (W ｏ = W ｏ１ ), output signal S corresponding to the wearing of goggles ＯＵＴ＿１ and output signal S corresponding to goggles not being worn ＯＵＴ＿２ It can output the output signal S. ＯＵＴ＿１ and S ＯＵＴ＿２ The system can detect whether the goggles are being attached or removed based on their relative size.

[0062] Figure 3C, for example, schematically represents an RC model for detecting abnormal blinking.

[0063] Figure 4 is an example of a flowchart for switching the weights of the output layer in the RC model shown in Figures 3B and 3C.

[0064] Initially, the system switches to goggle attachment / detachment detection mode (step S31).

[0065] The weights of the RC model are fixed weights, namely weights W. ｉ , W ｒ Weight W for detecting when goggles are put on or taken off. ｏ１ Update to (step S32).

[0066] Based on the data entered into the RC model, a determination is made as to whether or not goggles are being worn (step S33). If goggles are not being worn, the determination of whether or not goggles are being worn continues (NO). If goggles are being worn (YES), the process proceeds to step S34.

[0067] With the goggles in place, the system switches to blink detection mode for the user's eyes (step S34).

[0068] The weights of the RC model are fixed weights, namely weights W. ｉ , W ｒ A weight W is used to maintain and detect abnormal blinking. ｏ２ Update to (step S35).

[0069] Based on the data input to the RC model, a determination is made as to whether or not there is abnormal blinking (step S36). If no abnormal blinking is detected, the determination of whether or not there is abnormal blinking continues (NO). If abnormal blinking is detected (YES), the process proceeds to step S37.

[0070] If abnormal blinking is detected and a warning is required for the user, the system performs processes such as displaying a warning image on the display unit and stopping the drive circuit unit (step S37).

[0071] As shown in Figures 3A to 3C and Figure 4, in the RC model, the function detected by the output signal can be switched by switching the weights of the output layer 193. Therefore, a display device having an arithmetic circuit unit capable of executing the RC model can be equipped with a memory circuit unit for holding the weights of the output layer and a weight switching unit that outputs a signal to switch the weights according to the output signal, enabling high-speed dynamic weight switching in response to function switching such as blink detection and goggle attachment / detachment detection. As a result, it is possible to create an electronic device with excellent convenience. Furthermore, since the operation of switching the weights can be configured to be executed by the hardware within the display device, it is possible to shorten the time required for a series of processes.

[0072] Next, an example of a configuration that allows dynamic weight switching in a display device having a calculation circuit unit capable of executing the above RC model will be explained using the block diagram in Figure 5.

[0073] The display device 10 shown in Figure 5 includes a display unit 13 having a light-emitting element 61 and a light-receiving element 62, a pixel circuit unit 55, a pixel circuit unit 57, a sum-of-accumulate operation circuit unit 59, a memory circuit unit 63, a peripheral operation circuit unit 48, a weight switching unit 49, and a drive circuit unit 47. The sum-of-accumulate operation circuit unit 59 and the peripheral operation circuit unit 48 are circuits that perform calculations to execute the RC model. In Figure 5, the sum-of-accumulate operation circuit unit 59 and the peripheral operation circuit unit 48 are combined to form the RC operation circuit unit 45.

[0074] Each block of the display device 10 will be described below. The description of each block will also be explained in conjunction with the series of operations for switching the weights of the output layer in the RC model.

[0075] The light-receiving element 62 generates an electric current I when light is shone upon it. ＰＳ A small current I flows through the photodetector 62. The pixel circuit section 57 has a pixel circuit provided for each of the multiple photodetector 62. The pixel circuit section 57 has a pixel circuit, which allows a small current I to flow through the photodetector 62. ＰＳ The current I amplified by the pixel circuit section 57 can be output. ＰＳThe signal corresponding to its magnitude can be used as input data u(t) (also called the input value) for the RC model.

[0076] The memory circuit 63 has the function of holding the weights set in the sum-of-accumulate circuit 59. One example is the weight W, which is a fixed value weight. ｉ , W ｒ The data is switched and used accordingly; the weights are W. ｏ (W ｏ１ , W ｏ２ The system includes multiple memory circuits that hold data corresponding to the operation. The memory circuit section 63 also has the function of holding data calculated by the operation of the sum-of-accumulate circuit section 59. For example, it includes multiple memory circuits that hold data x(t-1) calculated by the operation of the sum-of-accumulate circuit section 59.

[0077] Data x(t-1) corresponds to the data in the reservoir layer at time t-1. Data x(t-1) and data x(t) at time t are also called time-series data. The time-series data is sequentially calculated by sum-of-products operations between the input data and various weights in the sum-of-products operation circuit 59 and output to the memory circuit 63 and peripheral operation circuit 48.

[0078] Various data stored in the memory circuit unit 63 can be read out to the sum-of-accumulate circuit unit 59 as needed. The control of the memory circuit unit 63 can be switched according to the control of the weight switching unit 49.

[0079] The sum-of-products calculation circuit unit 59 has the function of performing a sum-of-products calculation between weights set by analog current signals and input data based on signals obtained by the photodetector 62, and outputting an output current corresponding to the calculation. For example, the sum-of-products calculation circuit unit 59 includes multiple sum-of-products calculation circuits that hold weights set by analog current signals and can supply an output current corresponding to the sum-of-products calculation between the weights and the input data.

[0080] In the sum-of-accumulate circuit 59, the fixed weight W read from the memory circuit 63 is used. ｉ , W ｒWhile maintaining the current, by providing the leakage rate σ, input data u(t), and data x(t-1), a current corresponding to the integration flows, and a current corresponding to the sum of these currents can be generated as a current of a magnitude corresponding to the sum-of-products calculation. Therefore, the sum-of-products calculation circuit 59 can perform a sum-of-products calculation based on the above-described equation (1) and output data x(t) as an output current. The sum-of-products calculation circuit 59 can maintain the weight of the analog value written according to the minute current for a long time. Therefore, the sum-of-products calculation circuit 59, which performs sum-of-products calculations using minute currents, can perform calculations with excellent computational efficiency.

[0081] In the sum-of-accumulate circuit 59, the weights W, which are weights that are switched and used, are stored in the memory circuit 63. ｏ (W ｏ１ , W ｏ２ By holding the data ) and providing data u(t) or data x(t), the sum-of-products operation based on equation (3) described above can be performed to output data z(t) as the output current. Data z(t) corresponds to the data of the output layer at time t.

[0082] The peripheral arithmetic circuit section 48 has the function of performing calculations using the output current flowing through the sum-of-products circuit section 59 and outputting an output signal corresponding to the calculation. For example, it has the function of outputting various data for performing sum-of-products calculations in the sum-of-products circuit section 59, and performing calculation processing on the data x(t) and z(t) obtained by the sum-of-products circuit section 59. The calculations performed by the peripheral arithmetic circuit section 48 include calculations based on activation functions such as the tanh function and the ReLU function, which are calculations other than sum-of-products calculations in the RC model.

[0083] The RC arithmetic circuit unit 45, which has a sum-of-products circuit unit 59 and a peripheral arithmetic circuit unit 48, has a function to control the execution of sum-of-products calculations using minute analog currents. This configuration reduces power consumption compared to a configuration that performs sum-of-products calculations using digital signals. The RC arithmetic circuit unit 45 takes a signal based on the minute current flowing through the photodetector 62 as input data and can obtain an output current corresponding to the result of the sum-of-products calculation with the weights held in the sum-of-products circuit unit 59. The RC arithmetic circuit unit 45 can perform calculation processing based on the RC model using the obtained output current. The calculation result obtained by the calculation processing is output signal S ｏｕｔ The output is then sent from the RC calculation circuit unit 45 to the weight switching unit 49.

[0084] The weight switching unit 49 controls the memory circuit unit 63 by sending a signal S according to the calculation result in the RC calculation circuit unit 45. ｊ It has the function of outputting signal S. ｊ This is the weight W, which is set in the sum-of-accumulate circuit unit 59. ｏ This is a signal for controlling the memory circuit unit 63 to switch between weights. The weight switching operation can be performed within the hardware of the display device, such as by transmitting a signal from the weight switching unit 49 to the memory circuit unit 63, thereby shortening the time required for the series of processes.

[0085] Also, signal Y ｊ This unit has functions to control the stopping of the drive circuit unit 47 or the switching of images displayed on the display unit 13. Therefore, if there is a concern that the user's health may be compromised due to prolonged use of an electronic device that provides a high level of immersion, a warning can be issued to the user during use. As a result, the electronic device can be made with safety and security in mind.

[0086] The drive circuit section 47 includes, for example, a gate driver circuit GD, a source driver circuit SD, and a display control circuit 41. The display control circuit 41 has the function of controlling the gate driver circuit GD and the source driver circuit SD in response to external signals such as those from the weight switching section 49. The gate driver circuit GD and the source driver circuit SD output signals GS and DS (for example, GS is a signal to drive the gate line, and DS is a signal corresponding to the image data) for controlling the pixel circuit sections 55 and 57.

[0087] The pixel circuit section 55 supplies a current I corresponding to the image data to the light-emitting element 61 in the display section 13. ＥＬ It outputs the following. The light-emitting element 61 (not shown) in the display unit 13 in layer 60 emits current I ＥＬ The system emits light accordingly, allowing the user to view the image.

[0088] As described above, the display device 10 having the blocks shown in Figure 5 can be configured to perform the weight switching operation in the RC model within the hardware of the display device, such as transmitting signals from the weight switching unit 49 to the memory circuit unit 63. Therefore, a series of processes to switch the weights of the output layer for each function, such as blink detection and goggle attachment / detachment detection, can be performed at high speed.

[0089] Figure 6A is a schematic perspective view showing the configuration of each layer provided between substrate 11 and substrate 12 in the display device 10 shown in Figure 1B. Figure 6A also shows how each layer is provided with respect to the block diagram shown in Figure 5.

[0090] A layer 40 is provided on the substrate 11. Layer 40 may include, for example, a drive circuit section 47, a weight switching section 49, and a peripheral calculation circuit section 48. Layer 40 has a silicon transistor 42 (also called a Si transistor) in its channel formation region 44. The substrate 11 is, for example, a silicon substrate. A silicon substrate is preferred because it has higher thermal conductivity compared to a glass substrate. Layer 40 may sometimes be referred to as the first layer.

[0091] The transistor 42 can be, for example, a transistor having single-crystal silicon in its channel formation region. In particular, using a transistor having single-crystal silicon in its channel formation region as the transistor provided in layer 40 allows for a large on-current of the transistor. Therefore, it is preferable because it allows the circuit of layer 40 to be driven at high speed. Furthermore, Si transistors can be formed with microfabrication such as a channel length of 3 nm to 10 nm. Therefore, it is possible to provide a peripheral arithmetic circuit section 48 that performs calculations other than sum-of-accumulate operations based on the RC model.

[0092] As described above, the drive circuit section 47 includes a gate driver circuit, a source driver circuit, etc. The gate driver circuit, source driver circuit, etc. can be arranged on top of the display section 13. Therefore, compared to the case where the drive circuit section 47 and the display section 13 are arranged side by side, the width of the non-display area (also called a frame) on the outer periphery of the display section 13 of the display device 10 can be made extremely narrow, enabling the realization of a compact display device 10. Furthermore, when arranged on the outer periphery of the display section 13 of the display device 10, the gate driver circuit and source driver circuit are arranged in a concentrated manner on the outer periphery, but the drive circuit section 47 can be divided into multiple sections and arranged in the area overlapping with the display section 13.

[0093] The peripheral arithmetic circuit unit 48, together with the sum-accumulate circuit unit 59, has the function of performing calculations based on the RC model. The peripheral arithmetic circuit unit 48, together with the sum-accumulate circuit unit 59, can perform inference processing regarding the state of the user wearing the electronic device based on the acquired imaging data by repeatedly performing sum-accumulate calculations on the input time-series data.

[0094] The weight switching unit 49 receives output signals corresponding to the calculation processing from the peripheral calculation circuit unit 48. The weight switching unit 49 can output signals to control the memory circuit unit 63 for switching weights held in the sum-of-accumulate calculation circuit unit 59, stop the drive circuit unit 47, or switch the image displayed on the display unit. Therefore, if there is a concern that the user's health may be harmed by using an electronic device that provides a high level of immersion for a long period of time, a warning can be issued to the user during use. As a result, the electronic device can be made with safety and security in mind.

[0095] A layer 50 is provided on layer 40. Layer 50 is provided with a pixel circuit section 55, a pixel circuit section 57, a memory circuit section 63, and a multiply-accumulate circuit section 59. Layer 50 has a transistor 52 (also called an OS transistor) having a metal oxide (also called an oxide semiconductor) in the channel formation region 54. Layer 50 can be configured to be stacked on layer 40. It is also possible to form layer 50 on a separate substrate and then bond it together.

[0096] It is preferable to use an OS transistor (transistor 52) that has an oxide containing at least one of indium, element M (where element M is aluminum, gallium, yttrium, or tin), and zinc in its channel formation region. Such an OS transistor has the characteristic of having a very low off-current. Therefore, it is preferable to use an OS transistor as the transistor provided in the pixel circuit section 55, pixel circuit section 57, memory circuit section 63, and multiply-accumulate circuit section 59, because it can retain analog data, which is the potential of the analog value written to the pixel circuit section 55, pixel circuit section 57, memory circuit section 63, and multiply-accumulate circuit section 59, for a long period of time.

[0097] The pixel circuit section 55 has the function of controlling the light emission of the light-emitting element 61. The pixel circuit section 55 is provided with a plurality of pixel circuits that control the light emission of the light-emitting element 61. By arranging the pixel circuit section 55 in a separate area from the pixel circuit section 57, the memory circuit section 63, and the multiply-accumulate operation circuit section 59, it becomes possible to arrange the plurality of pixel circuits in the pixel circuit section 55 at an extremely high density. As a result, the pixel resolution can be made extremely high in the pixel circuit section 55.

[0098] The pixel circuit section 57 has the function of controlling the reception of light by the photodetector 62. The pixel circuit section 57 is provided with multiple pixel circuits that control the output of signals corresponding to the reception of light by the photodetector 62. The pixel circuit section 57 is provided with multiple pixel circuits that hold, amplify, and output the photocurrent generated by the reception of light by the photodetector 62. Furthermore, the pixel circuits in the pixel circuit section 57 are located close to the photodetector 62. Therefore, even if the current flowing due to the reception of light by the photodetector 62 is a very small current, it can be amplified and output.

[0099] The sum-of-accumulate circuit unit 59 has the function of holding weights set by analog current signals and the function of performing sum-of-accumulate calculations between the weights and input data. The sum-of-accumulate circuit unit 59 has multiple sum-of-accumulate circuits that hold weights set by analog current signals and perform sum-of-accumulate calculations between the weights and input data. The sum-of-accumulate circuits can be divided into reference cells and calculation cells depending on their function. The sum-of-accumulate circuits can hold analog data written in response to minute currents for a long time. Furthermore, the sum-of-accumulate circuit unit 59, which performs sum-of-accumulate calculations using minute currents, can perform calculations with excellent computational efficiency.

[0100] A layer 60 is provided on layer 50. A substrate 12 is provided on layer 60. The substrate 12 is preferably a light-transmitting substrate or a layer made of a light-transmitting material. Layer 60 has a display section 13 on which a plurality of light-emitting elements 61 and a plurality of light-receiving elements 62 are provided. Layer 60 can be configured to be stacked on layer 50. As the light-emitting elements 61, for example, an organic electroluminescent element (also called an organic EL element) can be used. However, the light-emitting elements 61 are not limited to this, and for example, an inorganic EL element made of an inorganic material may be used. Note that "organic EL elements" and "inorganic EL elements" are sometimes collectively referred to as "EL elements". The light-emitting elements 61 may have an inorganic compound such as a quantum dot. For example, quantum dots can be used as a light-emitting layer to function as a light-emitting material. As the light-receiving element 62, for example, an organic photodiode can be used.

[0101] As shown in Figure 6A, a display device 10 according to one aspect of the present invention can have a stacked configuration of a light-emitting element 61, a pixel circuit section 55, and a drive circuit section 47, which allows for an extremely high aperture ratio (effective display area ratio) of pixels. Furthermore, the pixel circuits 51 can be arranged at an extremely high density, allowing for an extremely high resolution of pixels. Because such a display device 10 is extremely high-resolution, it can be suitably used in VR devices such as head-mounted displays, or AR devices in the form of glasses. For example, even in a configuration where the display section of the display device 10 is viewed through an optical element such as a lens, the display device 10 has an extremely high-resolution display section, so even when the display section is magnified with a lens, pixels are not visible, enabling a highly immersive display.

[0102] As shown in Figure 6A, the display device 10 according to one embodiment of the present invention can be configured by stacking a light-receiving element 62, a pixel circuit unit 57, a memory circuit unit 63, a multiply-accumulate circuit unit 59, a peripheral calculation circuit unit 48, and a weight switching unit 49. Therefore, it is possible to use the minute current output by the light-receiving element 62 as input data and perform a multiply-accumulate calculation based on the input data and the held weights. Furthermore, by configuring the device to enable weight switching according to the calculation result, it is possible to perform calculation processing with excellent calculation efficiency. In addition, the display device 10 can be configured to place the light-receiving unit 14 close to the display unit 13, so that the user can view the image with their eyes and capture images of the user's eyes and / or surrounding area. Furthermore, the multiply-accumulate circuit unit 59 can hold the analog data written according to the minute current for a long time. Furthermore, the multiply-accumulate circuit unit 59, which performs multiply-accumulate calculations using minute currents, can perform calculations with excellent calculation efficiency.

[0103] Figure 6B also shows block diagrams of the configurations of layers 40, 50, and 60 in Figure 6A. The drive circuit unit 47 in layer 40 outputs signals GS and DS (for example, GS is a signal to drive the gate line, and DS is a signal corresponding to the image data) to control the pixel circuit unit 55 in layer 50. The pixel circuit unit 55 in layer 50 supplies a current I corresponding to the image data to the light-emitting element 61 in layer 60. ＥＬ It outputs the following. The light-emitting element 61 (not shown) in the display unit 13 in layer 60 emits current I ＥＬ The system emits light accordingly, allowing the user to view the image.

[0104] Furthermore, in the block diagram shown in Figure 6B, the light-receiving element 62 in layer 60 captures an image of the area around the user's eyes, causing a current I to flow. ＰＳ Outputs current I ＰＳ This is amplified by the pixel circuit section 57 in layer 50 and output as data u(x) to the sum-of-accumulate circuit section 59 in layer 50. The memory circuit section 63 stores the weight W ｉ , W ｒ The data is switched and used accordingly; the weights are W. ｏ (W ｏ１ , W ｏ２The layer 50 holds data and data x(t-1) corresponding to the weights and outputs them to the sum-of-accumulate circuit unit 59 in layer 50. The sum-of-accumulate circuit unit 59 in layer 50 outputs data x(t-1) corresponding to the sum-of-accumulate calculation of the held weights and the input data to the memory circuit unit 63. The sum-of-accumulate circuit unit 59 in layer 50 also outputs data x(t) and z(t) corresponding to the sum-of-accumulate calculation of the held weights and each input data to the peripheral arithmetic circuit unit 48. The peripheral arithmetic circuit unit 48 in layer 40 outputs an output signal to the weight switching unit 49, which in turn controls the memory circuit unit 63 to switch the weights held by the sum-of-accumulate circuit unit 59 in layer 50.

[0105] The layer 50 provided on layer 40 can have a structure of two or more layers. For example, as shown in the display device 10A in Figure 7A, it can have layers 50_1 and 50_2, each having a transistor 52 which is an OS transistor. In Figure 7A, layer 50_1 is provided with a pixel circuit section 55 and a pixel circuit section 57, and layer 50_2 is provided with a memory circuit section 63 and a multiply-accumulate circuit section 59. This configuration allows for a larger area to be provided for the pixel circuit section 55 and 57, as well as the memory circuit section 63 and the multiply-accumulate circuit section 59.

[0106] Figure 7B shows block diagrams of the configurations of layers 40, 50_1, 50_2, and 60 in Figure 7A, similar to Figure 6B. As shown in Figure 7B, the drive circuit section 47 in layer 40 and the pixel circuit section 55 in layer 50_1 are connected via layer 50_2. It is preferable to have layers for wiring between layer 40 and layer 50_2, and between layer 50_1 and layer 50_2, as this facilitates the connection of circuits between different layers.

[0107] As shown in Figure 7B, the light-receiving element 62 in layer 60 and the sum-of-accumulate circuit unit 59 in layer 50_2 are connected via layer 50_1, which has a pixel circuit unit 57. It is preferable to have layers with wiring between layer 60 and layer 50_1, and between layer 50_1 and layer 50_2, as this makes it easier to connect circuits between different layers.

[0108] As described above, one aspect of the present invention can be configured by stacking a light-emitting element, a pixel circuit section that controls the light-emitting element, and a drive circuit section that controls the pixel circuit section. The drive circuit section, which is a peripheral circuit, can be placed on top of the pixel circuit section, and the width of the bezel can be made extremely narrow, so that a miniaturized and lightweight display device can be made. For this reason, one aspect of the present invention can be an electronic device with excellent mountability.

[0109] Furthermore, one aspect of the present invention allows for a lightweight display device by stacking the circuits, thereby shortening the wiring connecting the circuits. Additionally, one aspect of the present invention allows for a display unit with increased pixel resolution. Therefore, an electronic device equipped with this display device can be an electronic device with superior display quality.

[0110] Furthermore, in one aspect of the present invention, the display device can have a stacked configuration comprising a memory circuit unit that provides an input value corresponding to the current flowing through a light-receiving element, and an arithmetic circuit unit that provides weight values ​​to the memory circuit unit. Since the distance between the light-receiving element and the sum-of-products arithmetic circuit unit, and the distance between the memory circuit unit and the sum-of-products arithmetic circuit unit can be brought closer together, the minute current flowing through the light-receiving element can be used as the input value for the sum-of-products arithmetic circuit unit. In addition, the time-series data obtained by the sum-of-products arithmetic circuit unit can be efficiently stored in the memory circuit unit. Furthermore, the data corresponding to the weights stored in the memory circuit unit can be efficiently stored in the sum-of-products arithmetic circuit unit.

[0111] Furthermore, in an electronic device equipped with a display device according to one aspect of the present invention, a light-receiving element can be arranged in the display unit, or in a configuration in which a light-receiving element is arranged near the display unit, allowing the user to view the image with their eyes and simultaneously capture images of the user's eyes and / or surrounding area. In addition, the cell array in the display device can retain analog data written in response to minute currents for a long period of time. The multiply-accumulate circuit unit using minute currents can perform calculations with excellent computational efficiency.

[0112] <Example of the configuration of the sum-of-accumulate circuit section> As described above, the display device 10 applicable to the display devices 10_L and 10_R shown in Figures 1A and 1B has a sum-of-accumulate circuit section 59 that is capable of sum-of-accumulate calculations. Below, the sum-of-accumulate circuit 58, which has a sum-of-accumulate circuit section 59 that is capable of holding data according to weights and performing sum-of-accumulate calculations using the held weight data, will be described. Figure 8 is a diagram for illustrating the sum-of-accumulate circuit 58.

[0113] The sum-of-accumulate circuit 58 has a reference cell 21 and an operation cell 31. The reference cell 21 has transistors 22, 23, 24, and a capacitance element 25. The operation cell 31 has transistors 32, 33, 34, and a capacitance element 35. The transistors and capacitances in the reference cell 21 and the operation cell 31 are connected to at least one of the wirings WSL, XCL, VBL, WCL, and a ground potential wiring, as shown in Figure 8.

[0114] The reference cell 21 has the function of executing calculation operations in the calculation cell 31 by allowing a set current to flow during data writing and data reading. Specifically, during data writing, the reference cell 21 maintains a reference voltage within the reference cell 21 by allowing a reference current to flow, and then, during data reading, it has the function of controlling the current flowing to the calculation cell 31 by allowing a current corresponding to the input data (x) given to the calculation cell 31 to flow through the reference cell 21. Note that the reference cell 21 is sometimes simply referred to as a cell.

[0115] Next, I will explain the connection relationships within reference cell 21.

[0116] The gate of transistor 22 is connected to wiring WSL. One of the sources or drains of transistor 22 is connected to one of the sources or drains of transistor 23 and wiring XCL. The other of the sources or drains of transistor 22 is connected to the gate of transistor 24 and one electrode of capacitive element 25. Transistor 22 can write the reference voltage to the holding node (gate of transistor 24) in the reference cell 21 when it is in the ON state during data writing, and can hold the reference voltage in the reference cell 21 when it is in the OFF state.

[0117] The gate of transistor 23 is connected to wiring VBL. The back gate of transistor 23 is connected to the other source or drain of transistor 24. One source or drain of transistor 23 is connected to one source or drain of transistor 22 and wiring XCL. The other source or drain of transistor 23 is connected to one source or drain of transistor 24. Transistor 23 sets the potential of one source or drain of transistor 24 to a potential corresponding to the potential of the gate of transistor 23.

[0118] The gate of transistor 24 is connected to the other side of the source or drain of transistor 22, and to one electrode of the capacitive element 25. The node to which the gate of transistor 24, the other side of the source or drain of transistor 22, and one electrode of the capacitive element 25 are connected is also called a holding node. The holding node can be set to a potential corresponding to the current flowing through transistor 24. The back gate of transistor 24 is connected to the other side of the source or drain of transistor 24. The other side of the source or drain of transistor 24 is connected to a wire that provides a low power supply potential (e.g., ground potential). This wire that provides the ground potential functions as a wire for current to flow between the source and drain of transistor 24. The other side of the source or drain of transistor 24 is connected to the back gate of transistor 23 and the back gate of transistor 24. A fixed potential is applied to the back gates of transistor 23 and transistor 24, stabilizing the transistor characteristics of transistors 23 and 24. Transistor 24 flows an output current corresponding to the potential of its gate to the other side of the source or drain.

[0119] One electrode of the capacitive element 25 is connected to the other side of the source or drain of transistor 22 and to the gate of transistor 24. The other electrode of the capacitive element 25 is connected to wiring XCL. When one electrode of the capacitive element 25 is in an electrically floating state, it changes the potential of one electrode in response to a change in the potential of the other electrode.

[0120] The calculation cell 31 has the function of maintaining a voltage corresponding to the weight data (w) it holds when data is written by supplying a current corresponding to that current. Furthermore, when data is read, the calculation cell 31 has the function of supplying a current corresponding to the calculation of the weight data and input data by boosting the voltage held during data writing in accordance with the current flowing through the reference cell 21. Note that the calculation cell 31 is sometimes simply referred to as a cell.

[0121] Weight data (w) is sometimes referred to as the first data, and input data (x) as the second data. Note that weight data corresponds to the weights of the input layer, reservoir layer, and output layer in the RC model described above. Input data corresponds to time series data such as data u(t) and z(t) in the RC model described above.

[0122] Next, I will explain the connections within the calculation cell 31.

[0123] The gate of transistor 32 is connected to wiring WSL. One of the sources or drains of transistor 32 is connected to one of the sources or drains of transistor 33 and wiring WCL. The other of the sources or drains of transistor 32 is connected to the gate of transistor 34 and one electrode of capacitive element 35. Transistor 32 can be turned on during data writing to write a voltage corresponding to the weight data into the calculation cell 31, and can be turned off to retain a voltage corresponding to the weight data in the calculation cell 31.

[0124] The gate of transistor 33 is connected to wiring VBL. The back gate of transistor 33 is connected to the other source or drain of transistor 34. One source or drain of transistor 33 is connected to one source or drain of transistor 32 and wiring WCL. The other source or drain of transistor 33 is connected to one source or drain of transistor 34. Transistor 33 sets the potential of one source or drain of transistor 34 to a potential corresponding to the potential of the gate of transistor 33.

[0125] The gate of transistor 34 is connected to the other source or drain of transistor 32 and to one electrode of the capacitive element 35. The node to which the gate of transistor 34, the other source or drain of transistor 32, and one electrode of the capacitive element 35 are connected is also called a holding node. The back gate of transistor 34 is connected to the other source or drain of transistor 34. The other source or drain of transistor 34 is connected to a wire that provides a low power supply potential (e.g., ground potential). This wire that provides the ground potential functions as a wire for current to flow between the source and drain of transistor 34. The other source or drain of transistor 34 is connected to the back gate of transistor 33 and the back gate of transistor 34. A fixed potential is applied to the back gates of transistor 33 and transistor 34, stabilizing the transistor characteristics of transistors 33 and 34. Transistor 34 flows an output current to the other source or drain corresponding to the potential of its gate.

[0126] One electrode of the capacitive element 35 is connected to the other source or drain of transistor 32 and to the gate of transistor 34. The other electrode of the capacitive element 35 is connected to wiring XCL. When one electrode of the capacitive element 35 is floating, it changes the potential of the other electrode in response to a change in the potential of the other electrode.

[0127] Next, the transistors in the reference cell 21 and the calculation cell 31 will be described.

[0128] Transistors 24 and 34 operate in the subthreshold region unless otherwise specified. The drain current Id of transistors operating in the subthreshold region can be expressed by equation (4).

[0129]

[0130] In formula (4), I ０ is V ｇ = V ｔｈ The drain current at this time is q, where q is the elementary charge, and Vｇ V is the gate voltage. ｔｈ η is the threshold voltage, η is a coefficient determined by the device structure, etc., k Ｂ is the Boltzmann constant, and T is the temperature. As shown in equation (4), the drain current Id of a transistor operating in the subthreshold region does not depend on the drain voltage. The current flowing through transistors 24 and 34 is the amount of current that flows when operating in the subthreshold region. The current in the subthreshold region of transistors 24 and 34 can reduce the effect of variations in drain voltage. Therefore, the accuracy of the data obtained by calculation can be improved.

[0131] In this specification, the subthreshold region refers to the region in a graph showing the gate voltage (Vg)-drain current (Id) characteristics of a transistor where the gate voltage is lower than the threshold voltage. Alternatively, the subthreshold region refers to the region where current flows due to carrier diffusion, deviating from the gradient dual-channel approximation (a model that only considers drift current). Alternatively, the subthreshold region refers to the region where the drain current increases exponentially with increasing gate voltage. Alternatively, the subthreshold region includes regions that can be considered as the regions described in each of the above explanations.

[0132] Furthermore, the drain current when a transistor operates in the subthreshold region is called the subthreshold current. The subthreshold current increases exponentially with respect to the gate voltage, regardless of the drain voltage. Circuit operation using the subthreshold current can reduce the effects of variations in drain voltage.

[0133] Furthermore, transistors 32 and 22 have the function of maintaining the potential of the gates of transistor 24 and transistor 34 when they are in the off state. Specifically, they have the function of maintaining a potential corresponding to the data supplied to the gate of transistor 34 via transistor 32. Transistors 32 and 22 are preferably OS transistors, as an example.

[0134] As mentioned above, OS transistors have extremely low leakage current, which is the current flowing between the source and drain when they are off. By using OS transistors as transistors 32 and 22, the leakage current of transistors 32 and 22 can be suppressed, thereby reducing the power consumption of the multiply-accumulate circuit 58. Specifically, the fluctuations in the potential held at the gates of transistors 24 and 34 can be made very small, thus reducing the need for potential refresh operations. Reducing refresh operations also reduces the power consumption of the multiply-accumulate circuit 58. Furthermore, by making the leakage current from the holding node to the wiring WCL or wiring XCL very small, the cell can hold the potential of the holding node for a long time.

[0135] Furthermore, when the gate voltage of an OS transistor is less than the transistor's threshold voltage, it is 1 × 10⁻¹⁰ −２０ Less than A, 1 x 10 −２２ Less than A, or 1 x 10 −２４ It is possible to pass extremely small currents as drain current per 1 μm of channel width, such as less than A. Also, when the gate voltage of the OS transistor is the threshold voltage of the transistor, it is 1.0 × 10 −８ A or less, 1.0×10 −１２ A or less, or 1.0 × 10 −１５ It is possible to pass a drain current of less than A per 1 μm channel width. Therefore, OS transistors can pass subthreshold currents of different magnitudes within the gate voltage range in which they operate in the subthreshold region. In other words, OS transistors can have a wide gate voltage range in which they operate in the subthreshold region. Specifically, the threshold voltage of the OS transistor is set to V ｔｈ In that case, in the subthreshold region, (V ｔｈ -1.0V) or more V ｔｈ The following, or (V ｔｈ -0.5V) or more V ｔｈ The circuit can be operated using gate voltages within the following voltage range.

[0136] On the other hand, Si transistors have a large off-current and a narrow gate voltage range in which they operate in the subthreshold region. When utilizing the subthreshold current, OS transistors can operate in a wider gate voltage range than Si transistors.

[0137] Next, the wiring WSL, wiring XCL, wiring VBL, and wiring WCL connected to the reference cell 21 and calculation cell 31 will be described.

[0138] Wiring WSL is supplied with signals that control the on / off state of transistors 22 and 32, which function as switches. Wiring WSL functions as a write word line when writing data to reference cell 21 and calculation cell 31. Data is written to reference cell 21 and calculation cell 31 by supplying a current or voltage corresponding to the data to be written to wiring XCL or wiring WCL. This data is written by turning on transistors 22 and 32. In this case, wiring WCL is set to H level (high level potential). In reference cell 21 and calculation cell 31, the data is held in reference cell 21 and calculation cell 31 by controlling transistors 22 and 32 to be turned off. In this case, wiring WCL is set to L level (low level potential).

[0139] The wiring WCL supplies a current (weight current or current I) to the calculation cell 31 according to the weight data (also called first data or first input data). Ｗｕｔ It has the function of supplying current, or the function of supplying a voltage Vd to supply current according to the potential held in the calculation cell.

[0140] The wiring XCL supplies current (reference current or current I) to the reference cell 21 and the calculation cell 31 according to the reference data. Ｘｕｔ ), or the amount of current corresponding to the input data (also called second data or second input data) (input current or current I Ｘ It has the function of distributing (a substance).

[0141] Wiring VBL is a wiring to which a constant potential Vb is applied. The constant potential Vb is the potential used to fix the potential of the drain terminals of transistors 24 and 34 in the reference cell 21 and the calculation cell 31. By applying a constant potential Vb to the gates of transistors 23 and 33, the transistor characteristics of transistors 24 and 34, such as the threshold voltage, can be stabilized in response to fluctuations in the potential of wiring WCL.

[0142] In particular, if transistors 34 and 24 are short-channel transistors with short channel lengths, the threshold voltage decreases due to drain-induced barrier lowering (DIBL), causing the drain current to become dependent on the drain voltage. Therefore, a configuration that applies a constant potential Vb to the gates of transistors 23 and 33 and reduces the change in the drain voltage of transistors 24 and 34 is effective. This configuration can improve the accuracy of the data obtained by calculations.

[0143] Next, the configuration in which multiple reference cells 21 and calculation cells 31 are provided in Figure 8 will be explained with reference to Figures 9A and 9B. Figure 9A shows an overview of the operation when data is written, and Figure 9B shows an overview of the operation when data is read.

[0144] Figures 9A and 9B show a reference cell section 20 equipped with multiple reference cells 21_1 to 21_m (corresponding to reference cell 21 in Figure 8), and a calculation cell section 30 equipped with multiple calculation cells 31_1, 1 to 31_m, n (corresponding to calculation cell 31 in Figure 8). Also in Figures 9A and 9B, multiple wiring XCLs are shown as wiring XCL_1 to XCL_m. Also in Figures 9A and 9B, multiple wiring WCLs are shown as wiring WCL_1 to WCL_n. Note that m and n are both natural numbers.

[0145] In FIGS. 9A and 9B, the cells of the reference cell unit 20 and the arithmetic cell unit 30 are arranged in a matrix of n + 1 cells in the row direction and m cells in the column direction. The cells of the reference cell unit 20 and the arithmetic cell unit 30 may have any configuration as long as they are arranged in a matrix of two or more cells in the row direction and one or more cells in the column direction.

[0146] In FIGS. 9A and 9B, for the sake of explanation, the reference cell 21 and the arithmetic cell 31 are illustrated in a simplified manner. Terminal C of the reference cell 21 in the reference cell unit 20 Ｐ corresponds to the other electrode of the capacitive element 25 in FIG. 8. Terminal T of the reference cell 21 in the reference cell unit 20 Ｗ corresponds to the terminal to which one of the source or drain of the transistor 22 and one of the source or drain of the transistor 23 in FIG. 8 are connected. Terminal C of the arithmetic cell 31 in the arithmetic cell unit 30 Ｐ corresponds to the other electrode of the capacitive element 35 in FIG. 8. Terminal T of the arithmetic cell 31 in the arithmetic cell unit 30 Ｘ corresponds to the terminal to which one of the source or drain of the transistor 32 and one of the source or drain of the transistor 33 in FIG. 8 are connected.

[0147] In the operation during data writing shown in FIG. 9A, a current I Ｘｕｔ is passed through the reference cells 21 of each row. The current applied to each row is a normalized current I Ｘｕｔ and is equal for each row. The current I Ｘｕｔ corresponds to the amount of current (reference current) according to the reference data. Since the arithmetic cells 31 of each row are connected via a capacitor, no current flows. In the reference cell 21, it operates so as to hold the voltage corresponding to the flowing current.

[0148] Also, in the operation during data writing shown in FIG. 9A, currents I Ｗ１ to I Ｗｎ (I Ｗ ) are passed through the arithmetic cells of each column. The current applied to each column corresponds to the amount of current obtained by multiplying the normalized current I Ｗｕｔ by the weight data w (I Ｗ = w × I Ｗｕｔ ). Currents I Ｗ１ to I ＷｎThese values ​​may differ from column to column.

[0149] In the data reading operation shown in Figure 9B, current I is supplied to the reference cell 21 of each row. Ｘ１ ~I Ｘｍ (I ｘ ) is passed through. Current I is applied to each row. Ｘ１ ~I Ｘｍ This is a normalized current I Ｘｕｔ This corresponds to the current amount obtained by multiplying the input data x by (I Ｘ = x × I Ｘｕｔ ). current I Ｘ１ ~I Ｘｍ The values ​​may differ from row to row. Note that current I Ｘｕｔ is current I Ｗｕｔ It is preferable that it be equal to.

[0150] In the data reading operation shown in Figure 9B, current I Ｘ１ ~I Ｘｍ The voltage held in reference cell 21 is increased. In response to this increase, the voltages of wiring XCL_1 to XCL_m are also increased, so the voltage held by the capacitive coupling of capacitive element 35 in calculation cell 31 is increased. The potential of wiring WCL_1 to WCL_n is then set to voltage Vd. At this time, the current I flowing through transistor 34 ｒ This is the current value (I) held in the calculation cell 31 when writing data. ｗ ) and the current value (I) that flowed through the reference cell 21 when reading the data. ｘ ) and the product of (current I ｒ１１ ~I ｒｍｎ ). Current I flowing through each column ｒ１１ ~I ｒｍ By estimating the sum of these values, it is possible to output data equivalent to the result of the sum of the products of the input data and the weight data.

[0151] It is preferable that the sizes (e.g., channel length, channel width, transistor configuration, etc.) of the transistors 32 to 34 contained in each cell of the calculation cell unit 30 are equal. It is also preferable that the sizes of the transistors 22 to 24 contained in each cell of the reference cell unit 20 are equal. Furthermore, it is preferable that the sizes of transistors 22 and 32 are equal. Furthermore, it is preferable that the sizes of transistors 23 and 33 are equal. Furthermore, it is preferable that the sizes of transistors 24 and 34 are equal.

[0152] By making the sizes of the transistors equal, the electrical characteristics of each transistor can be made approximately equal. Therefore, by making the size of the transistor 32 contained in each of cells 31_1,1 to 31_m,n equal, the size of the transistor 33 contained in each of cells 31_1,1 to 31_m,n equal, and the size of the transistor 34 contained in each of cells 31_1,1 to 31_m,n equal, each of cells 31_1,1 to 31_m,n can perform approximately the same operation under identical conditions. These identical conditions refer to, for example, the input potentials to the source, drain, and gate of transistor 32, the input potentials to the source, drain, and gate of transistor 33, the input potentials to the source, drain, and gate of transistor 34, and the voltages held in each of cells 31_1,1 to 31_m,n. Furthermore, by making the size of the transistors 22, 23, and 24 contained in each of cells 21_1 to 21_m equal, for example, cells 21_1 to 21_m can be made to operate and produce substantially the same results. They can perform substantially the same operation under the same conditions. The same conditions here refer to, for example, the input potentials to the source, drain, and gate of transistor 22, the input potentials to the source, drain, and gate of transistor 23, the input potentials to the source, drain, and gate of transistor 24, and the voltages held in each of cells 21_1 to 21_m.

[0153] The operation of the reference cell 21 and the calculation cell 31 during data writing will be explained with reference to Figure 10A.

[0154] Set wiring WSL to the high level, and turn on transistors 22 and 32. A current I corresponding to the reference current is drawn into wiring XCL. Ｘｕｔ The current flows through the wiring WCL. Also, current I Ｗ Current IＷ This is the current I normalized to the weight data w. Ｗｕｔ The current obtained by multiplying by (in the figure, I ｗ =wI Ｗｕｔ This corresponds to ).

[0155] In reference cell 21, transistor 22 is turned ON. The potential of the holding node, which is the gate of transistor 24, is such that transistor 24 is subjected to current I Ｘｕｔ V is the potential through which the current flows. ｇ１ As a result, transistor 24 receives current I Ｘｕｔ The current can be passed between the source and drain of transistor 24. In this specification, this operation is referred to as "the current flowing between the source and drain of transistor 24 of reference cell 21 is I Ｘｕｔ It is sometimes referred to as "setting (programming) it."

[0156] In the calculation cell 31, transistor 32 is turned ON. The potential of the holding node, which is the gate of transistor 34, is such that transistor 34 is subjected to current I Ｗ V is the potential through which the current flows. ｇ２ This results in the current flowing between the source and drain of the transistor 34 of the calculation cell 31 being I ｗ Set to this.

[0157] Current I supplied to the reference cell 21 via wiring XCL during data writing. Ｘｕｔ This can be expressed by equation (5).

[0158]

[0159] In equation (5), V ｇ１ V is the potential of the holding node, which is the gate of transistor 24. In equation (5), V ｔｈ１’ This is the threshold voltage of transistor 24.

[0160] Current I supplied to the calculation cell 31 via the wiring WCL during data writing. Ｗ This can be expressed by equation (6).

[0161]

[0162] In equation (6), V ｇ２V is the potential of the holding node, which is the gate of transistor 34. In equation (6), V ｔｈ１ This is the threshold voltage of transistor 34. Current I ｗ This consists of weight data w and normalized current I. Ｗｕｔ It can be expressed as a product of .

[0163] Furthermore, the constant potential Vb applied to the wiring VBL is V ｔｈ２ If we let Vb be the threshold voltage of transistor 33 and Vth2' be the threshold voltage of transistor 23, then we set Vb > Vth2' and Vb > Vth2. With this configuration, the drain voltage of transistor 24 can be set to (Vb - Vth2). Therefore, the drain voltage of transistor 34 can also be set to (Vb - Vth2'). In other words, the drain voltages of transistors 24 and 34 can be set to a potential that does not depend on the potential of wiring WCL and XCL. Therefore, the decrease in the threshold voltage of transistors 34 and 24 due to DIBL can be suppressed, and the accuracy of the data obtained by calculation can be improved.

[0164] The operation of the reference cell 21 and the calculation cell 31 during data reading will be explained with reference to Figure 10B. A period of holding a set current can be provided between data writing and data reading. During this period of holding the set current, transistors 22 and 32 are set to the OFF state. By using OS transistors, transistors 22 and 32 can continuously maintain the potential of the holding node corresponding to the set current.

[0165] In reference cell 21, the wiring WSL is set to the L level, and the transistor 22 is turned OFF. The current I corresponding to the input current is supplied to the wiring XCL. ｘ Current I Ｘ This is the current I normalized to the input data x. ｘｕｔ The current obtained by multiplying by (in the figure, I Ｘ = xIx ｕｔ This corresponds to the current I of transistor 24. Ｘ As V flowsｇ１ As the voltage fluctuates by +Δ, the potential of the wiring XCL also fluctuates along with it.

[0166] In the calculation cell 31, the wiring WSL is set to the L level, and the transistor 32 is turned off. Therefore, the holding node of the calculation cell 31 is in a floating state. Due to the capacitive coupling of the capacitive element 35 caused by the fluctuation in the potential of the wiring XCL due to the operation of the reference cell 21, the potential V of the holding node of the calculation cell 31 is affected. ｇ２ V fluctuates, ｇ２ The result is +Δ. The potential of the holding node of the calculation cell 31 is V ｇ２ As it fluctuates by +Δ, the transistor 34 of the calculation cell 31 receives current I ｒ It plays.

[0167] Current I supplied to the reference cell 21 via the wiring WSL during data retrieval. Ｘ This can be expressed by equation (7). V ｇ１ +Δ represents current I Ｘ This is the change in potential of the holding node of reference cell 21 due to the flow of the current through reference cell 21.

[0168]

[0169] In equation (7), Δ can be expressed as the input data x shown in equation (8).

[0170]

[0171] From equations (7) and (8), the current I Ｘ This involves input data x and a normalized current I. Ｘｕｔ It can be expressed as a product of .

[0172] When reading data, the wiring WCL is voltage V so that current flows to the calculation cell 31 of each row. ｄ Set to V. Then, the potential of the holding node of the calculation cell 31 is V. ｇ２ The change to +Δ causes the current I flowing through the transistor 34 of the calculation cell 31. ｒ This can be expressed by equation (9).

[0173]

[0174] I in equations (6), (8) through (9) ｒThis can be estimated as the current corresponding to the product of the weight data w and the input data x. Since the currents flowing through the calculation cells 31 in each row can be added together, by outputting the current flowing through the wiring WCL to the outside, a signal corresponding to the calculation result of the sum-of-products operation based on the weight data w and the input data x can be output.

[0175] Figure 11 shows an example configuration of a sum-of-products (SMA) circuit unit 59 that performs a SMA operation on first data (weight data) and second data (input data), as well as peripheral circuits (circuits WCS, XCS, WSD, SWS1, SWS2, ITRZ_1 to ITRZ_n). The SMA circuit unit 59 shown in Figure 11 is a circuit that performs a SMA operation on first data corresponding to the potential held in each cell and the input second data. The first data and second data can be analog data or multi-level data (discrete data), for example.

[0176] Circuits such as Circuit WCS, Circuit XCS, Circuit WSD, Circuit ITRZ (Circuit ITRZ_1 to ITRZ_n), and Circuit SMP (Circuit SMP_1 to SMP_n) correspond to the peripheral arithmetic circuit section 48 described in Figures 5, 6A, and 6B. Circuits WCS, Circuit XCS, Circuit WSD, Circuit ITRZ (Circuit ITRZ_1 to ITRZ_n), and Circuit SMP can each be provided in layer 40. Therefore, it is possible to provide them so as to have an overlapping area with the sum-of-accumulate arithmetic circuit section 59 provided in layer 50, and the connection distance (wiring length) between the peripheral arithmetic circuit section 48 and the sum-of-accumulate arithmetic circuit section 59 can be made extremely short. As a result, wiring resistance and parasitic capacitance are reduced, so the time required for charging and discharging is reduced, and high-speed operation can be achieved. Power consumption can also be reduced. Furthermore, miniaturization and weight reduction can be achieved.

[0177] The sum-of-accumulate circuit section 59 has cells 31_1,1 to 31_m,n and cells 21_1 to 21_m. Each of cells 31_1,1 to 31_m,n has, for example, a transistor 32, a transistor 33, a transistor 34, and a capacitive element 35, similar to the calculation cell 31 described above. Each of cells 21_1 to 21_m has, for example, a transistor 22, a transistor 23, a transistor 24, and a capacitive element 25, similar to the reference cell 21 described above. In the following description, the "one of the source or drain" described above may be referred to as the "first terminal," and the "other of the source or drain" may be referred to as the "second terminal." Also, in the following description, one electrode of a capacitor may be referred to as the "first terminal," and the "other electrode" may be referred to as the "second terminal."

[0178] In Figure 11, in cell 31_1,1, the connection point between the first terminal of transistor 32, the gate of transistor 34, and the first terminal of capacitive element 35 is designated as node NN_11. Similarly, in Figure 11, in cells 31_1,n, 31_m,1, and 31_m,n, the same connection points are designated as nodes NN_1n, NN_m1, and NN_mn. Similarly, in Figure 11, in cells 21_1 and 21_m, the same connection points are designated as nodes NN_ref1 and NNref_m. Note that nodes NN_11 through NN_mn, and nodes NNref_1 through NNref_m, function as holding nodes for their respective cells.

[0179] Circuit SWS1, as an example, includes transistors F3_1 to F3_n. The first terminal of transistor F3_1 is connected to wiring WCL_1, the second terminal of transistor F3_1 is connected to circuit WCS, and the gate of transistor F3_1 is connected to wiring SWL1. The first terminal of transistor F3_n is connected to wiring WCL_n, the second terminal of transistor F3_n is connected to circuit WCS, and the gate of transistor F3_n is connected to wiring SWL1.

[0180] For each of transistors F3_1 to F3_n, for example, transistors applicable to the transistors in the multiply-accumulate circuit section 59 can be used. In particular, it is preferable to use OS transistors for each of transistors F3_1 to F3_n.

[0181] Circuit SWS1 functions as a circuit that switches the connection state between circuit WCS and each of the wirings WCL_1 to WCL_n.

[0182] Circuit SWS2, as an example, includes transistors F4_1 to F4_n. The first terminal of transistor F4_1 is connected to wiring WCL_1, the second terminal of transistor F4_1 is connected to the input terminal of circuit ITRZ_1, and the gate of transistor F4_1 is connected to wiring SWL2. The first terminal of transistor F4_n is connected to wiring WCL_n, the second terminal of transistor F4_n is connected to the input terminal of circuit ITRZ_n, and the gate of transistor F4_n is connected to wiring SWL2.

[0183] For each of transistors F4_1 to F4_n, for example, transistors applicable to the transistors in the multiply-accumulate circuit section 59 can be used. In particular, it is preferable to use OS transistors for each of transistors F4_1 to F4_n.

[0184] Circuit SWS2 functions as a circuit that switches the connection state between wiring WCL_1 and circuit ITRZ_1, and between wiring WCL_n and circuit ITRZ_n.

[0185] The WCS circuit has the function of supplying data to be stored in each cell of the sum-of-accumulate circuit unit 59. When the cells of the sum-of-accumulate circuit unit 59 perform calculations in pairs of cells that handle positive data and cells that handle negative data, the WCS circuit has the function of supplying positive data and negative data to the cells in each column.

[0186] Circuit XCS is connected to wiring XCL_1 to XCL_m. Circuit XCS has the function of supplying current to cells 21_1 and 21_m of the sum-of-accumulate circuit unit 59, respectively, according to the reference data described later, or according to the second data.

[0187] Circuit WSD is connected to wiring WSL_1 to WSL_m. When writing first data to cells 31_1,1 to 31_m,n, circuit WSD has the function of selecting the row of the sum-of-accumulate circuit 59 to which the first data will be written by supplying a predetermined signal to wiring WSL_1 to WSL_m. In other words, wiring WSL_1 to WSL_m functions as a write word line.

[0188] Furthermore, circuit WSD is connected, for example, to wiring SWL1 and wiring SWL2. Circuit WSD has the function of switching the connection state between circuit WCS and the multiply-accumulate circuit unit 59 by supplying a predetermined signal to wiring SWL1, and the function of switching the connection state between circuits ITRZ_1 to ITRZ_n and the multiply-accumulate circuit unit 59 by supplying a predetermined signal to wiring SWL2.

[0189] Each of circuits ITRZ_1 through ITRZ_n has, for example, an input terminal and an output terminal. For instance, the output terminal of circuit ITRZ_1 is connected to wiring OL_1, and the output terminal of circuit ITRZ_n is connected to wiring OL_n.

[0190] Each of circuits ITRZ_1 through ITRZ_n has the function of outputting a current from its output terminal corresponding to the amount of current input to its input terminal. When the cells of the sum-of-accumulate circuit 59 perform calculations using pairs of cells that handle positive data and cells that handle negative data, each of circuits ITRZ_1 through ITRZ_n receives current corresponding to the positive and negative data from the pair of cells in each column.

[0191] Each of circuits ITRZ_1 to ITRZ_n has a function-based arithmetic circuit. In this case, the converted voltage can be used to perform function calculations using the arithmetic circuit, and the result of the calculation can be output to wiring OL_1 to wiring OL_n. When performing calculations related to reservoir computing, the above-mentioned functions can be, for example, the tanh function, the ReLU function, etc.

[0192] Each of the circuits SMP_1 to SMP_n has, for example, an input terminal and an output terminal. For instance, the output terminal of circuit SMP_1 is connected to wiring OL_1, and the output terminal of circuit SMP_n is connected to wiring OM_n.

[0193] Each of the circuits SMP_1 to SMP_n has the function of holding the current input to the input terminal from circuits ITRZ_1 to ITRZ_n, and the function of outputting the held current from the output terminal. The current output from the output terminal can be input to the sum-of-accumulate circuit unit 59 as input data. The current output from the output terminal can also be converted into a voltage signal to produce output data indicating the calculation result.

[0194] <<Circuit WCS, Circuit XCS>> Here, we will explain specific examples of Circuit WCS and Circuit XCS.

[0195] First, the WCS circuit will be explained. Figure 12A is a block diagram showing an example of the WCS circuit. In addition, Figure 12A also shows the circuit SWS1, transistor F3, wiring SWL1, and wiring WCL to show the connections to the surrounding circuits of the WCS circuit. Transistor F3 is one of transistors F3_1 to F3_n shown in Figure 11, and wiring WCL is one of wirings WCL_1 to WCL_n shown in Figure 11.

[0196] The circuit WCS shown in Figure 12A includes a switch SWW as an example. The first terminal of switch SWW is connected to the second terminal of transistor F3, and the second terminal of switch SWW is connected to wiring VINIL1. Wiring VINIL1 functions as a wire that provides an initialization potential to wiring WCL, and the initialization potential can be ground potential (GND), low level potential, high level potential, etc. Note that switch SWW is ON only when providing an initialization potential to wiring WCL, and OFF at all other times.

[0197] As the switch SWW, for example, an analog switch or an electrical switch such as a transistor can be used. If a transistor is used as the switch SWW, for example, a transistor that can be used in the multiply-accumulate circuit 59 can be used. In addition to electrical switches, mechanical switches may also be used.

[0198] Furthermore, the circuit WCS in Figure 12A has, as an example, multiple current sources CS. Specifically, the circuit WCS has K bits (2 Ｋ It has the function of outputting the first data of value (K is an integer greater than or equal to 1) as current, and in this case, the circuit WCS is 2 Ｋ - It has one current source CS. The circuit WCS has one current source CS that outputs information corresponding to the value of the 1st bit as current, two current sources CS that output information corresponding to the value of the 2nd bit as current, and two current sources CS that output information corresponding to the Kth bit as current. Ｋ−１ To possess.

[0199] In Figure 12A, each current source CS has terminal T1 and terminal T2. Terminal T1 of each current source CS is connected to the second terminal of transistor F3 of circuit SWS1. Also, terminal T2 of one current source CS is connected to wiring DW_1, and each of the terminals T2 of two current sources CS is connected to wiring DW_2, Ｋ−１ Each of the terminals T2 of the current source CS is connected to the wiring DW_K.

[0200] The multiple current sources CS in the circuit WCS each have the same current I Ｗｕｔ It has the function of outputting current I from terminal T1. Ｗｕｔ This refers to the normalized current I described above. Ｗｕｔ This corresponds to [this]. However, in reality, errors may appear during the manufacturing stage of the display device due to variations in the electrical characteristics of the transistors included in each current source CS. Therefore, the current I output from each of the terminals T1 of the multiple current sources CS Ｗｕｔ The error is preferably within 10%, more preferably within 5%, and most preferably within 1%. In this embodiment, the current I output from terminal T1 of the multiple current sources CS included in the circuit WCS is Ｗｕｔ We will explain assuming there is no error.

[0201] Wirings DW_1 through DW_K receive current I from the connected current source CS. Ｗｕｔ It functions as wiring that transmits a control signal to output I Ｗｕｔ When current flows through the second terminal of transistor F3, and a low-level potential is applied to wiring DW_1, the current source CS connected to wiring DW_1 is I Ｗｕｔ It does not output.

[0202] The current supplied by the single current source CS connected to wiring DW_1 corresponds to the value of the first bit, the current supplied by the two current sources CS connected to wiring DW_2 corresponds to the value of the second bit, and the current supplied by the K current sources CS connected to wiring DW_K corresponds to the value of the K bit.

[0203] Note that Figure 12A shows the circuit WCS when K is an integer of 3 or more. However, when K is 1, the circuit WCS in Figure 12A can be configured without the current source CS connected to wiring DW_2 to DW_K. Also, when K is 2, the circuit WCS in Figure 12A can be configured without the current source CS connected to wiring DW_3 to DW_K.

[0204] Next, we will explain a specific example of the configuration of the current source CS.

[0205] The current source CS shown in Figure 12B is a circuit that can be applied to the current source CS included in the circuit WCS in Figure 12A, and the current source CS has transistor Tr1 and transistor Tr2.

[0206] The first terminal of transistor Tr1 is connected to wiring VDDL, and the second terminal of transistor Tr1 is connected to the gate of transistor Tr1, the back gate of transistor Tr1, and the first terminal of transistor Tr2. The second terminal of transistor Tr2 is connected to terminal T1, and the gate of transistor Tr2 is connected to terminal T2. Terminal T2 is also connected to wiring DW.

[0207] Wiring DW is one of the wirings DW_1 to DW_K shown in Figure 12A.

[0208] The VDDL wiring functions as wiring that provides a constant voltage. This constant voltage can be, for example, a high-level potential.

[0209] When the constant voltage supplied by the wiring VDDL is set to a high-level potential, a high-level potential is input to the first terminal of transistor Tr1. The potential at the second terminal of transistor Tr1 is lower than this high-level potential. In this case, the first terminal of transistor Tr1 functions as the drain, and the second terminal functions as the source. Furthermore, since the gate and the second terminal of transistor Tr1 are connected, the gate-source voltage of transistor Tr1 is 0V. Therefore, if the threshold voltage of transistor Tr1 is within an appropriate range, a current (drain current) within the subthreshold current range flows between the first and second terminals of transistor Tr1. Note that this current is as described above. Ｗｕｔ , or I described later Ｘｕｔ It corresponds to this.

[0210] Transistor Tr2 functions as a switching element. When the potential of the first terminal of transistor Tr2 is higher than the potential of the second terminal of transistor Tr2, the first terminal of transistor Tr2 functions as a drain and the second terminal of transistor Tr2 functions as a source. Also, since the back gate of transistor Tr2 and the second terminal of transistor Tr2 are connected, the back gate-source voltage is 0V. Therefore, when the threshold voltage of transistor Tr2 is within an appropriate range, transistor Tr2 will turn on when a high-level potential is input to its gate, and transistor Tr2 will turn off when a low-level potential is input to its gate. Specifically, when transistor Tr2 is on, a current within the current range of the subthreshold region described above flows from the second terminal of transistor Tr1 to terminal T1, and when transistor Tr2 is off, no current flows from the second terminal of transistor Tr1 to terminal T1.

[0211] Furthermore, transistors Tr1 and Tr2 can be, for example, transistors applicable to the transistors in the sum-of-accumulate circuit section 59. In particular, it is preferable to use OS transistors for transistors Tr1 and Tr2.

[0212] Next, we will explain a specific example of the XCS circuit.

[0213] Figure 12C is a block diagram showing an example of circuit XCS. Figure 12C also shows wiring XCL to illustrate the connection to the surrounding circuits of circuit WCS. Wiring XCL is one of the wirings XCL_1 to XCL_m shown in Figure 11.

[0214] The circuit XCS shown in Figure 12C includes a switch SWX as an example. The first terminal of switch SWX is connected to wiring XCL and multiple current sources CS, and the second terminal of switch SWX is connected to wiring VINIL2. Wiring VINIL2 functions as wiring that provides an initialization potential to wiring XCL, and the initialization potential can be ground potential (GND), low level potential, high level potential, etc. Also, the initialization potential provided by wiring VINIL2 may be equal to the potential provided by wiring VINIL1. Note that switch SWX is ON only when providing an initialization potential to wiring XCL, and OFF at all other times.

[0215] Switch SWX can, for example, be a switch that can be applied to switch SWW.

[0216] Furthermore, the circuit configuration of circuit XCS in Figure 12C can be made almost the same as that of circuit WCS in Figure 12A. Specifically, circuit XCS has the function of outputting reference data as current, and L bits (2 Ｌ It has a function to output a second data value (where L is an integer greater than or equal to 1) as current, and in this case, circuit XCS is 2 Ｌ - It has one current source CS. Circuit XCS has one current source CS that outputs information corresponding to the value of the 1st bit as current, two current sources CS that output information corresponding to the value of the 2nd bit as current, and two current sources CS that output information corresponding to the Lth bit as current. Ｌ−１ They possess it individually.

[0217] By the way, the reference data that the XCS circuit outputs as current can, for example, be information where the value of the first bit is "1" and the values ​​of the second bit and subsequent bits are "0".

[0218] In Figure 12C, terminal T2 of one current source CS is connected to wiring DX_1, and terminal T2 of each of the two current sources CS is connected to wiring DX_2, 2 Ｌ−１ Each of the terminals T2 of the current source CS is connected to the wiring DX_L.

[0219] The multiple current sources CS in circuit XCS each have the same constant current I Ｘｕｔ It has the function of outputting from terminal T1. In addition, wiring DX_1 to wiring DX_L receive I from the connected current source CS. Ｘｕｔ It functions as a wire that transmits a control signal to output. In other words, circuit XCS has the function of supplying current to wire XCL according to the information of the L bit sent from wires DX_1 to DX_L.

[0220] Furthermore, if errors occur due to variations in the electrical characteristics of the transistors contained in each current source CS of the circuit XCS, the current I output from each of the terminals T1 of the multiple current sources CS will be affected. Ｘｕｔ The error is preferably within 10%, more preferably within 5%, and most preferably within 1%. In this embodiment, the current I output from terminal T1 of the multiple current sources CS included in circuit XCS is Ｘｕｔ We will explain assuming there is no error.

[0221] Furthermore, the current source CS of circuit XCS can be the same as the current source CS of circuit WCS, as shown in Figure 12B. This allows circuit XCS to supply current within the subthreshold current range to wiring XCL as reference data or second data of L bits.

[0222] <<Circuit ITRZ, Circuit SMP>> Here, specific examples of Circuit ITRZ applicable to Circuit ITRZ_1 to Circuit ITRZ_n in Figure 11, and specific examples of Circuit SMP applicable to Circuit SMP_1 to Circuit SMP_n in Figure 11 will be described. Note that Circuit ITRZ shown in Figure 13 illustrates a configuration in which current corresponding to positive and negative data flows between pairs of cells in each column. Also, Circuit SMP shown in Figure 13 illustrates a configuration in which a voltage corresponding to the magnitude of the current flowing through wiring OL is maintained, and a current corresponding to the magnitude of that current is supplied to the subsequent circuit.

[0223] The circuit ITRZ shown in Figure 13, as an example, includes transistors MP1i, MP1o, MP2i, MP2o, MP3i, MP3o, MP4i, MP4o, MN1i, MN1o, MN2i, and MN2o.

[0224] In the circuit ITRZ shown in Figure 13, the first current mirror circuit is composed of p-channel transistors MP1i, MP2i, MP1o, and MP2o. The second current mirror circuit is composed of n-channel transistors MN1i, MN2i, MN1o, and MN2o. The third current mirror circuit is composed of p-channel transistors MP3i, MP4i, MP3o, and MP4o. Because the circuit ITRZ contains three current mirror circuits, it is sometimes called a three-stage current mirror circuit.

[0225] The drain of transistor MP1i is connected to the first input terminal of circuit ITRZ, the drain of transistor MP1o is connected to the drain of transistor MN2i, the drain of transistor MN2o is connected to the drain of transistor MP3i, and the drain of transistor MP3o is connected to the output terminal of circuit ITRZ.

[0226] The first current mirror circuit ideally has the function of flowing the same amount of current between the source and drain of transistor MP2o as the source and drain current corresponding to the gate-source potential of transistor MP2i. Similarly, the second current mirror circuit ideally has the function of flowing the same amount of current between the source and drain of transistor MN1o as the source and drain current corresponding to the gate-source potential of transistor MN1i. Similarly, the third current mirror circuit ideally has the function of flowing the same amount of current between the source and drain of transistor NP4o as the source and drain current corresponding to the gate-source potential of transistor MP4i.

[0227] In the first current mirror circuit, transistor MP1i functions as a clamp transistor to prevent a decrease in the threshold voltage of transistor MP2i due to DIBL. Similarly, transistor MP1o also functions as a clamp transistor to prevent a decrease in the threshold voltage of transistor MP2o due to DIBL. Therefore, wiring VE1, which provides a desired bias potential, is connected to the gates of transistors MP1i and MP1o, respectively.

[0228] In the second and third current mirror circuits, each of the transistors MN2i, MN2o, MP3i, and MP3o also functions as a clamp transistor to prevent a drop in the threshold voltage of the transistors connected in series by DIBL. In this case, each of the wires VE2 and VE3 functions as a wire that provides a desired bias potential.

[0229] Furthermore, the bias potentials provided by wiring VE1 and wiring VE3 can be made equal to each other. Therefore, wiring VE1 and wiring VE3 can be identical to each other.

[0230] Furthermore, transistors MP1i and MP1o can each function as switching transistors. In this case, it is preferable that wiring VE1 functions as wiring for controlling the switching between the on and off states of these transistors. Also, by turning these transistors off, the first current mirror circuit can be stopped, thereby reducing the power consumption in circuit ITRZ. The same applies to transistors MN2i and MN2o of the second current mirror circuit and transistors MP3i and MP3o of the third current mirror circuit.

[0231] In the first current mirror circuit, the source of transistor MP2i and the source of transistor MP2o are connected to wiring VD2. Since the first current mirror circuit is composed of p-channel transistors, it also functions as a current source circuit. Therefore, wiring VD2 functions as wiring that provides a high-level potential, acting as a high-power supply potential for the first current mirror circuit. Similarly, the third current mirror circuit also functions as a current source circuit, and therefore the high-level potential provided by wiring VD2 also functions as a high-power supply potential for the third current mirror circuit. Note that the high-level potential provided by wiring VD2 may be equal to the high-level potential provided by wiring VD1 described above. In this case, wiring VD1 and wiring VD2 can be combined as the same wiring.

[0232] In the second current mirror circuit, the source of transistor MN1i and the source of transistor MN1o are connected to wiring VS2. Since the second current mirror circuit is composed of n-channel transistors, it also functions as a current sink circuit. Therefore, wiring VS2 functions as wiring that provides a low-level potential as the low power supply potential of the second current mirror circuit. The low-level potential provided by wiring VS2 may be equal to the low-level potential provided by wiring VS1 described above. In this case, wirings VS1 and VS2 can be combined into a single wiring.

[0233] Assume that a current of quantity Isp flows through the first input terminal of circuit ITRZ, and a current of quantity Isn flows through the second input terminal of circuit ITRZ. Since a current of quantity Isp flows between the source and drain of transistor MP2i, ideally, a current of quantity Isp flows between the source and drain of transistor MP2o.

[0234] Furthermore, if Isp is greater than Isn, then according to Kirchhoff's current law, the current Is flowing between the source and drain of transistor MN1i is Isp - Isn. Therefore, ideally, the currents flowing between the source and drain of transistors MN1o, MP4i, and MP4o are also Is. As a result, circuit ITRZ can output the difference between the current Isp flowing through the first input terminal and the current Isn flowing through the second input terminal as Is at the output terminal.

[0235] Furthermore, when Isp is less than or equal to Isn, the amount of current flowing between the source and drain of transistor MP2o becomes Isn, and therefore no current flows between the source and drain of transistor MN1i. For this reason, no current is output from the output terminal of circuit ITRZ.

[0236] Therefore, by using the circuit ITRZ in Figure 13, it is possible to perform calculations on the ReLU function using the difference current between the first input terminal and the second input terminal as the input value.

[0237] Next, circuit SMP will be described. Analog switches, switches AS1 and AS2, are provided between wiring OL and circuit SMP, and between circuit SMP and wiring OM.

[0238] Each of the analog switches, switch AS1 and switch AS2, has transistors Tr9p and Tr9n, respectively. Switches AS1 and AS2 are controlled to be on or off by control signals supplied to wiring PCKn and PCKp.

[0239] The SMP circuit is a sample-and-hold circuit consisting of an n-channel current mirror circuit with a writing transistor (also called a holding transistor), transistor MN7. Specifically, the SMP circuit has n-channel transistors MN6i, MN6o, and MN7. The first terminals of transistor MN6i and MN7 correspond to the input terminals of the SMP circuit, and the first terminal of transistor MN6o corresponds to the output terminal of the SMP circuit. The gate of transistor MN7 corresponds to the control terminal of the SMP circuit.

[0240] The first terminal of transistor MN6i and the first terminal of transistor MN7 are connected to the second terminal of transistor Tr9p and the second terminal of transistor Tr9n, which are included in switch AS1. The second terminal of transistor MN7 is connected to the gate of transistor MN6i and the gate of transistor MN6o. The second terminal of transistor MN6o is connected to the first terminal of transistor Tr9p and the first terminal of transistor Tr9n, which are included in switch AS2. The second terminal of transistor MN6i and the second terminal of transistor MN6o are connected to wiring VS3. The gate of transistor MN7 is connected to wiring PCKp. In this specification, the connection point between the gate of transistor MN6i, the gate of transistor MN6o, and the second terminal of transistor MN7 is referred to as node SN1.

[0241] Wiring VS3 can, for example, function as a low-level potential wire, similar to wiring VS1 or wiring VS2 described above, as a low power supply potential. Furthermore, if the potential provided by wiring VS3 is equal to the potential provided by one or both of wiring VE1 and wiring VS2, wiring VS3 can be combined with one or both of wiring VE1 and wiring VS2. Similarly, wiring VD3 can, for example, function as a high-level potential wire, similar to wiring VD1 or wiring VD2 described above, as a high power supply potential. Furthermore, if the potential provided by wiring VD3 is equal to the potential provided by one or both of wiring VD1 and wiring VD2, wiring VD3 can be combined with one or both of wiring VD1 and wiring VD2.

[0242] The operation of the SMP circuit will now be explained. The SMP circuit can maintain a voltage at node SN1 corresponding to the magnitude of the current flowing through wiring OL, based on the control signals supplied to wiring PCKn and PCKp. The SMP circuit can also supply a current of a magnitude corresponding to the voltage held at node SN1 to wiring OM. Although each transistor in the SMP circuit is shown as an n-channel transistor, it is also possible to use p-channel transistors by inverting the potential of each wiring. Furthermore, it is possible to have multiple SMP circuits, in which case it is possible to configure them to hold data for sum-of-accumulate operations corresponding to different time-series data.

[0243] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0244] (Embodiment 2) In this embodiment, we will describe the configuration of the three-dimensional structure of the drive circuit, pixel circuit, and light-emitting element, the configuration of the memory circuit, the configuration of the pixel circuit connected to the light-receiving element, a schematic top view of the light-emitting element and its schematic cross-sectional view, the configuration of the light-emitting element, the configuration of the light-emitting element and the light-receiving element, and the configuration of a cross-sectional view of the display device.

[0245] <Example Configuration of Pixel Circuit Connected to Driving Circuit and Light-Emitting Device> Figures 14A and 14B show an example configuration of a pixel circuit 51 applicable to the pixel circuit of the pixel circuit section 55, and a light-emitting device 61 connected to the pixel circuit 51. Figure 14A is a diagram showing the connections of each element, and Figure 14B is a diagram schematically showing the vertical relationship of the layer 40 comprising the driving circuit section 47, the layer 50 comprising the plurality of transistors of the pixel circuit 51, and the layer 60 comprising the light-emitting device 61.

[0246] The pixel circuit 51 shown as an example in Figures 14A and 14B comprises transistors 52A, 52B, 52C, and a capacitor 53. Transistors 52A, 52B, and 52C can be composed of OS transistors. Each of the OS transistors 52A, 52B, and 52C preferably has a back gate electrode, in which case the back gate electrode can be configured to receive the same signal as the gate electrode, or to receive a different signal from the gate electrode.

[0247] Transistor 52B includes a gate electrode connected to transistor 52A, a first electrode connected to the light-emitting element 61, and a second electrode connected to wiring ANO. Wiring ANO is wiring that provides a potential for supplying current to the light-emitting element 61.

[0248] Transistor 52A includes a first electrode connected to the gate electrode of transistor 52B, a second electrode connected to wiring SL which functions as a source line, and a gate electrode for controlling a conduction state or non-conduction state based on the potential of wiring GL1 which functions as a gate line.

[0249] Transistor 52C includes a first electrode connected to wiring V0, a ​​second electrode connected to light-emitting element 61, and a gate electrode for controlling a conduction or non-conduction state based on the potential of wiring GL2 which functions as a gate line. Wiring V0 is a wiring for supplying a reference potential and a wiring for outputting the current flowing through the pixel circuit 51 to the drive circuit 47.

[0250] Capacitor 53 comprises a conductive film connected to the gate electrode of transistor 52B and a conductive film connected to the second electrode of transistor 52C.

[0251] The light-emitting element 61 comprises a first electrode connected to the first electrode of the transistor 52B and a second electrode connected to the wiring VCOM. The wiring VCOM is a wire that provides a potential for supplying current to the light-emitting element 61.

[0252] This allows the intensity of light emitted by the light-emitting element 61 to be controlled in accordance with the image signal applied to the gate electrode of transistor 52B. Furthermore, variations in the gate-source voltage of transistor 52B can be suppressed by the reference potential of the wiring V0 provided via transistor 52C.

[0253] Furthermore, the wiring V0 can output a current value that can be used to set pixel parameters. More specifically, the wiring V0 can function as a monitor line to output the current flowing through the transistor 52B or the current flowing through the light-emitting element 61 to the outside. The current output to wiring V0 is converted into a voltage by a source follower circuit or the like and output to the outside. Alternatively, it can be converted into a digital signal by an A-D converter or the like and output to the drive circuit section 47, etc.

[0254] In one aspect of the present invention, the light-emitting element described refers to a self-emissive light-emitting element such as an organic EL element (also called an OLED (Organic Light Emitting Diode)). The light-emitting element connected to the pixel circuit can be a self-emissive light-emitting element such as an LED (Light Emitting Diode), microLED, QLED (Quantum-dot Light Emitting Diode), or semiconductor laser.

[0255] In the configuration shown as an example in Figure 14B, the wiring connecting the pixel circuit 51 and the drive circuit 47 can be shortened, thereby reducing the wiring resistance. As a result, data can be written at high speed, and the display device 10 can be driven at high speed. This allows for a sufficient frame duration even with a large number of pixel circuits 51 in the display device 10, thus increasing the pixel density of the display device 10. Furthermore, increasing the pixel density of the display device 10 improves the resolution of the image displayed by the display device 10. For example, the pixel density of the display device 10 can be set to 1000 ppi or more, or 5000 ppi or more, or 7000 ppi or more. Therefore, the display device 10 can be used as a display device for AR or VR, and can be suitably applied to electronic devices such as HMDs where the distance between the display unit and the user is close.

[0256] Figure 15A is a schematic diagram illustrating the connection relationship between the drive circuit section 47 (showing the gate driver circuit GD and source driver circuit SD) and the pixel circuit 51, as shown in Figure 14B. As described above, in one embodiment of the present invention, since the drive circuit section 47 and the pixel circuit 51 are provided on different layers, the pixel circuit 51 can be configured to be provided on the drive circuit section 47.

[0257] The drive circuit section 47 includes a gate driver circuit GD and a source driver circuit SD. The gate driver circuit GD is connected to the pixel circuit 51 located above it via wiring GL. Note that there may be multiple wirings GL, such as the aforementioned wirings GL1 and GL2. The source driver circuit SD is connected to the pixel circuit 51 located above it via wiring SL.

[0258] By overlapping the drive circuit section 47 and the pixel circuit 51, the connection distance (wiring length) between the drive circuit section 47 and the pixel circuit 51 can be made extremely short. As a result, wiring resistance and parasitic capacitance are reduced, so the time required for charging and discharging is reduced, enabling high-speed driving. Power consumption can also be reduced. Furthermore, miniaturization and weight reduction can be achieved. In addition, the integration density of the pixel circuit 51 can be increased.

[0259] Note that the gate driver circuit GD and the source driver circuit SD do not necessarily have to be in the region overlapping with the pixel circuit 51. For example, as shown in Figure 15B, it is possible to configure the system so that the gate driver circuit GD is located in the region overlapping with the pixel circuit 51, and the source driver circuit SD is located in a region that does not overlap with the pixel circuit 51.

[0260] Figures 14A and 14B show a pixel circuit 51 having a total of three transistors as an example, but the present invention is not limited to this. Below, we will describe examples of pixel circuit configurations applicable to the pixel circuit 51.

[0261] The pixel circuit 51A shown in Figure 16A includes transistors 52A and 52B, and a capacitor 53. Figure 16A also shows a light-emitting element 61 connected to the pixel circuit 51A. Wirings SL, GL, ANO, and VCOM are connected to the pixel circuit 51A.

[0262] Transistor 52A's gate is connected to wiring GL, one of its source and drain is connected to wiring SL, and the other is connected to the gate of transistor 52B and one electrode of capacitive element C1. Transistor 52B's source and drain are connected to wiring ANO, and the other is connected to the anode of light-emitting element 61. Capacitive element C1's other electrode is connected to the anode of light-emitting element 61. Light-emitting element 61's cathode is connected to wiring VCOM.

[0263] The pixel circuit 51B shown in Figure 16B is configured by adding a transistor 52C to the pixel circuit 51A. Wiring V0 is also connected to the pixel circuit 51B.

[0264] The pixel circuit 51C shown in Figure 16C is an example in which transistors 52A and 52B of the pixel circuit 51A are replaced with transistors having a pair of gates. Similarly, the pixel circuit 51D shown in Figure 16D is an example in which the same transistor is replaced with the same transistor in the pixel circuit 51B. This increases the current that the transistors can supply. While transistors with a pair of gates were used in this example, the design is not limited to this. Furthermore, transistors with a pair of gates, where these gates are connected to different wirings, may also be used. For example, reliability can be improved by using a transistor in which one of the gates is connected to the source.

[0265] The pixel circuit 51E shown in Figure 17A is configured by adding a transistor 52D to the above-mentioned pixel circuit 51B. Furthermore, three wires (wires GL1, GL2, and GL3) that function as gate lines are connected to the pixel circuit 51E.

[0266] Transistor 52D has its gate connected to wiring GL3, and one of its source and drain is connected to the gate of transistor 52B, while the other is connected to wiring V0. Also, the gate of transistor 52A is connected to wiring GL1, and the gate of transistor 52C is connected to wiring GL2.

[0267] By simultaneously making transistors 52C and 52D conduct, the source and gate of transistor 52B become at the same potential, making transistor 52B non-conducting. This allows the current flowing to the light-emitting element 61 to be forcibly interrupted. Such a pixel circuit is suitable when using a display method that alternates between display periods and off periods.

[0268] The pixel circuit 51F shown in Figure 17B is an example in which a capacitor 53A is added to the above-mentioned pixel circuit 51E. The capacitor 53A functions as a retaining capacitor.

[0269] The pixel circuit 51G shown in Figure 17C and the pixel circuit 51H shown in Figure 17D are examples of cases where a transistor having a pair of gates is applied to the above-mentioned pixel circuit 51E or pixel circuit 51F, respectively. Transistors 52A, 52C, and 52D are transistors with a pair of connected gates, while transistor 52B is a transistor in which one gate is connected to the source.

[0270] <Example of Memory Circuit Configuration> Here, examples of the configurations of memory circuits 63A to 63D applicable to the memory circuit of the memory circuit unit 63 described in Embodiment 1 above will be explained with reference to Figures 18A to 18D. The memory circuits 63A to 63D shown in Figures 18A to 18D are memory circuits using OS transistors, and can be broadly classified as NOSRAM (registered trademark) in Figures 18A and 18B, and DOSRAM (registered trademark) in Figures 18C and 18D.

[0271] NOSRAM is a type of gain-cell DRAM in which the writing transistors in the memory circuit are composed of OS transistors. NOSRAM is an abbreviation for Nonvolatile Oxide Semiconductor RAM. DOSRAM is a memory device in which the memory circuit is a 1T1C (1 transistor 1 capacitance) type cell and the writing transistors are transistors using oxide semiconductors. DOSRAM is an abbreviation for Dynamic Oxide Semiconductor Random Access Memory.

[0272] Figure 18A shows an example of a circuit configuration applicable to the memory circuit of the memory circuit unit 63. Here, the memory circuit 63A is a two-transistor type (2T) gain cell. The memory circuit 63A has transistors MW1 and MR1 and a capacitive element CS1. Transistor MW1 is a writing transistor, and transistor MR1 is a reading transistor. The back gates of transistors MW1 and MR1 are connected to wiring BGL.

[0273] Since the readout transistor is made up of OS transistors, the memory circuit 63A does not consume power to retain data. Therefore, the memory circuit 63A can be used as a low-power memory circuit capable of retaining data for a long period of time.

[0274] The memory circuit 63B shown in Figure 18B is a 3T type gain cell and has transistors MW2, MR2, MS2, and a capacitance element CS2. Transistors MW2, MR2, and MS2 are the write transistor, read transistor, and select transistor, respectively. The back gates of transistors MW2, MR2, and MS2 are connected to wiring BGL. The memory circuit 63B is connected to word lines RWL, WWL, bit lines RBL, WBL, capacitance line CDL, and power line PL2. For example, the ground potential GND is input to the capacitance line CDL and the power line PL2.

[0275] Figures 18C and 18D show examples of 1T1C (capacitance) type memory circuits. The memory circuit 63C shown in Figure 18C is connected to the word line WL, bit line BL, capacitance line CDL, and wiring BGL. The memory circuit 63C has a transistor MW3 and a capacitance element CS3. The back gate of transistor MW3 is connected to wiring BGL. The memory circuit 63D shown in Figure 18D illustrates the configuration of a ferroelectric memory using a capacitance element having a ferroelectric material in the capacitance element CS4. For example, HfZrO is used as the ferroelectric material. Ｘ You can use it.

[0276] <Example of Pixel Circuit Configuration Connected to Light-Receiving Element> Figure 19A shows an example of the configuration of a pixel circuit 56 applicable to the pixel circuit of the pixel circuit unit 57, and a light-receiving element 62 connected to the pixel circuit 56. The pixel circuit 56 has a transistor 132, a transistor 133, a transistor 134, a transistor 135, and a capacitor 138. Note that a configuration without the capacitor 138 is also possible.

[0277] One electrode (cathode) of the light-receiving element 62 is connected to either the source or the drain of transistor 132. The other source or drain of transistor 132 is connected to either the source or the drain of transistor 133. One source or drain of transistor 133 is connected to one electrode of capacitor 138. One electrode of capacitor 138 is connected to the gate of transistor 134. One source or drain of transistor 134 is connected to either the source or the drain of transistor 135.

[0278] Here, the wiring connecting the other source or drain of transistor 132, the other source or drain of transistor 133, one electrode of capacitor 138, and the gate of transistor 134 is defined as node FD. Node FD can function as a charge detection unit.

[0279] The other electrode (anode) of the light-receiving element 62 is connected to the wiring 121. The gate of transistor 132 is connected to the wiring 127. The other source or drain of transistor 133 is connected to the wiring 122. The other source or drain of transistor 134 is connected to the wiring 129. The gate of transistor 133 is connected to the wiring 126. The gate of transistor 135 is connected to the wiring 128. The other electrode of capacitor 138 is connected to a reference potential line, such as the GND wiring. The other source or drain of transistor 135 is connected to the wiring 352.

[0280] Wires 127, 126, and 128 function as signal lines to control the on and off states of each transistor. Wire 352 functions as an output line.

[0281] Wires 121, 122, and 129 function as power lines. In the configuration shown in Figure 19A, the cathode side of the photodetector 62 is connected to the transistor 132, and the node FD can be reset to a high potential. Therefore, wire 122 is set to a high potential (higher potential than wire 121).

[0282] In Figure 19A, the cathode side of the photodetector 62 is shown connected to node FD. However, the anode side of the photodetector 62 may be connected to either the source or drain of transistor 132. In this case, since node FD is reset to a low potential for operation, the wiring 122 is set to a low potential (lower than the wiring 121).

[0283] Transistor 132 has the function of controlling the potential of node FD. Transistor 132 is also called the "transfer transistor". Transistor 133 has the function of resetting the potential of node FD. Transistor 133 is also called the "reset transistor". Transistor 134 functions as a source follower circuit and can output the potential of node FD as image data to wiring 352. Transistor 135 has the function of selecting the pixel to which the image data is output. Transistor 134 is also called the "amplifier transistor". Transistor 135 is also called the "selection transistor".

[0284] Alternatively, as shown in Figure 19B, a configuration may be used in which multiple sets of light-receiving elements 62 and transistors 132 are connected to a single node FD, with each set of light-receiving elements 62 and transistor 132 considered as one unit. In Figure 19B, the first set of light-receiving elements 62 and transistor 132 is shown as light-receiving element 62_1 and transistor 132_1. The gate of transistor 132_1 is connected to wiring 127_1. The second set of light-receiving elements 62 and transistor 132 is shown as light-receiving element 62_2 and transistor 132_2. The gate of transistor 132_2 is connected to wiring 127_2. The kth set (where k is an integer greater than or equal to 1) of light-receiving elements 62 and transistor 132 is shown as light-receiving element 62_k and transistor 132_k. The gate of transistor 132_k is connected to wiring 127_k. By connecting multiple sets of photodetectors 62 and transistors 132 to a single node FD, the number of transistors per photodetector 62 can be reduced, thereby increasing the mounting density of the pixel circuit 56.

[0285] <Schematic top view of a light-emitting element and schematic cross-sectional view thereof> Figure 20A is a schematic top view showing an example of a configuration in a display device 10 according to one embodiment of the present invention, in which a light-emitting element and a light-receiving element are arranged within a single pixel. The display device 10 has a plurality of light-emitting elements 61R that emit red light, a light-emitting element 61G that emits green light, a light-emitting element 61B that emits blue light, and a plurality of light-receiving elements 62. In Figure 20A, the symbols R, G, and B are added to the light-emitting area of ​​each light-emitting element 61 to simplify the distinction between them. The symbol PD is added to the light-receiving area of ​​each light-receiving element 62.

[0286] The light-emitting elements 61R, 61G, and 61B are each arranged in a matrix. Figure 20A shows an example in which the light-emitting elements 61R, 61G, and 61B are arranged sequentially in the X direction, and the light-receiving elements 62 are locally arranged at the bottom edge. Figure 20A also shows an example configuration in which light-emitting elements 61 that emit light of the same color are arranged in the Y direction intersecting the X direction. In the display device 10 shown in Figure 20A, for example, a pixel 80 can be composed of sub-pixels having light-emitting elements 61R, sub-pixels having light-emitting elements 61G, and sub-pixels having light-emitting elements 61B arranged in the X direction.

[0287] It is preferable to use EL elements such as OLEDs (Organic Light Emitting Diodes) or QLEDs (Quantum-dot Light Emitting Diodes) as light-emitting elements 61R, 61G, and 61B. Examples of light-emitting materials for EL elements include fluorescent materials, phosphorescent materials, inorganic compounds (quantum dot materials, etc.), and thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) materials).

[0288] For example, a pn-type or PIN-type photodiode can be used as the light-receiving element 62. The light-receiving element 62 functions as a photoelectric conversion element that detects light incident on it and generates an electric charge. The amount of charge generated is determined based on the amount of incident light.

[0289] In particular, it is preferable to use an organic photodiode having a layer containing an organic compound as the light-receiving element 62. Organic photodiodes can be easily made thinner, lighter, and larger in area, and because they offer a high degree of freedom in shape and design, they can be applied to various display devices.

[0290] In one aspect of the present invention, an organic EL element is used as the light-emitting element 61, and an organic photodiode is used as the light-receiving element 62. The organic EL element and the organic photodiode can be formed on the same substrate. Therefore, an organic photodiode can be incorporated into a display device using an organic EL element. It is preferable to separate the organic EL elements and the organic photodiode by photolithography. This allows the spacing between the light-emitting elements and the organic photodiode to be reduced, thereby enabling a display device with a higher aperture ratio compared to the case where a shadow mask such as a metal mask is used.

[0291] Figure 20A shows a common electrode 81 and a connecting electrode 82. Here, the connecting electrode 82 is connected to the common electrode 81. The connecting electrode 82 is provided outside the display section where the light-emitting element 61 and the light-receiving element 62 are arranged. Also in Figure 20A, the common electrode 81, which has an overlapping region with the light-emitting element 61, the light-receiving element 62, and the connecting electrode 82, is shown with a dashed line.

[0292] The connecting electrode 82 can be provided along the outer circumference of the display unit. For example, it may be provided along one side of the outer circumference of the display unit, or it may be provided across two or more sides of the outer circumference of the display unit. That is, if the top surface shape of the display unit is rectangular, the top surface shape of the connecting electrode 82 can be strip-shaped, L-shaped, U-shaped (angle bracket-shaped), or square, etc.

[0293] Figure 20B is a schematic top view showing an example configuration of the display device 10, and is a modified version of the display device 10 shown in Figure 20A. The display device 10 shown in Figure 20B differs from the display device 10 shown in Figure 20A in that it has a light-emitting element 61IR that emits infrared light. The light-emitting element 61IR can emit, for example, near-infrared light (light with a wavelength of 750 nm to 1300 nm).

[0294] In the example shown in Figure 20B, in addition to light-emitting elements 61R, 61G, and 61B, a light-emitting element 61IR is arranged in the X direction, and a light-receiving element 62 is arranged below them. The light-receiving element 62 has the function of detecting infrared light.

[0295] Figure 21A is a cross-sectional view corresponding to the dashed line A1-A2 in Figure 20A, and Figure 21B is a cross-sectional view corresponding to the dashed line B1-B2 in Figure 20A. Furthermore, Figure 21C is a cross-sectional view corresponding to the dashed line C1-C2 in Figure 20A, and Figure 21D is a cross-sectional view corresponding to the dashed line D1-D2 in Figure 20A. The light-emitting element 61R, light-emitting element 61G, light-emitting element 61B, and light-receiving element 62 are provided on the substrate 83. In addition, if the display device 10 has a light-emitting element 61IR, the light-emitting element 61IR is provided on the substrate 83.

[0296] Figure 21A shows an example of the cross-sectional configuration of the light-emitting element 61R, light-emitting element 61G, and light-emitting element 61B. Figure 21B also shows an example of the cross-sectional configuration of the light-receiving element 62.

[0297] The light-emitting element 61R has a pixel electrode 84R, a hole injection layer 85R, a hole transport layer 86R, a light-emitting layer 87R, an electron transport layer 88R, a common layer 89, and a common electrode 81. The light-emitting element 61G has a pixel electrode 84G, a hole injection layer 85G, a hole transport layer 86G, a light-emitting layer 87G, an electron transport layer 88G, a common layer 89, and a common electrode 81. The light-emitting element 61B has a pixel electrode 84B, a hole injection layer 85B, a hole transport layer 86B, a light-emitting layer 87B, an electron transport layer 88B, a common layer 89, and a common electrode 81. The light-receiving element 62 has a pixel electrode 84PD, a hole transport layer 86PD, a light-receiving layer 90, an electron transport layer 88PD, a common layer 89, and a common electrode 81.

[0298] In the light-emitting element 61, the common layer 89 functions as an electron injection layer. On the other hand, in the photodetector 62, the common layer 89 functions as an electron transport layer. Therefore, the photodetector 62 does not need to have an electron transport layer 88PD.

[0299] The hole injection layer 85, the hole transport layer 86, the electron transport layer 88, and the common layer 89 can also be called functional layers.

[0300] The pixel electrode 84, hole injection layer 85, hole transport layer 86, light-emitting layer 87, and electron transport layer 88 can be provided separately for each element. The common layer 89 and common electrode 81 are provided in common for the light-emitting element 61R, light-emitting element 61G, light-emitting element 61B, and light-receiving element 62.

[0301] Furthermore, the light-emitting element 61 and the light-receiving element 62 may have a hole-blocking layer and an electron-blocking layer in addition to the layers shown in Figure 21A. Also, the light-emitting element 61 and the light-receiving element 62 may have layers containing bipolar material (a material with high electron transport and hole transport properties), etc.

[0302] A gap is provided between the common layer 89 and the insulating layer 92, which will be described later. This prevents the common layer 89 from coming into contact with the side surfaces of the light-emitting layer 87, the light-receiving layer 90, the hole transport layer 86, and the hole injection layer 85. This prevents short circuits in the light-emitting element 61 and the light-receiving element 62.

[0303] Figure 21A shows a configuration in which the light-emitting element 61 is provided with, in order from the bottom layer, a pixel electrode 84, a hole injection layer 85, a hole transport layer 86, a light-emitting layer 87, an electron transport layer 88, a common layer 89 (electron injection layer), and a common electrode 81, and the light-receiving element 62 is provided with, in order from the bottom layer, a pixel electrode 84PD, a hole transport layer 86PD, a light-receiving layer 90, an electron transport layer 88PD, a common layer 89, and a common electrode 81. However, the present invention is not limited to this configuration. For example, the light-emitting element 61 may be provided with, in order from the bottom layer, a pixel electrode, an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, a hole injection layer, and a common electrode, and the light-receiving element 62 may be provided with, in order from the bottom layer, a pixel electrode, an electron transport layer, a light-receiving layer, a hole transport layer, and a common electrode. In this case, the hole injection layer of the light-emitting element 61 can be a common layer, and this common layer can be provided between the hole transport layer of the light-receiving element 62 and the common electrode. Furthermore, in the light-emitting element 61, the electron injection layer can be separated for each element.

[0304] In the following explanation, we will assume that the electron transport layer is located above the hole transport layer. However, by, for example, substituting "electron" with "hole" and "hole" with "electron," the following explanation can also be applied when the electron transport layer is located below the hole transport layer.

[0305] The light-emitting layer 87R of the light-emitting element 61R has a light-emitting organic compound that emits light having a peak in at least the red wavelength range. The light-emitting layer 87G of the light-emitting element 61G has a light-emitting organic compound that emits light having a peak in at least the green wavelength range. The light-emitting layer 87B of the light-emitting element 61B has a light-emitting organic compound that emits light having a peak in at least the blue wavelength range. The light-receiving layer 90 of the light-receiving element 62 has, for example, an organic compound that has detection sensitivity in the visible light wavelength range.

[0306] A conductive film that is transparent to visible light is used on either the pixel electrode 84 or the common electrode 81, and a conductive film that is reflective is used on the other. By making the pixel electrode 84 transparent and the common electrode 81 reflective, the display device 10 can be made into a bottom-emission type display device. On the other hand, by making the pixel electrode 84 reflective and the common electrode 81 transparent, the display device 10 can be made into a top-emission type display device. Furthermore, by making both the pixel electrode 84 and the common electrode 81 transparent, the display device 10 can be made into a dual-emission type display device.

[0307] An insulating layer 92 is provided to cover the ends of the pixel electrode 84R, the ends of the pixel electrode 84G, the ends of the pixel electrode 84B, and the ends of the pixel electrode 84PD. The ends of the insulating layer 92 are preferably tapered. The insulating layer 92 may be omitted if it is not needed.

[0308] For example, the hole injection layer 85R, hole injection layer 85G, hole injection layer 85B, and hole transport layer 86PD each have a region in contact with the upper surface of the pixel electrode 84 and a region in contact with the surface of the insulating layer 92. Furthermore, the ends of the hole injection layer 85R, the ends of the hole injection layer 85G, the ends of the hole injection layer 85B, and the ends of the hole transport layer 86PD are located on the insulating layer 92.

[0309] As shown in Figure 21A, a gap is provided between two light-emitting elements 61 that emit light of different colors, for example, between two light-emitting layers 87. In this way, it is preferable that light-emitting layers 87R, 87G, and 87B are arranged so that they do not touch each other. This effectively prevents current from flowing through two adjacent light-emitting layers 87 and causing unintended light emission. As a result, the contrast of the display device 10 can be increased, and thus the display quality of the display device 10 can be improved.

[0310] A protective layer 91 is provided on the common electrode 81. The protective layer 91 has the function of preventing impurities such as water from diffusing to each light-emitting element from above.

[0311] The protective layer 91 can be, for example, a single-layer structure or a multilayer structure including at least an inorganic insulating film. Examples of inorganic insulating films include oxide films or nitride films such as silicon oxide film, silicon oxide nitride film, silicon nitride film, silicon nitride film, aluminum oxide film, aluminum oxide nitride film, and hafnium oxide film. Alternatively, semiconductor materials such as indium gallium oxide and indium gallium zinc oxide may be used as the protective layer 91.

[0312] In this specification, a silicon oxide-nitride film refers to a film in which the oxygen content is greater than the nitrogen content. Similarly, a silicon nitride-oxide film refers to a film in which the nitrogen content is greater than the oxygen content.

[0313] Figure 21C shows an example of the cross-sectional configuration of the display device 10 in the Y direction, specifically showing an example of the cross-sectional configuration of the light-emitting element 61R and the light-receiving element 62. Note that the light-emitting elements 61G and 61B can also be arranged in the Y direction in the same way as the light-emitting element 61R.

[0314] Figure 21D shows a connection portion 93 where the connecting electrode 82 and the common electrode 81 are connected. At the connection portion 93, the common electrode 81 is placed in contact with the connecting electrode 82, and a protective layer 91 is provided to cover the common electrode 81. In addition, an insulating layer 92 is provided to cover the end of the connecting electrode 82.

[0315] <Example of configuration in cross-section> Figure 22 shows an example of the configuration in cross-section of the display device 10. The display device 10 has a configuration in which a transistor 310 with a channel formed on a substrate 301 and a transistor 320 containing a metal oxide on a semiconductor layer in which the channel is formed are stacked.

[0316] An insulating layer 261 is provided covering the transistor 310, and a conductive layer 251 is provided on the insulating layer 261. A conductive layer 271 is also provided on the insulating layer 261 to connect the transistor 310 and the conductive layer 251. An insulating layer 262 is provided covering the conductive layer 251, and a conductive layer 252 is provided on the insulating layer 262. The conductive layers 251 and 252 each function as wiring. An insulating layer 263 and an insulating layer 332 are provided covering the conductive layer 252, and a transistor 320 is provided on the insulating layer 332. An insulating layer 265 is provided covering the transistor 320, and a capacitor 240 is provided on the insulating layer 265. The capacitor 240 and the transistor 320 are connected by a plug 274.

[0317] Transistor 320 can be used as a transistor constituting a pixel circuit or a transistor constituting a memory circuit. Transistor 310 can be used as a transistor constituting a memory circuit, a transistor constituting a drive circuit for driving the pixel circuit, or a transistor constituting an arithmetic circuit. Transistors 310 and 320 can also be used as transistors constituting various circuits such as arithmetic circuits or memory circuits.

[0318] The transistor 310 is a transistor having a channel-forming region in the substrate 301. As the substrate 301, a semiconductor substrate such as a single-crystal silicon substrate can be used. The transistor 310 has a part of the substrate 301, a conductive layer 311, a low-resistance region 312, an insulating layer 313, and an insulating layer 314. The conductive layer 311 functions as a gate electrode. The insulating layer 313 is located between the substrate 301 and the conductive layer 311 and functions as a gate insulating layer. The low-resistance region 312 is a region of the substrate 301 doped with impurities and functions as either a source or a drain. The insulating layer 314 is provided covering the side surface of the conductive layer 311.

[0319] Furthermore, an element isolation layer 315 is provided between two adjacent transistors 310 so as to be embedded in the substrate 301.

[0320] Transistor 320 is a transistor in which a metal oxide (also called an oxide semiconductor) is applied to the semiconductor layer where the channel is formed.

[0321] The transistor 320 has a semiconductor layer 321, an insulating layer 323, a conductive layer 324, a pair of conductive layers 325, an insulating layer 326, and a conductive layer 327.

[0322] The insulating layer 332 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the substrate 301 to the transistor 320, and prevents oxygen from detaching from the semiconductor layer 321 to the insulating layer 332. As the insulating layer 332, for example, a film that is less susceptible to hydrogen or oxygen diffusion than a silicon oxide film can be used, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film.

[0323] A conductive layer 327 is provided on the insulating layer 332, and an insulating layer 326 is provided covering the conductive layer 327. The conductive layer 327 functions as the first gate electrode of the transistor 320, and a part of the insulating layer 326 functions as the first gate insulating layer. It is preferable to use an oxide insulating film such as a silicon oxide film for at least the portion of the insulating layer 326 that is in contact with the semiconductor layer 321. It is preferable that the upper surface of the insulating layer 326 is flattened.

[0324] The semiconductor layer 321 is provided on the insulating layer 326. Preferably, the semiconductor layer 321 has a metal oxide (also called an oxide semiconductor) film having semiconductor properties. Preferably, the semiconductor layer 321 uses a metal oxide containing at least one of indium, element M (element M is aluminum, gallium, yttrium, or tin), and zinc. OS transistors using such metal oxides in the channel formation region have the characteristic of having a very low off-current. Therefore, using an OS transistor as a transistor provided in a pixel circuit is preferable because it can retain analog data written to the pixel circuit for a long period of time. Similarly, using an OS transistor as a transistor used in a memory circuit is preferable because it can retain analog data written to the memory circuit for a long period of time.

[0325] A pair of conductive layers 325 are provided in contact with the semiconductor layer 321 and function as source electrodes and drain electrodes.

[0326] Furthermore, an insulating layer 328 is provided covering the top and side surfaces of the pair of conductive layers 325, as well as the side surfaces of the semiconductor layer 321, and an insulating layer 264 is provided on the insulating layer 328. The insulating layer 328 functions as a barrier layer to prevent impurities such as water or hydrogen from diffusing into the semiconductor layer 321 from the insulating layer 264, etc., and to prevent oxygen from detaching from the semiconductor layer 321. An insulating film similar to that used for the insulating layer 332 can be used for the insulating layer 328.

[0327] An opening is provided in the insulating layer 328 and the insulating layer 264 that reaches the semiconductor layer 321. Inside this opening, the insulating layer 323 and the conductive layer 324 are embedded, in contact with the insulating layer 264, the insulating layer 328, the side surfaces of the conductive layer 325, and the upper surface of the semiconductor layer 321. The conductive layer 324 functions as a second gate electrode, and the insulating layer 323 functions as a second gate insulating layer.

[0328] The upper surfaces of the conductive layer 324, the insulating layer 323, and the insulating layer 264 are flattened so that their heights are roughly the same, and the insulating layer 329 and insulating layer 265 are provided covering them.

[0329] The insulating layers 264 and 265 function as an interlayer insulating layer. The insulating layer 329 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the insulating layer 265 or the like into the transistor 320. As the insulating layer 329, an insulating film similar to the insulating layer 328 and the insulating layer 332 can be used.

[0330] The plug 274 connected to one of the pair of conductive layers 325 is provided so as to be embedded in the insulating layer 265, the insulating layer 329, and the insulating layer 264.

[0331] The capacitor 240 has a conductive layer 241, a conductive layer 245, and an insulating layer 243 positioned therebetween. The conductive layer 241 functions as one electrode of the capacitor 240, the conductive layer 245 functions as the other electrode of the capacitor 240, and the insulating layer 243 functions as a dielectric of the capacitor 240.

[0332] The conductive layer 245 is provided on the insulating layer 265 and is embedded in the insulating layer 254. The conductive layer 245 is connected to one of the source or drain of the transistor 320 by a plug 274 embedded in the insulating layers 328, 264, 329, and 265. The insulating layer 243 is provided to cover the conductive layer 245. The conductive layer 241 is provided in a region overlapping the conductive layer 245 via the insulating layer 243.

[0333] An insulating layer 255 is provided to cover the capacitor 240, and a light-emitting element 61, a light-receiving element 62, and the like are provided on the insulating layer 255. A protective layer 91 is provided on the light-emitting element 61 and the light-receiving element 62, and a substrate 420 is bonded to the upper surface of the protective layer 91 by a resin layer 419. The substrate 420 can be a light-transmissive substrate. [[ID=I4]]

[0334] The pixel electrode 84 of the light-emitting element 61 and the pixel electrode 84PD of the light-receiving element 62 are connected to one of the source or drain of the transistor 320 by a plug 256 embedded in the insulating layer 255, the conductive layer 245 embedded in the insulating layer 254, and a plug 274 embedded in the insulating layers 328, 264, 329, and 265.

[0335] With such a configuration, pixel circuits and OS transistors that form memory circuits can be arranged directly below the light-receiving elements and light-emitting elements, and drive circuits, arithmetic circuits, etc. can be arranged, so that it becomes possible to miniaturize a display device with improved performance.

[0336] Note that the transistor 320 can also be a transistor with a different configuration.

[0337] FIG. 23A is a plan view of the transistor 752 that can be replaced with the transistor 320 or added to the configuration of FIG. 22. FIG. 23B is a cross-sectional view corresponding to the portion of the dashed-dotted line A1 - A2 shown in FIG. 23A. FIG. 23C is a cross-sectional view corresponding to the portion of the dashed-dotted line A3 - A4 shown in FIG. 23A.

[0338] In FIGS. 23A to 23C, the direction of the dashed-dotted line A1 - A2 is defined as the X direction, the direction of the dashed-dotted line A3 - A4 is defined as the Y direction. Also, the direction perpendicular to the X direction and the Y direction is defined as the Z direction.

[0339] The transistor 752 shown in FIGS. 23A to 23C includes insulators IS1 to IS3, an insulator GI1, conductors ME1 to ME3, and a semiconductor SC1.

[0340] As an example, the insulator IS1 functions as an underlying film for providing a source, a drain, and a channel formation region of the transistor 752 above it. For the insulator IS1, for example, silicon oxide, silicon oxynitride, silicon nitride oxynitride, or silicon nitride can be used. Alternatively, for the insulator IS1, for example, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, or silicon oxide having pores can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having pores are preferable because they can easily form a region containing oxygen that desorbs by heating. Alternatively, for the insulator IS1, for example, a resin can be used. Also, the material used for the insulator IS1 may be an appropriate combination of the above-described insulating materials.

[0341] Conductor ME1 is a conductor (sometimes referred to as a terminal, wire, etc.) that functions as either the source or the drain in transistor 752. Conductor ME2 is a conductor (sometimes referred to as a terminal, wire, etc.) that functions as either the source or the drain in transistor 752.

[0342] In Figures 23A to 23C, the conductor ME1 is provided as a wiring element, extending in the Y direction, as an example. Similarly, the conductor ME2 is provided as a wiring element, extending in the X direction, as an example.

[0343] For conductors ME1, ME2, and ME3, it is preferable to use metallic elements selected from, for example, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, cobalt, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or alloys comprising two or more of the above-mentioned metallic elements, or alloys combining two or more of the above-mentioned metallic elements. Furthermore, for conductors ME1, ME2, and ME3, it is preferable to use, for example, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel. Tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Alternatively, the conductor may be a semiconductor with high electrical conductivity, such as polycrystalline silicon containing impurity elements (e.g., phosphorus or arsenic), or a silicide (e.g., nickel silicide).

[0344] Furthermore, conductive oxides may be used for conductors ME1, ME2, and ME3. Examples of conductive oxides include indium oxide, zinc oxide, In-Sn oxide (ITO), In-Zn oxide (also known as IZO®), In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn-Si oxide (also known as silicon-containing ITO or ITSO), zinc oxide with added gallium, and In-Ga-Zn oxide. Conductive oxides containing indium are particularly preferred due to their high conductivity.

[0345] Furthermore, multiple conductive films formed from the above materials may be used in a laminated structure. For example, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material. Specific examples of laminated conductive film structures include, for instance, a laminated structure of indium oxide and a ruthenium-containing metal film. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with a nitrogen-containing conductive material. Furthermore, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material and a nitrogen-containing conductive material.

[0346] Furthermore, the insulator IS2 functions, for example, as an interlayer film separating the source and drain in the transistor 752. For the insulating film IS2, for example, a material applicable to the insulator IS1 can be used. When the semiconductor SC1 functions as an oxide semiconductor, it is preferable to use silicon oxide, silicon oxynitride, or silicon oxide with vacancies. These materials can easily form regions containing oxygen that is desorbed by heating, and the desorbed oxygen can be supplied to the metal oxide. As a result, the carrier concentration of the metal oxide decreases at the interface of the semiconductor SC1 in contact with the insulator IS2 and in the vicinity of the interface, making the interface of the semiconductor SC1 and the vicinity of the interface i-type or substantially i-type. Therefore, the interface of the semiconductor SC1 and the vicinity of the interface can function as a channel formation region in the transistor 752.

[0347] The semiconductor SC1 can be, for example, a metal oxide that functions as an oxide semiconductor. In this case, the transistor 752 becomes an OS transistor. As an example, the metal oxide preferably contains at least indium, or preferably contains indium or zinc. In particular, it is preferable that it contains indium and zinc. In addition, it is preferable that it contains element M. As element M, one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and antimony can be used. In particular, it is preferable that element M is one or more of aluminum, gallium, yttrium, or tin. Furthermore, it is even more preferable that element M contains either or both of gallium and tin.

[0348] More specifically, indium oxide (sometimes called indium oxide) can be suitably used as the metal oxide. Alternatively, as metal oxides, gallium oxide, zinc oxide (also called zinc oxide), indium zinc oxide (In-Zn oxide, also written as IZO®), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also written as GZO), aluminum zinc oxide (Al-Zn oxide, also written as AZO), and Examples include zinc-aluminum oxide (In-Al-Zn oxide, also written as IAZO), indium-tin zinc oxide (In-Sn-Zn oxide, also written as ITZO®), indium-titanium zinc oxide (In-Ti-Zn oxide), indium-gallium zinc oxide (In-Ga-Zn oxide, also written as IGZO), indium-gallium-tin zinc oxide (In-Ga-Sn-Zn oxide, also written as IGZTO), and indium-gallium-aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as IGAZO, IGZAO, or IAGZO). Other examples include silicon-containing indium-tin oxide, gallium-tin oxide (Ga-Sn oxide), and aluminum-tin oxide (Al-Sn oxide).

[0349] Furthermore, if the semiconductor SC1 is a metal oxide that functions as an oxide semiconductor, it is preferable to form it using the ALD method. As shown in Figures 23B and 23C, when forming the semiconductor SC1 in a stepped region, using the ALD method allows for good coverage.

[0350] Furthermore, when using a metal oxide that functions as an oxide semiconductor for semiconductor SC1, it is preferable to perform microwave treatment in an oxygen-containing atmosphere during or after film formation of the metal oxide to reduce the impurity concentration in the metal oxide. Examples of impurities include hydrogen and carbon. Microwave treatment can also sometimes improve the crystallinity of the metal oxide. Here, microwave treatment refers to a process using, for example, a device with a power supply that generates high-density plasma using microwaves.

[0351] Furthermore, it is preferable to use a crystalline metal oxide layer for the semiconductor SC1. For example, a metal oxide layer having a CAAC (c-axis-aligned crystalline) structure, a polycrystalline structure, a microcrystalline structure, or a nanocrystalline (nc: nanocrystalline) structure can be used. By using a crystalline metal oxide layer for the semiconductor SC1, the defect level density in the semiconductor SC1 can be reduced, and a highly reliable display device can be realized.

[0352] For semiconductor SC1, it is preferable to use indium oxide (also called In oxide or IO) as an example. Alternatively, it is preferable to use In-Ga-Zn oxide for semiconductor SC1. In particular, it is more preferable that the In-Ga-Zn oxide be a metal oxide with a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or close to that, 4:2:3 [atomic ratio] or close to that, or 3:1:2 [atomic ratio] or close to that. Furthermore, for semiconductor film SC1A, it is preferable to use In-Zn oxide as another example. In particular, it is more preferable that the In-Zn oxide be a metal oxide with a composition of In:Zn = 4:1 [atomic ratio] or close to that.

[0353] The semiconductor SC1 preferably has a stacked structure of multiple oxide layers having different atomic ratios of each metal atom. For example, consider a first metal oxide and a second metal oxide formed on the first metal oxide. If each metal oxide contains at least indium (In) and element M, it is preferable that the ratio of the number of atoms of element M contained in the first metal oxide to the total number of atoms of all elements constituting the first metal oxide is higher than the ratio of the number of atoms of element M contained in the second metal oxide to the total number of atoms of all elements constituting the second metal oxide. Furthermore, it is preferable that the atomic ratio of element M contained in the first metal oxide to In is higher than the atomic ratio of element M contained in the second metal oxide to In.

[0354] Specifically, as the first metal oxide, a metal oxide with a composition of In:Ga:Zn = 1:3:4 [atomic ratio] or close to it, 1:3:2 [atomic ratio] or close to it, or 1:1:0.5 [atomic ratio] or close to it may be used. Furthermore, as the second metal oxide, a metal oxide with a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or close to it, 4:2:3 [atomic ratio] or close to it, or 3:1:2 [atomic ratio] or close to it may be used. Note that "close to it" includes a range of ±30% of the desired atomic ratio.

[0355] In this case, the primary carrier pathway becomes the second metal oxide. By configuring the first metal oxide as described above, the defect level density at the interface between the first and second metal oxides can be reduced. As a result, the influence of interface scattering on carrier conduction is reduced, and the transistor can achieve high on-current and high frequency characteristics.

[0356] Furthermore, an opening KK1 is formed in the region of the insulator IS2 where the transistor 752 is provided, with its side surface being approximately perpendicular to the X-Y plane (taper angle of 70° to 110°). In addition, the semiconductor SC1, which includes the channel formation region of the transistor 752, is provided to be in contact with the conductor ME1 and the conductor ME2 through the opening KK1.

[0357] Furthermore, in transistor 752, an insulator GI1 is provided on the semiconductor SC1. Specifically, in a plan view, the insulator GI1 is positioned so as to overlap the channel formation region included in the semiconductor SC1. The insulator GI1 functions as a gate insulating film in transistor 752.

[0358] Insulator GI1 includes, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), and strontium titanate (SrTiO). ３ ), or (Ba, Sr)TiO ３ It is preferable to use an insulator containing a so-called high-k material such as (BST) in a single layer or laminate. Alternatively, the insulator GI1 may be an oxide having aluminum and hafnium, an oxidized nitride having aluminum and hafnium, an oxide having silicon and hafnium (also called hafnium silicate, HfxSiOy (where x and y are any number)), an oxidized nitride having silicon and hafnium, or a nitride having silicon and hafnium, as an insulator with a high dielectric constant. Furthermore, the insulator GI1 may be made of a material that can be used for the insulator IS1. For example, the insulator GI1 may be silicon oxide, silicon oxidized nitride, silicon nitride, or silicon nitride.

[0359] Furthermore, in transistor 752, the conductor ME3 is provided on the insulator GI1 so as to fill the opening KK1. Conductor ME3 is a conductor (sometimes referred to as a terminal, wiring, etc.) that functions as a gate in transistor 752.

[0360] In Figures 23A to 23C, the conductor ME3 is provided as a wiring element, extending in the Y direction, as an example.

[0361] Insulator IS3 is, for example, a film that functions as an interlayer. Therefore, it is preferable that insulator IS3 has an insulating material with a low dielectric constant. By using an insulating material with a low dielectric constant as the interlayer, parasitic capacitance that occurs between wiring can be reduced.

[0362] As the insulator IS3, for example, materials applicable to the insulator IS1 can be used.

[0363] As described above, in the transistors 752 shown in FIGS. 23A to 23C, a conductor ME1 that functions as one of a source or a drain is located below the insulator IS2 serving as an interlayer film, and a conductor ME2 that functions as the other of the source or the drain is located above the insulator IS2. Therefore, the transistor 752 has a configuration in which a channel formation region is provided along the opening of the insulator IS2.

[0364] In the transistor 752, the source and the drain are located at different heights, and the current flowing through the semiconductor layer flows in the height direction. That is, since it can be said that the channel length direction has a component in the height direction (vertical direction), the transistor 752 can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel type transistor, or the like.

[0365] As shown in FIGS. 23A to 23C, by providing the channel formation region of the transistor along the side surface of the opening of the insulator that functions as an interlayer film, the occupied area of the transistor can be made smaller than the case where the channel formation region of the transistor is provided along the X-Y plane. Therefore, by forming a circuit using one or both of the transistors 752, the area of the circuit can be made smaller. As a result, it can lead to miniaturization of the display device including the circuit or the display device.

[0366] This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification.

[0367] (Embodiment 3) In this embodiment, an indium oxide film that can be used for the semiconductor SC1 of the transistor included in the display device described in Embodiment 2 above will be described.

[0368] In this specification, indium oxide having at least a crystalline portion or crystalline region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystal IO or crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0369] Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0370] This paper describes the carrier concentration dependence of the hole mobility of indium oxide, silicon, and IGZO.

[0371] IGZO tends to exhibit higher hole mobility as the carrier concentration increases. On the other hand, single-crystal indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases. This trend is similar to that of silicon, where lower dopant (impurity) concentrations in the material reduce impurity scattering and increase hole mobility. In other words, the higher the purity and intrinsic nature of single-crystal indium oxide, the higher its hole mobility. From these results, it can be said that single-crystal indium oxide, unlike IGZO, is a material with physical properties similar to silicon. Note that when indium oxide is not single-crystal (e.g., polycrystalline), the trend may differ from that of single crystals.

[0372] The range of carrier concentrations suitable for the channel formation region of a transistor is 1 × 10⁻⁶. １５ cm −３ This range includes, for example, 1 × 10 １４ cm −３ The above is 1 x 10 １８ cm −３ The range is as follows: By sufficiently reducing the carrier concentration, the hole mobility value can be increased to 270 cm⁻¹. ２ It can be expected to be raised to the level of / (V・s).

[0373] Indium oxide can contain elements that lower the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. These elements can lower the carrier concentration by substituting for indium. Other examples include nitrogen, phosphorus, arsenic, and antimony. These elements can lower the carrier concentration by substituting for oxygen.

[0374] On the other hand, electrical resistance can be reduced by increasing the carrier concentration. For example, the suitable carrier concentration range for the source and drain regions of a transistor, or for a resistor or transparent conductive film, is when the carrier concentration value is 1 × 10⁻⁶ ２０ cm −３ This range includes, for example, 1 × 10 １９ cm −３ The above is 1 x 10 ２２ cm −３ The range is as follows: By making the carrier concentration sufficiently high, the resistivity can be increased to 1 × 10⁻⁶. −４ It is expected that the level can be reduced to below Ω·cm.

[0375] Indium oxide may contain elements that increase the carrier concentration. For example, it is preferable to include elements common to the source and drain electrodes of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use elements in which the oxide is conductive or semiconducting.

[0376] Because indium oxide is an oxide whose valence electrons can be controlled, the region with a low carrier concentration can be used for the channel formation region of the transistor, and the region with a high carrier concentration can be used for the source and drain regions of the transistor. This makes it possible to create a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region). Valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technological concept that would not normally be conceived. By using this technological concept, it is possible to realize a transistor with high mobility, low off-current, normally-off capability, and high reliability.

[0377] The indium oxide film is preferably crystalline. In particular, the indium oxide film is preferably polycrystalline, and more preferably single-crystal. A single-crystal film does not have grain boundaries. By using a single-crystal film, carrier scattering at grain boundaries can be suppressed, enabling the realization of transistors that exhibit high field-effect mobility. Furthermore, it has the excellent effect of suppressing variations in transistor characteristics caused by these grain boundaries.

[0378] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using polycrystalline films, it is preferable to use films with the largest possible grain size and few grain boundaries. In a transistor to which a polycrystalline film is applied, if there are no grain boundaries in the channel formation region, or if no grain boundaries are observed, the channel formation region is located within the single-crystal region contained in the polycrystalline film, and therefore it can be considered a transistor to which a single-crystal film is applied.

[0379] The crystallinity of indium oxide can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for the analysis.

[0380] Furthermore, in this specification, a semiconductor layer in which no grain boundaries are observed in the channel formation region, a semiconductor layer in which the channel formation region is contained within a single crystal grain, or a semiconductor layer in which the crystal axis directions are the same in at least two regions within the channel formation region can be considered as a single crystal film.

[0381] The channel formation region refers to the region of the semiconductor layer that overlaps with (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The crystal grains, grain boundaries, crystal axes, and crystal orientation in the channel formation region can be confirmed by cross-sectional observation including the semiconductor layer, source electrode, and drain electrode.

[0382] Impurities in the indium oxide film can act as a source of carrier scattering, thus potentially causing a decrease in field-effect mobility and inhibiting crystal growth. Examples of impurities in the indium oxide film include boron and silicon. In the channel-forming region of the indium oxide film, lower concentrations of these impurities are preferable. For example, the concentration of each of the above impurity elements should be 0.1% or less, more preferably 0.01% (100 ppm) or less. Note that elements such as carbon and hydrogen may be present in the deposition gas or precursor during film formation, and may remain in the indium oxide film in higher concentrations than the above impurities.

[0383] By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be increased to 50 cm². ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ It can be set to (V・s) or more.

[0384] One of the characteristics of indium oxide films is their higher oxygen permeability (diffusivity) compared to IGZO films. For example, oxygen diffusing into an indium oxide film permeates the film and is released as oxygen molecules. In some cases, it may also be released as water molecules by reacting with hydrogen contained in the film. Furthermore, if there is an oxygen deficiency in the film, diffusing oxygen atoms will fill the deficiency. Because oxygen diffuses easily through indium oxide films, it can be said that oxygen deficiencies are more easily filled in compared to IGZO films.

[0385] Thus, because indium oxide films are more likely to reduce oxygen vacancies in the film compared to IGZO films, applying such indium oxide films to transistors makes it possible to realize transistors with extremely high reliability.

[0386] Furthermore, the indium oxide film diffuses hydrogen. Hydrogen diffusing into the indium oxide film from the outside permeates the film and is released as hydrogen molecules. Alternatively, it reacts with oxygen contained in the film and is released as water molecules.

[0387] Indium oxide is characterized by a small effective electron mass and a large effective hole mass. Furthermore, the effective electron mass of indium oxide is largely independent of the crystal orientation. Therefore, using crystalline indium oxide in transistors allows for the realization of transistors with high field-effect mobility and high frequency characteristics (also known as f-response). Moreover, due to the large effective hole mass, transistors with extremely low off-currents can be realized. For example, by applying an indium oxide film to a transistor, the off-current per 1 μm of channel width is 1 fA (1 × 10⁻¹⁶) at 125°C. −１５ A) Less than or equal to, or 1aA (1 × 10 −１８ A) Less than or equal to 1aA (1 × 10) in a room temperature (25°C) environment. −１８ A) Less than or equal to, or 1zA (1 × 10⁻¹⁰ −２１A) The following is possible. Furthermore, because indium oxide has a smaller effective electron mass and a larger effective hole mass than silicon, it may be possible to realize transistors with higher field-effect mobility and lower off-current than Si transistors.

[0388] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. It is preferable to use a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with the indium oxide for the seed layer. This improves the crystallinity of the indium oxide film. A substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0389] One method for evaluating the degree of lattice mismatch is to use the following lattice mismatch value. The lattice mismatch Δa [%] of the crystals in the formed film (in this case, the indium oxide film) relative to the crystals in the seed layer is given by Δa = ((L １ -L ２ ) / L ２ It is calculated as ) × 100. Here L １ L is the length of the unit cell vector of the crystals in the formed film, or the lattice constant. ２ This is the length of the unit cell vector of the crystal in the seed layer, or the lattice constant.

[0390] The lattice mismatch Δa between the seed layer and the indium oxide film is preferably small in absolute value, and most preferably zero. For example, Δa can be -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less.

[0391] Here, the indium oxide crystal has a cubic structure (bixbite type). For example, yttria-stabilized zirconia (YSZ) crystals can have a cubic structure (fluorite type). The lattice mismatch of the indium oxide crystal with respect to the cubic YSZ crystal is in the range of -2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on a YSZ substrate.

[0392] Furthermore, the crystal structure of the seed layer and the crystal structure of the indium oxide film do not necessarily have to be the same in terms of crystal system or crystal orientation. For example, a film with a hexagonal or trigonal crystal structure can be used beneath an indium oxide film with a cubic crystal structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to crystal orientation necessary for epitaxial growth can be met. Examples of hexagonal or trigonal crystals include wurtzite-type structures and YbFe. ２ O ４ Type structure, Yb ２ Fe ３ O ７ These include type structures and their modified type structures. YbFe ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a type structure is IGZO.

[0393] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0394] (Embodiment 4) This embodiment describes an example of the configuration of an electronic device having a display device according to one aspect of the present invention.

[0395] Figure 24A is a perspective view showing the back, bottom, and right side of the electronic device 100 described in Figure 1A of Embodiment 1.

[0396] In Figure 24A, the housing 101 of the electronic device 100 includes, as an example, a mounting section 106, a buffer member 107, a pair of lenses 108, and a pair of display devices 10_L and 10_R. The display sections 13 of the pair of display devices 10_L and 10_R are each positioned so that they can be seen through the lenses 108 inside the housing 101.

[0397] Furthermore, the light-receiving units 14 in the pair of display devices 10_L and 10_R are each positioned to acquire information about the user's eye 102 and its surroundings. The acquisition of information about the user's eye 102 and its surroundings by the light-receiving unit 14 may be performed via a lens 108 inside the housing 101, or it may be performed without using the lens 108.

[0398] Furthermore, the housing 101 shown in Figure 24A is provided with an input terminal 109 and an output terminal 110. The input terminal 109 can be connected to a cable that supplies image signals (image data) from a video output device or the like, or power to charge a battery provided inside the housing 101. The output terminal 110 functions, for example, as an audio output terminal, and earphones, headphones, etc., can be connected to it.

[0399] Furthermore, it is preferable that the housing 101 has a mechanism that allows adjustment of the left and right positions of the lens 108 and the display devices 10_L and 10_R so that they are in the optimal position according to the user's eye position. It is also preferable that the housing 101 has a mechanism that adjusts the focus by changing the distance between the lens 108 and the display devices 10_L and 10_R.

[0400] The cushioning member 107 is the part that comes into contact with the user's face (forehead, cheeks, etc.). By ensuring that the cushioning member 107 is in close contact with the user's face, light leakage can be prevented, thereby enhancing the sense of immersion. It is preferable to use a soft material for the cushioning member 107 so that it comes into close contact with the user's face when the user wears the electronic device 100. Using such a material is preferable because it feels good against the skin and prevents the user from feeling cold when wearing it in cold seasons. It is preferable to make the components that come into contact with the user's skin, such as the cushioning member 107 or the attachment part 106, removable so that they can be easily cleaned or replaced.

[0401] An electronic device according to one aspect of the present invention may further include an earphone 106A. The earphone 106A has a communication unit (not shown) and has wireless communication functionality. The earphone 106A can output audio data through its wireless communication functionality. The earphone 106A may also have a vibration mechanism to function as a bone conduction earphone.

[0402] Furthermore, the earphone 106A can be configured to be directly connected to the mounting part 106 or connected via a wire, as shown in the earphone 106B in Figure 24B. The earphone 106B and the mounting part 106 may also have magnets. This allows the earphone 106B to be fixed to the mounting part 106 by magnetic force, making storage easier and preferable.

[0403] Figure 25A is a perspective view of a glasses-type electronic device 100A, which is shown as another example of a wearable electronic device. The electronic device 100A shown in Figure 25A illustrates how a pair of display devices 10_L and 10_R are housed in a housing 101.

[0404] The electronic device 100A can project images displayed by the display units 13 of the display devices 10_L and 10_R onto the display area 104 of the optical element 103. Furthermore, because the optical element 103 is translucent, the user can view the image displayed in the display area 104 superimposed on the transmitted image seen through the optical element 103. Therefore, the electronic device 100A is an electronic device capable of AR display.

[0405] The housing 101 is also equipped with a wireless receiver or a connector to which a cable can be connected (not shown), allowing video signals and the like to be supplied to the housing 101. Furthermore, by equipping the housing 101 with an acceleration sensor such as a gyro sensor, the orientation of the user's head can be detected and an image corresponding to that orientation can be displayed in the display area 104.

[0406] Next, using Figure 25B, a method for projecting an image onto the display area 104 of the electronic device 100A will be described. Inside the housing 101, a display device 10, a lens 111, and a reflector 112 are provided. In addition, the portion of the optical element 103 corresponding to the display area 104 has a reflective surface 113 that functions as a half-mirror.

[0407] Light 115 emitted from the display device 10 passes through the lens 111 and is reflected towards the optical member 103 by the reflector 112. Inside the optical member 103, the light 115 undergoes total internal reflection repeatedly at the end face of the optical member 103 and reaches the reflective surface 113, thereby projecting an image onto the reflective surface 113. As a result, the user can see both the light 115 reflected by the reflective surface 113 and the transmitted light 116 that has passed through the optical member 103 (including the reflective surface 113).

[0408] Figure 25B shows an example where the reflector 112 and the reflective surface 113 each have curved surfaces. This increases the degree of freedom in optical design and allows for a thinner optical component 103 compared to when they are flat. However, the reflector 112 and the reflective surface 113 may also be flat.

[0409] As the reflector 112, a material having a mirror surface can be used, and it is preferable that it has a high reflectivity. Also, as the reflective surface 113, a half-mirror that utilizes the reflection of a metal film may be used, but using a prism that utilizes total internal reflection can increase the transmittance of transmitted light 116.

[0410] Here, it is preferable that the housing 101 has a mechanism for adjusting the distance between the lens 111 and the display device 10, or the angle between them. This makes it possible to adjust the focus, enlarge or reduce the image, etc. For example, one or both of the lens 111 or the display device 10 may be configured to move in the optical axis direction.

[0411] Furthermore, it is preferable that the housing 101 has a mechanism that allows the angle of the reflector 112 to be adjusted. By changing the angle of the reflector 112, the position of the display area 104 on which the image is displayed can be changed. This makes it possible to position the display area 104 in an optimal position according to the user's eye position.

[0412] Figure 26 is a perspective view of a goggle-type electronic device 100B, which is shown as another example of a wearable electronic device. The electronic device 100B shown in Figure 26 illustrates an operation button 123, a band-shaped fastener 124, and a pair of display devices 10_L and 10_R provided inside the housing 101. The operation button 123 has functions such as a power button. In addition to the operation button 123, there may be other buttons. The housing 101 is also equipped with a wireless receiver or a connector to which a cable can be connected, so that video signals and the like can be supplied to the housing 101.

[0413] Having two display devices 10_L and 10_R allows the user to view one display unit per eye. This enables the display of high-resolution images even when performing 3D displays using parallax. The fixing device 124 is also equipped with a battery 125. The battery 125 may also be installed in the housing 101. Installing the battery 125 in the fixing device 124 is preferable because it allows the center of gravity of the electronic device 100B to be moved to the rear, improving the user's wearing comfort.

[0414] <Notes Regarding the Description in This Specification, etc.> The above embodiments and descriptions of each component in the embodiments are provided below.

[0415] The configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. Furthermore, if multiple configuration examples are shown within a single embodiment, these configuration examples can be appropriately combined.

[0416] Furthermore, the content described in one embodiment (even if only a part of it) can be applied to, combined with, or substituted for other content described in the same embodiment (even if only a part of it), and / or content described in one or more other embodiments (even if only a part of it).

[0417] The content described in the embodiments refers to the content described using various figures or the content described using text in the specification in each embodiment.

[0418] Furthermore, a diagram (even a part of it) described in one embodiment can be combined with another part of that diagram, another diagram (even a part of it) described in that embodiment, and / or a diagram (even a part of it) described in one or more other embodiments to form even more diagrams.

[0419] Furthermore, in this specification, block diagrams classify components by function and show them as independent blocks. However, in actual circuits, it is difficult to separate components by function, and there may be cases where multiple functions are involved in a single circuit, or where a single function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification and can be appropriately rephrased.

[0420] Furthermore, in the drawings, the size, layer thickness, or area are shown at arbitrary sizes for the sake of explanation. Therefore, they are not necessarily limited to that scale. Also, the drawings are schematic for clarity and are not limited to the shapes or values ​​shown in the drawings. For example, they may include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences.

[0421] In this specification, when describing the connection relationships of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. This is because the source and drain of a transistor vary depending on the transistor's structure or operating conditions. The terms source and drain of a transistor can be appropriately rephrased as source (drain) terminal or source (drain) electrode, etc.

[0422] Furthermore, in this specification, the terms "electrode" or "wiring" do not functionally limit these components. For example, "electrode" may be used as part of "wiring," and vice versa. Moreover, the terms "electrode" or "wiring" also include cases where multiple "electrodes" or "wiring" are formed as a single unit.

[0423] Furthermore, in this specification, voltage and potential may be used interchangeably as appropriate. Voltage is the potential difference from a reference potential; for example, if the reference potential is the ground voltage (earth voltage), then voltage can be replaced with potential. Ground potential does not necessarily mean 0V. Note that potential is relative, and depending on the reference potential, it may change the potential applied to wiring, etc.

[0424] In this specification, terms such as "film" and "layer" can be interchanged. For example, the term "conductive layer" may be changed to "conductive film." Or, for example, the term "insulating film" may be changed to "insulating layer."

[0425] In this specification, a switch refers to a device that has the function of controlling whether or not to allow current to flow by being in a conductive state (on state) or a non-conductive state (off state). Alternatively, a switch refers to a device that has the function of selecting and switching the path through which current flows.

[0426] In this specification, the channel length in a planar transistor refers, for example, to the distance between the source and drain in the region where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate overlap in a planar view of the transistor, or in the region where the channel is formed.

[0427] In this specification, channel width refers, for example, to the length of the region where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate electrode overlap, or the region in which the channel is formed, where the source and drain face each other.

[0428] Furthermore, in this specification, the term "node" can be replaced with terms such as terminal, wiring, electrode, conductive layer, conductor, impurity region, etc., depending on the circuit configuration, device structure, etc. Also, terminals, wiring, etc. can be replaced with "node."

[0429] In this specification, the "on state" of a transistor refers to a state in which the source and drain of the transistor can be considered to be short-circuited. For example, in an n-channel transistor, the state in which the voltage between the gate and source is higher than the threshold voltage, or in a p-channel transistor, the state in which the voltage between the gate and source is lower than the threshold voltage, is called the "on state." The "on state" of a transistor is a state in which current can flow between the source and drain. Therefore, the state in which a transistor is "on" is sometimes referred to as the "conducting state" of the transistor.

[0430] In this specification, the "off state" of a transistor refers to a state in which the source and drain of the transistor can be considered disconnected. For example, in an n-channel transistor, the state in which the voltage between the gate and source is lower than the threshold voltage, or in a p-channel transistor, the state in which the voltage between the gate and source is higher than the threshold voltage, is called the "off state." In some cases, the state of a transistor being in the "off state" is also referred to as the transistor being in a "non-conducting state."

[0431] In this specification, the voltage between the gate and source (gate-source) is sometimes referred to as the "gate voltage," the voltage between the drain and source (drain-source) is sometimes referred to as the "drain voltage," and the voltage between the back gate and source (back gate-source) is sometimes referred to as the "back gate voltage." In addition, the current flowing from the drain to the source is sometimes referred to as the "drain current."

[0432] In this specification, unless otherwise specified, the "off-current" of a transistor refers to the drain current when the transistor is in the off state. In this specification, the off-current, as well as the current flowing from the gate to the source and drain (also called gate leakage current), may be referred to as leakage current.

[0433] In this specification, "connection" includes, for example, "electrical connection." The term "electrical connection" is sometimes used to define the connection relationship of circuit elements as a physical object. Furthermore, "electrical connection" includes both "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the use of circuit elements (e.g., transistors, switches, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected through one or more circuit elements. A and B refer to objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0434] For example, assuming a circuit including A and B is in operation, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected" as physical objects. Furthermore, even if there is a timing during the circuit's operation when no electrical signals are exchanged or potential interactions occur between A and B, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected."

[0435] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where "A and B are not indirectly connected" is when an insulator is interposed in the path from A to B. Specifically, this includes cases where a capacitive element is connected between A and B, or where a transistor gate insulating film is interposed between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of a transistor are indirectly connected."

[0436] Another example of a situation where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via source and drain in the path from A to B, and a constant potential V is supplied to the nodes between the transistors from a power supply, GND, etc.

[0437] 10: Display device, 11: Substrate, 12: Substrate, 13: Display unit, 15: Terminal unit, 16: Pixel, 40: Layer, 41: Display control circuit, 45: RC calculation circuit unit, 47: Drive circuit unit, 48: Peripheral calculation circuit unit, 49: Weight switching unit, 50: Layer, 55: Pixel circuit unit, 57: Pixel circuit unit, 59: Sum-accumulate calculation circuit unit, 60: Layer, 61: Light-emitting element, 62: Light-receiving element, 63: Memory circuit unit, 100: Electronic device, 101: Housing, 102: Eye

Claims

It comprises a housing and a display device provided inside the housing, The display device is provided with a first layer, a second layer, and a third layer stacked in that order. The first layer is provided with a weight switching unit and a peripheral calculation circuit unit. The second layer is provided with a first pixel circuit section, a second pixel circuit section, a memory circuit section, and a multiply-accumulate circuit section. The third layer is provided with a light-receiving element and a light-emitting element. The first pixel circuit section has a function to control the light-emitting element, The second pixel circuit section has a function of controlling the light-receiving element, The memory circuit unit has the function of holding the weight values ​​to be set in the sum-of-accumulate circuit unit. The sum-of-products circuit unit has the function of performing a sum-of-products operation on the weight value set by the analog current signal and the input value based on the signal obtained by the light-receiving element, and outputting an output current corresponding to the sum-of-products operation. The peripheral arithmetic circuit unit has the function of performing calculations using the output current and outputting an output signal corresponding to the calculation. The weight switching unit has the function of controlling the memory circuit unit in accordance with the output signal and updating the weight values ​​set in the sum-of-accumulate circuit unit. electronic equipment. 　 In claim 1, The light-emitting element is provided on the display unit of the display device, The light-receiving element is provided in the area outside the display unit. electronic equipment. 　 In claim 1, The first layer is further provided with a drive circuit section. The weight switching unit has the function of outputting a signal to control the drive circuit unit in accordance with the signal output from the peripheral calculation circuit unit. electronic equipment. 　 In claim 1, The first layer has a first transistor having a semiconductor layer with silicon in the channel formation region, The second layer has a second transistor having a semiconductor layer with a metal oxide in the channel formation region. electronic equipment. 　 In claim 4, The metal oxide is an oxide containing at least one of indium, element M, or zinc, where element M is Al, Ga, Y, or Sn, in an electronic device. 　 In claim 1, The aforementioned light-receiving element is an organic photodiode, The aforementioned light-emitting element is an organic electroluminescent element, which is an electronic device. 　 In claim 1, The housing is an electronic device including a mounting portion and an optical component.

Images