Display device

Abstract

The present invention provides a display device having a high aperture ratio and high performance. Provided is a display device comprising a silicon substrate, a first pixel electrode, a second pixel electrode, a third pixel electrode, and a fourth pixel electrode. The silicon substrate has a photoelectric conversion region included in a photodiode. The first to fourth pixel electrodes are provided on the silicon substrate. The second pixel electrode is adjacent to the first pixel electrode in a first direction. The third pixel electrode is adjacent to the first pixel electrode in a second direction. The fourth pixel electrode is adjacent to the second pixel electrode in the second direction, and adjacent to the third pixel electrode in the first direction. The second direction is perpendicular or substantially perpendicular to the first direction in plan view. A least a part of the photoelectric conversion region is provided in a region surrounded by the first to fourth pixel electrodes in plan view.

Description

Display device

[0001] One aspect of the present invention relates to a display device. One aspect of the present invention relates to an electronic device having a display device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. Examples of the technical field of one aspect of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, storage devices, lighting devices, input devices, input / output devices, their driving methods, or their manufacturing methods.

[0003] In recent years, display devices have been applied to various uses. Examples of the uses of large display devices include, for example, home television sets, digital signage (electronic billboards), and PIDs (public information displays). Examples of the uses of small display devices include, for example, portable information terminals such as smartphones and tablet terminals, and wearable devices such as devices for VR (virtual reality) and AR (augmented reality). In addition, by赋予 the display device functions other than display, the high functionality and high added value of the display device are being achieved. For example, by赋予 the display device a touch sensor, a display device having a function as a touch panel has been developed.

[0004] In addition, display devices having light-emitting devices (also referred to as light-emitting elements) have been developed. For example, a light-emitting device (also referred to as an EL device or an EL element) that uses the electroluminescence (EL) phenomenon has characteristics such as being easily thinned and lightened, being able to respond quickly to an input signal, and being able to be driven using a DC constant voltage power supply. Patent Document 1 discloses an example of a display device using an organic EL element.

[0005] In addition, the use of In ２ O ３ in thin film transistors has been reported (Non-Patent Document 1).

[0006] Japanese Patent Application Laid-Open No. 2002-324673

[0007] Dhananjay and C. W. Chu, “Realization of In2O3 thin film transistors through reactive evaporation process,” Appl. Phys. Lett. 91, 132111 (2007). Takashi Koida, “High-mobility transparent conductive film,” National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Presentation Meeting 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0008] One aspect of the present invention aims to provide a display device with a high aperture ratio. One aspect of the present invention aims to provide a highly functional display device. One aspect of the present invention aims to provide a low-power consumption display device. One aspect of the present invention aims to provide a display device capable of displaying high-brightness images. One aspect of the present invention aims to provide a display device capable of high-sensitivity imaging. One aspect of the present invention aims to provide a highly reliable display device. One aspect of the present invention aims to provide a novel display device.

[0009] Furthermore, the description of these problems does not preclude the existence of other problems. One aspect of the present invention does not necessarily have to solve all of these problems. It is possible to extract other problems from the description in the specification, drawings, and claims.

[0010] One aspect of the present invention is a display device comprising a silicon substrate, a first pixel electrode, a second pixel electrode, a third pixel electrode, and a fourth pixel electrode, wherein the silicon substrate has a photoelectric conversion region, the first to fourth pixel electrodes are provided on the silicon substrate, the second pixel electrode is adjacent to the first pixel electrode in a first direction, the third pixel electrode is adjacent to the first pixel electrode in a second direction, the fourth pixel electrode is adjacent to the second pixel electrode in a second direction and also adjacent to the third pixel electrode in a first direction, the second direction is perpendicular or substantially perpendicular to the first direction in a plan view, and at least a part of the photoelectric conversion region is provided in a region surrounded by the first to fourth pixel electrodes in a plan view.

[0011] Alternatively, in the above embodiment, the photoelectric conversion region may have, in a plan view, a region located between the first pixel electrode and the second pixel electrode, and a region located between the third pixel electrode and the fourth pixel electrode.

[0012] Alternatively, in the above embodiment, the photoelectric conversion region may have a region located between the second pixel electrode and the fourth pixel electrode in a plan view.

[0013] Alternatively, in the above embodiment, the image pixel has an imaging pixel, a display pixel, a first transistor, and a second transistor, the imaging pixel has a photoelectric conversion region and a third transistor, the display pixel has a first pixel electrode, a fourth transistor, and a fifth transistor, the first transistor and the second transistor have channel formation regions in the silicon substrate, the third transistor is provided above the first transistor and is electrically connected to the first transistor, the fourth transistor is provided above the third transistor and is electrically connected to the second transistor, the fifth transistor is provided on the same surface to be formed as the fourth transistor, and the source electrode or drain electrode of the fifth transistor may be electrically connected to the first pixel electrode.

[0014] Alternatively, in the above embodiment, the photoelectric conversion region may have a region that does not overlap with any of the first to fourth pixel electrodes or the first to fifth transistors.

[0015] Alternatively, in the above embodiment, the third to fifth transistors may have a metal oxide in the channel formation region.

[0016] Alternatively, one aspect of the present invention includes a silicon substrate, a first photodiode, a second photodiode, a first transistor, a second transistor, a first pixel electrode, a second pixel electrode, a third pixel electrode, a fourth pixel electrode, a fifth pixel electrode, a sixth pixel electrode, a seventh pixel electrode, and an eighth pixel electrode, wherein the first photodiode has a first low-resistance region, the second photodiode has a second low-resistance region, the first transistor has a first low-resistance region and a third low-resistance region, and the second transistor has a second The transistor has a first low-resistance region and a third low-resistance region, the first low-resistance region functions as the photoelectric conversion region of the first photodiode and as one of the source region and drain region of the first transistor, the second low-resistance region functions as the photoelectric conversion region of the second photodiode and as one of the source region and drain region of the second transistor, and the third low-resistance region functions as the other of the source region and drain region of the first transistor and as the other of the source region and drain region of the second transistor, and the first to third The eight pixel electrodes are provided on a silicon substrate, the second pixel electrode is adjacent to the first pixel electrode in a first direction, the third pixel electrode is adjacent to the first pixel electrode in a second direction, the fourth pixel electrode is adjacent to the second pixel electrode in a second direction and also adjacent to the third pixel electrode in a first direction, the fifth pixel electrode is adjacent to the third pixel electrode in a second direction, the sixth pixel electrode is adjacent to the fourth pixel electrode in a second direction and also adjacent to the fifth pixel electrode in a first direction, the seventh pixel electrode is adjacent to the fifth pixel electrode in a second direction, and the eighth pixel electrode is adjacent to the sixth pixel electrode The display device is provided such that the first transistor and the second transistor are adjacent to the third to sixth pixel electrodes in a plan view, and the seventh pixel electrode is adjacent to the seventh pixel electrode in a second direction and to the seventh pixel electrode in a first direction, and the first low-resistance region has, in a plan view, a region located between the first and second pixel electrodes and a region located between the third and fourth pixel electrodes, and the second low-resistance region has, in a plan view, a region located between the fifth and sixth pixel electrodes and a region located between the seventh and eighth pixel electrodes.

[0017] Alternatively, in the above embodiment, the image sensor may have a first image sensor and a second image sensor, the first image sensor having a first photodiode, a first transistor, and a third transistor, and the second image sensor having a second photodiode, a second transistor, and a third transistor, the third transistor having a region located between the third pixel electrode and the fifth pixel electrode in a plan view.

[0018] Alternatively, in the above embodiment, the first low-resistance region may have a region located between the second pixel electrode and the fourth pixel electrode in a plan view, and the second low-resistance region may have a region located between the sixth pixel electrode and the eighth pixel electrode in a plan view.

[0019] According to one aspect of the present invention, a display device with a high aperture ratio can be provided. According to one aspect of the present invention, a highly functional display device can be provided. According to one aspect of the present invention, a low-power consumption display device can be provided. According to one aspect of the present invention, a display device capable of displaying high-brightness images can be provided. According to one aspect of the present invention, a display device capable of high-sensitivity imaging can be provided. According to one aspect of the present invention, a highly reliable display device can be provided. According to one aspect of the present invention, a novel display device can be provided.

[0020] Furthermore, the description of these effects does not preclude the existence of other effects. One aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description, drawings, and claims.

[0021] Figure 1 is a plan view showing an example of the configuration of a display device. Figures 2A and 2B are circuit diagrams showing an example of the pixel configuration. Figure 3 is a perspective view showing an example of the configuration of a display device. Figure 4 is a plan view showing an example of the configuration of a display device. Figure 5 is a plan view showing an example of the configuration of a display device. Figure 6 is a plan view showing an example of the configuration of a display device. Figure 7 is a plan view showing an example of the configuration of a display device. Figure 8 is a plan view showing an example of the configuration of a display device. Figure 9 is a plan view showing an example of the configuration of a display device. Figure 10 is a cross-sectional view showing an example of the configuration of a display device. Figure 11 is a cross-sectional view showing an example of the configuration of a display device. Figure 12A is a cross-sectional view showing an example of the configuration of a display device. Figure 12B is a cross-sectional view showing an example of the configuration of a memory cell. Figure 13 is a cross-sectional view showing an example of the configuration of a display device. Figure 14 is a cross-sectional view showing an example of the configuration of a display device. Figure 15 is a cross-sectional view showing an example of the configuration of a display device. Figure 16 is a cross-sectional view showing an example of the configuration of a display device. Figure 17 is a cross-sectional view showing an example of the configuration of a display device. Figure 18 is a cross-sectional view showing an example of the configuration of a display device. Figure 19 is a cross-sectional view showing an example of the configuration of a display device. Figure 20 is a cross-sectional view showing an example of the configuration of a display device. Figure 21 is a cross-sectional view showing an example of the configuration of a display device. Figure 22 is a plan view showing an example of the configuration of a display device. Figure 23A is a circuit diagram showing an example of the configuration of a pixel. Figure 23B is a cross-sectional view showing an example of the configuration of a display device. Figure 24 is a plan view showing an example of the configuration of a display device. Figure 25 is a plan view showing an example of the configuration of a display device. Figure 26 is a plan view showing an example of the configuration of a display device. Figure 27 is a plan view showing an example of the configuration of a display device. Figure 28 is a plan view showing an example of the configuration of a display device. Figures 29A, 29B, 29C, and 29D are cross-sectional views showing an example of the configuration of a display device. Figures 30A, 30B, 30C, and 30D are cross-sectional views showing an example of the configuration of a display device. Figure 31A is a plan view showing an example of the configuration of a transistor. Figures 31B and 31C are cross-sectional views showing an example of the configuration of a transistor. Figure 32A is a plan view showing an example of the configuration of a transistor. Figure 32B is a cross-sectional view showing an example of the configuration of a transistor. Figures 33A and 33B are diagrams illustrating the carrier concentration dependence of Hall mobility. Figure 33C is a cross-sectional view illustrating an indium oxide film.Figures 34A, 34B, 34C, and 34D show examples of the configuration of electronic equipment. Figures 35A, 35B, 35C, 35D, 35E, and 35F show examples of the configuration of electronic equipment. Figures 36A, 36B, 36C, 36D, 36E, 36F, and 36G show examples of the configuration of electronic equipment.

[0022] Embodiments will be described in detail with reference to the drawings. However, it will be readily apparent to those skilled in the art that the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the present invention. Accordingly, the present invention shall not be construed as being limited to the descriptions of the embodiments shown below.

[0023] In the invention described below, the same reference numerals are used in common across different drawings for identical parts or parts having similar functions, and repeated explanations are omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used, and reference numerals may not be assigned.

[0024] Furthermore, the position, size, and scope of each component shown in the drawings may not represent the actual position, size, and scope for the sake of ease of understanding. Therefore, the disclosed invention is not necessarily limited to the position, size, and scope disclosed in the drawings.

[0025] In this specification, ordinal numbers such as "first," "second," etc., are used to avoid confusion of constituent elements and do not indicate any order or rank, such as process order, layering order, or arrangement order. Furthermore, even if a term in this specification does not have an ordinal number, an ordinal number may be added in the claims to avoid confusion of constituent elements. Also, even if a term in this specification has an ordinal number, a different ordinal number may be added in the claims. Furthermore, even if a term in this specification has an ordinal number, the ordinal number may be omitted in the claims.

[0026] Furthermore, a transistor is a type of semiconductor device that can perform functions such as amplifying current or voltage, and switching operations that control conduction or non-conductivity. Transistors in this specification include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs).

[0027] In this specification, transistors using an oxide semiconductor or metal oxide in the semiconductor layer, and transistors having an oxide semiconductor or metal oxide in the channel formation region, are sometimes referred to as OS (Oxide Semiconductor) transistors. Furthermore, transistors having silicon in the channel formation region are sometimes referred to as Si transistors.

[0028] Furthermore, the functions of "source" and "drain" may be reversed when transistors with different polarities are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" may be used interchangeably.

[0029] In this specification, an oxidized nitride is a material containing oxygen and nitrogen, and the nitrogen and oxygen content in its composition is not limited. In other words, oxidized nitrides include materials in which the oxygen content is greater than the nitrogen content, and materials in which the nitrogen content is greater than the oxygen content.

[0030] In this specification, the terms "film" and "layer" can be interchanged as needed or depending on the context. For example, the term "conductive layer" can be changed to the term "conductive film." Alternatively, the term "insulating film" can be changed to the term "insulating layer."

[0031] Furthermore, in this specification, "parallel" means a state in which two lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Furthermore, "approximately parallel" means a state in which two lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" means a state in which two lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Furthermore, "approximately perpendicular" means a state in which two lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0032] In this specification, "connection" includes, for example, "electrical connection." The term "electrical connection" is sometimes used to define the connection relationship of circuit elements as a physical object. Furthermore, "electrical connection" includes both "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the use of circuit elements (e.g., transistors, switches, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected through one or more circuit elements. A, B, and C (described later) refer to objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0033] For example, assuming a circuit including A and B is in operation, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected" as physical objects. Furthermore, even if there is a timing during the circuit's operation when no electrical signals are exchanged or potential interactions occur between A and B, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected."

[0034] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where "A and B are not indirectly connected" is when an insulator is interposed in the path from A to B. Specifically, this includes cases where a capacitive element is connected between A and B, or where the gate insulating layer of a transistor is interposed between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of a transistor are indirectly connected."

[0035] Another example of a situation where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via source and drain in the path from A to B, and a constant potential V is supplied from a power supply, GND, etc., to the nodes between the transistors.

[0036] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferable that there is a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. The side surface of the structure, the substrate surface, and the surface to be formed do not necessarily have to be perfectly flat, and may be substantially planar with a small curvature, or substantially planar with fine irregularities.

[0037] In this specification, "heights match" refers to a configuration in which the heights from a reference surface (for example, a flat surface such as the substrate surface) are equal in a cross-sectional view. For example, if there are two layers with different heights (here referred to as layer A and layer B) with respect to the reference surface, the heights match if the difference between the height of the top surface of layer A and the height of the top surface of layer B is 10 nm or less.

[0038] In this specification, "side edges coincide" means that, in a plan view, at least a portion of the contours of the stacked layers overlap. For example, in the case of two stacked layers (here referred to as layer A and layer B), if the shortest distance from the side edge of layer A to the side edge of layer B in a plan view is 10 nm or less, then the side edges also coincide.

[0039] In general, it can be difficult to clearly distinguish between "exact match" and "approximate match." Therefore, in this specification, "match" may include both exact matches and approximate matches.

[0040] In drawings and other illustrations relating to this specification, arrows indicating the X, Y, and Z directions may be included. In this specification, the "X direction" refers to the direction along the X-axis, and unless explicitly stated, the forward and reverse directions may not be distinguished. The same applies to the "Y direction" and "Z direction." Furthermore, the X, Y, and Z directions are directions that intersect each other. For example, the X, Y, and Z directions are directions that are perpendicular or nearly perpendicular to each other.

[0041] In this specification, the cubic crystal structure is sometimes referred to as cubic crystal, cubic structure, etc. The same applies to other crystal systems (hexagonal, trigonal, tetragonal, orthorhombic, monoclinic, and triclinic).

[0042] In this specification, the high power supply potential VDD (hereinafter also simply referred to as "high potential" or "VDD") refers to a power supply potential that is higher than the low power supply potential VSS (hereinafter also simply referred to as "low potential" or "VSS"). The low power supply potential VSS refers to a power supply potential that is lower than the high power supply potential VDD.

[0043] In this specification and the like, the space group is represented using the Short notation of the international notation (or Hermann-Mauguin symbol). Also, the crystal plane and crystal orientation are represented using Miller indices. In crystallography, the notations of the space group, crystal plane, and crystal orientation are represented by numbers with a bar on top, but in this specification and the like, due to formatting constraints, instead of putting a bar on top of the numbers, a - (minus sign) may be attached before the numbers for expression. Also, the individual orientation indicating the orientation within the crystal is represented by [ ], the set orientation indicating all equivalent orientations is represented by < >, the individual plane indicating the crystal plane is represented by ( ), and the set plane having equivalent symmetry is represented by {}, respectively.

[0044] In this specification and the like, the content ratio of a certain metal element in a metal oxide refers to the ratio of the number of atoms of that element to the total number of atoms of the metal element contained in the metal oxide. For example, if the metal oxide contains metal element X, metal element Y, and metal element Z, and the number of atoms of metal element X, metal element Y, and metal element Z contained in the metal oxide are A Ｘ , A Ｙ , A Ｚ , when taking them as such, the content ratio of metal element X can be represented by A Ｘ / (A Ｘ + A Ｙ + A Ｚ ). Also, when the ratio of the number of atoms (atom ratio) of metal element X, metal element Y, and metal element Z in the metal oxide is B Ｘ : B Ｙ : B Ｚ , the content ratio of metal element X can be represented by B Ｘ / (B Ｘ + B Ｙ + B Ｚ ).

[0045] (Embodiment 1) In this embodiment, a display device according to one aspect of the present invention will be described. One aspect of the present invention relates to a display device having a photodiode. The photodiode is provided in a substrate, for example, provided in a silicon substrate. The display device has, for example, a light-emitting element.

[0046] <Example of Display Device Configuration 1> Figure 1 is a plan view showing an example of the configuration of a display device 10. Pixels 21 are arranged in a matrix in the display device 10. Figure 1 shows a 3x2 arrangement of pixels 21. Here, the 3x2 arrangement of pixels 21 are denoted as pixel 21[1,1], pixel 21[1,2], pixel 21[2,1], pixel 21[2,2], pixel 21[3,1], and pixel 21[3,2], respectively.

[0047] In this specification and drawings, when the same reference numeral is used for multiple elements, and especially when it is necessary to distinguish them, the reference numeral may be accompanied by an identifying numeral such as "_1", "[1]", or "[1,1]". Furthermore, when describing a common matter for multiple elements that have been given an identifying numeral, or when it is not necessary to distinguish them, the identifying numeral may be omitted.

[0048] Each pixel 21 has subpixels. Figure 1 shows an example in which pixel 21 has subpixels 22R, 22G, and 22B.

[0049] Sub-pixels 22R, 22G, and 22B can emit light of different colors from each other. For example, sub-pixel 22R can emit red light, sub-pixel 22G can emit green light, and sub-pixel 22B can emit blue light. As a result, the display device 10 can display, for example, a full-color image. Thus, the display device can display an image using pixels 21. In this specification, pixels 21 are also referred to as display pixels.

[0050] In the following, when explaining matters common to sub-pixels 22R, 22G, and 22B, they may simply be referred to as sub-pixel 22.

[0051] Sub-pixels 22R, 22G, and 22B are each provided with a display element, for example, a light-emitting element. The display element has a pixel electrode. In Figure 1, the pixel electrode provided in sub-pixel 22R is shown as pixel electrode 23R. The pixel electrode provided in sub-pixel 22G is shown as pixel electrode 23G. Furthermore, the pixel electrode provided in sub-pixel 22B is shown as pixel electrode 23B.

[0052] Furthermore, the pixel electrodes 23R, 23G, and 23B provided in pixel 21[1,1] are denoted as pixel electrode 23R[1,1], pixel electrode 23G[1,1], and pixel electrode 23B[1,1], respectively. Similarly, the pixel electrodes 23R, 23G, and 23B provided in pixel 21[1,2] are denoted as pixel electrode 23R[1,2], pixel electrode 23G[1,2], and pixel electrode 23B[1,2], respectively. The same notation method is used for the pixel electrodes provided in pixels 21[2,1] to 21[3,2].

[0053] In the following, when describing matters common to pixel electrode 23R, pixel electrode 23G, and pixel electrode 23B, they may simply be referred to as pixel electrode 23.

[0054] In the example shown in Figure 1, pixel electrode 23G[1,1] is adjacent to pixel electrode 23R[1,1] in the X direction, pixel electrode 23B[1,1] is adjacent to pixel electrode 23G[1,1] in the X direction, pixel electrode 23R[1,2] is adjacent to pixel electrode 23B[1,1] in the X direction, pixel electrode 23G[1,2] is adjacent to pixel electrode 23R[1,2] in the X direction, and pixel electrode 23B[1,2] is adjacent to pixel electrode 23G[1,2] in the X direction. The same applies to pixel electrodes 23R[2,1] to 23R[3,2], pixel electrodes 23G[2,1] to 23G[3,2], and pixel electrodes 23B[2,1] to 23B[3,2]. Furthermore, pixel electrode 23R[2,1] is adjacent to pixel electrode 23R[1,1] in the Y direction, pixel electrode 23R[3,1] is adjacent to pixel electrode 23R[2,1] in the Y direction, pixel electrode 23G[2,1] is adjacent to pixel electrode 23G[1,1] in the Y direction, pixel electrode 23G[3,1] is adjacent to pixel electrode 23G[2,1] in the Y direction, pixel electrode 23B[2,1] is adjacent to pixel electrode 23B[1,1] in the Y direction, and pixel electrode 23B[3,1] is adjacent to pixel electrode 23B[2,1] in the Y direction. The same applies to pixel electrodes 23R[1,2] to 23R[3,2], pixel electrodes 23G[1,2] to 23G[3,2], and pixel electrodes 23B[1,2] to 23B[3,2].

[0055] In this specification and other documents, the X direction may be referred to as the row direction, and the Y direction may be referred to as the column direction.

[0056] The display device 10 is equipped with a photodiode PD. The photodiode PD is provided so that at least a portion of it does not overlap with the pixel electrodes 23. Figure 1 shows an example in which the photodiode PD is provided in a region surrounded by four pixel electrodes 23. In the display device 10 shown in Figure 1, the number of photodiode PDs can be the same as the number of pixel electrodes 23, for example.

[0057] In Figure 1, the photodiode PD located in the region surrounded by pixel electrodes 23B[1,1], 23R[1,2], 23B[2,1], and 23R[2,2] is denoted as photodiode PDr. The region surrounded by pixel electrodes 23B[1,1], 23R[1,2], 23B[2,1], and 23R[2,2] is referred to as region R1. The same notation will be used in subsequent plan views showing examples of the configuration of the display device 10.

[0058] Figure 2A is a circuit diagram showing an example configuration of a pixel 25 having a photodiode PD. In addition to the photodiode PD, the pixel 25 also has a pixel circuit 26. The pixel circuit 26 includes transistors Tr21, Tr22, Tr23, Tr24, and a capacitive element C1.

[0059] One electrode of the photodiode PD (the cathode in the example shown in Figure 2A) is connected to one of the source and drain of transistor Tr21. The other source and drain of transistor Tr21 is connected to one of the source and drain of transistor Tr22. One of the source and drain of transistor Tr22 is connected to the gate of transistor Tr23. The gate of transistor Tr23 is connected to one electrode of the capacitive element C1. One of the source and drain of transistor Tr23 is connected to one of the source and drain of transistor Tr24.

[0060] Node FD is defined as the node to which the source and drain of transistor Tr21, the source and drain of transistor Tr22, the gate of transistor Tr23, and the capacitive element C1 are connected. Node FD can function as a charge detection unit.

[0061] The other electrode of the photodiode PD (the anode in the example shown in Figure 2A) is connected to the wiring CT. The gate of transistor Tr21 is connected to the wiring TX. The gate of transistor Tr22 is connected to the wiring RS. The source and the other drain of transistor Tr22 are connected to the wiring VR. The source and the other drain of transistor Tr23 are connected to the wiring VDE. The gate of transistor Tr24 is connected to the wiring SE. The source and the other drain of transistor Tr24 are connected to the wiring OL.

[0062] Wiring TX functions as a signal line that controls the conduction of transistor Tr21. Wiring RS functions as a signal line that controls the conduction of transistor Tr22. Wiring SE functions as a signal line that controls the conduction of transistor Tr24. Wiring OL functions as an output line.

[0063] Wiring CT, wiring VR, and wiring VDE function as power lines. In the example shown in Figure 2A, the cathode side of the photodiode PD is connected to the transistor Tr21, and the node FD is reset to a high potential for operation. Therefore, wiring VR is set to a high potential and wiring CT to a low potential. Also, wiring VDE can be supplied with a high potential, for example.

[0064] Transistor Tr21 has the function of writing the signal potential acquired by the photodiode PD to node FD. Transistor Tr22 has the function of resetting the potential of node FD. Transistor Tr23 functions as an element of a source follower circuit and can output the potential of node FD as imaging data to wiring OL. Transistor Tr24 has the function of selecting the pixel 25 to which the imaging data is output.

[0065] As described above, by connecting the pixel circuit 26 to one electrode of the photodiode PD, the photodiode PD can be made to function as a light sensor. In one embodiment of the present invention, imaging can be performed using a pixel 25 having a photodiode PD and a pixel circuit 26. Because the display device of one embodiment of the present invention has the function of imaging, for example, it can detect the eyes of a user viewing the display device of one embodiment of the present invention and perform eye tracking. It can also detect objects such as fingers that are in contact with or close to the display device of one embodiment of the present invention. This allows the display device of one embodiment of the present invention to function as a touch panel. Furthermore, it can detect fingerprints of fingers that are in contact with the display device of one embodiment of the present invention, and the display device of one embodiment of the present invention can function as a fingerprint sensor. As a result, the display device of one embodiment of the present invention can be a highly functional display device. In this specification, the pixel 25 is also referred to as an imaging pixel.

[0066] In one embodiment of the present invention, the resolution of the pixels 25 in the display device is preferably 400 ppi or more, more preferably 500 ppi or more, and even more preferably 600 ppi or more. This allows the above-mentioned detection to be performed with high accuracy. In particular, fingerprint authentication can be performed with high accuracy.

[0067] Figure 2B is a circuit diagram showing an example configuration of a sub-pixel 22. The sub-pixel 22 shown in Figure 2B includes a light-emitting element EL and a pixel circuit 27. The pixel circuit 27 includes a transistor Tr31, a transistor Tr32, and a capacitive element C2.

[0068] One of the sources and drains of transistor Tr31 is connected to the gate of transistor Tr32. The gate of transistor Tr32 is connected to one electrode of the capacitive element C2. One of the sources and drains of transistor Tr32 is connected to the other electrode of the capacitive element C2. The other electrode of the capacitive element C2 is connected to one electrode of the light-emitting element EL (the anode in the example shown in Figure 2B). Here, one electrode of the light-emitting element EL corresponds to the pixel electrode 23 shown in Figure 1.

[0069] The gate of transistor Tr31 is connected to wiring GL. The source and the other drain of transistor Tr31 are connected to wiring SL. The source and the other drain of transistor Tr32 are connected to wiring VL1. The other electrode of the light-emitting element EL (the cathode in the example shown in Figure 2B) is connected to wiring VL2.

[0070] Wiring GL functions as a gate wire. The potential of wiring GL controls the conduction of transistor Tr31. Wiring SL functions as a source wire. By making transistor Tr31 conduct, image data corresponding to the potential of wiring SL is written to the pixel circuit 27.

[0071] Wires VL1 and VL2 function as power lines. In the example shown in Figure 2B, the anode side of the light-emitting element EL is connected to the transistor Tr32. Therefore, wire VL1 is set to a high potential and wire VL2 to a low potential.

[0072] When image data is written to the pixel circuit 27, the potential of the gate of the transistor Tr32 becomes the potential corresponding to the image data. As a result, a current of a magnitude corresponding to the image data flows to the light-emitting element EL. Therefore, the light-emitting element EL emits light with a brightness corresponding to the image data. Thus, a display device according to one aspect of the present invention can display an image.

[0073] Figure 3 is a perspective view showing an example configuration of the display device 10. The display device 10 has a layer 20, a layer 40 on the layer 20, a layer 50 on the layer 40, and a layer 60 on the layer 50.

[0074] A photodiode PD is provided in layer 20. The photodiode PD is a pn junction type photodiode having a photoelectric conversion region 13. Alternatively, the photodiode PD may be a pin junction type photodiode.

[0075] The photoelectric conversion region 13 is provided in the substrate 11. The substrate 11 can be a silicon substrate (also called a silicon substrate), for example, a single-crystal silicon substrate (also called a single-crystal silicon substrate). Here, when the substrate 11 is a silicon substrate, the photodiode PD is also called a Si photodiode.

[0076] For example, as shown in Figure 2A, when the cathode of the photodiode PD is connected to the pixel circuit 26, the substrate 11 has a p-type semiconductor region (not shown). A photoelectric conversion region 13, which is an n-type semiconductor region, is provided on a part of the surface side (upper side in the drawing) of the p-type semiconductor region of the substrate 11. Here, the photoelectric conversion region 13 can be a region with lower electrical resistivity than the p-type semiconductor region described above. In this case, the photoelectric conversion region 13 can be called a low-resistance region.

[0077] The following description will explain an example where the photoelectric conversion region 13 is an n-type region. However, by appropriately swapping p-type and n-type regions, swapping anodes and cathodes, and swapping high and low potentials, the following explanation can also be applied when the photoelectric conversion region 13 is a p-type region. For example, when the photoelectric conversion region 13 is a p-type region, the substrate 11 has an n-type semiconductor region. The anode of the photodiode PD is connected to the pixel circuit 26 shown in Figure 2A. Furthermore, a low potential is supplied to the wiring VR and a high potential is supplied to the wiring CT.

[0078] Furthermore, a transistor Tr10 is provided in layer 20. When the substrate 11 is a silicon substrate, the transistor Tr10 is a transistor (also called a Si transistor) having silicon in the channel formation region 31a. The substrate 11 is provided with a low-resistance region 33a that functions as one of the source region and drain region of the transistor Tr10, and a low-resistance region 33b that functions as the other of the source region and drain region of the transistor Tr10.

[0079] Transistor Tr10 is a transistor in the drive circuit. The drive circuit is, for example, a circuit for supplying a signal to at least one of the wirings TX, RS, and SE shown in Figure 2A. The drive circuit is also, for example, a readout circuit for reading out the imaging data output to wiring OL. The drive circuit is also, for example, a gate driver circuit for supplying a signal to wiring GL shown in Figure 2B. Furthermore, the drive circuit is, for example, a source driver circuit for supplying image data to wiring SL shown in Figure 2B.

[0080] Furthermore, at least one of the transistors in the pixel circuit 26 shown in Figure 2A may be provided in layer 20. Also, at least one of the transistors in the pixel circuit 27 shown in Figure 2B may be provided in layer 20. In the following, even if the transistor provided in layer 20 is not transistor Tr10, one of its source region and drain region will be a low-resistance region 33a. The other of its source region and drain region will be a low-resistance region 33b.

[0081] A transistor Tr20 is provided in layer 40. Transistor Tr20 can be a transistor in the pixel circuit 26 shown in Figure 2A. Therefore, transistor Tr20 corresponds to, for example, transistors Tr21 to Tr24. Transistor Tr20 can be, for example, a transistor (also called an OS transistor) having a metal oxide in the channel formation region 31b. At least one of the transistors in the drive circuit may also be provided in layer 40.

[0082] A transistor Tr30 is provided in layer 50. Transistor Tr30 can be a transistor in the pixel circuit 27 shown in Figure 2B. Therefore, transistor Tr30 can correspond to, for example, transistor Tr31, or to transistor Tr32. Transistor Tr30, like transistor Tr20, can be a transistor having a metal oxide in the channel formation region 31b, for example. As shown in Figure 3, the pixel circuits 27 can be arranged in a matrix in layer 50.

[0083] The Si transistors provided in layer 20 can have a higher on-current compared to OS transistors. Therefore, by using Si transistors as the transistors in the drive circuit, the drive circuit can be operated at high speed.

[0084] OS transistors can reduce the off-current compared to Si transistors. Therefore, if an OS transistor is used as the transistor in the pixel circuit 26 shown in Figure 2A, the signal potential acquired by the photodiode PD can be retained for a long period of time. Consequently, it becomes easier to apply a global shutter method in which imaging data is acquired simultaneously at all pixels 25 and read out sequentially. Furthermore, if an OS transistor is used as the transistor in the pixel circuit 27 shown in Figure 2B, the image data written to the pixel circuit 27 can be retained for a long period of time. This reduces the frequency of rewriting image data and lowers the power consumption of the display device 10.

[0085] A light-emitting element EL is provided in layer 60. As described above, the light-emitting element EL has a pixel electrode 23. Therefore, the pixel electrode 23 is provided in layer 60. For example, pixel electrode 23R, pixel electrode 23G, and pixel electrode 23B are provided in layer 60.

[0086] As described above, the photodiode PD is placed in a different layer from the light-emitting element EL. This allows for a higher aperture ratio of the light-emitting element EL compared to the case where the photodiode PD is placed in the same layer 60 as the light-emitting element EL. Therefore, even if the current flowing between the anode and cathode of the light-emitting element EL is small, the display device 10 can display a high-brightness image. Thus, the display device 10 can be a low-power display device.

[0087] In the display device 10, as shown in Figure 1, the photodiode PD is provided such that at least a portion of it does not overlap with the pixel electrode 23. Specifically, at least a portion of the photoelectric conversion region 13 of the photodiode PD is provided so as not to overlap with the pixel electrode 23. The pixel electrode 23 has low transmittance to visible light (wavelength 450 nm to 700 nm). Therefore, if the photoelectric conversion region 13 overlaps with the pixel electrode 23, it becomes difficult for light to enter the photoelectric conversion region 13, and the imaging sensitivity decreases. By providing the photoelectric conversion region 13 so as not to overlap with the pixel electrode 23, a display device that can perform imaging with high sensitivity can be provided.

[0088] In the example shown in Figure 1, no pixel electrodes 23 are provided in the region surrounded by the four pixel electrodes 23 in either the X or Y direction. In other words, in the example shown in Figure 1, neither the straight line extending in the X direction nor the straight line extending in the Y direction that passes through the region surrounded by the four pixel electrodes 23 passes through the pixel electrodes 23. Therefore, by providing the photoelectric conversion region 13 in the region surrounded by the four pixel electrodes 23, the photoelectric conversion region 13 is less likely to overlap with the pixel electrodes 23 compared to the case where the photoelectric conversion region 13 is provided only between two adjacent pixel electrodes 23.

[0089] By using a Si photodiode PD, the photodiode PD can be formed with a smaller footprint than, for example, the light-emitting element EL. Therefore, compared to a case where the display device 10 does not have a photodiode PD, the photodiode PD can be installed without reducing the aperture ratio of the light-emitting element EL and without overlapping with the pixel electrode 23. Note that transistors Tr10, Tr20, Tr30, etc., shown in Figure 3 can be installed so as to overlap with the pixel electrode 23. This increases the integration density of transistors and allows for miniaturization of the display device.

[0090] <Example of Display Device Configuration 2> Below, we will describe an example in which the arrangement of the photodiodes PD differs from that in Figure 1. Note that we will mainly explain the differences from Figure 1, and explanations of similar configurations will be omitted as appropriate.

[0091] Figure 4 shows an example in which a photodiode PD is provided at a position spanning four pixels 21, but no photodiode PD is provided at a position spanning two pixels 21. In the example shown in Figure 4, for example, a photodiode PD is provided in the region surrounded by pixel electrode 23B[1,1], pixel electrode 23R[1,2], pixel electrode 23B[2,1], and pixel electrode 23R[2,2]. On the other hand, for example, no photodiode PD is provided in the region surrounded by pixel electrode 23G[1,1], pixel electrode 23B[1,1], pixel electrode 23G[2,1], and pixel electrode 23B[2,1].

[0092] In the example shown in Figure 4, the display device 10 is provided with the same number of photodiodes PD as pixels 21. In the display devices 10 described later, the same number of photodiodes PD as pixels 21 can also be provided.

[0093] If the resolution of the pixels 25 in the display device 10 can be set to, for example, 400 ppi or more, as described above, the number of photodiodes PD provided in the display device 10 can be reduced from the example shown in Figure 1. The number of photodiodes PD provided in the display device 10 may also be less than the example shown in Figure 4. For example, one photodiode PD may be provided for every 2 rows and 2 columns of pixels 21, or one photodiode PD may be provided for every 3 rows and 3 columns or more of pixels 21.

[0094] Figure 5 shows an example in which sub-pixels 22R, 22G, and 22B are arranged in an S-stripe pattern. In Figure 5, an example is shown in which pixel 21 has a column where sub-pixels 22R and 22G are provided, and a column where sub-pixel 22B is provided.

[0095] In the example shown in Figure 5, a photodiode PD is provided in a region of pixel 21 where none of the pixel electrodes 23R, 23G, or 23B are provided. Figure 5 shows an example where the photodiode PD is provided in the same column as the pixel electrodes 23B. Although Figure 5 shows an example where one photodiode PD overlaps with one pixel 21, it may overlap with two, three, or four pixels 21. In other words, it may be provided across two, three, or four pixels 21.

[0096] Figure 5 shows an example in which a photodiode PD is provided for all pixels 21. However, if the resolution of the pixels 25 in the display device 10 can be set to, for example, 400 ppi or more as described above, then a photodiode PD may be provided for only some of the pixels 21. For example, one photodiode PD may be provided for every 2 rows and 2 columns of pixels 21, or one photodiode PD may be provided for every 3 rows or more and 3 columns or more of pixels 21. In this case, the number of photodiode PDs provided in the display device 10 will be less than the number of pixels 21.

[0097] Figure 6 shows an example where the shape of the photodiode PD in plan view is cross-shaped. In the example shown in Figure 6, the photodiode PD has a region surrounded by four pixel electrodes 23, two regions located between two adjacent pixel electrodes 23 in the X direction, and two regions located between two adjacent pixel electrodes 23 in the Y direction. The photodiode PDr shown in Figure 6 has a region located in region R1, a region located between pixel electrodes 23B[1,1] and 23R[1,2], a region located between pixel electrodes 23B[2,1] and 23R[2,2], a region located between pixel electrodes 23B[1,1] and 23B[2,1], and a region located between pixel electrodes 23R[1,2] and 23R[2,2].

[0098] In the example shown in Figure 6, the occupied area of ​​the photodiode PD can be increased compared to the example shown in Figure 1. Therefore, the display device 10 shown in Figure 6 can be a display device with higher imaging sensitivity than the display device 10 shown in Figure 1. On the other hand, in the example shown in Figure 1, it is easier to prevent multiple photodiodes PD from coming into contact with each other compared to the example shown in Figure 6. Therefore, the display device 10 shown in Figure 1 can be a more reliable display device than the display device 10 shown in Figure 6, and can also be manufactured at a lower cost.

[0099] Figure 7 shows an example where the shape of the photodiode PD in plan view is a combination of two rectangles. In the example shown in Figure 7, the photodiode PD has a region surrounded by four pixel electrodes 23, two regions located between two adjacent pixel electrodes 23 in the X direction, and one region located between two adjacent pixel electrodes 23 in the Y direction. The photodiode PDr shown in Figure 7 has a region located in region R1, a region located between pixel electrodes 23B[1,1] and 23R[1,2], a region located between pixel electrodes 23B[2,1] and 23R[2,2], and a region located between pixel electrodes 23R[1,2] and 23R[2,2]. Note that the photodiode PDr may have a region located between pixel electrodes 23B[1,1] and 23B[2,1] instead of the region located between pixel electrodes 23R[1,2] and 23R[2,2]. In the example shown in Figure 7, as in the example shown in Figure 6, the occupied area of ​​the photodiode PD can be made larger than in the example shown in Figure 1.

[0100] Figure 8 shows an example where the shape of the photodiode PD in plan view is rectangular. Also, Figure 8 shows an example where the number of photodiodes PD in the display device 10 is less than the number of pixel electrodes 23. Furthermore, Figure 8 shows an example where the photodiodes PD are arranged in a zigzag pattern. In the example shown in Figure 8, the photodiode PD has a region surrounded by four pixel electrodes 23, as well as two regions located between two adjacent pixel electrodes 23 in the X direction. The photodiode PDr shown in Figure 8 has a region located in region R1, a region located between pixel electrodes 23B[1,1] and 23R[1,2], and a region located between pixel electrodes 23B[2,1] and 23R[2,2]. Here, no photodiode PD is provided in the region surrounded by pixel electrodes 23B[2,1], 23R[2,2], 23B[3,1], and 23R[3,2].

[0101] By reducing the number of photodiodes PD in the display device 10 to less than the number of pixel electrodes 23, the area occupied by each photodiode PD can be increased. Also, Figure 8 shows an example where the number of rows of photodiodes PD, i.e., the number of photodiodes PD per column, is less than the number of rows of pixel electrodes 23, i.e., the number of pixel electrodes 23 per column. For example, the movement of the pupil in the vertical direction (also called the up and down direction) may be smaller than the movement of the pupil in the horizontal direction (also called the left and right direction). In this case, even if the number of rows of photodiodes PD is reduced, the display device 10 can perform eye-tracking with high accuracy.

[0102] The photodiode PD may have three or more regions located between two adjacent pixel electrodes 23 in the X direction. In addition to the regions described above, the photodiode PDr may have a region located between pixel electrode 23B[3,1] and pixel electrode 23R[3,2]. In this case, the photodiode PDr has a region surrounded by pixel electrode 23B[2,1], pixel electrode 23R[2,2], pixel electrode 23B[3,1], and pixel electrode 23R[3,2].

[0103] Figure 9 shows an example where the shape of the photodiode PD shown in Figure 8 in a plan view is cross-shaped. The photodiode PD shown in Figure 9 has two regions located between two adjacent pixel electrodes 23 in the Y direction. The photodiode PDr shown in Figure 9 has a region located in region R1, a region located between pixel electrodes 23B[1,1] and 23R[1,2], and a region located between pixel electrodes 23B[2,1] and 23R[2,2], as well as a region located between pixel electrodes 23B[1,1] and 23B[2,1], and a region located between pixel electrodes 23R[1,2] and 23R[2,2].

[0104] In the example shown in Figure 9, the occupied area of ​​the photodiode PD can be increased compared to the example shown in Figure 8. Therefore, the display device 10 shown in Figure 9 can be a display device with higher imaging sensitivity than the display device 10 shown in Figure 8. On the other hand, in the example shown in Figure 8, it is easier to prevent multiple photodiodes PD from coming into contact with each other compared to the example shown in Figure 9. Therefore, the display device 10 shown in Figure 8 can be a more reliable display device than the display device 10 shown in Figure 9, and can also be manufactured at a lower cost.

[0105] <Example of Display Device Configuration 3> Below, an example of the cross-sectional configuration of the display device 10 will be described.

[0106] Figure 10 is a cross-sectional view showing an example of the configuration of the display device 10. The display device 10 shown in Figure 10 has a layer 20, a layer 40 on the layer 20, a layer 50 on the layer 40, and a layer 60 on the layer 50, similar to the example shown in Figure 3.

[0107] As explained in Figure 3, a photodiode PD is provided in layer 20. Also in Figure 10, transistors Tr11 and Tr12 are shown as transistors provided in layer 20. Transistor Tr21 is shown as a transistor provided in layer 40. Furthermore, transistors Tr31 and Tr32 are shown as transistors provided in layer 50. Also, as explained in Figure 3, a light-emitting element EL is provided in layer 60.

[0108] The transistors in layer 40 are located above the photodiode PD and transistors in layer 20. Specifically, in the example shown in Figure 10, transistor Tr21 is located above the photodiode PD, above transistor Tr11, and above transistor Tr12. Furthermore, the transistors in layer 50 are located above the transistors in layer 40. Specifically, in the example shown in Figure 10, transistors Tr31 and Tr32 are located above transistor Tr21. In addition, the light-emitting element EL in layer 60 is located above the transistors in layer 50. Specifically, in the example shown in Figure 10, the light-emitting element EL is located above transistor Tr31 and above transistor Tr32.

[0109] Transistors Tr11 and Tr12 are transistors in the aforementioned drive circuit. Specifically, transistor Tr11 is included in the circuit for supplying a signal to the gate electrode of transistor Tr21. Specifically, transistor Tr12 is included in the source driver circuit.

[0110] Transistor Tr11 has a low-resistance region 33a, a low-resistance region 33b, a conductive layer 35, and an insulating layer 37. Similarly, transistor Tr12 also has a low-resistance region 33a, a low-resistance region 33b, a conductive layer 35, and an insulating layer 37.

[0111] The low-resistance regions 33a and 33b are provided in the substrate 11 as described above. The channel formation regions of transistors such as transistor Tr11 and transistor Tr12, which are provided in layer 20, are also provided in the substrate 11. The low-resistance region 33a functions as one of the source region and drain region of the transistor. The low-resistance region 33b functions as the other of the source region and drain region of the transistor.

[0112] The conductive layer 35 functions as the gate electrode of the transistor. The insulating layer 37 is located between the substrate 11 and the conductive layer 35 and functions as the gate insulating layer of the transistor. Here, an insulating layer 39 can be provided so as to be in contact with the side surface of the conductive layer 35.

[0113] An element isolation layer 203 can be provided between the photodiode PD and the transistor, and between two adjacent transistors. The element isolation layer 203 can be formed on the substrate 11 using, for example, the LOCOS (Local Oxidation of Silicon) method, the STI (Shallow Trench Isolation) method, or the mesa isolation method. However, it is not necessary to provide the element isolation layer 203 on the substrate 11.

[0114] An insulating layer 253 is provided on the photodiode PD, transistor Tr11, transistor Tr12, and element isolation layer 203. A conductive layer 256 is embedded in the insulating layer 253. In Figure 10, conductive layer 256 is shown as conductive layer 256_1, conductive layer 256_2, and conductive layer 256_3. Conductive layer 256_1 has a region in contact with the photoelectric conversion region 13. Conductive layer 256_2 has a region in contact with the low-resistance region 33a of transistor Tr11. Conductive layer 256_3 has a region in contact with the low-resistance region 33a of transistor Tr12.

[0115] An insulating layer 252 is provided on the insulating layer 253. A conductive layer 257 is embedded in the insulating layer 252. In Figure 10, conductive layer 257 is shown as conductive layer 257_1, conductive layer 257_2, and conductive layer 257_3. Conductive layer 257_1 has a region in contact with conductive layer 256_1. Conductive layer 257_2 has a region in contact with conductive layer 256_2. Conductive layer 257_3 has a region in contact with conductive layer 256_3.

[0116] A layer 40 is provided on the insulating layer 252 and the conductive layer 257. Layer 40 includes an insulating layer 211, an insulating layer 281 on the insulating layer 211, an insulating layer 212 on the insulating layer 281, an insulating layer 261 on the insulating layer 212, an insulating layer 262 on the insulating layer 261, an insulating layer 282 on the insulating layer 262, an insulating layer 213 on the insulating layer 282, an insulating layer 283 on the insulating layer 213, an insulating layer 214 on the insulating layer 283, an insulating layer 284 on the insulating layer 214, and an insulating layer 254 on the insulating layer 284. A transistor is provided between the insulating layer 281 and the insulating layer 283. In Figure 10, this transistor is shown as transistor Tr21. Here, the multiple transistors in layer 40 can be provided on the same surface to be formed.

[0117] Transistor Tr21 includes a conductive layer 231, an insulating layer 261 on the conductive layer 231, an insulating layer 262 on the insulating layer 261, an insulating layer 263 on the insulating layer 262, a semiconductor layer 251 on the insulating layer 263, a conductive layer 232a, a conductive layer 232b, and an insulating layer 264 on the semiconductor layer 251, and a conductive layer 233 on the insulating layer 264. In addition, a low-resistance region 271a may be formed at the interface between the semiconductor layer 251 and the conductive layer 232a, and in its vicinity. Similarly, a low-resistance region 271b may be formed at the interface between the semiconductor layer 251 and the conductive layer 232b, and in its vicinity. Here, transistors other than transistor Tr21 provided in layer 40 can have the same configuration as transistor Tr21 shown in Figure 10. Also, transistors provided in layer 50 can have the same configuration as transistor Tr21 shown in Figure 10.

[0118] The conductive layer 232a functions as one of the source and drain electrodes of the transistor. The conductive layer 232b functions as the other of the source and drain electrodes of the transistor. The low-resistance region 271a functions as one of the source and drain regions of the transistor. The low-resistance region 271b functions as the other of the source and drain regions of the transistor.

[0119] The conductive layer 233 functions as the first gate electrode of the transistor (also called the top gate electrode or front gate electrode). The insulating layer 264 functions as the first gate insulating layer of the transistor. The conductive layer 231 functions as the second gate electrode of the transistor (also called the bottom gate electrode or back gate electrode). The insulating layers 261, 262, and 263 function as the second gate insulating layers of the transistor.

[0120] The semiconductor layer 251 may, for example, have a metal oxide. In this case, the transistor having the semiconductor layer 251 can be an OS transistor.

[0121] A conductive layer 234 is embedded in insulating layers 211, 281, 212, 261, 262, 282, 213, 283, 214, and 284. In Figure 10, conductive layers 234_1, 234_2, and 234_3 are shown as conductive layers 234 provided in layer 40. Conductive layer 234_1 has a region in contact with conductive layer 257_1. Conductive layer 234_2 has a region in contact with conductive layer 257_2. Conductive layer 234_3 has a region in contact with conductive layer 257_3.

[0122] A conductive layer 235 is embedded in insulating layers 282, 213, 283, 214, and 284. In Figure 10, conductive layer 235_1 is shown as the conductive layer 235 provided in layer 40. Conductive layer 235_1 has a region that is in contact with the conductive layer 232a of transistor Tr21.

[0123] A conductive layer 236 is embedded in insulating layer 283, insulating layer 214, and insulating layer 284. In Figure 10, conductive layer 236_1 is shown as the conductive layer 236 provided in layer 40. Conductive layer 236_1 has a region that is in contact with the conductive layer 233 of transistor Tr21.

[0124] An insulating layer 254 is provided on the insulating layer 284. A conductive layer 267 is embedded in the insulating layer 254. In Figure 10, conductive layers 267_1, conductive layer 267_2, and conductive layer 267_3 are shown as conductive layers 267 provided on layer 40. Conductive layer 267_1 has a region in contact with conductive layer 234_1 and a region in contact with conductive layer 235_1. Conductive layer 267_2 has a region in contact with conductive layer 234_2 and a region in contact with conductive layer 236_1. Conductive layer 267_3 has a region in contact with conductive layer 234_3.

[0125] As described above, the photoelectric conversion region 13 and the conductive layer 232a of transistor Tr21 are connected via conductive layers 256_1, 257_1, 234_1, 267_1, and 235_1. In addition, the low-resistance region 33a of transistor Tr11 and the conductive layer 233 of transistor Tr21 are connected via conductive layers 256_2, 257_2, 234_2, 267_2, and 236_1.

[0126] Layer 50 can have the same configuration as layer 40. As mentioned above, in Figure 10, transistors Tr31 and Tr32 are shown as transistors provided in layer 50. Transistors Tr31 and Tr32 can have the same configuration as transistor Tr21. Here, the multiple transistors in layer 50 can be provided on the same surface to be formed. For example, transistors Tr31 and Tr32 can be provided on the same surface to be formed.

[0127] In Figure 10, conductive layer 234_4 is shown as conductive layer 234 provided in layer 50. Conductive layers 235_2 and conductive layer 235_3 are shown as conductive layers 235 provided in layer 50. Furthermore, conductive layers 267_4 and conductive layer 267_5 are shown as conductive layers 267 provided in layer 50.

[0128] Conductive layer 234_4 has a region in contact with conductive layer 267_3. Conductive layer 235_2 has a region in contact with conductive layer 232b of transistor Tr31. Conductive layer 235_3 has a region in contact with conductive layer 232a of transistor Tr32. Conductive layer 267_4 has a region in contact with conductive layer 234_4 and a region in contact with conductive layer 235_2. Conductive layer 267_5 has a region in contact with conductive layer 235_3.

[0129] As described above, the low-resistance region 33a of transistor Tr12 and the conductive layer 232b of transistor Tr31 are connected via conductive layers 256_3, 257_3, 234_3, 267_3, 234_4, 267_4, and 235_2.

[0130] Layer 60 includes an insulating layer 255 on layer 50, a light-emitting element EL on the insulating layer 255, a protective layer 273 on the light-emitting element EL, an adhesive layer 258 on the protective layer 273, and a substrate 12 on the adhesive layer 258. A conductive layer 237 is embedded in the insulating layer 255. The conductive layer 237 has a region in contact with the conductive layer 267_5.

[0131] The light-emitting element (EL) includes a pixel electrode 23, an EL layer 172 on the pixel electrode 23, a common layer 174 on the EL layer 172, and a common electrode 173 on the common layer 174. The pixel electrode 23 is provided on a conductive layer 237 and an insulating layer 255. The pixel electrode 23 has a region that contacts, for example, the upper surface of the conductive layer 237. As a result, the conductive layer 232a of the transistor Tr32 and the pixel electrode 23 are connected via conductive layers 235_3, 267_5, and 237.

[0132] Figure 10 shows an example in which the EL layer 172 is provided so as to cover the side surface of the pixel electrode 23. The EL layer 172 has at least an emissive layer. By sandwiching the EL layer 172 between the pixel electrode 23 and the common electrode 173, the EL layer 172 can emit light. The light output can be, for example, red, green, or blue light. Alternatively, the light output may be white light. In this case, a colored layer can be provided on the light-emitting element EL.

[0133] The common layer 174 may have a region in contact with the upper surface of the EL layer 172, for example. The common electrode 173 may have a region in contact with the upper surface of the common layer 174, for example. The common layer 174 and the common electrode 173 can be shared among multiple light-emitting elements (ELs), although they are not shown in Figure 10. For the common electrode 173, for example, a material with high transmittance to visible light is used, specifically a material with higher transmittance to visible light than the pixel electrode 23. This prevents the light output from being reflected or absorbed by the common electrode 173 and not emitted outside the display device 10. Therefore, the efficiency of light output can be increased.

[0134] An insulating layer 270 is provided on the EL layer 172. The insulating layer 270 has a region that contacts the upper surface of the EL layer 172 that does not contact the common layer 174. The insulating layer 270 has a region that does not overlap with the pixel electrode 23. The side edges of the insulating layer 270 can coincide with or substantially coincide with the side edges of the EL layer 172. An insulating layer 271 is provided on the insulating layer 270. The insulating layer 271 may have a region that contacts the upper surface of the insulating layer 270, a region that contacts the side surface of the insulating layer 270, a region that contacts the side surface of the EL layer 172, and a region that contacts the upper surface of the insulating layer 255. An insulating layer 278 is provided on the insulating layer 271. The insulating layer 271 may be, for example, an inorganic insulating layer. The insulating layer 278 may be, for example, an organic insulating layer. A common layer 174, a common electrode 173, a protective layer 273, an adhesive layer 258, and a substrate 12 are provided on the insulating layer 278.

[0135] The insulating layers 271 and 278 cover both a portion of the upper surface and the sides of the EL layer 172, thereby preventing the EL layer 172 from peeling off. This improves the reliability of the display device 10 and allows for low-cost manufacturing.

[0136] The insulating layer 271 preferably functions as a barrier insulating layer. By providing the display device 10 with an insulating layer 271 that functions as a barrier insulating layer, the diffusion of components contained in the insulating layer 278 to the EL layer 172 side can be suppressed. This suppresses the diffusion of impurities into the light-emitting layer of the light-emitting element EL. Therefore, the reliability of the display device 10 can be improved. The insulating layer 271 can have a single-layer structure or a multi-layer structure.

[0137] In this specification, a barrier insulating layer refers to an insulating layer that has barrier properties. Furthermore, in this specification, having barrier properties means having the property of making it difficult for the corresponding substance to diffuse (also referred to as the property of making it difficult for the corresponding substance to permeate, the property of having low permeability to the corresponding substance, or the function of suppressing the diffusion of the corresponding substance). Alternatively, it means having the function of capturing or fixing the corresponding substance within the insulating layer (also referred to as gettering). Note that when hydrogen is described as a corresponding substance, it refers to, for example, hydrogen atoms, hydrogen molecules, and water molecules and OH groups. − This refers to at least one substance that is bonded with hydrogen, such as [substance name]. Furthermore, when an impurity is described as a corresponding substance, unless otherwise specified, it refers to an impurity in the channel-forming region or semiconductor layer, such as a hydrogen atom, hydrogen molecule, water molecule, nitrogen atom, nitrogen molecule, nitrogen oxide molecule (N ２ O, NO, NO ２ This refers to at least one of the following: copper atoms, etc. Furthermore, when oxygen is described as a corresponding substance, it refers to at least one of the following: oxygen atoms, oxygen molecules, etc.

[0138] The insulating layer 278 has the function of flattening the large unevenness of the insulating layer 271. In other words, the display device 10 can improve the flatness of the surfaces forming the common layer 174 and the common electrode 173 by having the insulating layer 278.

[0139] The substrate 12 is bonded to the protective layer 273 by an adhesive layer 258. The substrate 12 is made of a material with high transmittance to visible light. This improves the efficiency of light output extraction. The substrate 12 preferably has a visible light transmittance of 70% or more, more preferably 80% or more, and even more preferably 85% or more. For example, it is preferable to use a glass substrate as the substrate 12.

[0140] The photodiode PD provided in layer 20 has the function of detecting light Lin incident from outside the display device 10. As described above, the photodiode PD is provided so that at least a portion of it does not overlap with the pixel electrode 23. Specifically, the photoelectric conversion region 13 of the photodiode PD is provided so that at least a portion of it does not overlap with the pixel electrode 23. In addition, the transistors of the display device are also provided so that they do not overlap with the photoelectric conversion region 13. In the example shown in Figure 10, transistors Tr11, Tr12, Tr21, Tr31, and Tr32 are provided so that they do not overlap with the photoelectric conversion region 13. Furthermore, conductive layers 257 and 267 are also provided so that they do not overlap with the photoelectric conversion region 13. As a result, it is possible to suppress the reflection or absorption of light Lin by the conductive layers, etc., and prevent it from entering the photoelectric conversion region 13. Thus, a decrease in imaging sensitivity can be suppressed. Furthermore, since the common electrode 173 has high transmittance to visible light, it may overlap with the photoelectric conversion region 13.

[0141] <Materials Constituting the Display Device> The materials constituting each layer of the display device 10 will be described below.

[0142] It is preferable to use materials with a low dielectric constant for insulating layers 253, 252, 211, 212, 263, 213, 214, 254, and 255. This reduces parasitic capacitance between wirings. Examples of materials with a low dielectric constant include silicon oxide, silicon oxynitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and silicon oxide with vacancies.

[0143] Preferably, at least one of insulating layers 281, 261, 262, 282, 283, and 284 functions as a barrier insulating layer against hydrogen. Furthermore, preferably at least one of insulating layers 281, 261, 262, 282, 283, and 284 functions as a barrier insulating layer against impurities. Preferably, at least one of insulating layers 281, 261, 262, 282, 283, and 284 functions as a barrier insulating layer against oxygen. Here, the barrier insulating layer against hydrogen has, for example, a function to suppress hydrogen diffusion, or a function to capture or fix hydrogen. Note that insulating layers 281, 261, 262, 282, 283, and 284 do not necessarily need to be provided in their entirety. If sufficient barrier properties are provided against hydrogen, impurities, oxygen, etc., the insulating layers can be appropriately selected from insulating layers 281, 261, 262, 282, 283, and 284. For example, the insulating layer 281 can be omitted, and the insulating layer 212 and the conductive layer 231 can be in contact with the upper surface of the insulating layer 211.

[0144] As an insulating layer having the function of suppressing hydrogen diffusion, it is preferable to use, for example, silicon nitride or silicon nitride oxide. In addition, for example, aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium (hafnium aluminate), oxides containing hafnium and zirconium (hafnium zirconium oxide), gallium oxide, indium gallium zinc oxide, etc. may also be used.

[0145] As an insulating layer having the function of capturing or fixing hydrogen, it is preferable to use metal oxides such as hafnium oxide, aluminum oxide, aluminum and hafnium oxide (hafnium aluminate), or magnesium oxide. The insulating layer having the function of capturing or fixing hydrogen preferably has an amorphous structure. In metal oxides having such an amorphous structure, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. In other words, metal oxides having an amorphous structure can be said to have a high ability to capture or fix hydrogen. By adding silicon to the above metal oxide, polycrystallization can be suppressed and it can be made more amorphous. Therefore, it is preferable to use metal oxides to which silicon has been added (for example, hafnium silicate, aluminum silicate, etc.).

[0146] Furthermore, the insulating layers listed as having the function of suppressing hydrogen diffusion and the insulating layers having the function of capturing or fixing hydrogen also possess barrier properties against oxygen.

[0147] The insulating layer 271 is preferably an inorganic insulating layer having barrier properties against hydrogen, as described above. As the insulating layer 271, for example, one or more of the following can be used: an oxide having one or both of aluminum and hafnium, an oxide having magnesium, an oxide having gallium, a nitride having silicon, and a nitride oxide having silicon. Typically, the barrier layer can preferably be one or more of the following: aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, zinc gallium oxide, silicon nitride, and silicon nitride oxide. For example, a silicon nitride film can preferably be used as the insulating layer 271 that functions as a barrier insulating layer.

[0148] As described above, the insulating layer 278 is preferably an organic insulating layer. It is preferable to use a photosensitive resin as the insulating layer 278. As organic materials, acrylic resins, polyimide resins, epoxy resins, imide resins, polyamide resins, polyimidoamide resins, silicone resins, siloxane resins, benzocyclobutene resins, phenolic resins, and precursors of these resins can be used. Alternatively, organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resins can be used. Furthermore, a photoresist can be used as the photosensitive resin. As the photosensitive resin, a positive-type or negative-type material can be used. In this specification, the term "acrylic resin" does not refer only to polymethacrylate esters or methacrylic resins, but may refer to acrylic polymers in a broad sense.

[0149] The conductive layers 35, 234, 235, 236, 237, 256, 257, and 267 can be made from any of the conductive materials listed below. Preferably, the conductive material is a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, cobalt, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal elements, or an alloy combining the above-mentioned metal elements. Examples of conductive materials include tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicide may be used.

[0150] When the conductive layer is made into a laminated structure, for example, a laminated structure combining the aforementioned metal element material and an oxygen-containing conductive material, a laminated structure combining the aforementioned metal element material and a nitrogen-containing conductive material, or a laminated structure combining the aforementioned metal element material, an oxygen-containing conductive material, and a nitrogen-containing conductive material may be applied.

[0151] As the pixel electrode 23, metals, alloys, electrically conductive compounds, and mixtures thereof can be used as appropriate. Examples of such materials include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, and alloys containing these in appropriate combinations. Other examples of such materials include aluminum alloys such as aluminum, nickel, and lanthanum alloys (Al-Ni-La alloys), as well as silver alloys of silver and magnesium, and silver alloys of silver, palladium, and copper (Ag-Pd-Cu alloys, also written as APC). Other examples of such materials include elements belonging to Group 1 or Group 2 of the periodic table that are not exemplified above (for example, lithium, cesium, calcium, strontium), rare earth metals such as europium and ytterbium, and alloys containing these in appropriate combinations, graphene, and the like.

[0152] Examples of electrically conductive compounds include nitrides of metals or alloys, and oxides of metals or alloys (specifically, for example, oxide conductors described later).

[0153] Examples of electrically conductive compounds include silicides such as nickel silicide.

[0154] The pixel electrode 23 is particularly preferably made of a conductive material with high reflectivity. For example, a metal or alloy can be used as the conductive material with high reflectivity. More specifically, for example, metals such as silver, aluminum, gold, platinum, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, and titanium, or alloys containing these metals, can be used.

[0155] As mentioned above, the common electrode 173 is made of a material with high transmittance to visible light, specifically a material with higher transmittance to visible light than the pixel electrode 23. For the common electrode 173, for example, an oxide conductor can be used. Examples of oxide conductors include indium oxide, zinc oxide, In-Sn oxide, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn-Si oxide (In-Sn oxide containing silicon, also called ITSO), zinc oxide with gallium added, In-Ga-Zn oxide, In-Sn-Zn oxide, and the like.

[0156] The conductivity of the protective layer 273 is not required. At least one of an insulating film, a semiconductor film, and a conductive film can be used as the protective layer 273.

[0157] The protective layer 273 has an inorganic film, which prevents oxidation of the common electrode 173. It also suppresses the intrusion of impurities (such as moisture and oxygen) into the light-emitting element EL, thereby suppressing the deterioration of the light-emitting element EL. This improves the reliability of the display device 10.

[0158] For example, inorganic insulating films such as oxide insulating films, nitride insulating films, oxidoxide-nitride insulating films, and nitride-oxide insulating films can be used for the protective layer 273. Specific examples of these inorganic insulating films are given in the description of the insulating layer 271. In particular, the protective layer 273 preferably has a nitride insulating film or a nitride-oxide insulating film, and more preferably has a nitride insulating film.

[0159] By using, for example, a laminated structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film, or a laminated structure of an aluminum oxide film and an In-Ga-Zn oxide film on the aluminum oxide film as the protective layer 273, it is possible to suppress impurities (water, oxygen, etc.) from entering the EL layer.

[0160] Furthermore, the protective layer 273 may have an organic film. For example, the protective layer 273 may have both an organic film and an inorganic film. Examples of organic materials that can be used for the protective layer 273 include organic insulating materials that can be used for the insulating layer 278.

[0161] Various types of curing adhesives can be used as the adhesive layer 258, including UV-curing adhesives, reaction-curing adhesives, thermosetting adhesives, and anaerobic adhesives. Examples of these adhesives include epoxy resins, acrylic resins, silicone resins, phenolic resins, polyimide resins, imide resins, PVC (polyvinyl chloride) resins, PVB (polyvinyl butyral) resins, and EVA (ethylene vinyl acetate) resins. Materials with low moisture permeability, such as epoxy resins, are particularly preferred. Two-component mixed resins may also be used. Adhesive sheets may also be used.

[0162] <Example of Display Device Configuration 4> Below, we will describe an example of a display device 10 configuration different from that shown in Figure 10. Note that we will mainly explain the differences from Figure 10, and similar configurations will be omitted as appropriate.

[0163] Figure 11 shows an example in which transistor Tr11 is provided in layer 40. In the example shown in Figure 11, transistor Tr11 can have the same configuration as, for example, transistor Tr21. The conductive layer 232a of transistor Tr11 is connected to conductive layer 267_2 via conductive layer 235_4. As described above, at least a portion of the transistors in the above-mentioned drive circuit can be provided in layer 40.

[0164] Figure 12A shows an example in which memory cells MC are provided in layer 40. Figure 12B is an enlarged view of the memory cells MC shown in Figure 12A.

[0165] Figure 12A shows transistor Tr13. Transistor Tr13 is a transistor provided in the drive circuit of the memory cell MC. Specifically, transistor Tr13 can be provided in a sense amplifier circuit for amplifying the data read from the memory cell MC.

[0166] As shown in Figure 12B, the memory cell MC includes a transistor Tr41 and a capacitive element C3. Transistor Tr41 can have the same configuration as, for example, transistor Tr21. Capacitive element C3 includes a conductive layer 267_7 on an insulating layer 284, an insulating layer 285 on the conductive layer 267, and a conductive layer 268 on the insulating layer 285. Figure 12B shows an example where the capacitive element C3 is a MIM (Metal-Insulator-Metal) capacitance with an insulating layer 285 sandwiched between the conductive layer 267_7 and the conductive layer 268.

[0167] In the example shown in Figures 12A and 12B, the low-resistance region 33a of transistor Tr13 and the conductive layer 232b of transistor Tr41 are connected via conductive layers 256_4, 257_4, 234_5, 267_6, and 235_5. Furthermore, conductive layer 267_7 and the conductive layer 232a of transistor Tr41 are connected via conductive layer 235_6. For example, conductive layer 235_6 has a region that contacts the upper surface of conductive layer 232a of transistor Tr41, and conductive layer 267_7 has a region that contacts the upper surface of conductive layer 235_6, thereby connecting the conductive layer 232a of transistor Tr41 and conductive layer 267_7.

[0168] In Figures 12A and 12B, an insulating layer 285 is provided on the conductive layer 267 and on the insulating layer 254, and an insulating layer 286 is provided on the insulating layer 285. The conductive layer 268 is provided so as to embed the insulating layer 286. In addition, the conductive layer 234_4 is provided so as to embed the insulating layer 254 and the insulating layer 286, in addition to the insulating layers 211, 281, 212, 261, 262, 282, 213, 283, 214, and 284.

[0169] Layer 20 can be equipped with arithmetic circuits. Examples of arithmetic circuits include integrated circuits such as CPUs (Central Processing Units), GPUs (Graphics Processor Units), and FPGAs (Field Programmable Gate Arrays). Here, as shown in Figure 12A, etc., if memory cells MC are provided in the display device 10, the transmission distance between the arithmetic circuits and memory cells can be shortened compared to, for example, if the storage device is externally attached to the display device 10. Therefore, the power required for data transmission can be reduced.

[0170] Figure 13 shows an example in which the transistor Tr11 and memory cell MC are provided in layer 40. Figure 13 can be said to show an example of a configuration that combines the configuration shown in Figure 11 and the configuration shown in Figure 12A.

[0171] Figure 14 shows an example in which layer 41 is provided between layer 40 and layer 50, and memory cells MC as shown in Figure 12A are provided on layer 41. In the display device 10 shown in Figure 14, a conductive layer 267_8 is provided on layer 40. In addition, conductive layers 234_6, 234_7, 235_5, 235_6, 267_6, and 267_9 are provided on layer 41.

[0172] Conductive layer 234_6 has a region in contact with conductive layer 267_3. Conductive layer 267_9 has a region in contact with conductive layer 234_6. Conductive layer 234_4 has a region in contact with conductive layer 267_9. Conductive layer 267_8 has a region in contact with conductive layer 234_5. Conductive layer 234_7 has a region in contact with conductive layer 267_8. Conductive layer 267_6 has a region in contact with conductive layer 234_7 and a region in contact with conductive layer 235_5.

[0173] By placing the memory cell MC in layer 41, the capacitance value of the capacitive elements in the memory cell MC can be increased compared to when it is placed in layer 40. This stabilizes the read operation from the memory cell MC. Furthermore, data can be retained in the memory cell MC for a longer period of time.

[0174] Multiple memory cells (MCs) can be provided in layer 41. In this case, multiple transistors can be provided in layer 41. The multiple transistors in layer 41 can be provided on the same surface to be formed.

[0175] The memory cell MC of layer 41 is located above the transistor of layer 40. That is, in the example shown in Figure 14, the memory cell MC is located above transistor Tr21. Also, the transistor of layer 50 is located above the memory cell MC of layer 41. That is, in the example shown in Figure 14, transistors Tr31 and Tr32 are located above the memory cell MC.

[0176] Figure 15 shows an example in which the transistor Tr11 is provided in layer 40 and the memory cell MC is provided in layer 41. Figure 15 can be said to show an example of a configuration that combines the configuration shown in Figure 11 and the configuration shown in Figure 14.

[0177] Figure 16 shows an example where the transistor Tr21 shown in Figure 10 is provided in layer 20. In Figure 16, transistor Tr22 is shown as a transistor provided in layer 40. Also in Figure 16, transistor Tr14 is shown as a transistor provided in layer 20.

[0178] The transistor Tr21 shown in Figure 16 has a photoelectric conversion region 13 as one of its source region and drain region. That is, when the transistor Tr21 is provided in layer 20, the photoelectric conversion region 13 is shared by the photodiode PD and the transistor Tr21. The transistor Tr21 shown in Figure 16 also has a low-resistance region 33 as the other of its source region and drain region.

[0179] The low-resistance region 33 and the conductive layer 232a of transistor Tr22 are connected via conductive layers 256_5, 257_5, 234_8, 267_10, and 235_7. The conductive layer 233 of transistor Tr22 and the low-resistance region 33a of transistor Tr14 are connected via conductive layers 236_2, 267_11, 234_9, 257_6, and 256_6.

[0180] Transistor Tr14 is a transistor in the aforementioned drive circuit. Specifically, transistor Tr14 is included in the circuit for supplying a signal to the gate electrode of transistor Tr22.

[0181] The following describes an example configuration of the display device 10 that differs from that shown in Figure 16. Note that the differences from Figure 16 will be the main focus of the explanation, and similar configurations will be omitted as appropriate.

[0182] Figure 17 shows an example in which transistor Tr14 is provided in layer 40. In the example shown in Figure 17, the conductive layer 233 of transistor Tr22 and the conductive layer 232a of transistor Tr14 are connected via conductive layers 236_2, 267_11, and 235_8.

[0183] Figure 18 shows an example in which the transistor Tr22 shown in Figure 17 is provided in layer 20. In the example shown in Figure 18, the low-resistance region 33 functions as the other of the source region and drain region of transistor Tr21, as well as one of the source region and drain region of transistor Tr22. Furthermore, the conductive layer 35 of transistor Tr22 and the conductive layer 232a of transistor Tr14 are connected via conductive layers 256_7, 257_7, 234_10, 267_12, and 235_9.

[0184] For example, one or both of the transistors Tr23 and Tr24 shown in Figure 2A may be provided in layer 20. Also, for example, at least one of the transistors provided in the pixel circuit 27 shown in Figure 2B may be provided in layer 20.

[0185] Figure 19 shows an example in which a transistor Tr13 is provided in layer 20 and a memory cell MC is provided in layer 40. For an explanation of the transistor Tr13 and the memory cell MC, please refer to Figures 12A and 12B.

[0186] Figure 20 shows an example in which layer 41 is provided between layer 40 and layer 50, and the memory cell MC shown in Figure 19 is provided in layer 41. For an explanation of layer 41, please refer to Figure 14.

[0187] Figure 21 shows an example in which at least a portion of the photoelectric conversion region 13 has an area that does not overlap with any of the insulating layers 281, 261, 262, 282, 283, 284, 271, and 278. In the example shown in Figure 21, it can be said that insulating layers 281, 261, 262, 282, 283, 284, 271, and 278 overlap with the photoelectric conversion region 13 and have an opening in which no conductive layers other than the common electrode 173 are provided.

[0188] By having at least a portion of the photoelectric conversion region 13 that does not overlap with the insulating layer 278, the absorption of photo-Lin by the insulating layer 278 can be suppressed. In particular, when the transmittance of visible light in the insulating layer 278 is low, it is preferable that the insulating layer 278 has an opening that overlaps with the photoelectric conversion region 13.

[0189] Furthermore, since at least a portion of the photoelectric conversion region 13 has a region that does not overlap with any of the insulating layers 281, 261, 262, 282, 283, 284, and 271, the number of insulating layers that light Lin passes through before entering the photoelectric conversion region 13 can be reduced. This suppresses the reflection of light Lin at the interfaces of insulating layers that are in contact with each other.

[0190] In particular, an insulating layer with a high refractive index, such as silicon oxide (refractive index of approximately 1.5), having an opening that overlaps with the photoelectric conversion region 13 can reduce the difference in refractive index between two insulating layers in contact with each other. Therefore, the reflection of light Lin at the interface of the insulating layers in contact with each other can be suitably suppressed. For example, an insulating layer with a refractive index of 1.7 or higher is preferably an opening that overlaps with the photoelectric conversion region 13. Note that at least one of insulating layers 281, 261, 262, 282, 283, 284, and 271 does not need to have an opening that overlaps with the photoelectric conversion region 13 and does not have a conductive layer. Also, at least one of insulating layers 253, 252, 211, 212, 213, 214, 254, and 255 may have an opening that overlaps with the photoelectric conversion region 13 and does not have a conductive layer.

[0191] As a result, light Lin can be efficiently incident on the photoelectric conversion region 13. Therefore, the imaging sensitivity of the display device 10 can be increased.

[0192] <Example of Display Device Configuration 5> Below, an example of the configuration of display device 10A, which is a modified version of display device 10, will be described. Note that the differences from display device 10 will be mainly explained, and explanations of similar configurations will be omitted as appropriate.

[0193] Figure 22 is a plan view showing an example configuration of the display device 10A. Figure 22 shows a 4x2 pixel arrangement 21. Here, the 4x2 pixel arrangement 21 is denoted as pixel 21[1,1], pixel 21[1,2], pixel 21[2,1], pixel 21[2,2], pixel 21[3,1], pixel 21[3,2], pixel 21[4,1], and pixel 21[4,2].

[0194] In Figure 22, for example, the pixel electrodes 23R, 23G, and 23B provided in pixel 21[4,1] are shown as pixel electrode 23R[4,1], pixel electrode 23G[4,1], and pixel electrode 23B[4,1], respectively. Similarly, the pixel electrodes 23R, 23G, and 23B provided in pixel 21[4,2] are shown as pixel electrode 23R[4,2], pixel electrode 23G[4,2], and pixel electrode 23B[4,2], respectively.

[0195] The display device 10A is provided with a photodiode PDa and a photodiode PDb. The photodiodes PDa and PDb are provided so that at least a portion of them does not overlap with the pixel electrodes 23. Figure 22 shows an example in which the photodiodes PDa and PDb are provided in a region surrounded by four pixel electrodes 23.

[0196] Figure 22 shows transistors Tr21a and Tr21b. Transistors Tr21a and Tr21b are transistors provided in an imaging pixel having photodiodes PDa and PDb. Transistor Tr21a is connected to photodiode PDa. Transistor Tr21b is connected to photodiode PDb.

[0197] Figure 22 shows an example in which transistors Tr21a and Tr21b are located in a region surrounded by four pixel electrodes 23.

[0198] Figure 22 shows the shape of the photodiode Pda in a plan view, and an example where the shape of the photodiode Pda in a plan view is rectangular. Also, Figure 22 shows an example where the total number of photodiodes Pda and photodiodes PDb in the display device 10A is less than the number of pixel electrodes 23. Furthermore, Figure 22 shows an example where the photodiodes Pda and photodiodes PDb are arranged in a zigzag pattern. From the above, it can be said that the display device 10A shown in Figure 22 is a modified version of the display device 10 shown in Figure 8. Therefore, the explanation of the display device 10A shown in Figure 22 can be appropriately explained by referring to the explanation of the display device 10 shown in Figure 8.

[0199] In Figure 22, a photodiode PDa having a region surrounded by pixel electrodes 23B[1,1], 23R[1,2], 23B[2,1], and 23R[2,2], a region located between pixel electrodes 23B[1,1] and 23R[1,2], and a region located between pixel electrodes 23B[2,1] and 23R[2,2] is denoted as photodiode PDar. Similarly, a photodiode PDb having a region surrounded by pixel electrodes 23B[3,1], 23R[3,2], 23B[4,1], and 23R[4,2], a region located between pixel electrodes 23B[3,1] and 23R[3,2], and a region located between pixel electrodes 23B[4,1] and 23R[4,2] is denoted as photodiode PDbr. Furthermore, the region enclosed by pixel electrode 23B[2,1], pixel electrode 23R[2,2], pixel electrode 23B[3,1], and pixel electrode 23R[3,2] is defined as region R2. In the example shown in Figure 22, transistors Tr21a and Tr21b are provided in region R2. The same description will be used in the subsequent plan views showing an example of the configuration of the display device 10A.

[0200] Figure 23A is a circuit diagram showing an example configuration of image pixels 25A1 and 25A2. Pixel 25A1 includes a photodiode PDa, transistors Tr21a, Tr22, Tr23, Tr24, and a capacitive element C1. Pixel 25A2 includes a photodiode PDb, transistors Tr21b, Tr22, Tr23, Tr24, and a capacitive element C1. When explaining aspects common to pixels 25A1 and 25A2, they may simply be referred to as pixel 25A. Below, we will mainly explain the differences from pixel 25, and explanations of similar configurations will be omitted as appropriate.

[0201] One electrode of photodiode PDa (the cathode in the example shown in Figure 23A) is connected to one of the source and drain of transistor Tr21a. One electrode of photodiode PDb (the cathode in the example shown in Figure 23A) is connected to one of the source and drain of transistor Tr21b. The other source and drain of transistor Tr21a is connected to the other source and drain of transistor Tr21b. The other source and drain of transistor Tr21b is connected to node FD.

[0202] The other electrode of photodiode PDa (the anode in the example shown in Figure 23A) is connected to wiring CTa. The other electrode of photodiode PDb (the anode in the example shown in Figure 23A) is connected to wiring CTb. The gate of transistor Tr21a is connected to wiring TXa. The gate of transistor Tr21b is connected to wiring TXb.

[0203] Wiring TXa functions as a signal line that controls the conduction of transistor Tr21a. Wiring TXb functions as a signal line that controls the conduction of transistor Tr21b. Wirings CTa and CTb function as power lines. In the example shown in Figure 23A, a low potential is supplied to wirings CTa and CTb.

[0204] In the imaging pixel shown in Figure 23A, transistors Tr22, Tr23, Tr24, and capacitive element C1 are each shared by pixels 25A1 and 25A2. That is, in the example shown in Figure 23A, at least one of the transistors and capacitive elements is shared among multiple imaging pixels. This reduces the area occupied by the pixel circuit. Therefore, for example, the area occupied by the photodiode can be increased, and the imaging sensitivity of the display device can be improved. Also, by reducing the area occupied by the imaging pixel, it becomes easier to form, for example, a drive circuit in layer 20 as shown in Figure 3.

[0205] Figure 23B is a cross-sectional view between the dashed lines A1 and A2 shown in Figure 22. Figure 23B shows the substrate 11, photodiode PDa, photodiode PDb, transistor Tr21a, and transistor Tr21b. It also shows the insulating layers 253 on photodiode PDa, photodiode PDb, transistor Tr21a, and transistor Tr21b.

[0206] As shown in Figure 23B, photodiode PDa is a pn junction type photodiode having a photoelectric conversion region 13a. Similarly, photodiode PDb is a pn junction type photodiode having a photoelectric conversion region 13b. The photoelectric conversion regions 13a and 13b are provided in the substrate 11. For a description of the photoelectric conversion regions 13a and 13b, refer to the description of the photoelectric conversion region 13.

[0207] The photoelectric conversion region 13a also functions as either the source region or the drain region of the transistor Tr21a. That is, the photoelectric conversion region 13a is shared by the photodiode PDa and the transistor Tr21a. Similarly, the photoelectric conversion region 13b also functions as either the source region or the drain region of the transistor Tr21b. That is, the photoelectric conversion region 13b is shared by the photodiode PDb and the transistor Tr21b. The photoelectric conversion regions 13a and 13b can be low-resistance regions.

[0208] Furthermore, in the example shown in Figure 23B, the low-resistance region 33 functions as the other of the source region and drain region of transistor Tr21a, and the other of the source region and drain region of transistor Tr21b. That is, in the example shown in Figure 23B, the low-resistance region 33 is shared by transistors Tr21a and Tr21b.

[0209] Transistor Tr21a has a conductive layer 35 that functions as a gate electrode and an insulating layer 37 that functions as a gate insulating layer. Similarly, transistor Tr21b also has a conductive layer 35 and an insulating layer 37. Here, the conductive layer 35 of transistor Tr21a and the conductive layer 35 of transistor Tr21b can be different conductive layers. Also, the insulating layer 37 of transistor Tr21a and the insulating layer 37 of transistor Tr21b can be different insulating layers. Note that in Figure 23B, the insulating layer 39 in contact with the side surface of the conductive layer 35 is shown.

[0210] As shown in Figure 23B, transistor Tr21a is connected to photodiode PDa and is provided in close proximity. Similarly, transistor Tr21b is connected to photodiode PDb and is provided in close proximity. Therefore, as shown in Figure 22, by providing transistors Tr21a and Tr21b such that at least a portion of each does not overlap with the pixel electrode 23, it becomes easier to prevent photodiodes PDa and PDb from overlapping with the pixel electrode 23. Specifically, it becomes easier to prevent photoelectric conversion regions 13a and 13b shown in Figure 23B from overlapping with the pixel electrode 23. Therefore, a display device capable of high-sensitivity imaging can be provided. Note that Figure 22 shows an example in which transistors Tr21a and Tr21b are provided in a region surrounded by four pixel electrodes 23, but transistors Tr21a and Tr21b may also be provided between two pixel electrodes 23.

[0211] The following describes an example in which the arrangement of at least one of the photodiodes Pda, PDb, transistor Tr21a, and transistor Tr21b differs from that in Figure 22. Note that the differences from Figure 22 will be explained primarily, and similar configurations will be omitted as appropriate.

[0212] Figure 24 shows an example where the shape of the photodiode PDa and the photodiode PDb in a plan view are cross-shaped. In the example shown in Figure 24, the photodiode PDa and the photodiode PDb each have a region surrounded by four pixel electrodes 23, a region located between two adjacent pixel electrodes 23 in the X direction, and a region located between two adjacent pixel electrodes 23 in the Y direction. Specifically, the photodiode PDa has two regions located between two adjacent pixel electrodes 23 in the X direction, and two regions located between two adjacent pixel electrodes 23 in the Y direction. The same applies to the photodiode PDb. The photodiode PDar shown in Figure 24 has a region located between two adjacent pixel electrodes 23 in the Y direction, specifically a region located between pixel electrode 23B[1,1] and pixel electrode 23B[2,1], and a region located between pixel electrode 23R[1,2] and pixel electrode 23R[2,2].

[0213] In the example shown in Figure 24, the occupied area of ​​photodiode PDa and photodiode PDb can be increased compared to the example shown in Figure 22. Therefore, the display device 10A shown in Figure 24 can be made into a display device with higher imaging sensitivity than the display device 10A shown in Figure 22. On the other hand, in the example shown in Figure 22, it is easier to prevent multiple photodiodes from coming into contact with each other compared to the example shown in Figure 24. Therefore, the display device 10A shown in Figure 22 can be made into a display device with higher reliability and can be manufactured at a lower cost than the display device 10A shown in Figure 24.

[0214] Figure 25 is a plan view showing an example in which transistors Tr22, Tr23, and Tr24, shown in Figure 23A, are provided between transistors Tr21a and Tr21b and a photodiode PDb adjacent in the X direction. In the example shown in Figure 25, transistors Tr22, Tr23, and Tr24 are provided between two adjacent pixel electrodes 23 in the Y direction. Thus, in a display device according to one aspect of the present invention, for example, transistors shared by pixels 25A1 and 25A2 can be provided between two adjacent pixel electrodes 23.

[0215] For example, by arranging transistors Tr22 to Tr24 between two adjacent pixel electrodes 23 in the Y direction, transistors Tr22 to Tr24 can be brought closer to transistors Tr21a and Tr21b compared to the case where they are arranged so as to overlap with the pixel electrodes 23. This makes it possible to reduce the wiring resistance in pixel 25A, as shown in Figure 23A. Therefore, the operating speed of the display device 10A can be increased.

[0216] In the example shown in Figure 25, transistors Tr22 to Tr24 are provided adjacent to transistors Tr21a and Tr21b in the X direction, but transistors Tr22 to Tr24 may also be provided adjacent to transistors in the -X direction. Alternatively, for example, one or two of transistors Tr22 to Tr24 may be provided adjacent to transistors Tr21a and Tr21b in the X direction, and the remaining ones may be provided adjacent to transistors in the -X direction. Transistors Tr22 and Tr23 may be provided between two adjacent pixel electrodes 23 in the Y direction, and transistor Tr24, which is not directly connected to transistors Tr21a and Tr21b, may be provided so as to overlap with the pixel electrode 23. The same applies to the display device 10A described later.

[0217] Figure 26 shows an example where the shape of the photodiode Pda in a plan view and the shape of the photodiode PDb in a plan view are cross-shaped. The photodiodes Pda and PDb shown in Figure 26 each have two regions located between two adjacent pixel electrodes 23 in the Y direction. The photodiode PDar shown in Figure 26 has a region located between pixel electrodes 23B[1,1] and 23B[2,1], and a region located between pixel electrodes 23R[1,2] and 23R[2,2] as regions located between two adjacent pixel electrodes 23 in the Y direction. The photodiode PDbr shown in Figure 26 has a region located between pixel electrodes 23B[3,1] and 43B[4,1], and a region located between pixel electrodes 23R[3,2] and 43B[4,2] as regions located between two adjacent pixel electrodes 23 in the Y direction.

[0218] In the example shown in Figure 26, the occupied area of ​​photodiode PDa and photodiode PDb can be increased compared to the example shown in Figure 25. Therefore, the display device 10A shown in Figure 26 can be made into a display device with higher imaging sensitivity than the display device 10A shown in Figure 25. On the other hand, in the example shown in Figure 25, it is easier to prevent multiple photodiodes from coming into contact with each other compared to the example shown in Figure 26. Therefore, the display device 10A shown in Figure 25 can be made into a display device with higher reliability and can be manufactured at a lower cost than the display device 10A shown in Figure 26.

[0219] Figure 27 shows an example where the shape of the photodiode PDa and the photodiode PDb in a plan view are combined into two rectangles. In the example shown in Figure 27, the photodiode PDa and the photodiode PDb each have a region surrounded by four pixel electrodes 23, a region located between two adjacent pixel electrodes 23 in the X direction, and a region located between two adjacent pixel electrodes 23 in the Y direction. Specifically, the photodiode PDa and the photodiode PDb each have one region located between two adjacent pixel electrodes 23 in the Y direction. The photodiode PDar shown in Figure 27 has a region located between two adjacent pixel electrodes 23 in the Y direction, specifically between pixel electrodes 23R[1,2] and pixel electrodes 23R[2,2]. The photodiode PDbr shown in Figure 27 has a region located between two adjacent pixel electrodes 23 in the Y direction, specifically between pixel electrodes 23R[3,2] and pixel electrodes 23B[4,2]. Furthermore, the photodiode PDar may have a region located between pixel electrodes 23B[1,1] and 23B[2,1] instead of the region located between pixel electrodes 23R[1,2] and 23R[2,2]. Similarly, the photodiode PDbr may have a region located between pixel electrodes 23B[3,1] and 23B[4,1] instead of the region located between pixel electrodes 23R[3,2] and 23R[4,2]. In the example shown in Figure 27, as in the example shown in Figure 26, the occupied area of ​​photodiode PDa and the occupied area of ​​photodiode PDb can be made larger than in the example shown in Figure 25.

[0220] Figure 28 shows a modified version of the display device 10A shown in Figure 27, in which transistors Tr21a, Tr21b, and Tr22 to Tr24 are provided between the first row of pixel electrodes 23 and the second row of pixel electrodes 23, and between the second row of pixel electrodes 23 and the third row of pixel electrodes 23. In the example shown in Figure 28, photodiodes PDa and PDb each have three regions between two adjacent pixel electrodes 23 in the X direction. For example, photodiode PDbr has a region located between pixel electrodes 23B[2,1] and 23R[2,2], a region located between pixel electrodes 23B[3,1] and 23R[3,2], and a region located between pixel electrodes 23B[4,1] and 23R[4,2]. Photodiode PDbr also has a region located between pixel electrodes 23R[3,2] and 23R[4,2]. Furthermore, the transistor Tr21b, which is connected to the photodiode PDbr, is located in the region surrounded by the pixel electrodes 23B[1,1], 23R[1,2], 23B[2,1], and 23R[2,2].

[0221] <Examples of Photodiode Configurations> Below, detailed examples of photodiode PD configurations will be explained using Figures 29A to 29D and Figures 30A to 30D. While the explanation describes an example where the photoelectric conversion region 13 of the photodiode PD is an n-type region, the following explanation can also be applied when the photoelectric conversion region 13 is a p-type region by appropriately swapping p-type and n-type regions, swapping anodes and cathodes, and swapping high and low potentials. Furthermore, the following examples of photodiode PD configurations can also be applied to photodiode PDa and photodiode PDb, respectively, by replacing the photoelectric conversion region 13 with photoelectric conversion region 13a and photoelectric conversion region 13b.

[0222] Figures 29A to 30D are cross-sectional views showing examples of the configuration of the layer 20 on which the substrate 11 is provided. In Figures 29A to 30D, in addition to the photodiode PD, a transistor Tr11 is shown. In the following, the configuration described in Figure 10 will be omitted from explanation as appropriate.

[0223] In the example shown in Figure 29A, conductive layers 259_1 and 259_2 are provided so as to embed the insulating layer 253. Conductive layer 259_1 has a region that is in contact with the p-type semiconductor region of the substrate 11. Conductive layer 259_2 has a region that is in contact with the low-resistance region 33b of the transistor Tr11.

[0224] Furthermore, a conductive layer 265 is provided so as to embed the insulating layer 252. The conductive layer 265 has a region in contact with conductive layer 259_1 and a region in contact with conductive layer 259_2. As a result, the p-type semiconductor region of the substrate 11 is connected to the conductive layer 265 via conductive layer 259_1. Also, the low-resistance region 33b of the transistor Tr11 is connected to the conductive layer 265 via conductive layer 259_2.

[0225] The conductive layer 265 can be supplied with a low potential, such as the ground potential. This allows a low potential to be supplied to the anode of the photodiode PD and to the source region and the other drain region of the transistor Tr11, such as the ground potential. As described above, the wiring CT shown in Figure 2A and the power line for supplying a low potential to the drive circuit can be shared. This reduces the occupied area of ​​the display device 10 compared to when the power line for supplying a low potential to the drive circuit is a separate wiring from the wiring CT.

[0226] Figure 29B shows an example in which a semiconductor region 14 is provided on a part of the surface side (upper side in the drawing) of the photoelectric conversion region 13 shown in Figure 29A. The semiconductor region 14 can be a p-type semiconductor region.

[0227] In the example shown in Figure 29B, the area of ​​the region in contact between the insulating layer 253 and the photoelectric conversion region 13 can be made smaller than in the example shown in Figure 29A. Therefore, noise generated in the photodiode PD can be reduced. Thus, the imaging sensitivity of the display device according to one embodiment of the present invention can be increased.

[0228] Figure 29C shows an example in which a semiconductor region 15 is provided below the photoelectric conversion region 13 shown in Figure 29A, and a semiconductor region 16 is provided below the semiconductor region 15. In the example shown in Figure 29C, a part of the front surface of the substrate 11 is the semiconductor region 15, and the other part is the semiconductor region 16.

[0229] The semiconductor region 15 can be a p-type semiconductor region. The semiconductor region 16 can be an n-type semiconductor region. In the photodiode PD shown in Figure 29C, a pn-junction type photodiode can be constructed using the photoelectric conversion region 13 and the semiconductor region 15.

[0230] The insulating layer 253 shown in Figure 29C has conductive layers 259_1 and 259_2 embedded in it, as well as conductive layers 259_3 and 259_4. Conductive layer 259_3 has a region in contact with the semiconductor region 15. Conductive layer 259_4 has a region in contact with the semiconductor region 16.

[0231] As shown in Figure 29C, the insulating layer 252 has a conductive layer 265, as well as a conductive layer 265a and a conductive layer 266 embedded within it. Conductive layer 265a has a region in contact with conductive layer 259_3. Conductive layer 266 has a region in contact with conductive layer 259_4. Thus, the semiconductor region 15 is connected to conductive layer 265a via conductive layer 259_3. Also, the semiconductor region 16 is connected to conductive layer 266 via conductive layer 259_4.

[0232] A low potential can be supplied to the conductive layer 265a, similar to the conductive layer 265, for example, the ground potential. A high potential can be supplied to the conductive layer 266. As a result, a reverse bias voltage can be applied between the p-type semiconductor region 15 and the n-type semiconductor region 16. This allows the photodiode PD to be isolated from other semiconductor elements, such as transistors. In the example shown in Figure 29C, the photodiode PD and the transistor Tr11 can be isolated.

[0233] In the example shown in Figure 29C, the wiring CT shown in Figure 2A can be separated from the power supply line (conductive layer 265) for supplying a low potential to the drive circuit. This makes it possible to suppress noise caused by, for example, the transistor Tr11 from affecting the photodiode PD. Therefore, the imaging sensitivity of the display device according to one embodiment of the present invention can be increased.

[0234] Figure 29D shows an example in which a p-type semiconductor region 14 is provided on a part of the surface side (upper side in the drawing) of the photoelectric conversion region 13 shown in Figure 29C. This reduces noise generated in the photodiode PD and improves the imaging sensitivity of the display device according to one embodiment of the present invention.

[0235] Figures 30A, 30B, 30C, and 30D show examples in which a transistor Tr21 is provided on layer 20 as shown in Figures 29A, 29B, 29C, and 29D, respectively. For an explanation of transistor Tr21, please refer to the explanation in Figure 16.

[0236] In the examples shown in Figures 30C and 30D, the channel formation region of transistor Tr21 is formed in the semiconductor region 15. Furthermore, the semiconductor region 16 allows transistor Tr21 to be isolated from other semiconductor elements, such as other transistors.

[0237] <Transistor Configuration Example 1> Figure 31A is a plan view showing a configuration example of transistor 200. Figure 31B is a cross-sectional view between the dashed lines B1 and B2 shown in Figure 31A. Figure 31C is a cross-sectional view between the dashed lines B3 and B4 shown in Figure 31A. Figure 31B is a cross-sectional view showing a configuration example of transistor 200 in the channel length direction. Figure 31C is a cross-sectional view showing a configuration example of transistor 200 in the channel width direction. Transistor 200 can be applied to the transistor provided in layer 40, the transistor provided in layer 41, and the transistor provided in layer 50 as described above.

[0238] As shown in Figures 31A to 31C, the transistor 200 includes, as an example, a semiconductor layer 251, a conductive layer 231, a conductive layer 232a, a conductive layer 232b, a conductive layer 233, and insulating layers 261 to 264. Figures 31B and 31C also show insulating layers 212 to 214 and insulating layers 281 to 283. Note that the transistor 200 may not have all of the above-mentioned components. For example, although the conductive layer 231 functions as a back gate electrode in the transistor 200, the transistor 200 can also be configured without the conductive layer 231.

[0239] The conductive layer 231 (conductive layer 231a and conductive layer 231b) and the insulating layer 212 are arranged on top of the substrate (not shown). It is preferable that the conductive layer 231 is embedded in the insulating layer 212. Specifically, it is preferable that the conductive layer 231a is provided in contact with the bottom surface and side wall of an opening provided in the insulating layer 212. It is also preferable that the conductive layer 231b is provided so as to be embedded in a recess formed in the conductive layer 231a. In the transistor 200 shown in Figures 31B and 31C, the height of the upper surface of the conductive layer 231b is approximately the same as the height of the upper surface of the conductive layer 231a and the height of the upper surface of the insulating layer 212.

[0240] The insulating layer 212 functions as a planarizing film, for example, to flatten steps caused by plugs or the like. Therefore, a material that functions as a planarizing film can be used for the insulating layer 212.

[0241] Furthermore, by using a material with a low dielectric constant as described above for the insulating layer 212, the parasitic capacitance between the wiring can be reduced. In particular, using materials such as silicon oxide, silicon oxynitride, or silicon oxide with vacancies is preferable because it is possible to easily form regions containing oxygen that is desorbed by heating.

[0242] Furthermore, the semiconductor layer 251 (semiconductor layer 251a and semiconductor layer 251b) and the conductive layer 233 are arranged in a region that overlaps with the conductive layer 231. Also, the semiconductor layer 251b is arranged on top of the semiconductor layer 251a. Furthermore, the conductive layers 232a and 232b are arranged on top of the semiconductor layer 251b, spaced apart from each other. Furthermore, the insulating layer 213 is arranged on top of the conductive layers 232a and 232b. In particular, an opening is formed in the insulating layer 213 in the region between the conductive layers 232a and 232b. Furthermore, the conductive layer 233 is arranged within this opening. Furthermore, the insulating layer 264 is arranged between the semiconductor layer 251b, the conductive layer 232a, the conductive layer 232b, the insulating layer 213, and the conductive layer 233. Here, as shown in Figures 31B and 31C, it is preferable that the upper surface of the conductive layer 233 substantially coincides with the upper surfaces of the insulating layer 264 and the insulating layer 213.

[0243] Furthermore, as shown in Figure 31B, a low-resistance region 271a may be formed at the interface between the semiconductor layer 251b and the conductive layer 232a, and in its vicinity. Similarly, a low-resistance region 271b may be formed at the interface between the semiconductor layer 251b and the conductive layer 232b, and in its vicinity. In this case, the low-resistance region 271a functions as one of the source region and drain region of the transistor 200. The low-resistance region 271b functions as the other of the source region and drain region of the transistor 200. A channel-forming region is formed in the region sandwiched between the low-resistance region 271a and the low-resistance region 271b.

[0244] For the semiconductor layer 251, it is preferable to use a metal oxide that functions as an oxide semiconductor and includes a channel formation region. In particular, indium oxide, as described in Embodiment 2, is preferred as the metal oxide. In addition to indium oxide, various other metal oxides that form the channel formation region of the transistor 200 will also be described below.

[0245] As the metal oxide that forms the channel formation region of the transistor 200, it is preferable to use one with a band gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3.0 eV or more. Specifically, for example, in the case of the transistor 200 shown in Figures 31A to 31C, it is preferable to use a metal oxide that functions as an oxide semiconductor for the semiconductor layer 251.

[0246] Metal oxide structures can be classified into single-crystal structures and other structures (non-single-crystal structures). Examples of non-single-crystal structures include CAAC (c-axis aligned crystalline) structures, polycrystalline structures, nanocrystalline structures, a-like (amorphous-like) structures, and amorphous structures. The structure of the metal oxide in one aspect of the present invention is not particularly limited, and any of the above structures can be used. However, using crystalline metal oxides such as CAAC structures and nc structures is preferable because it allows for the creation of a highly reliable display device.

[0247] Furthermore, it is preferable that the above metal oxide contains at least indium. It may also contain indium and zinc. In addition to these, it may also contain element M. Element M can be one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony. In particular, element M can be one or more selected from aluminum, gallium, yttrium, or tin. It is even more preferable that element M is one or more selected from aluminum, gallium, yttrium, and tin.

[0248] As the above metal oxides, indium oxide (also called indium oxide), gallium oxide, zinc oxide, indium zinc oxide, indium tin oxide, indium titanium oxide, indium gallium oxide, indium gallium aluminum oxide, indium gallium tin oxide, gallium zinc oxide, aluminum zinc oxide, indium aluminum zinc oxide, indium tin zinc oxide, indium titanium zinc oxide, indium gallium zinc oxide, indium gallium tin zinc oxide, indium gallium aluminum zinc oxide, etc. can be used. Alternatively, indium tin oxide, gallium tin oxide, aluminum tin oxide, etc. containing silicon can be used.

[0249] As described above, the metal oxide preferably contains indium. Specifically, it is preferable to use indium oxide as the metal oxide. Crystalline indium oxide is particularly preferable.

[0250] Metal oxides can be suitably formed using sputtering or ALD (Advanced Laser Deposition). When metal oxides are formed by sputtering, films with high crystallinity or high film density can be formed. When metal oxides are formed using ALD, atoms can be deposited layer by layer, resulting in film formation with fewer defects such as pinholes, excellent coverage, and the ability to form films at low temperatures. Furthermore, it is preferable to perform an impurity removal treatment after the formation of the metal oxide to remove impurities (typically water, hydrogen, carbon, nitrogen, etc.) from the metal oxide film. Examples of impurity removal treatments include plasma treatment, microwave plasma treatment, and heat treatment.

[0251] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less. Microwave plasma processing refers to processing using a device that has a power supply that generates high-density plasma using microwaves, for example. Microwave plasma processing can also be called microwave-excited high-density plasma processing.

[0252] Although the transistor 200 is shown with a configuration in which two semiconductor layers, semiconductor layer 251a and semiconductor layer 251b, are stacked in the channel formation region and its vicinity, the present invention is not limited to this. For example, a single-layer structure of semiconductor layer 251b or a stacked structure of three or more layers may be provided. Furthermore, each of semiconductor layer 251a and semiconductor layer 251b may have a stacked structure of two or more layers.

[0253] The conductive layer 233 functions as the first gate electrode of the transistor 200. The conductive layer 232a functions as one of the source electrode and drain electrode of the transistor 200. The conductive layer 232b functions as the other of the source electrode and drain electrode of the transistor 200. As described above, the conductive layer 233 is formed to be embedded in the opening of the insulating layer 213 and in the region sandwiched between the conductive layers 232a and 232b. Here, the arrangement of the conductive layer 233, conductive layer 232a and conductive layer 232b is formed in a self-aligned manner with respect to the opening of the insulating layer 213. In other words, in the transistor 200, the first gate electrode can be positioned in a self-aligned manner between the source electrode and the drain electrode. Therefore, since the conductive layer 233 can be formed without providing a positional margin, the occupied area of ​​the transistor 200 can be reduced. This makes it possible to increase the density of arithmetic cells in the arithmetic unit.

[0254] In Figures 31B and 31C, the conductive layer 233 is shown as a two-layer structure. Here, it is preferable that the conductive layer 233 has a conductive layer 233a and a conductive layer 233b disposed on top of the conductive layer 233a. For example, it is preferable that the conductive layer 233a is arranged to enclose the bottom and sides of the conductive layer 233b. In this case, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion as the conductive layer 233a.

[0255] It is preferable to use a conductive material for the conductive layer 233a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen. Furthermore, by having the function of suppressing the diffusion of oxygen in the conductive layer 233a, it is possible to suppress oxidation of the conductive layer 233b by oxygen contained in the insulating layer 213, etc., and a decrease in conductivity. As a conductive material that has the function of suppressing the diffusion of oxygen, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc.

[0256] Furthermore, it is preferable to use a conductive layer with high conductivity for the conductive layer 233b. For example, the conductive layer 233b can be made of a conductive material mainly composed of tungsten, copper, or aluminum. The conductive layer 233b may also be in a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0257] For conductive layers 232a and 232b, it is preferable to use conductive materials that are resistant to oxidation or conductive materials that have a function to suppress the diffusion of oxygen. Examples of such conductive materials include conductive materials containing nitrogen and conductive materials containing oxygen. This makes it possible to suppress a decrease in the conductivity of conductive layers 232a and 232b. When conductive materials containing metal and nitrogen are used as conductive layers 232a and 232b, conductive layers 232a and 232b become conductive layers having at least metal and nitrogen. For example, as materials to be applied to conductive layers 232a and 232b, conductive materials that are resistant to oxidation or conductive materials that have a function to suppress the diffusion of oxygen can be selected from the materials that can be applied to conductive layers 233a and 233b respectively as described above.

[0258] The conductive layer 231 may function as a second gate electrode of the transistor 200. In this case, the threshold voltage V of the transistor 200 can be changed by independently changing the potential applied to the conductive layer 231, separate from the potential applied to the conductive layer 233. ｔｈ This can be controlled. In particular, by applying a negative potential to the conductive layer 231, the V of the transistor 200 can be controlled. ｔｈ This makes it possible to increase the voltage and decrease the off-current. Therefore, applying a negative potential to the conductive layer 231 reduces the drain current when the potential applied to the conductive layer 233 is 0V compared to when no potential is applied.

[0259] The conductive layer 231 should be larger than the channel formation region in the semiconductor layer 251. In particular, as shown in Figure 31C, it is preferable that the conductive layer 231 extends as wiring even in the region outside the edge that intersects with the channel width direction of the semiconductor layer 251. That is, it is preferable that the conductive layer 231 and the conductive layer 233 are superimposed on the outside of the side surface in the channel width direction of the semiconductor layer 251, with an insulating layer in between.

[0260] As shown in Figure 31B, the conductive layer 233 preferably has a conductive layer 233a provided inside the insulating layer 264 and a conductive layer 233b provided so as to be embedded inside the conductive layer 233a. Although Figures 31B and 31C show the conductive layer 233 as a two-layer laminated structure, the present invention is not limited thereto. For example, the conductive layer 233 may be a single-layer structure or a laminated structure of three or more layers.

[0261] For the conductive layer 231 and conductive layer 233, for example, materials applicable to conductive layer 233a and conductive layer 233b described above can be selected and used.

[0262] As shown in Figures 31B and 31C, it is preferable that an insulating layer 282 is placed between the insulating layer 262, insulating layer 263, semiconductor layer 251a, semiconductor layer 251b, conductive layer 232a, conductive layer 232b, and insulating layer 213. Here, as shown in Figures 31B and 31C, it is preferable that the insulating layer 282 is in contact with the side surface of the insulating layer 264, the top and side surfaces of the conductive layer 232a, the top and side surfaces of the conductive layer 232b, the semiconductor layer 251a, semiconductor layer 251b, the side and top surfaces of the insulating layer 263, and the top surface of the insulating layer 262.

[0263] The insulating layer 264 functions as the first gate insulating layer in the transistor 200. For example, the insulating layer 264 can be silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or silicon oxide with vacancies. Other materials that can be used include, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO2). ３ ) or (Ba, Sr)TiO ３ An insulating layer containing a so-called high-k material such as (BST) can be used in a single layer or a multilayer configuration. Furthermore, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the above insulating layer material. Alternatively, these insulating layers may be subjected to nitriding treatment.

[0264] Furthermore, insulating layers 261 to 263 function as a second gate insulating layer in the transistor 200. In addition to the materials mentioned above, insulating layers 261 to 263 can be made from materials that can be used for insulating layer 264.

[0265] Preferably, insulating layers 283 and 214, which function as interlayer films, are arranged on the transistor 200. Here, it is preferable that the insulating layer 283 is arranged in contact with the upper surfaces of the conductive layer 233, the insulating layer 264, and the insulating layer 213. In this case, it is preferable that the upper surface of the insulating layer 213 is flattened.

[0266] As shown in Figure 31C, in the region of semiconductor layer 251b that does not overlap with either conductive layer 232a or conductive layer 232b, in other words, in the channel formation region of semiconductor layer 251, the side surface of semiconductor layer 251 is covered by conductive layer 233. This makes it easier to apply the electric field of conductive layer 233, which functions as the first gate electrode, to the side surface of semiconductor layer 251, and as a result, the channel formation region of semiconductor layer 251 can be electrically surrounded by the electric field of conductive layer 233. Therefore, the on-current of transistor 200 can be increased and the frequency characteristics can be improved.

[0267] <Example of Transistor Configuration 2> Figure 32A is a plan view of transistor 700. Figure 32B is a cross-sectional view between the dashed lines C1 and C2 shown in Figure 32A. Transistor 700 can be applied to the transistors provided in layer 40, layer 41, and layer 50 described above.

[0268] The transistor 700 has a conductive layer 755 on top of an insulating layer 701. Furthermore, it has an insulating layer 757 on top of the conductive layer 755, an insulating layer 758 on top of the insulating layer 757, and an insulating layer 759 on top of the insulating layer 758. In this specification, the insulating layers 757, 758, and 759 may be collectively referred to as an insulating layer 756 or a spacer layer. Additionally, it has a conductive layer 761 on top of the insulating layer 759.

[0269] Furthermore, in a region overlapping with a portion of the conductive layer 755, an opening 762 is provided that penetrates the conductive layer 761, the insulating layer 759, the insulating layer 758, and the insulating layer 757. In addition, a semiconductor layer 720 is provided covering the inner wall of the opening 762.

[0270] The semiconductor layer 720 has a region that overlaps with the bottom of the opening 762 and a region that overlaps with the side of the opening 762. That is, the semiconductor layer 720 has a region that is in contact with the insulating layer 756 inside the opening 762. The semiconductor layer 720 also has a region that is in contact with the conductive layer 755 and a region that is in contact with the conductive layer 761 inside the opening 762.

[0271] Furthermore, an insulating layer 750 is provided on top of the insulating layer 759, the conductive layer 761, and the semiconductor layer 720. A conductive layer 765 is also provided on top of the insulating layer 750. The conductive layer 765 has a region that overlaps with the semiconductor layer 720. The conductive layer 765 has a region that overlaps with the semiconductor layer 720 via the insulating layer 750. The conductive layer 765 functions as a gate electrode.

[0272] Furthermore, each of the insulating layer 750 and the conductive layer 765 has a region that overlaps with the opening 762. Also, each of the insulating layer 750 and the conductive layer 765 has a region that overlaps with the inside of the opening 762. Inside the opening 762, the semiconductor layer 720 has a region that overlaps with the conductive layer 765 via the insulating layer 750, and a region that overlaps with the side surface of the opening 762 (the side surface of the insulating layer 756).

[0273] Furthermore, an insulating layer 785 is provided on top of the insulating layer 750. It is preferable that the upper surface of the insulating layer 785 is flat. Alternatively, it is preferable that the heights (positions in the Z direction) of the upper surfaces of the insulating layer 785 and the conductive layer 765 coincide or substantially coincide. For example, the flatness of the upper surface of the insulating layer 785 can be improved by performing CMP treatment. Also, by performing CMP treatment, the positions of the upper surfaces of the insulating layer 785 and the conductive layer 765 can be made to coincide or substantially coincide. By performing CMP treatment, surface irregularities of the sample can be reduced, thereby improving the coverage of the insulating layer and conductive layer formed thereafter.

[0274] The semiconductor layer 720 can be made of a material that can be used for the semiconductor layer 251 described above, for example, an oxide semiconductor can be used. When an oxide semiconductor is used for the semiconductor layer 720, it is preferable that the conductive layer 755 and the conductive layer 761 in contact with the semiconductor layer 720 use a conductive material that converts the oxide semiconductor to n-type. For example, it is preferable to use a conductive material containing nitrogen. For example, it is preferable to use a conductive material containing titanium or tantalum and nitrogen. It is also possible to provide other conductive materials on top of the conductive material containing nitrogen.

[0275] Furthermore, when an oxide semiconductor is used for the semiconductor layer 720, it is preferable to use a material with reduced hydrogen and containing oxygen for the insulating layer 758. For example, it is preferable to use a material containing silicon and oxygen. Specifically, it is preferable to use silicon oxide or silicon oxynitride. Since hydrogen is an impurity element in oxide semiconductors, the contact between the semiconductor layer 720, which is an oxide semiconductor, and the insulating layer 758 with reduced hydrogen makes it less likely for the semiconductor layer 720 to become n-type. In addition, the contact between the semiconductor layer 720, which is an oxide semiconductor, and the insulating layer 758 containing oxygen reduces oxygen vacancies in the semiconductor layer 720, stabilizing the characteristics of the transistor and improving reliability.

[0276] Furthermore, when an oxide semiconductor is used for the semiconductor layer 720, the insulating layer 758 may contain excess oxygen. In this specification, excess oxygen refers to oxygen that is desorbed by heating. A material that desorbs oxygen by heating is one in which the amount of oxygen desorbed, converted to oxygen atoms, is 1.0 × 10¹⁶ by TDS (Thermal Desorption Spectroscopy) analysis. １８ atoms / cm ３ Preferably 1.0 × 10 １９ atoms / cm ３ More preferably 2.0 × 10 １９ atoms / cm ３ The above or 3.0 x 10 ２０ atoms / cm ３ The material is as described above. Furthermore, the surface temperature of the film during the TDS analysis is preferably in the range of 100°C to 700°C or 100°C to 500°C.

[0277] Furthermore, when using a material containing excess oxygen for the insulating layer 758, it is preferable to use materials that are impermeable to oxygen for the insulating layers 757 and 759. Examples of materials that are impermeable to oxygen include oxides containing one or both of aluminum and hafnium, silicon nitrides, etc. By using materials that are impermeable to oxygen for the insulating layers 757 and 759, excess oxygen contained in the insulating layer 758 is less likely to desorb to the lower or upper layer. Therefore, sufficient oxygen can be supplied to the oxide semiconductor. For example, a configuration having an insulating layer (insulating layer 758) containing silicon and oxygen between two insulating layers (insulating layer 757, insulating layer 759) containing silicon and nitrogen is preferred.

[0278] Furthermore, when an oxide semiconductor is used for the semiconductor layer 720, by using a hydrogen-containing material for the insulating layer 757 and the insulating layer 759, hydrogen is supplied to the region of the semiconductor layer 720 in contact with the insulating layer 757 and the region of the semiconductor layer 720 in contact with the insulating layer 759, and depending on the composition of the oxide semiconductor used for the semiconductor layer 720, each region becomes n-type. Therefore, the region of the semiconductor layer 720 in contact with the conductive layer 761 and the region of the semiconductor layer 720 in contact with the insulating layer 759 function as one of the source region and the other of the drain region.

[0279] The conductive layer 761 functions as one of the source and drain electrodes of the transistor 700. The conductive layer 755 functions as the other of the source and drain electrodes of the transistor 700.

[0280] Transistor 700 is a transistor in which the source electrode and drain electrode are arranged in the Z direction. That is, the source and drain of transistor 700 are positioned at different heights. In other words, the source and drain of transistor 700 are positioned at different locations in the Z direction. Such a transistor is also called a "vertical channel transistor," "vertical transistor," or "VFET (Vertical Field Effect Transistor)."

[0281] In the above configuration, for the VFET transistor 700, the length of the side surface of the insulating layer 758 viewed from the X or Y direction becomes the channel length L (channel length L1) (see Figure 32B). Therefore, the channel length L of the transistor 700 is determined according to the thickness t1 of the insulating layer 758.

[0282] Furthermore, it is possible to use materials that do not contain hydrogen or contain very little hydrogen for the insulating layers 757 and 759. When silicon nitride or silicon oxide nitride with very little hydrogen is used for the insulating layers 757 and 759, the regions of the semiconductor layer 720 that are in contact with the insulating layer 757 and the regions of the semiconductor layer 720 that are in contact with the insulating layer 759 are not n-type. Therefore, the region of the semiconductor layer 720 that is in contact with the conductive layer 761 functions as one of the source region and the drain region. The region of the semiconductor layer 720 that is in contact with the conductive layer 755 functions as the other of the source region and the drain region. The region of the semiconductor layer 720 that is in contact with the insulating layer 758 functions as a channel-forming region.

[0283] In this case, the sum of the lengths of the sides of insulating layers 757, 758, and 759 as viewed from the X or Y direction becomes the channel length L (channel length L2). Therefore, the channel length L of the transistor 700 is determined according to the thickness t2 obtained by adding the thicknesses of insulating layers 757, 758, and 759. Thus, the transistor 700 has a channel formation region that is aligned with the side surface of the insulating layer 756.

[0284] Furthermore, since the semiconductor layer 720 is provided in the opening 762, the length of the perimeter of the opening 762 when viewed from the Z direction becomes the channel width W of the transistor 700 (see Figure 32A). The length of the perimeter can be determined, for example, at a position halfway through the thickness t1 or halfway through the thickness t2 of the insulating layer 758. If necessary, the length of the perimeter at any position of the opening 762 can be used as the channel width W. For example, the length of the perimeter at the bottom of the opening 762 can be used as the channel width W, or the length of the perimeter at the top of the opening 762 can be used as the channel width W. Also, although the contour (planar shape) of the opening 762 when viewed from the Z direction is shown as a circle in Figure 32A, it is not limited to this. For example, the contour of the opening 762 when viewed from the Z direction can be an ellipse, a rectangle, etc.

[0285] Furthermore, in order to improve the coverage of the semiconductor layer 720, insulating layer 750, and conductive layer 765 formed inside the opening 762, it is preferable that the taper angle θ of the side surface of the opening 762, that is, the taper angle θ of the side surfaces of the insulating layer 757, insulating layer 758, and insulating layer 759, be 45° or more and less than 90°, preferably 50° or more and 75° or less. Note that the taper angle θ of the side surface of a layer (insulating layer, conductive layer, or semiconductor layer) refers to the angle between the bottom surface and the side surface of the layer (see Figure 32B).

[0286] Vertical transistors can reduce the area occupied by a vertical channel transistor compared to a transistor (also called a "horizontal transistor") in which the channel formation region, source region, and drain region are separately located on the XY plane. Therefore, by using vertical channel transistors in a display device, the area occupied by the display device can be reduced. Furthermore, by using vertical channel transistors in a display device, high integration of the display device can be achieved.

[0287] Furthermore, in horizontal transistors, the channel length was limited by the exposure limit of photolithography. In one aspect of the present invention, the vertical channel transistor allows the channel length to be set by the thickness of the insulating layer 756 or insulating layer 758. Therefore, the channel length of the transistor can be made into an extremely fine structure below the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 1 nm or more or 5 nm or more). This increases the on-current of the transistor 700, and improves the frequency characteristics. By using a vertical channel transistor, a display device with a high operating speed can be provided.

[0288] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0289] (Embodiment 2) This embodiment describes an indium oxide film that can be used in the semiconductor layer of a transistor in a display device according to one aspect of the present invention.

[0290] In this specification, indium oxide having at least a crystalline portion or crystalline region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystal IO or crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0291] Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0292] The carrier concentration dependence of the hole (Hall) mobility of indium oxide, silicon, and IGZO is described. Figure 33A shows silicon (Si) and indium oxide (InO Ｘ Figure 33B is a schematic diagram of the carrier concentration dependence of hole mobility with respect to IGZO.

[0293] First, as indicated by the arrows in Figure 33B, IGZO tends to exhibit higher hole mobility as the carrier concentration increases. On the other hand, as indicated by the arrows in Figure 33A, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases (see Non-Patent Literature 2). This trend is similar to that of silicon, where the lower the concentration of dopants (impurities) in the material, the less impurity scattering occurs and the higher the hole mobility. In other words, the higher the purity and intrinsic nature of indium oxide, the higher its hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to silicon. Note that the properties of indium oxide shown in Figure 33A are assumed to be those of a single crystal. Therefore, when indium oxide is not a single crystal (for example, polycrystalline), the properties may differ from those shown in Figure 33A.

[0294] In Figure 33A, the low carrier concentration range R1 exhibits extremely high hole mobility, making it a suitable carrier concentration range for, for example, the channel formation region of a transistor. For example, in the case of indium oxide, the carrier concentration range R1 is 1 × 10⁻⁶. １５ cm −３ This range includes, for example, 1 × 10 １４ cm −３ The above is 1 x 10 １８ cm −３ The range is as follows: By sufficiently reducing the carrier concentration, the hole mobility value can be increased to 270 cm⁻¹. ２ It can be expected to be raised to the level of / (V・s).

[0295] Furthermore, in indium oxide, the region where the carrier concentration is in the range R1 may contain elements that lower the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Other elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0296] On the other hand, the range R2 with high carrier concentration has low electrical resistance and can be said to be a suitable range of carrier concentration for applications such as the source and drain regions of a transistor, or for resistors or transparent conductive films. The range R2 is when the carrier concentration value is 1 × 10⁻⁶. ２０ cm −３ This range includes, for example, 1 × 10 １９ cm −３ The above is 1 x 10 ２２ cm −３ The range is as follows: By making the carrier concentration sufficiently high, the resistivity can be increased to 1 × 10⁻⁶. −４ It is expected that the level can be reduced to below Ω·cm.

[0297] In the case of indium oxide, the region where the carrier concentration is in the range R2 may contain elements that increase the carrier concentration. For example, it is preferable to include elements common to the source and drain electrodes of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use elements whose oxides are conductive or semiconducting. As for the supply method of elements that increase the carrier concentration, a method of forming a film containing the element and diffusing it, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. In this specification, unless otherwise specified, the presence or absence of mass separation is not limited. For example, in this specification, a method of supplying ions by mass separation is called ion implantation, and a method of supplying ions without mass separation is called ion doping.

[0298] In this way, indium oxide uses regions with low carrier concentrations for the transistor's channel formation region and regions with high carrier concentrations for the transistor's source and drain regions. In other words, indium oxide can be said to be an oxide in which valence electron control is possible. In contrast, with IGZO, strain may be formed in the source and drain regions due to stress on the electrodes in contact with IGZO, and an n-type region may be formed. On the other hand, unlike IGZO, indium oxide allows for valence electron control, so it does not require the formation of strain in the film as in IGZO. Less strain in the film is expected to improve reliability. For example, by creating regions with carrier concentrations in the range R1 and range R2 shown in Figure 33A within the indium oxide film, a so-called n-i-n junction (a junction of an n-type region, an i-type region, and an n-type region) can be created. Valence electron control in silicon transistors is generally known. On the other hand, valence electron control in indium oxide transistors is a novel technological concept that would not normally be conceived.

[0299] By applying the above technical concept, the indium oxide transistor described herein has two or more, preferably three or more, more preferably four or more, and most preferably five of the following features (1) to (5): (1) High on-current (in other words, high mobility). (2) Low off-current. (3) Normally off is possible. (4) High reliability. (5) High cutoff frequency (fT). For example, the indium oxide transistor described herein has high mobility, low off-current, and is normally off. This transistor is different from a transistor that is high mobility and normally on.

[0300] In addition, the i-type nature of a semiconductor means that the Fermi level (Ef) and the intrinsic Fermi level (Ei) are the same (Ef = Ei). As shown in Figure 33B, in IGZO, the lower the carrier concentration, the lower the hole mobility. Therefore, when Ef = Ei is reached, there are no carriers left (in other words, the material has properties similar to an insulator), and it may cease to function as a transistor. On the other hand, in indium oxide, as shown in Figure 33A, the lower the carrier concentration, the higher the hole mobility, and when Ef = Ei is reached, the hole mobility is maximized. That is, transistors containing indium oxide can achieve high field-effect mobility by setting Ef = Ei. Furthermore, because transistors containing indium oxide have a low carrier concentration, they tend to be normally off. Therefore, transistors containing indium oxide can be normally off and achieve high field-effect mobility.

[0301] Normally off refers to the state in which no current flows through a transistor when no potential is applied to the gate or when the gate-source voltage is 0V. Normally off can be evaluated using the transistor's threshold voltage (Vth) or shift value (Vsh). Unless otherwise specified, Vth will be calculated using the constant current method. More specifically, Vth is the value of drain current (Id) × channel length (L) ÷ channel width (W) in the transistor's Id-Vg characteristic, where Vth is 1nA (1 × 10⁻¹⁰). −９ Let Vsh be the gate voltage (Vg) when A) is true. Also, Vsh is the tangent to the maximum slope when the drain current (Id) in the Id-Vg characteristic of the transistor is expressed logarithmically, and Id = 1pA (1 × 10⁻¹⁰). −１２ Vg is the gate voltage (Vg) at the intersection with line A), or the Vg at the intersection of the line extrapolated from the two points where the slope of Id is maximized when Id is expressed logarithmically in the transistor's Id-Vg characteristic, and the line where Id = 1 pA. For example, if either or both of Vth and Vsh are zero or positive values, it can be considered a normally-off transistor.

[0302] Furthermore, in transistors containing indium oxide, the film configuration in contact with the indium oxide film is crucial for making the semiconductor i-type, that is, for achieving Ef = Ei. For example, in transistors containing indium oxide, a film configuration can be obtained in which a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in contact with the indium oxide film. By using this film configuration, it is possible to create a semiconductor device that satisfies Ef = Ei and is highly reliable.

[0303] Furthermore, in the above film configuration, oxygen-containing films such as silicon oxide-nitride films, silicon oxide nitride films, aluminum oxide films, and gallium oxide films can be used instead of the silicon oxide film. Also, in the above film configuration, silicon oxide nitride films, silicon oxide nitride films, etc. can be used instead of the silicon nitride film. In addition, the hafnium oxide film located on the indium oxide side of the silicon nitride film functions as a hydrogen gettering site.

[0304] Furthermore, the above film configuration can also be viewed as a layered structure consisting of a film that can supply oxygen to the indium oxide film (e.g., a silicon oxide film), a film that can getter hydrogen (e.g., a hafnium oxide film), and a film that suppresses the intrusion of oxygen and hydrogen (e.g., a silicon nitride film). With this configuration, oxygen deficiencies in the indium oxide film are compensated for by oxygen in the silicon oxide film. Also, hydrogen in the indium oxide film is captured by the hafnium oxide film through heat treatment or other means. In addition, the silicon nitride film provides a film configuration that minimizes the intrusion of oxygen and hydrogen from the outside. In other words, by using the above film configuration, the indium oxide film can be made closer to type i. Therefore, transistors having the above-described indium oxide film have high field-effect mobility and high reliability.

[0305] Next, we will describe indium oxide films applied to transistors. Indium oxide films are preferably crystalline (i.e., they have crystal grains). Examples of films with crystal grains include single-crystal films, polycrystalline films, or amorphous films containing crystal grains (also called microcrystalline films). In particular, polycrystalline films are preferred for indium oxide films, and single-crystal films are more preferred. Single-crystal films do not have crystal grain boundaries. Impurities that inhibit carrier flow (typically insulating impurities, insulating oxides, etc.) tend to segregate at crystal grain boundaries. By using single-crystal films, carrier scattering at crystal grain boundaries can be suppressed, enabling the realization of transistors exhibiting high field-effect mobility. Furthermore, it has the excellent effect of suppressing variations in transistor characteristics caused by these crystal grain boundaries.

[0306] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using polycrystalline films, it is preferable to use films with the largest possible grain size and few grain boundaries. In a transistor to which a polycrystalline indium oxide film is applied, if there are no grain boundaries in the channel formation region, or if no grain boundaries are observed, the channel formation region is located within the single-crystal region contained in the polycrystalline film, and therefore it can be considered a transistor to which single-crystal indium oxide is applied.

[0307] The crystallinity of indium oxide can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0308] Furthermore, in this specification, a semiconductor layer in which no grain boundaries are observed in the channel-forming region, a semiconductor layer in which the channel-forming region is contained within a single crystal grain, or a semiconductor layer in which the direction of the crystal axes is the same in at least two regions within the channel-forming region can be called a single crystal film. In addition, a semiconductor layer in which, within a single crystal grain in the channel-forming region, the direction of other crystal axes changes continuously with respect to a certain crystal axis or crystal orientation as the axis of rotation can be called a single crystal film.

[0309] The channel formation region refers to the area within the semiconductor layer that overlaps with (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, grain boundaries, crystal axes, and crystal orientation in the channel formation region can be confirmed by cross-sectional observation including the semiconductor layer, source electrode, and drain electrode.

[0310] The indium oxide film in the channel-forming region is preferable to have a low impurity concentration. Impurities in the indium oxide film in the channel-forming region can act as a scattering source for carriers, and thus can cause a decrease in field-effect mobility. Furthermore, these impurities can also inhibit crystal growth in the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The concentration of these impurities in the indium oxide film is preferably 0.1% or less, and more preferably 0.01% (100 ppm) or less. Note that elements such as carbon and hydrogen may be present in the deposition gas or precursor during film formation, and may remain in the indium oxide film in higher concentrations than the impurities mentioned above.

[0311] Furthermore, the indium oxide film in the channel-forming region may contain elements that can become trivalent cations like indium, as long as their crystals maintain a cubic crystal structure (Bixbite type). Examples include Group 13 elements of the periodic table such as gallium and aluminum, and Group 3 elements of the periodic table. Since these elements mainly exist as trivalent cations in the oxide, the carrier concentration of indium oxide can be kept low.

[0312] Furthermore, the indium oxide film described herein has a high film density. The theoretical value of the film density of the indium oxide film is 7.18 g / cm³. ３ In this specification, the range of film density for indium oxide films is 6.70 g / cm³. ３ 7.18g / cm or more ３ The following, preferably 6.90 g / cm³ ３ 7.18g / cm or more ３ The following, and more preferably 7.00 g / cm³ ３ 7.18g / cm or more ３ The following applies:

[0313] Furthermore, film density can be evaluated using methods such as Rutherford backscattering (RBS) or X-ray reflectivity (XRR). Differences in film density can sometimes be evaluated using transmission electron microscopy (TEM) images of the cross-section. In TEM observation, a high film density results in a darker (more intense) transmission electron (TE) image, while a low film density results in a fainter (brighter) transmission electron (TE) image.

[0314] By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be increased to 50 cm². ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ It can be set to (V・s) or more.

[0315] One of the characteristics of indium oxide films is that they have higher oxygen permeability (diffusivity) compared to IGZO films. As shown in Figure 33C, indium oxide films (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and oxygen molecules (O) ２ It is released as water molecules (H) by reacting with hydrogen contained in the membrane. ２ It may also be released as O. Furthermore, oxygen deficiencies (V) can form in the membrane. ＯIf oxygen atoms are present, diffusing oxygen atoms will fill the oxygen deficiency. Indium oxide films allow oxygen to diffuse easily, so they can be said to fill oxygen deficiencies more easily than IGZO films.

[0316] Thus, because indium oxide films are more likely to reduce oxygen vacancies in the film compared to IGZO films, applying such indium oxide films to transistors makes it possible to realize transistors with extremely high reliability.

[0317] Furthermore, as shown in Figure 33C, the indium oxide film diffuses hydrogen. Hydrogen diffusing into the indium oxide film from the outside permeates the film and forms hydrogen molecules (H ２ It is released as ) or by reacting with oxygen contained in the film, and released as water molecules. The above-mentioned oxygen and hydrogen diffuse through the indium oxide film by heat treatment. The temperature of the heat treatment is 200°C to 700°C, preferably 350°C to 650°C, and more preferably 400°C to 500°C.

[0318] Transistors using indium oxide films are storage-type transistors that use electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, in a transistor, the on-current or field-effect mobility of the transistor can be increased.

[0319] Table 1 shows single crystal indium oxide (here, In ２ O ３The effective masses of indium oxide and single-crystal silicon (Si) are shown below. As shown in Table 1, indium oxide is characterized by a small effective electron mass and a large effective hole mass. Furthermore, the effective electron mass of indium oxide is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in transistors, transistors with high field-effect mobility and high frequency characteristics (also called f-characteristics) can be realized. In addition, because the effective hole mass is large, transistors with extremely low off-currents can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width is 1 fA (1 × 10⁻¹⁶) in an environment of 125°C. −１５ A) Less than or equal to, or 1aA (1 × 10 −１８ A) Less than or equal to 1aA (1 × 10) in a room temperature (25°C) environment. −１８ A) Less than or equal to, or 1zA (1 × 10⁻¹⁰ −２１ A) The following is possible. Also, as shown in Table 1, indium oxide has a smaller effective electron mass and a larger effective hole mass than silicon, so it may be possible to realize a transistor with higher field-effect mobility and lower off-current than a Si transistor.

[0320]

[0321] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. It is preferable to use a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with the indium oxide for the seed layer. This improves the crystallinity of the indium oxide film. A substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0322] One method for evaluating the degree of lattice mismatch is to use the following lattice mismatch value. The lattice mismatch Δa [%] of the crystals in the formed film (in this case, the indium oxide film) relative to the crystals in the seed layer is given by Δa = ((L １ -L ２ ) / L ２ It is calculated as ) × 100. Here L１ L is the length of the unit cell vector of the crystals in the formed film, or the lattice constant. ２ This is the length of the unit cell vector of the crystal in the seed layer, or the lattice constant.

[0323] The lattice mismatch Δa between the seed layer and the indium oxide film is preferably small in absolute value, and most preferably zero. For example, Δa can be -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less.

[0324] Here, the indium oxide crystal has a cubic structure (bixbite type). For example, yttria-stabilized zirconia (YSZ) crystals can have a cubic structure (fluorite type). The lattice mismatch of the indium oxide crystal with respect to the cubic YSZ crystal is in the range of -2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on a YSZ substrate.

[0325] Furthermore, the crystal structure of the seed layer and the crystal structure of the indium oxide film do not necessarily have to be the same in terms of crystal system or crystal orientation. For example, a film with a hexagonal or trigonal crystal structure can be used beneath an indium oxide film with a cubic crystal structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to crystal orientation necessary for epitaxial growth can be met. Examples of hexagonal or trigonal crystals include wurtzite-type structures and YbFe. ２ O ４ Type structure, Yb ２ Fe ３ O ７ These include type structures and their modified type structures. YbFe ２ O ４ Type structure or Yb ２ Fe ３ O ７An example of a crystal with a crystalline structure is IGZO. Indium oxide single crystal films can be formed not only on YSZ substrates but also on insulating films. On the other hand, it is difficult to form silicon single crystal films on insulating films. Silicon crystals have a diamond structure. Thus, in terms of single crystals, indium oxide and silicon have similar properties. However, when comparing indium oxide and silicon from the perspective of whether single crystals can be formed on insulating films, they have different properties.

[0326] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0327] (Embodiment 3) This embodiment describes an electronic device according to one aspect of the present invention.

[0328] The electronic device of this embodiment has a display device according to one aspect of the present invention in its display unit. The display device according to one aspect of the present invention is easily made high-definition and high-resolution. Therefore, it can be used in the display units of various electronic devices.

[0329] Examples of electronic devices include television sets, desktop or notebook computers, computer monitors, digital signage, large game machines such as pachinko machines, and other electronic devices with relatively large screens, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, personal digital assistants, and audio playback devices.

[0330] In particular, a display device according to one aspect of the present invention can be used suitably in electronic devices having a relatively small display area because it can increase the resolution. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), as well as wearable devices that can be worn on the head, such as VR devices such as head-mounted displays, AR devices such as glasses, and MR devices.

[0331] A display device according to one aspect of the present invention preferably has an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels). In particular, a resolution of 4K, 8K, or higher is preferred. Furthermore, the pixel density (resolution) of the display device according to one aspect of the present invention is preferably 100 ppi or more, preferably 300 ppi or more, more preferably 500 ppi or more, more preferably 1000 ppi or more, more preferably 2000 ppi or more, more preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 7000 ppi or more. By using a display device having either high resolution or high detail, or both, it becomes possible to further enhance the sense of presence and depth. Furthermore, there are no particular limitations on the aspect ratio of the display device according to one embodiment of the present invention. For example, the display device can support various aspect ratios such as 1:1 (square), 4:3, 16:9, and 16:10.

[0332] The electronic device of this embodiment may also be configured to include sensors (including functions for detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation).

[0333] The electronic device of this embodiment can have a variety of functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, a function to execute various software (programs), a wireless communication function, a function to read programs or data recorded on a recording medium, and so on.

[0334] Figures 34A to 34D illustrate an example of a wearable device that can be worn on the head. These wearable devices have at least one of the following functions: a function to display AR content, a function to display VR content, a function to display SR content, and a function to display MR content. By having an electronic device that has the function to display at least one of the following content types, such as AR, VR, SR, and MR, it is possible to enhance the user's sense of immersion.

[0335] The electronic device 8700A shown in Figure 34A and the electronic device 8700B shown in Figure 34B each include a pair of display panels 8751, a pair of housings 8721, a communication unit (not shown), a pair of mounting units 8723, a control unit (not shown), an imaging unit (not shown), a pair of optical members 8753, a frame 8757, and a pair of nose pads 8758. Note that the display panel 8751 is omitted in Figure 34B.

[0336] A display device according to one embodiment of the present invention can be applied to the display panel 8751. Therefore, an electronic device capable of displaying extremely high resolution can be made. Furthermore, an electronic device that is low power consumption and high functionality can be made. For example, electronic devices 8700A and 8700B can be electronic devices that have an eye-tracking function.

[0337] Electronic devices 8700A and 8700B can each project an image displayed on a display panel 8751 onto the display area 8756 of an optical element 8753. Because the optical element 8753 is translucent, the user can see the image displayed on the display area superimposed on the transmitted image visible through the optical element 8753. Therefore, electronic devices 8700A and 8700B are electronic devices capable of AR display.

[0338] Electronic devices 8700A and 8700B can be equipped with cameras capable of capturing images of the area in front of them as imaging units. Furthermore, electronic devices 8700A and 8700B can each be equipped with acceleration sensors such as gyro sensors to detect the orientation of the user's head and display an image corresponding to that orientation in the display area 8756.

[0339] The communications unit has a wireless communication device, which can supply video signals and the like. Alternatively, instead of the wireless communication device, or in addition to the wireless communication device, a connector may be provided to which a cable supplying video signals and power potential can be connected.

[0340] Electronic devices 8700A and 8700B are equipped with batteries (not shown) that can be charged wirelessly, wired, or both.

[0341] A touch sensor module can be installed in the housing 8721. The touch sensor module has the function of detecting when the outer surface of the housing 8721 is touched. The touch sensor module can detect the user's tap or slide operations and execute various processes. For example, a tap operation can be used to pause or resume the video, and a slide operation can be used to fast forward or rewind. Furthermore, by installing a touch sensor module in each of the two housings 8721, the range of operations can be expanded.

[0342] Various types of touch sensors can be applied to the touch sensor module. For example, various methods such as capacitive, resistive, infrared, electromagnetic induction, surface acoustic wave, and optical sensors can be used. In particular, it is preferable to apply a capacitive or optical sensor to the touch sensor module.

[0343] When using an optical touch sensor, a photoelectric conversion device (also called a photoelectric conversion element) can be used as the light-receiving device. The active layer of the photoelectric conversion device can be made of either an inorganic semiconductor or an organic semiconductor, or both.

[0344] The electronic device 8800A shown in Figure 34C and the electronic device 8800B shown in Figure 34D each include a pair of display units 8820, a housing 8821, a communication unit 8822, a pair of mounting units 8823, a control unit 8824, a pair of imaging units 8825, and a pair of lenses 8832. Note that the display unit 8820, communication unit 8822, and imaging unit 8825 are omitted in Figure 34D.

[0345] A display device according to one aspect of the present invention can be applied to the display unit 8820. Therefore, an electronic device capable of displaying extremely high resolution can be created. This allows the user to experience a high level of immersion. Furthermore, by applying a display device according to one aspect of the present invention to the display unit 8820, an electronic device with low power consumption and high functionality can be created. For example, electronic devices 8800A and 8800B can be electronic devices that have an eye-tracking function.

[0346] The display unit 8820 is located inside the housing 8821 in a position where it can be seen through the lens 8832. Furthermore, by displaying different images on a pair of display units 8820, a three-dimensional display using parallax can also be performed.

[0347] Electronic devices 8800A and 8800B can each be described as electronic devices for VR. A user wearing electronic device 8800A or electronic device 8800B can view the image displayed on the display unit 8820 through the lens 8832.

[0348] It is preferable that electronic devices 8800A and 8800B each have a mechanism that allows adjustment of the left and right positions of the lens 8832 and the display unit 8820 so that they are in the optimal position according to the user's eye position. It is also preferable that they have a mechanism that adjusts the focus by changing the distance between the lens 8832 and the display unit 8820.

[0349] The attachment portion 8823 allows the user to attach the electronic device 8800A or 8800B to their head. While Figure 34C and other figures illustrate it as having a shape similar to the temples of eyeglasses, it is not limited to this. The attachment portion 8823 only needs to be wearable by the user; for example, it can be in the shape of a helmet or a band.

[0350] The imaging unit 8825 has the function of acquiring external information. The data acquired by the imaging unit 8825 can be output to the display unit 8820. An image sensor can be used in the imaging unit 8825. In addition, multiple cameras can be provided to support multiple angles of view, such as telephoto and wide-angle.

[0351] Although an example with an imaging unit 8825 is shown here, the imaging unit 8825 is not necessary if a distance measuring sensor (hereinafter also referred to as a detection unit) capable of measuring the distance to an object is provided. In other words, the imaging unit 8825 is one form of the detection unit. As the detection unit, for example, an image sensor or a distance image sensor such as LiDAR (Light Detection and Ranging) can be used. By using the image obtained by the camera and the image obtained by the distance image sensor, more information can be acquired, enabling more accurate gesture control.

[0352] The electronic device 8800A may also have a vibration mechanism that functions as bone conduction earphones. For example, the vibration mechanism can be applied to one or more of the display unit 8820, the housing 8821, and the mounting unit 8823. This eliminates the need for separate audio equipment such as headphones, earphones, or speakers, allowing users to enjoy video and audio simply by wearing the electronic device 8800A.

[0353] Electronic devices 8800A and 8800B may each have input terminals. Cables can be connected to the input terminals to supply video signals from video output devices, etc., and power for charging batteries provided within the electronic devices.

[0354] An electronic device according to one aspect of the present invention may also have a function for wireless communication with an earphone 8750. The earphone 8750 has a communication unit (not shown) and has a wireless communication function. The earphone 8750 can receive information (e.g., voice data) from the electronic device through its wireless communication function. For example, the electronic device 8700A shown in Figure 34A has a function for transmitting information to the earphone 8750 through its wireless communication function. Also, for example, the electronic device 8800A shown in Figure 34C has a function for transmitting information to the earphone 8750 through its wireless communication function.

[0355] The electronic device can be configured to include an earphone section. The electronic device 8700B shown in Figure 34B has an earphone section 8727. For example, the earphone section 8727 and the control unit can be connected to each other by a wire. Part of the wiring connecting the earphone section 8727 and the control unit may be located inside the housing 8721 or the mounting section 8723.

[0356] Similarly, the electronic device 8800B shown in Figure 34D has an earphone unit 8827. For example, the earphone unit 8827 and the control unit 8824 can be connected to each other by a wire. Part of the wiring connecting the earphone unit 8827 and the control unit 8824 may be located inside the housing 8821 or the mounting unit 8823. Also, the earphone unit 8827 and the mounting unit 8823 may have magnets. This allows the earphone unit 8827 to be fixed to the mounting unit 8823 by magnetic force, which is preferable as it facilitates storage.

[0357] Furthermore, the electronic device may have an audio output terminal to which earphones or headphones can be connected. The electronic device may also have an audio input terminal and / or an audio input mechanism. For example, a sound-collecting device such as a microphone can be used as the audio input mechanism. By having an audio input mechanism, the electronic device may be given the function of a so-called headset.

[0358] Thus, in one aspect of the present invention, the electronic device is preferably of the glasses type (electronic device 8700A, electronic device 8700B, etc.) or the goggle type (electronic device 8800A, electronic device 8800B, etc.).

[0359] An electronic device according to one aspect of the present invention can transmit information to earphones by wire or wireless means.

[0360] The electronic device 6500 shown in Figure 35A is a portable information terminal that can be used as a smartphone.

[0361] The electronic device 6500 includes a housing 6501, a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, and a light source 6508. The display unit 6502 has a touch panel function.

[0362] A display device according to one embodiment of the present invention can be applied to the display unit 6502. This makes the electronic device 6500 a low-power and high-performance electronic device. For example, the display unit 6502 can function as a touch panel. Furthermore, the display unit 6502 can function as a fingerprint sensor.

[0363] Figure 35B is a schematic cross-sectional view of the housing 6501 including the end on the microphone 6506 side.

[0364] A light-transmitting protective member 6510 is provided on the display side of the housing 6501, and the display panel 6511, optical member 6512, touch sensor panel 6513, printed circuit board 6517, battery 6518, etc. are arranged in the space enclosed by the housing 6501 and the protective member 6510.

[0365] The protective member 6510 is fixed to the display panel 6511, the optical member 6512, and the touch sensor panel 6513 by an adhesive layer (not shown).

[0366] In the area outside the display unit 6502, a portion of the display panel 6511 is folded back, and the FPC 6515 is connected to this folded portion. IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to terminals provided on the printed circuit board 6517.

[0367] A display device according to one embodiment of the present invention can be applied to the display panel 6511. In particular, by using a resin film for the substrate of the display panel 6511, an extremely lightweight electronic device can be realized. Furthermore, because the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted while keeping the thickness of the electronic device low. In addition, by folding back a part of the display panel 6511 and placing the connection part with the FPC 6515 on the back of the pixel section, an electronic device with a narrow bezel can be realized.

[0368] Figure 35C shows an example of a television system. The television system 7100 has a display unit 7000 incorporated into a housing 7101. Here, the housing 7101 is shown to be supported by a stand 7103.

[0369] A display device according to one embodiment of the present invention can be applied to the display unit 7000. This makes the television device 7100 a low-power, high-performance electronic device. For example, the display unit 7000 can function as a touch panel.

[0370] The television device 7100 shown in Figure 35C can be operated using the operation switches on the housing 7101 and a separate remote control unit 7111. Alternatively, the display unit 7000 may be equipped with a touch sensor, and the television device 7100 can be operated by touching the display unit 7000 with a finger or the like. The remote control unit 7111 may have a display unit that displays information output from the remote control unit 7111. Channels and volume can be controlled and the image displayed on the display unit 7000 can be controlled using the operation keys or touch panel on the remote control unit 7111.

[0371] The television system 7100 is configured to include a receiver and a modem, etc. The receiver can receive general television broadcasts. Furthermore, by connecting to a wired or wireless communication network via the modem, it is possible to perform one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.

[0372] Figure 35D shows an example of a notebook computer. The computer 7200 has a casing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, etc. A display unit 7000 is incorporated into the casing 7211.

[0373] A display device according to one embodiment of the present invention can be applied to the display unit 7000. This makes the computer 7200 a low-power, high-performance electronic device. For example, the display unit 7000 can function as a touch panel.

[0374] Figures 35E and 35F show examples of digital signage.

[0375] The digital signage 7300 shown in Figure 35E includes a housing 7301, a display unit 7000, and a speaker 7303, etc. Furthermore, it may include LED lamps, operation keys (including a power switch or operation switch), connection terminals, various sensors, a microphone, etc.

[0376] Figure 35F shows a digital signage 7400 mounted on a cylindrical column 7401. The digital signage 7400 has a display unit 7000 that is provided along the curved surface of the column 7401.

[0377] In Figures 35E and 35F, a display device according to one embodiment of the present invention can be applied to the display unit 7000. This makes the digital signage 7300 and digital signage 7400 low-power and high-performance electronic devices. For example, the display unit 7000 can function as a touch panel.

[0378] The larger the display area 7000, the more information can be provided at once. Furthermore, a larger display area 7000 is more eye-catching, which can, for example, enhance the effectiveness of advertising.

[0379] Applying a touch panel to the display unit 7000 is preferable because it not only displays images or videos on the display unit 7000, but also allows users to operate it intuitively. Furthermore, when used for purposes such as providing route information or traffic information, intuitive operation can enhance usability.

[0380] As shown in Figures 35E and 35F, it is preferable that the digital signage 7300 or digital signage 7400 can be linked wirelessly with an information terminal 7311 or information terminal 7411 such as a smartphone owned by the user. For example, the advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or information terminal 7411. In addition, the display on the display unit 7000 can be switched by operating the information terminal 7311 or information terminal 7411.

[0381] The digital signage 7300 or digital signage 7400 can also be used to run games using the screen of the information terminal 7311 or information terminal 7411 as the control device (controller). This allows an unspecified number of users to participate in and enjoy the game simultaneously.

[0382] The electronic device shown in Figures 36A to 36G includes a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or operation switch), connection terminals 9006, a sensor 9007 (including a function to detect, detect, or measure force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation), a microphone 9008, and the like.

[0383] In Figures 36A to 36G, a display device according to one embodiment of the present invention can be applied to the display unit 9001. This makes the electronic device having the display unit 9001 a low-power and high-function electronic device. For example, the display unit 9001 can function as a touch panel. Furthermore, the display unit 9001 can function as a fingerprint sensor.

[0384] The electronic devices shown in Figures 36A to 36G have various functions. For example, they may have functions to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date or time, a function to control processing by various software (programs), a wireless communication function, a function to read and process programs or data recorded on a recording medium, etc. However, the functions of electronic devices are not limited to these and can have various functions. Electronic devices may have multiple display units. Furthermore, electronic devices may be equipped with a camera, etc., and have functions to capture still images or videos and save them on a recording medium (external or built into the camera), a function to display the captured images on a display unit, etc.

[0385] Details of the electronic equipment shown in Figures 36A to 36G will be explained below.

[0386] Figure 36A is a perspective view showing a personal digital information terminal (PDI) 9101. The PDI 9101 can be used, for example, as a smartphone. The PDI 9101 may also be equipped with a speaker 9003, connection terminals 9006, sensors 9007, etc. The PDI 9101 can also display text and image information on multiple surfaces. Figure 36A shows an example where three icons 9050 are displayed. Information 9051, indicated by a dashed rectangle, can also be displayed on other surfaces of the display unit 9001. Examples of information 9051 include notifications of incoming emails, SNS messages, phone calls, etc., the title of emails or SNS messages, sender name, date and time, time, battery level, and signal strength. Alternatively, icons 9050, etc., may be displayed in the position where the information 9051 is displayed.

[0387] Figure 36B is a perspective view showing the personal digital assistant (PDA) 9102. The PDA 9102 has the function of displaying information on three or more sides of the display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different sides. For example, a user can check information 9053, which is displayed in a position that can be observed from above the PDA 9102, while the PDA 9102 is stored in the breast pocket of their clothing. The user can check the display without taking the PDA 9102 out of their pocket and decide, for example, whether or not to answer a call.

[0388] Figure 36C is a perspective view showing the tablet terminal 9103. The tablet terminal 9103 can run various applications, such as mobile phone calls, email, document viewing and creation, music playback, internet communication, and computer games. The tablet terminal 9103 has a display unit 9001, a camera 9002, a microphone 9008, and a speaker 9003 on the front of the housing 9000, operation keys 9005 as buttons for operation on the side of the housing 9000, and connection terminals 9006 on the bottom.

[0389] Figure 36D is a perspective view showing a wristwatch-type personal information terminal 9200. The personal information terminal 9200 can be used, for example, as a smartwatch (registered trademark). The display unit 9001 has a curved display surface, allowing it to display information along the curved surface. The personal information terminal 9200 can also make hands-free calls by communicating with, for example, a wireless communication headset. Furthermore, the personal information terminal 9200 can transmit data to other information terminals and be charged via a connection terminal 9006. The charging operation can be configured to be performed by wireless power supply.

[0390] Figures 36E to 36G are perspective views showing a foldable portable information terminal 9201. Figure 36E shows the portable information terminal 9201 in an unfolded state, Figure 36G shows it in a folded state, and Figure 36F shows a perspective view of the state in between, transitioning from one of Figures 36E or 36G to the other. The portable information terminal 9201 offers excellent portability in its folded state and excellent readability of the display due to its seamless, wide display area in its unfolded state. The display unit 9001 of the portable information terminal 9201 is supported by three housings 9000 connected by hinges 9055. For example, the display unit 9001 can be bent with a radius of curvature of 0.1 mm to 150 mm.

[0391] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0392] 10: Display device, 10A: Display device, 11: Substrate, 12: Substrate, 13: Photoelectric conversion region, 13a: Photoelectric conversion region, 13b: Photoelectric conversion region, 14: Semiconductor region, 15: Semiconductor region, 16: Semiconductor region, 20: Layer, 21[1,1]: Pixel, 21[1,2]: Pixel, 21[2,1]: Pixel, 21[2,2]: Pixel, 21[3,1]: Pixel, 21[3,2]: Pixel, 21[4,1]: Pixel, 21[4,2]: Pixel, 21: Pixel, 22: Sub-pixel, 22B: Sub-pixel, 22G: Sub-pixel, 22R: Sub-pixel, 23: Pixel electrode, 23B: Pixel electrode, 23B[1,1]: Pixel electrode Pixel electrode, 23B[1,2]: pixel electrode, 23B[2,1]: pixel electrode, 23B[3,1]: pixel electrode, 23B[3,2]: pixel electrode, 23B[4,1]: pixel electrode, 23B[4,2]: pixel electrode, 23G: pixel electrode, 23G[1,1]: pixel electrode, 23G[1,2]: pixel electrode, 23G[2,1]: pixel electrode, 23G[3,1]: pixel electrode, 23G[3,2]: pixel electrode, 23G[4,1]: pixel electrode, 23G[4,2]: pixel electrode, 23R: pixel electrode, 23R[1,1]: pixel electrode, 23R[1,2]: pixel electrode, 23R[2,1]: pixel electrode, 23R[ 2,2]: Pixel electrode, 23R[3,1]: Pixel electrode, 23R[3,2]: Pixel electrode, 23R[4,1]: Pixel electrode, 23R[4,2]: Pixel electrode, 25: Pixel, 25A: Pixel, 26: Pixel circuit, 27: Pixel circuit, 31a: Channel formation region, 31b: Channel formation region, 33: Low resistance region, 33a: Low resistance region, 33b: Low resistance region, 35: Conductive layer, 37: Insulating layer, 39: Insulating layer, 40: Layer, 41: Layer, 50: Layer, 60: Layer, 172: EL layer, 173: Common electrode, 174: Common layer, 200: Transistor, 203: Element isolation layer, 211: Insulating layer, 212 : insulating layer, 213: insulating layer, 214: insulating layer, 231: conductive layer, 231a: conductive layer, 231b: conductive layer, 232a: conductive layer, 232b: conductive layer, 233: conductive layer, 233a: conductive layer, 233b: conductive layer, 234: conductive layer, 234_1: conductive layer, 234_10: conductive layer, 234_2: conductive layer, 234_3: conductive layer, 234_4: conductive layer, 234_5: conductive layer, 234_6: conductive layer, 234_7: conductive layer, 234_8: conductive layer, 234_9: conductive layer, 235: conductive layer, 235_1: conductive layer, 235_2: conductive layer, 235_3: conductive layer, 235_4: conductive layer,235_5: Conductive layer, 235_6: Conductive layer, 235_7: Conductive layer, 235_8: Conductive layer, 235_9: Conductive layer, 236: Conductive layer, 236_1: Conductive layer, 236_2: Conductive layer, 237: Conductive layer, 251: Semiconductor layer, 251a: Semiconductor layer, 251b: Semiconductor layer, 252: Insulating layer, 253: Insulating layer, 254: Insulating layer, 255: Insulating layer, 256: Conductive layer, 256_1: Conductive layer, 256_2: Conductive layer, 256_3: Conductive layer, 256_4: Conductive layer, 256_5: Conductive layer, 256_6: Conductive layer, 256_7: Conductive layer, 257: Conductive layer, 257_1: Conductive layer, 257_2: Conductive layer, 257_3: Conductive layer, 257_4: Conductive layer, 257_5: Conductive layer, 257_6: Conductive layer, 257_7: Conductive layer, 258: Adhesive layer, 259_1: Conductive layer, 259_2: Conductive layer, 259_3: Conductive layer, 259_4: Conductive layer, 261: Insulating layer, 262: Insulating layer, 263: Insulating layer, 264: Insulating layer, 265: Conductive layer, 265a: Conductive layer, 266: Conductive layer, 267: Conductive layer, 267_1: Conductive layer, 267_10: Conductive layer, 267_11: Conductive layer, 267_12: Conductive layer, 267_2: Conductive layer, 267_3: Conductive layer, 267_4: Conductive layer, 267_5: Conductive layer, 267_6: Conductive layer, 267_7: Conductive layer, 267_8: Conductive layer, 267_9: Conductive layer, 268: Conductive layer, 270: Insulating layer, 271: Insulating layer, 271a: Low resistance region, 271b: Low resistance region, 273: Protective layer, 278: Insulating layer, 281: Insulating layer, 282: Insulating layer, 283: Insulating layer, 284: Insulating layer, 285: Insulating layer, 286: Insulating layer, 700: Transistor, 701: Insulating layer, 720: Semiconductor layer, 750: Insulating layer, 755: Conductive layer, 756: Insulating layer, 757: Insulating layer, 758: Insulating layer, 759: Insulating layer, 761: Conductive layer, 762: Opening, 765: Conductive layer, 785: Insulating layer, 6500: Electronic equipment, 6501: Housing, 6502: Display unit, 6503: Power button, 6504: Button, 6505: Speaker, 6506: Microphone, 6507: Camera, 6508: Light source, 6510: Protective component, 6511: Display panel, 6512: Optical component, 6513: Touch sensor panel, 6515: FPC, 6516: IC, 6517: Printed circuit board, 6518: Battery, 7000: Display unit, 7100: Television equipment, 7101: Housing, 7103: Stand, 7111: Remote control unit, 7200: Computer, 7211: Housing,7212: Keyboard, 7213: Pointing device, 7214: External connection port, 7300: Digital signage, 7301: Enclosure, 7303: Speaker, 7311: Information terminal, 7400: Digital signage, 7401: Pillar, 7411: Information terminal, 8700A: Electronic equipment, 8700B: Electronic equipment, 8721: Enclosure, 8723: Mounting part, 8727: Earphone part, 8750: Earphone, 8751: Display panel, 8753: Optical component, 8756: Display area, 8757: Frame, 8758: Nose pad, 8800A: Electronic equipment, 8800B: Electronic equipment, 8820: Display unit, 8821: Housing, 8822: Communication unit, 8823: Mounting unit, 8824: Control unit, 8825: Imaging unit, 8827: Earphone unit, 8832: Lens, 9000: Housing, 9001: Display unit, 9002: Camera, 9003: Speaker, 9005: Operation key, 9006: Connection terminal, 9007: Sensor, 9008: Microphone, 9050: Icon, 9051: Information, 9052: Information, 9053: Information, 9054: Information, 9055: Hinge, 9101: Personal Information Terminal, 9102: Personal Information Terminal, 9103: Tablet terminal, 9200: Personal Information Terminal, 9201: Personal Information Terminal,

Claims

1. A display device comprising a silicon substrate, a first pixel electrode, a second pixel electrode, a third pixel electrode, and a fourth pixel electrode, wherein the silicon substrate has a photoelectric conversion region, the first to fourth pixel electrodes are provided on the silicon substrate, the second pixel electrode is adjacent to the first pixel electrode in a first direction, the third pixel electrode is adjacent to the first pixel electrode in a second direction, the fourth pixel electrode is adjacent to the second pixel electrode in a second direction and adjacent to the third pixel electrode in a first direction, the second direction is perpendicular or substantially perpendicular to the first direction in a plan view, and at least a portion of the photoelectric conversion region is provided in a region surrounded by the first to fourth pixel electrodes in a plan view.

2. The display device according to claim 1, wherein the photoelectric conversion region has, in a plan view, a region located between the first pixel electrode and the second pixel electrode, and a region located between the third pixel electrode and the fourth pixel electrode.

3. The display device according to claim 2, wherein the photoelectric conversion region has a region located between the second pixel electrode and the fourth pixel electrode in a plan view.

4. A display device according to any one of claims 1 to 3, comprising: an imaging pixel; a display pixel; a first transistor; a second transistor; the imaging pixel comprising a photoelectric conversion region; a third transistor; the display pixel comprising a first pixel electrode; a fourth transistor; a fifth transistor; the first transistor and the second transistor having channel formation regions in the silicon substrate; the third transistor provided above the first transistor; the third transistor electrically connected to the first transistor; the fourth transistor provided above the third transistor; the fourth transistor electrically connected to the second transistor; the fifth transistor provided on the same surface to be formed as the fourth transistor; and the source electrode or drain electrode of the fifth transistor electrically connected to the first pixel electrode.

5. The display device according to claim 4, wherein the photoelectric conversion region has a region that does not overlap with any of the first to fourth pixel electrodes or the first to fifth transistors.

6. The display device according to claim 4, wherein the third to fifth transistors have a metal oxide in the channel forming region.

7. The device comprises a silicon substrate, a first photodiode, a second photodiode, a first transistor, a second transistor, a first pixel electrode, a second pixel electrode, a third pixel electrode, a fourth pixel electrode, a fifth pixel electrode, a sixth pixel electrode, a seventh pixel electrode, and an eighth pixel electrode, wherein the first photodiode has a first low-resistance region, the second photodiode has a second low-resistance region, the first transistor has a first low-resistance region and a third low-resistance region, the second transistor has a second low-resistance region and a third low-resistance region, the first low-resistance region functions as the photoelectric conversion region of the first photodiode and as one of the source region and drain region of the first transistor, the second low-resistance region functions as the photoelectric conversion region of the second photodiode and as one of the source region and drain region of the second transistor, The third low-resistance region functions as the other of the source region and drain region of the first transistor, and the other of the source region and drain region of the second transistor, the first to eighth pixel electrodes are provided on the silicon substrate, the second pixel electrode is adjacent to the first pixel electrode in a first direction, the third pixel electrode is adjacent to the first pixel electrode in a second direction, the fourth pixel electrode is adjacent to the second pixel electrode in a second direction and adjacent to the third pixel electrode in a first direction, the fifth pixel electrode is adjacent to the third pixel electrode in a second direction, the sixth pixel electrode is adjacent to the fourth pixel electrode in a second direction and adjacent to the fifth pixel electrode in a first direction, the seventh pixel electrode is adjacent to the fifth pixel electrode in a second direction, The eighth pixel electrode is adjacent to the sixth pixel electrode in the second direction and adjacent to the seventh pixel electrode in the first direction, and the first transistor and the second transistor are provided in a region surrounded by the third to sixth pixel electrodes in a plan view.A display device wherein the first low-resistance region has, in a plan view, a region located between the first pixel electrode and the second pixel electrode, and a region located between the third pixel electrode and the fourth pixel electrode, and the second low-resistance region has, in a plan view, a region located between the fifth pixel electrode and the sixth pixel electrode, and a region located between the seventh pixel electrode and the eighth pixel electrode.

8. The display device according to claim 7, comprising a first imaging pixel and a second imaging pixel, wherein the first imaging pixel comprises a first photodiode, a first transistor, and a third transistor, and the second imaging pixel comprises a second photodiode, a second transistor, and a third transistor, wherein the third transistor has a region located between the third pixel electrode and the fifth pixel electrode in a plan view.

9. The display device according to claim 7 or claim 8, wherein the first low-resistance region has a region located between the second pixel electrode and the fourth pixel electrode in a plan view, and the second low-resistance region has a region located between the sixth pixel electrode and the eighth pixel electrode in a plan view.

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