Ultra high-density non-volatile memory

Abstract

A non-volatile memory (NVM) (100, 200) based on memristors is disclosed. The NVM comprises a substrate (102), a processing unit (104) coupled to the substrate (102) for generating control signals for memory operations, an interconnect fabric (202) comprising insulating layers (204-1, 204-2) and conductive layers (206-1, 206-2), a first conductive layer (208-1-1) patterned to form bit lines, a layer of molecular material (1) disposed on the bit lines, and a second conductive layer (210-1-1) patterned to form word lines oriented perpendicular to the bit lines forming a crossbar array. A memristor is formed at each intersection, comprising molecular material sandwiched between a respective bit line and word line, wherein each memristor stores multiple bits of data.

Description

ULTRA HIGH-DENSITY NON-VOLATILE MEMORYTECHNICAL FIELD

[0001] The present subject matter, in general, relates to non-volatile memories, and in particular, relates to ultra high-density non-volatile memories using molecular materials.BACKGROUND OF SUBJECT MATTER

[0002] Non-volatile memory (NVM) is an essential component of modern-day electronic systems for retaining stored information even after power is removed. NVMs are predominantly based on NAND flash technology which is widely used in electronic devices for data storage. Typically, NVMs comprise an array of memory cells, each containing a floating-gate transistor wherein data is stored by trapping electrons in a floating gate which alters a threshold voltage of the floating-gate transistor. The threshold voltage determines the minimum voltage required to turn on the floating-gate transistor and enable current flow through the memory cell. To read data from the NVM, a low voltage is applied to the memory cell. If the threshold voltage has been altered by stored charge, current may or may not flow through the memory cell. The resulting current flow is measured to determine the stored data state. Similarly, to write data into the NVM, a high voltage is applied to the control gate. This forces electrons into the floating gate, changing the threshold voltage. The changed threshold voltage represents the programmed data state of the memory cell.

[0003] As may be understood, NVMs are generally resistant to physical shocks as compared to traditional memories such as hard disk drives (HDDs), magnetic tape storage, optical disc drives (CDs, DVDs, Blu-ray), floppy disks, and dynamic random-access memory (DRAM), and may offer high speed processing for reading and writing operations. Due to such advantages, NVMs are ubiquitous in modem technologyapplications and may be commonly found in smartphones, tablets, solid-state drives (SSDs), USB drives and memory cards, and as embedded flash memory systems in various consumer electronics.BRIEF DESCRIPTION OF FIGURES

[0004] Systems and / or methods in accordance with examples of the present subject matter are now described with reference to the accompanying figures, in which:

[0005] FIG. 1 illustrates a non-volatile memory (NVM) comprising a processing unit, as per an example of the present subject matter;

[0006] FIGS. 2(A) and 2(B) illustrate cross-sectional views of a nonvolatile memory (NVM) integrated with a silicon chip, in accordance with an example of the present subject matter. The illustrations show the front-end CMOS circuitry, with the NVM layer implemented as a back-end-of-the-line (BEOL) structure positioned between metal interconnect layers.

[0007] FIG. 3 illustrates an architecture of an array of the NVM comprising memristors along with the processing unit consisting of mixed signal peripheral and control circuitry, as per an example of the present subject matter;

[0008] FIG. 4 illustrates an exemplary circuit during a read operation of the NVM architecture, as per an example of the present subject matter;

[0009] FIG. 5 illustrates an exemplary circuit during a write operation of the NVM architecture, as per an example of the present subject matter; and

[0010] FIG. 6 illustrates an exemplary circuit during an erase operation of the NVM architecture, as per an example of the present subject matter.

[0011] It may be noted that throughout the drawings, identical reference numbers designate similar, but not necessarily identical, elements. The figures are not necessarily to scale, and the size of some parts may be exaggerated to more clearly illustrate the example shown. Moreover, the drawings provide examples and / or implementations consistent with the description; however, the description is not limited to the examples and / or implementations provided in the drawings.DETAILED DESCRIPTION

[0012] As may be understood, non-volatile memory (NVM) refers to memory technology capable of retaining stored information even after an external power source is removed. Flash memory, which is a type of electrically erasable programmable read-only memory (EEPROM), is one example of NVM technology that allows data storage and retrieval without requiring a constant power supply.

[0013] Typically, conventional flash memories comprise an array of columns (bit lines) and rows (word lines), wherein each intersection has a memory cell with a floating gate transistor. The floating gate transistor is a type of metal-oxide-semiconductor field-effect transistor (MOSFET) that includes an electrically isolated floating gate positioned between a control gate and a channel region. The floating gate is capable of storing electrical charges to represent data states. A control gate connects the floating gate transistor to a respective row in the array and is separated from the floating gate by an insulating layer.

[0014] The memory cell stores data as an electrical charge on the floating gate. Each memory cell may typically store 1 bit of data, corresponding to two binary levels - 0 and 1. The process of writing data in each memory cell involves applying a high voltage to the control gate. Such high voltage causes electrons to tunnel through the insulating layer and accumulate on the floating gate, thereby programming the memory cell. The presence of charge on the floating gate may indicate a binary0. Conversely, removing the charge from the floating gate may reset the memory cell to a binary 1.

[0015] Conventionally, there have been attempts to store more than 1 bit of data in the memory cell. However, there are various limitations associated with floating gate transistor-based memory cells. One such limitation is the challenge of scaling the dimensions of the memory cell, which may lead to a reduction in the amount of charge that may be stored. Such limitations may cause the memory cell to be prone to external noise, especially while trying to store more than 1 bit of information, since the difference in charge stored between adjacent states continues to diminish with scaling. Hence, there is a need for efficient NVMs that may overcome the inherent limitations of susceptibility to noise due to a small amount of stored charge.

[0016] In the current state of the art, Phase Change Memory (PCM) is one technology that stores information in high or low resistance states depending on whether the material in the cell is amorphous or polycrystalline. Resistive RAM (RRAM) is another promising technology that stores information in high or low resistance states based on breaking or making a filamentary conductive path in an insulating material that constitutes the memory cell. Ferroelectric RAM (FeRAM or FeFET) is also a candidate technology that stores information by exploiting hysteretic behavior observed in the Polarization versus Electric Field relationship (PE loop) of ferroelectric material in the cell. Magnetic RAM (MRAM) is based on magnetic tunnel junctions and stores information based on magnetization of ferromagnetic material that constitutes the cell.

[0017] It may be understood that PCM and RRAM are inherently amenable for 3D stacking of memory cells, are also compatible with CMOS back-end-of-line (BEOL) processing, at the same time do not consume the underlying active silicon substrate. Despite their substantial promise, such technologies have significant limitations asthey are severely limited in terms of the number of bits per cell and the number of states each cell can store. Hence, there is a need for ultra-high density 3D NVM technology that is compatible with CMOS back-end-of-line processing, capable of storing multiple bits per cell, and supports a large number of states per cell.

[0018] The present subject matter provides a non-volatile memory (NVM) based on molecular materials. In one example, the NVM comprises a substrate, a processing unit coupled to the substrate, and an insulating layer disposed on the substrate and the processing unit. The processing unit may be controlled to generate a control signal for performing one or more memory operations. Examples of the one or more memory operations include, but are not limited to, a read operation, a write operation, an erase operation, and combinations thereof.

[0019] In one example, the NVM also comprises a first conductive layer disposed on the insulating layer. The first conductive layer is patterned to form a plurality of bit lines. The NVM further comprises a layer of molecular material disposed on the plurality of bit lines, and a second conductive layer disposed on the layer of molecular material. The second conductive layer is patterned to form a plurality of word lines.

[0020] In one example, the plurality of word lines is oriented in a direction perpendicular to the plurality of bit lines to form a crossbar array. A memristor is formed at each intersection of the crossbar array. The memristor comprises a portion of the molecular material sandwiched between a respective bit line and a respective word line. Each memristor may store multiple bits of data for performing the one or more memory operations.

[0021] In one example, the multiple bits of data correspond to k-bit data associated with 2kdiscrete states, wherein k is in a range of 1 to 14. The 2kdiscrete states correspond to distinct conductance states of the molecular material, wherein each conductance state is associated with an electrical resistance exhibited by the molecular material.

[0022] The NVM described herein is compatible with complementary metal-oxide semiconductor (CMOS) back-end-of-line (BEOL) processing. As used herein, "CMOS" is a technology used for constructing integrated circuits based on complementary and symmetrical pairs of p-type and n-type MOSFETs for logic functions. "BEOL" is a process in semiconductor device fabrication that consists of depositing metal interconnect layers onto a substrate (for example, silicon) that has already undergone front-end-of-line (FEOL) processing, wherein active semiconductor devices such as transistors, capacitors, and resistors have been fabricated and patterned on the substrate. Consequently, compatibility with CMOS BEOL implies that the NVM may be integrated into existing CMOS manufacturing processes without requiring significant changes to the established fabrication techniques.

[0023] As used herein, the term "conductive layer" refers to an electrically conductive layer which is attached to a voltage adjusting or measuring device to facilitate flow of electrons through the NVM memory cell.

[0024] The term "substrate" refers to a layer or film which acts as a template upon which other components are arranged.

[0025] As used herein, the term "NVM" refers to non-volatile memory wherein the memory cell consists of a memristor based on molecular material wherein information is stored deterministically in the individual redox state of the molecule, leading to massive data capacity for the memory device.

[0026] In one example, the NVM is made of a molecular material deposited using, for example, but not limited to, spin coating techniques.

[0027] In one example, the molecular material may be composed of, but not limited to, transition metal complex of azo-aromatic ligands, polycyclic redox-active organic materials, multi-metallic transition metal complexes, heterolytic transition metal complexes, and combinations thereof. The compounds described herein when used in NVMs exhibitdifferent functional attributes, such as distinct conductance states, varying electrical resistance levels, and multiple stable redox states that enable multi-bit data storage, in response to certain categories of stimuli. The type of functional attributes of the NVM may be expanded by applying additional or varying stimuli.

[0028] The construction of the NVM compatible with the CMOS BEOL process enables creation of memory in the middle of an interconnect fabric. In one example, the underlying substrate may support logic, for example, CMOS logic for accessing the memory for memory operations, such as read, write, and erase operations for standalone NVM applications. The underlying substrate may also support more complex logic such as digital processing units including microcontrollers, central processing units (CPUs), graphics processing units (GPUs), and tensor processing units (TPUs), enabling embedded NVM applications.

[0029] In an example, the insulating layer, the first conductive layer, the layer of molecular material, and the second conductive layer are fabricated using complementary metal-oxide semiconductor (CMOS) back-end-of-line (BEOL) processing. The fabrication process begins with planarizing a top surface of the insulating layer using chemical mechanical polishing.

[0030] In one example, a plurality of metal vias are formed through the insulating layer to connect the plurality of bit lines to underlying conductive layers of the processing unit. The via openings are filled with metal such as tungsten or copper using standard CMOS processing such as chemical vapor deposition (CVD) or electroplating.

[0031] The first conductive layer and the second conductive layer may be selected from a group comprising titanium-titanium nitride (Ti-TiN), titanium-titanium nitride-Aluminum-titanium Nitride (Ti-TIN-AI-TiN), titanium-titanium nitride-Copper-titanium Nitride (Ti-TIN-Cu-TiN), titanium-titanium nitride-chromium-gold (Ti-TiN-Cr-Au), titanium-titanium nitride-chromium (Ti-TiN-Cr), chromium-gold (Cr-Au), indium tin oxide (ITO), fluorine doped tin oxide (FTO), chromium, titanium, platinum, gold, tungsten, nickel, or graphite.

[0032] In one example, lithographic techniques are implemented to define the plurality of bit lines. Reactive ion etching is performed to pattern the first conductive layer. A thin insulating layer may be deposited and planarized using chemical mechanical polishing (CMP), so that the patterned bit lines and the insulating layer are co-planar.

[0033] The layer of molecular material having a thickness in a range of about 5 nanometers (nm) to about 500 nm is deposited using spin coating techniques on top of the patterned bit lines. The molecular material may be selected from a group comprising transition metal complex of azo-aromatic ligands, polycyclic redox-active organic materials, multi-metallic transition metal complexes, heterolytic transition metal complexes, or a combination thereof.

[0034] In one example, additional metal vias are formed through the molecular material layer and underlying insulator layers to connect the plurality of word lines to underlying conductive layers of the processing unit.

[0035] In one example, the second conductive layer is deposited ensuring no contaminating interfacial layer between the molecular material and the second conductive layer. This may be achieved by having inert chambers for spin coating and metal deposition so that the molecular material is not exposed to ambient conditions before the metal deposition.

[0036] In one example, lithography is performed to define the crossbar array of word lines with appropriate connectivity to the underlying via layers. Reactive ion etching is performed to pattern the second conductive layer to define isolated word lines. The arrangement of the molecular material layer sandwiched between the word lines and bit lines forms the array of memristors.

[0037] In one example, an insulating layer is deposited on top of the word lines. Additional crossbar layers may be added to create multiple memristor layers by stacking, further expanding the density of the NVM.

[0038] In operation, the processing unit generates control signals for performing one or more memory operations including read, write, and erase operations. The word lines are used to select specific rows of memristors, while the bit lines are used to read from or write to the memristors in the selected row. In a read operation, a voltage is applied to a word line to activate all memristors in that row, and the bit lines are used to sense the state of each memristor. In a write operation, the word line selects the row, and the bit lines carry the data to be written to the selected memristors. Such a crossbar arrangement allows for efficient addressing and access of individual memristors within a large array, enabling high-density storage and rapid data retrieval.

[0039] Each memristor stores multiple bits of data corresponding to k-bit data associated with 2kdiscrete states, wherein k is in a range of 1 to 14. For example, when k=14, the memristor may store 214= 16384 discrete states. The 2kdiscrete states correspond to distinct conductance states of the molecular material, wherein each conductance state is associated with an electrical resistance exhibited by the molecular material. Thus, a single memristor may store k-bit data as opposed to a conventional 1 -bit storage architecture with 2 discrete states, which requires k-cells to achieve similar data capacity.

[0040] Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The above-mentioned implementations are further described herein with reference to the accompanying figures. It should be noted that the description and figures relate to exemplary implementations and should not be construed as a limitation to the present subject matter. It is also to be understood that various arrangements may be devised that, althoughnot explicitly described or shown herein, embody the principles of the present subject matter. Moreover, all statements herein reciting principles, aspects, and embodiments of the present subject matter, as well as specific examples, are intended to encompass equivalents thereof.

[0041] FIG. 1 illustrates a non-volatile memory (NVM) 100 having a substrate 102 and a processing unit 104, in accordance with an example of the present subject matter. The NVM 100 is disposed on the substrate 102. The processing unit 104 is coupled to the substrate 102 and is configured to generate control signals for performing one or more memory operations on the NVM 100. The processing unit 104 may operate autonomously based on pre-programmed instructions, or may receive commands from an external host device, an on-chip controller, or a user interface. The memory operations may include a read operation, a write operation, and an erase operation. The processing unit 104 may be an internal component formed on the substrate 102, or an external component coupled to the NVM 100 via interconnects.

[0042] In some examples, when the processing unit 104 is an internal component, the processing unit 104 may comprise complementary metal-oxide semiconductor (CMOS) logic circuits fabricated on the substrate 102 using a CMOS front-end-of-line (FEOL) processing. In some examples, the processing unit 104 may be selected from a microcontroller, a central processing unit (CPU), a graphics processing unit (GPU), or a tensor processing unit (TPU).

[0043] In one example, the processing unit 104 comprises a word line signal decoder 106 coupled to a word line analog demultiplexer 108, and a bit line signal decoder 110 coupled to a bit line analog multiplexer 112. The word line signal decoder 106 receives an M-bit wide digital signal and sends control signals to the word line analog demultiplexer 108. In response to the control signals, the word line analog demultiplexer 108 routes an input read / write signal to one of M word lines, thereby selectingthe memristors in a particular row of word lines. The bit line signal decoder 110 receives an N-bit wide digital signal and sends control signals to the bit line analog multiplexer 112. In response to the control signals, the bit line analog multiplexer 112 routes one of N bit lines to a mode select logic processor 114, thereby selecting a specific memristor to be read from or written to.

[0044] The processing unit 104 may further comprise a mode select logic processor 114 coupled to the bit line analog multiplexer 112. The mode select logic processor 114 has a read path and a write path. The mode select logic processor 114 is controlled by a mode input signal which determines whether a read operation or a write operation is to be performed. During a read operation, the mode select logic processor 114 connects a selected bit line to the read path. During a write operation, the mode select logic processor 114 connects a selected bit line to the write path.

[0045] The processing unit 104 may further comprise an analog-to-digital converter (ADC) 116 coupled to the read path of the mode select logic processor 114. The ADC 116 may sense a conductance state of a selected memristor and convert an analog signal representing the conductance state to a k-bit digital value. The k-bit digital value represents the data stored in the selected memristor. In one example, the ADC may be a k-bit wide ADC capable of distinguishing between 2kdiscrete conductance states of the memristor.

[0046] The processing unit 104 may further comprise a first set of switches ‘ST, a second set of switches ‘S2’, and a third set of switches ‘S3’, a fourth set of switches ‘S4’, a fifth set of switches ‘S5’, and so on (not shown). The first set of switches ‘ST is associated with the plurality of word lines and enables connection of the word lines to the word line analog demultiplexer 108. The second set of switches ‘S2’ couples the plurality of word lines to ground. The third set of switches ‘S3’ couples the plurality of bit lines to an erase voltage source. The configuration ofthese switches, ‘ST, ‘S2’, ‘S3’, determines the operation mode of the NVM 100.

[0047] The processing unit 104 may further comprise a read / write signal block (not shown) for initiating control signals for read, write, and erase operations. The read / write signal block may generate various control signals such as an erase signal (E), a mode signal (M), a read pulse signal (Tpulse_Read), and a write pulse signal (Tpulse_Write). These control signals coordinate the operation of the word line signal decoder, the bit line signal decoder, the mode select logic processor 114, and the switches to perform the desired memory operation on the NVM 100.

[0048] FIG. 2(A) and FIG. 2(B) illustrate a detailed cross-sectional view of a non-volatile memory (NVM) 200 (same as NVM 100 depicted in FIG. 1 ), as per an example of the present subject matter.

[0049] In one example, the NVM 200 is made of a molecular material deposited using, for example, but not limited to, spin coating techniques. In one example, the molecular material may be composed of, but not limited to, transition metal complex of azo-aromatic ligands, polycyclic redox-active organic materials, multi-metallic transition metal complexes, heterolytic transition metal complexes, or a combination thereof. The compounds described herein when used in NVM 200 are such that they exhibit different functional attributes in response to certain categories of stimuli.

[0050] Specifically, the type of functional attributes of the NVM 200 may be expanded by applying additional or varying stimuli. The deposition of the NVM 200 is compatible with the CMOS BEOL process, thus enabling creation of memory in the middle of an interconnect fabric. In one example, an underlying substrate 102 (same as substrate 102 in FIG. 1) may support logic, for example, the CMOS logic for accessing the memory for memory operations, such as read, write, and erase operations for standalone NVM applications. The underlying substratemay also support more complex logic such as digital processing units such as microcontroller, CPU, GPU, TPU, etc., enabling embedded NVM applications.

[0051] In one example, the NVM 200 may be created on top of CMOS interconnect fabric 202. The CMOS interconnect fabric 202 comprises a plurality of insulating layers 204 and a plurality of conductive layers 206. For example, the CMOS interconnect fabric 202 is formed by depositing a plurality of insulating layers 204-1, 204-2... (collectively referred as insulating layers 204) of an insulating material and a plurality of conductive layers 206-1, 206-2... (collectively referred as conductive layers 206) of a conductive material, wherein the insulating layers 204 and the conductive layers 206 are alternately stacked. As depicted in FIG. 2, the insulating layers 204 and conductive layers 206 are deposited in an alternate manner. The alternating arrangement of insulating and conductive layers enables the creation of a three-dimensional interconnect fabric 202 of CMOS.

[0052] Further, the crossbar array (not shown) of the NVM 200 consists of a plurality of word line layers and bit line layers running perpendicular to each other with a non-volatile molecular material (represented as non-volatile molecular material layer 1, 2,..., in FIG. 2) sandwiched between them. In the vertical stacking the plurality of Word line layers is indicated as 210-1, 210-2 (more layers can be present).

[0053] On a given horizontal Bit line layer, a plurality of isolated Bit lines are defined as 208-1-1 , 208-1-2, ... 208-1 -N. On a given horizontal Word line layer, a plurality of isolated Word lines are defined as 210-1 -1, 210-1-2, ... 210-1 -M. Similarly, in the vertical stacking the plurality of Bit line layers is indicated as 208-1, 208-2 (more layers can be present).

[0054] In one example, a first conductive layer 208-1-1 is disposed on the insulating layer 204-N and is patterned to form a plurality of bit lines. A layer of molecular material is disposed on the plurality of bit lines. A second conductive layer 210-1 -1 is disposed on the layer of molecularmaterial and is patterned to form a plurality of word lines. The plurality of word lines is oriented in a direction perpendicular to the plurality of bit lines to form a crossbar array. A memristor is formed at each intersection of the crossbar array, the memristor comprising a portion of the molecular material sandwiched between a respective bit line and a respective word line.

[0055] In one example, at the intersection of each of the word line 210-1-1 and the bit line 208-1-1, a memristor may be formed. The memristor may be capable of storing k-bit precision data. Thus, a single memristor may store k-bit data as opposed to a conventional 1 -bit storage architecture, which requires k-cells to get similar amount of data. In order to further increase the density of the NVM 200, additional insulating layers 204 N+1 followed by additional word line layers 210-2-1 ,... ,210-2-M and bit line layers 208-2-1,..., 208-2-N may be stacked upon each other.

[0056] In an example, each memristor stores data using distinct conductance states of the molecular material. Each conductance state is associated with an electrical resistance exhibited by the molecular material. The electrical resistance of the molecular material changes based on the number of electrons transferred to or from molecules in the molecular material. A lower electrical resistance corresponds to a higher conductance state, while a higher electrical resistance corresponds to a lower conductance state. The distinct conductance states are stable and non-volatile, retaining data when power is removed. In one example, the 2kdiscrete states correspond to 2kdistinct conductance states, wherein each conductance state is distinguishable from other conductance states by a measurable difference in electrical resistance.

[0057] In various examples, the value of k may range from 1 to 14. When k=2, the memristor may store 22=4 discrete states corresponding to 2 bits of data. When k=4, the memristor may store 24=16 discrete states corresponding to 4 bits of data. When k=8, the memristor maystore 28=256 discrete states corresponding to 8 bits of data. When k=14, the memristor may store 214=16384 discrete states corresponding to 14 bits of data. The number of discrete states achievable depends on the molecular material used and the precision of the analog-to-digital converter in the processing unit coupled to the substrate.

[0058] The NVM 200 further comprises a plurality of metal vias 212 formed through the insulating layer 204 to connect the plurality of bit lines 208 to underlying conductive layers 206 of the processing unit coupled to the substrate. The metal vias 212 provide electrical connectivity between the crossbar array and the processing unit. In one example, the metal vias 212 may comprise tungsten or copper. The metal vias 212 may be formed using lithography to define via openings in the insulating layer, followed by metal deposition using chemical vapor deposition (CVD) or electroplating.

[0059] The fabrication process for the NVM 200 may begin with planarizing the top surface of an insulating layer 204 using chemical mechanical polishing. This is followed by metal via 212 formation to bring connections from underlying conductive layers to Bit lines to be formed subsequently.

[0060] In one example, lithographic techniques are employed to define the crossbar array of bit line layers 208 with the connectivity to the underlying Via layers. Further, reactive Ion etching techniques may be performed to pattern the bit line layer as per the pattern defined by the photolithographic technique. A thin insulating layer is deposited and planarized using Chemical Mechanical Polishing (CMP), so that the patterned bit line layer 208 (i.e., 208-1-1 ... 208-1 -N or 208-2-1 . 208- 2-N and so on) and the insulating layer 204 are co-planar. A molecular material (non-volatile memory material layer - 1, 2,..., in FIG. 2) of required thickness (for example, in the range of 5 nm - 500 nm) is then deposited using spin coating techniques.

[0061] This is followed by metal via 212 formation to bring connections from underlying conductive layers to Word lines to be formed subsequently. A metal via 212 connecting the bit line layer 208-1-1 to the underlying conductive layer 206 is shown in FIG. 2(A), and a metal via 212 connecting the word line layer 210 to the underlying conductive layer 206 is shown in FIG. 2(B).

[0062] In one example, another conductive layer 206-2 for the Word line layer 210 formation is then deposited ensuring that there is no contaminating interfacial layer between the molecular material and the conductive layer 206-2. Lithography is done to define an array of word line layers and also the appropriate connectivity to the underlying Via layers. Reactive Ion Etch is performed to pattern the top electrode conductive layer 206-2 as per the pattern defined by the lithography to define isolated word line layers 210. An arrangement of a molecular material layer sandwiched between two conductive layers of Word line and Bit line, thus forms an array of memristors.

[0063] An insulating layer 204-N-N+1 is deposited on top of the Word line layers 210. Lithography is performed to create contact hole(s) in this insulating layer 204-N-N+1. Additional layers of cross bars may be added to create multiple such memristor layers by stacking, and thus further expanding the density of NVM, by repeating the above steps. This layered NVM 200 demonstrates how multiple NVM layers may be stacked to increase memory density while utilizing molecular memory materials. The functioning of the NVM 200 is further explained in conjunction with FIGS. 3-6.

[0064] FIG. 3 illustrates an architecture 300 of the NVM 200, as per an example of the present subject matter. The architecture 300 depicts a detailed view of the crossbar array and associated circuitry, wherein the circuitry includes components that may be part of the processing unit 104 (as shown in FIG. 1) or may be implemented as separate circuits coupled to the processing unit 104. The architecture 300 depicts acrossbar array with a plurality of word line layers (WL-1 to WL-M, corresponding to 210-1-1 to 210-1 -M or 210-2-1 to 210-2-M, in FIG. 2) running horizontally and a plurality of bit line layers (BL-1 to BL-N, corresponding to 208-1-1 to 208-1 -N or 208-2-1 to 208-2-N, in FIG. 2) running vertically. At the intersections of the plurality of word line layers (WL-1 to WL-M) and the plurality of bit line layers (BL-1 to BL-N) are memristors, represented by numeral '302'.

[0065] The word line analog demultiplexer 108 is coupled to the word line signal decoder 106. The word line signal decoder 106, in response to an M-bit wide digital signal, sends controls to the word line analog demultiplexer 108. In response to this, the word line analog demultiplexer 108 routes the input READ / WRITE signal to one of the M word lines, thus selecting the memristors in that particular row of word line. The switches labeled 'ST and 'S2' connected to the Word line layers (WL-1 to WL-M) enable the connection of WL to either the word line analog demultiplexer 108 on the left or to the Ground line on the right respectively. The bit line analog multiplexer 112 is coupled to the bit line signal decoder 110. The bit line signal decoder 110, in response to an N-bit wide digital signal, sends controls to the bit line analog multiplexer 112. In response to this, the bit line analog multiplexer 112 routes one of the N bit lines to the input of mode select logic processor 114, thus selecting the specific memristor to be read or written. Additionally, a series of switches labeled as 'S3' enable the connection of N bit lines to voltage source 'VE'.

[0066] In one example, the mode select logic processor 114, with options for Read (R) and Write (W), is connected through switch S4 to the ADC 116 during Read operation and through switch 'S5' to ground signal during write operation. The mode select logic processor 114 is controlled by Mode input M, which decides whether Read or Write operation is to be performed. The ADC 116 is configured to sense theconductance state of the memristor 302 and read its analog value, and then convert to a k-bit digital value.

[0067] The architecture 300 also includes various control signals such as E, M, Tpulse\_Read, and Tpulse\_Write initiated in response to a command provided through read / write signal 304 representing "Read / Write signal". The architecture 300 supports multi-bit storage per memristor, with the output providing "k-bit wide memory data", as shown in k-bit wide memory data 306. Herein, each memristor 302 has a capability to store multiple bits of information, wherein 'k' represents the number of bits that may be stored in a single memristor 302. The NVM 200 may be implemented in various operations, such as read operation, write operation, and erase operation, as explained in conjunction to FIGs. 4-6.

[0068] FIG. 4 illustrates an exemplary circuit 400 of the NVM architecture 300 during a read operation, as per an example of the present subject matter. As depicted in Fig. 4, a memristor cell, 402, is selected by presenting its address through Word line Signal Decoder 106 and Bit Line Signal Decoder 110 so that a particular word line (1 out of M) is selected through Word line Signal Analog Demultiplexer 108 and Bit line Signal Analog Multiplexer 112. During Read operation an input signal may be received by the read / write signal 304.

[0069] In an example, the input signal is set to 0.5 Volts for Read operation which passes through switch ‘ST. A pulse signal labeled "Tpulse\_Read" is applied to close the switch ‘S4’, which connects the selected Memristor cell to the ADC 116, which outputs k-bit wide memory data, as shown by the k-bit wide memory data 306. In one example, value of "Tpulse\_Read" may have a range from a few picoseconds to a few microseconds, depending on the ADC sampling speed. This circuit configuration 400 allows for reading multiple bits of data (k bits) from a single memristor 402, converting the analog signal to digital data through the ADC 116.

[0070] During a read operation, the first set of switches ‘ST is closed to connect the word lines to the word line analog demultiplexer 108, while the second set of switches ‘S2’ and the third set of switches ‘S3’ are open. The word line signal decoder 106 and the bit line signal decoder 110 select a particular memristor, for example, the memristor 402 by activating a specific word line and bit line. An input signal, for example 0.5 Volts, is applied to the selected word line through the first set of switches ‘ST. A read pulse signal (Tpulse_Read) is applied to close a switch connecting the selected memristor 402 to the ADC 116. The ADC 116 senses the conductance state of the selected memristor 402 and outputs a k-bit wide digital value representing the data stored in the memristor 402. In one example, the duration of Tpulse_Read may range from a few picoseconds to a few microseconds, depending on the ADC sampling speed.

[0071] FIG. 5 illustrates an exemplary circuit 500 of the NVM architecture 300 during a write operation, as per examples of the present subject matter. A particular Memristor cell, 502, is selected by presenting an address (of that memory cell) through Word line Signal Decoder 106 and Bit Line Signal Decoder 110 so that a particular word line (1 out of M) is selected through Word line Signal Analog Demultiplexer 108 and Bit line Signal Analog Multiplexer 112. It shows a selected memristor 502 connected to two switches, S1 and S5. The Read / Write Signal 304 (input signal) is set to 0.9 Volts and is connected to switch S1.

[0072] The value of "T\_pulse\_Write" is proportional to the value of data to be written. In one example, for Data=0001 , "T\_pulse\_Write" is 80nS, while for Data=1010, "T\_pulse\_Write" is 800nS. These pulse durations are represented by rectangular waveforms below the memristor 502. The longer pulse corresponds to the higher value data. Switch S5 is connected to ground, completing the circuit for the write operation. FIG. 5 visually represents how the duration of the write pulse determines the value stored in the memristor 502.

[0073] During a write operation, the first set of switches ‘ST is closed to connect the word lines to the word line analog demultiplexer 108, while the second set of switches ‘S2’ and the third set of switches ‘S3’ are open. The word line signal decoder 106 and the bit line signal decoder 110 select a particular memristor, for example, the memristor 502, by activating a specific word line and bit line. An input signal, for example 0.9 Volts, is applied to the selected word line through the first set of switches. A write pulse signal (T_pulse_Write) is applied to program the selected memristor. The duration of T_pulse_Write is proportional to the value of data to be written.

[0074] In one example, for data value 0001, T_pulse_Write is 80 nanoseconds, while for data value 1010, T_pulse_Write is 800 nanoseconds. The longer pulse duration corresponds to a higher data value. A switch connects the bit line to ground, completing the circuit for the write operation.

[0075] FIG. 6 illustrates an exemplary circuit 600 of the NVM architecture 300 during an erase operation, as per examples of the present subject matter. It shows a crossbar with the plurality of word line layers (WL-1, WL-2, ..., WL-M-1, WL-M) running horizontally and the plurality of bit line layers (BL-1, BL-2, ..., BL-N-1, BL-N) running vertically. At the top, a voltage source labeled "VE = 0.75 Volts" is connected to a switch S3, which is connected to all the bit line layers. Another switch S2 is connected to all the word line layers WL-1,...,WL-M.

[0076] During an erase operation, the first set of switches ‘ST is open, while the second set of switches ‘S2’ and the third set of switches ‘S3’ are closed. The second set of switches ‘S2’ connects all word lines to ground. The third set of switches ‘S3’ connects all bit lines to an erase voltage source ‘VE’. In one example, the erase voltage is 0.75 Volts. All memristors 602 in the crossbar array simultaneously receive a reverse voltage to erase data stored thereon. This is depicted by arrows pointingto several intersections of bit line layers BL-1 ,BL-N and word line layers WL-1,...,WL-M, where the memristors are located. The configuration shown allows for a simultaneous erase of all memristors in the crossbar, which is referred to as an "Erase" operation in the present subject matter.

[0077] The approaches described herein may be implemented in a variety of other memory technologies. For example, the approaches may be implemented as phase change memories (PCMs), which store information in high and low resistance states based on whether the material of the memristors is in an amorphous state or a polycrystalline state. The approaches may also be implemented as resistive randomaccess memories (RRAM), which store information in high and low resistance states based on breaking or making a filamentary conductive path in an insulating material that constitutes the memristors.

[0078] Additionally, the present approaches may be implemented as ferroelectric random-access memories (FeRAM), which store information by exploiting the hysteretic polarization versus electric field behavior of a ferroelectric material constituting the memristors. Furthermore, the approaches may be implemented as magnetic random-access memories (MRAM), which are based on magnetic tunnel junctions and store information based on the magnetization of a ferromagnetic material constituting the memristors.

[0079] As described herein, some memory technologies such as PCM and RRAM are inherently amenable for 3-dimensional stacking of memristors and are compatible with CMOS BEOL processing without consuming the underlying active silicon substrate. However, such technologies have significant limitations as they are severely limited in terms of the number of bits per memristor and the number of states each memristor may store. The present subject matter addresses these limitations by providing ultra high-density 3-dimensional NVM that iscompatible with CMOS BEOL processing, capable of storing multiple bits per memristor, and supports a large number of states per memristor.

[0080] The NVM described herein enables ultra high-density storage by allowing each memristor to store multiple bits of data corresponding to k-bit data associated with 2kdiscrete states, wherein k is in a range of 1 to 14. This vastly surpasses the data density of conventional 1 -bit storage architectures based on floating gate flash memories. Furthermore, the 3D stacking capability allows for multiple layers of memristors to be fabricated vertically by stacking additional insulating layers followed by additional word line layers and bit line layers upon each other, thereby further increasing storage density without expanding the footprint. The fabrication process for the NVM is compatible with complementary metal-oxide semiconductor (CMOS) back-end-of-line (BEOL) processing, enabling seamless integration with existing semiconductor manufacturing techniques and creation of memory in the middle of an interconnect fabric.

[0081] Unlike conventional charge-based memories that store data by trapping electrons in a floating gate, the NVM stores information deterministically in the individual redox state of the molecular material. This non-charge-based storage approach is less susceptible to noise and charge leakage issues as technology scales down. The design enables fast and efficient read, write, and erase operations, including simultaneous flash erase across the entire crossbar array by connecting all word lines to ground and all bit lines to an erase voltage source.

[0082] The molecular material approach offers improved scalability compared to traditional semiconductor memories by relying on molecular-scale phenomena for data storage. The 2kdiscrete states correspond to distinct conductance states of the molecular material, wherein each conductance state is associated with an electrical resistance exhibited by the molecular material. By storing multiple bits per memristor using these distinct conductance states rather than smallcharge differences, the memory is more robust against noise-induced errors that affect conventional memories when trying to store more than 1 bit of information.

[0083] The ability to create crossbar arrays in the middle of the interconnect fabric opens new possibilities for system-on-chip designs and 3D integrated circuits. The underlying substrate may support logic, such as CMOS logic for accessing the memory for memory operations including read, write, and erase operations for standalone NVM applications. The underlying substrate may also support more complex logic such as digital processing units including microcontroller, CPU, GPU, and TPU, enabling embedded NVM applications. Such advantages collectively address many limitations of current memory technologies, potentially enabling next-generation high-density, high-performance non-volatile memory systems.

[0084] Although examples for the present disclosure have been described in language specific to structural features and / or methods, it is to be understood that these examples are not necessarily limited to the specific features or methods described. Rather, the specific features and methods are disclosed and explained as examples of the present description.

Claims

l / We Claim1. A non-volatile memory (NVM) comprising:a substrate (102);a processing unit (104) coupled to the substrate (102), wherein the processing unit (104) is to generate a control signal for performing one or more memory operations;an interconnect fabric (202) disposed on the substrate (102) and the processing unit (104), the interconnect fabric (202) comprising a plurality of insulating layers (204-1 , 204-2) and a plurality of conductive layers (206-1 , 206-2);an insulating layer (204-N) disposed on the substrate (102) and the processing unit (104) and the interconnect fabric (202);a first conductive layer (208-1-1) disposed on the insulating layer (204-N), wherein the first conductive layer (208-1-1) is patterned to form a plurality of bit lines;a layer of molecular material (1 ) disposed on the plurality of bit lines; anda second conductive layer (210-1-1) disposed on the layer of molecular material (1), wherein the second conductive layer (210-1-1) is patterned to form a plurality of word lines, wherein the plurality of word lines is oriented in a direction perpendicular to the plurality of bit lines to form a crossbar array, andwherein a memristor is formed at each intersection of the crossbar array, the memristor comprising a portion of the molecular material sandwiched between a respective bit line and a respective word line, wherein each memristor is to store multiple bits of data for performing the one or more memory operations.

2. The NVM as claimed in claim 1 , wherein the first conductive layer (208-1-1) and the second conductive layer (210-1-1) are selected from a groupcomprising titanium-titanium nitride (Ti-TiN), titanium-titanium nitride-Aluminum-titanium Nitride (Ti-TIN-AI-TiN), titanium-titanium nitride-Copper-titanium Nitride (Ti-TIN-Cu-TiN), titanium-titanium nitride-chromium-gold (Ti-TiN-Cr-Au), titanium-titanium nitride-chromium (Ti-TiN-Cr), chromiumgold (Cr-Au), indium tin oxide (ITO), fluorine doped tin oxide (FTO), chromium, titanium, platinum, gold, tungsten, nickel, or graphite.

3. The NVM as claimed in claim 1, wherein the layer of molecular material (1 ) has a thickness in a range of about 5 nanometers (nm) to about 500 nm.

4. The NVM as claimed in claim 1 , wherein the insulating layer (204-N), the first conductive layer (208-1-1), the layer of molecular material (1), and the second conductive layer (210-1-1) are fabricated using a complementary metal-oxide semiconductor (CMOS) back-end-of-line (BEOL) processing.

5. The NVM as claimed in claim 1, wherein the one or more memory operations comprise a read operation, a write operation, and an erase operation.

6. The NVM as claimed in claim 1, wherein the multiple bits of data correspond to k-bit data associated with 2kdiscrete states, wherein k is in a range of 1 to 14.

7. The NVM as claimed in claim 6, wherein the 2kdiscrete states correspond to distinct conductance states of the molecular material (1), wherein each conductance state is associated with an electrical resistance exhibited by the molecular material (1 ).

8. The NVM as claimed in claim 7, wherein the processing unit (104) comprises a k-bit analog-to-digital converter (ADC) (116) to convert each conductance state to digital word during memory read operation.

9. The NVM as claimed in claim 1, wherein the molecular material (1) is selected from a group comprising transition metal complex of azo-aromatic ligands, polycyclic redox-active organic materials, multi-metallic transition metal complexes, heterolytic transition metal complexes, or a combination thereof.

10. The NVM as claimed in claim 1, wherein the processing unit (104) comprises a word line signal decoder (106) coupled to a word line analog demultiplexer (108), and a bit line signal decoder (110) coupled to a bit line analog multiplexer (112).

11. The NVM as claimed in claim 10, wherein the processing unit (104) further comprises a mode select logic processor (114) coupled to the bit line analog multiplexer (112), the mode select logic processor (114) having a read path and a write path.

12. The NVM as claimed in claim 10, wherein the processing unit (104) further comprises a digital logic comprising a first set of switches associated with the plurality of word lines to enable connection of the word lines to the word line analog demultiplexer (108), a second set of switches to couple the plurality of word lines to ground, and a third set of switches to couple the plurality of bit lines to an erase voltage source, to facilitate connection of the plurality of bit lines to an erase voltage and the plurality of word lines to zero volt to enable block erase operation of each memristor.

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