Quantum semiconductor circuit and method for reading qubit

Abstract

The present invention addresses the problem of improving the accuracy of detecting an output current from a charge sensor when a quantum semiconductor is increased in capacity.　One aspect of the present invention for solving the above problem is a quantum semiconductor circuit that is a readout circuit for reading out the state of a qubit, the quantum semiconductor circuit being characterized by including: a transmission circuit that outputs a transmission wave of prescribed frequency and power to a reflective part; a transistor that constitutes part of the reflective part and discriminates the state of the qubit; a conversion circuit that converts the impedance of the reflective part based on the state of the qubit; and a reception circuit that receives a reflected wave resulting from the transmission wave being reflected from the reflective part, wherein the state of the qubit is read out on the basis of the reflected wave.

Description

Quantum Semiconductor Circuit and Method for Reading Quantum Bits

[0001] The present invention relates to a technique for reading quantum bits in a quantum semiconductor.

[0002] There is a great deal of interest in constructing a quantum computer that can be executed in a high-speed and cost-effective manner. In particular, a quantum computer constructed using silicon semiconductor process technology can scale up the number of quantum bits due to the characteristics of its manufacturing technology, and thus has the potential to significantly shorten calculations that require an enormous amount of time on classical computers, such as drug target search and financial asset risk assessment. An important point in realizing such a computer is to establish a reading method for accurately detecting the spin state of silicon quantum.

[0003] Patent Document 1 discloses a method of connecting a charge sensor SET (Single Electron Transistor) and a matching network (MN) circuit (a coupling circuit composed of a so-called inductor and a capacitor) to a quantum bit fabricated by applying an advanced fine semiconductor process, inputting an incident wave to the charge sensor and the coupling circuit, and detecting the difference in spin information in the quantum bit by reading information on the amplitude and phase of the reflected wave with respect thereto (for example, Fig. 14 thereof). [[ID=ll]]

[0004] US 2024 / 0022248 A1

[0005] Conventionally, quantum operations at the level of 1 to 100 quantum bits have been demonstrated in an absolute zero atmosphere realized using a dilution refrigerator or the like in a quantum semiconductor. However, in a system with a medium number of quantum bits, the computer resources for analyzing complex phenomena are not sufficient. On the other hand, if sufficient computer resources are to be secured by further increasing the capacity of the number of quantum bits, high integration of semiconductor elements for constructing quantum bits becomes important. As a means, it is desirable to apply an advanced fine semiconductor process to construct a quantum bit element.

[0006] The method disclosed in Patent Document 1 requires the same number of MN circuits as the number of qubits, as the MN circuit and charge sensor are connected in a one-to-one configuration. Furthermore, since the frequency of the incident wave input to the MN circuit is several hundred MHz, the inductor constant within the MN circuit is approximately μH. MN circuits with inductor constants on the order of μH are generally discrete components called chip inductors. When the number of qubits increases, it is desirable to select models with small material tolerances to maintain accuracy. If the characteristics of the passive components within the MN circuit vary, the resonance frequency with the quantum resistance value of the charge sensor (~26 kohm) will vary for each MN circuit, so reducing the tolerances of the aforementioned components is a challenge for high-level qubit integration.

[0007] In light of the above background, the object of the present invention is to improve the detection accuracy of the output current from the charge sensor when increasing the capacity of the quantum semiconductor.

[0008] One aspect of the present invention for solving the above problems is a readout circuit for reading the state of a qubit, comprising: a transmitting circuit that outputs a transmitting wave having a predetermined frequency and power to a reflecting section; a transistor that constitutes a part of the reflecting section and determines the state of the qubit; a conversion circuit that converts the impedance of the reflecting section based on the state of the qubit; and a receiving circuit that receives a reflected wave from the reflecting section that the transmitting wave has been reflected back, wherein the state of the qubit is read out based on the reflected wave.

[0009] Another aspect of the present invention for solving the above problems is a method for reading out a qubit, which reads out the spin state of a charged particle stored in a qubit array configured as a semiconductor integrated circuit, and includes: a readout step of using a charge sensor to detect the difference in spin state as a difference in charge and generate a readout output signal; a conversion step of using a conversion circuit to convert the output impedance of the charge sensor; and a detection step of transmitting a predetermined signal in the direction of the charge sensor, receiving a reflected wave reflected from the direction of the charge sensor, and detecting the difference in spin state based on the reflected wave.

[0010] According to this disclosure, the spin state of an electron stored in a qubit can be read out with high precision. The effects described herein are not necessarily limited and may include any of the effects described herein.

[0011] This is a circuit diagram for reading out a quantum bit signal from a quantum semiconductor according to an embodiment. This is a circuit diagram for amplifying a quantum bit signal from a quantum semiconductor according to an embodiment. This is a circuit diagram for amplifying a quantum bit signal from a quantum semiconductor according to an embodiment. This is a circuit diagram for reading out a quantum bit signal from a quantum semiconductor according to an embodiment. This is a sequence diagram for reading out a quantum bit signal from a quantum semiconductor according to an embodiment. This is a cross-sectional view showing a substrate mounting method for a quantum semiconductor chip according to an embodiment. This is a cross-sectional view showing a substrate mounting method for a quantum semiconductor chip according to an embodiment. This is a block diagram showing a quantum computer using a quantum semiconductor according to an embodiment. This is a block diagram showing a method for mounting a quantum computer into a dilution refrigerator according to an embodiment.

[0012] In the following embodiments, the description will be divided into multiple sections or embodiments where necessary for convenience. Unless otherwise specified, these are not unrelated, and one may be a modification, detail, or supplementary explanation of part or all of the other. Furthermore, in the following embodiments, when referring to the number of elements (including number, numerical value, quantity, range, etc.), unless otherwise specified or clearly limited to a specific number in principle, it is not limited to that specific number and may be greater than or less than the number of characteristics.

[0013] Furthermore, in the following embodiments, it goes without saying that the components (including element steps, etc.) are not necessarily essential unless specifically stated or considered to be clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of the components, etc., it shall include those that substantially approximate or resemble their shape, etc., unless specifically stated or considered to be not in principle. The same applies to the numerical values ​​and ranges mentioned above.

[0014] One embodiment described in the examples is a readout circuit for reading the state of a qubit, comprising: a transmitting circuit that outputs a transmitted wave having a predetermined frequency and power to a reflecting section; a transistor located near the qubit that determines the state of the qubit; a converting circuit that converts or amplifies the impedance of the reflecting section based on the state of the qubit; and a receiving circuit that receives a reflected wave from the reflecting section after the transmitted wave has been reflected back. The configuration described reads the state of the qubit based on the reflected wave. In this configuration, the spin state of an electron stored in a qubit can be read out with high precision and at high speed.

[0015] In a more specific form, the conversion circuit further comprises a plurality of current-voltage conversion units that convert the output current of the transistor into an output voltage, a voltage amplification unit that amplifies the output voltage, and a selection circuit that reduces a plurality of voltage signals, arranged between the plurality of current-voltage conversion units and the voltage amplification unit, to 1 / N. Furthermore, the control chip on which the conversion circuit is located and the quantum chip on which the qubit and the transistor are located are mounted at a thermally isolated distance.

[0016] The quantum semiconductor readout circuit configuration and its arrangement and wiring method in this embodiment will be explained with reference to Figures 1 to 9.

[0017] Figure 1 is a circuit diagram for reading out qubit signals from a quantum semiconductor according to Example 1. The main circuit blocks constituting Figure 1 are the qubit array section QBA, the conversion circuit section CONV, the resonant section LCM, and the transmit / receive circuit section TXRXCKT.

[0018] The qubit array section QBA comprises qubit storage elements Q1, Q2, Q1n, Q2n, qubit storage element gates PG1, PG2, barrier control elements M1, M2, M3, M1n, M2n, M3n, barrier control element gates BG1, BG2, BG3, electron supply section RESS, charge sensors SET, SETn, selection element gates LB, LBn, RB, RBn, and charge sensor drains Drain, nDrain, and charge sensor source.

[0019] In this implementation, the qubit array QBA stores charged particles such as electrons in qubit storage elements. By applying a desired voltage to barrier control elements Mx located on both sides of the qubit storage element Qx, the electrons, which are qubits, can be continuously secured near the qubit storage element while maintaining their spin state. When reading out the spin state of a qubit, a reference bit for reading (e.g., up spin, |0>) is stored in the qubit storage element Q2.

[0020] The qubit, which is the result of a quantum operation and stored in the qubit storage element Q1, is moved and stored in the qubit storage element Q2 based on the principle of Pauli spin blockade operation. At this time, if the qubit storage element Q1 is in a down-spin state, the qubit storage element Q2 will store two charged particles: the down-spin as the result of the operation and the up-spin of the previously stored reference bit.

[0021] On the other hand, if the upspin resulting from the calculation is stored in the qubit storage element Q1, this calculation result upspin cannot be moved to the qubit storage element Q2, and only the original reference upspin will be stored there. By controlling the spin state of the qubit in this way using Pauli spin blockade, the spin state of the qubit is divided into storage conditions of one or two charged particles and held in the qubit storage element Q2.

[0022] The charge sensor SET, for example, amplifies the information about the number of charged particles with high sensitivity. When there are two charged particles in the qubit storage element Q2, the output current is large (e.g., 1 nA), and when there is one charged particle, the output current is small (e.g., 100 pA).

[0023] In the example shown in Figure 1, the charge sensors SET are connected individually, but it goes without saying that the qubit storage element Q2 can also be used as a charge sensor. In this case, a path is needed for the charge sensor output current to flow in the direction of the qubit storage elements Q2 and Q2n. For example, to store one or two charged particles, the qubit storage elements Q1 and Q1n can be used, and the desired potential can be supplied to each control gate to form a current path in the direction of the qubit storage elements Q2 and Q2n.

[0024] Furthermore, the method for detecting the spin information of the qubits does not have to be the Pauli spin blockade operation. For example, the so-called Elzerman readout method may be used. In any case, the spin state is detected as the number of electrons (charge) and transferred as a readout output current to the downstream stage of the qubit array (QBA).

[0025] Next, we will explain the conversion circuit section CONV. In the example shown in Figure 1, the conversion circuit section CONV consists of amplifier circuits AMP0, AMP1, AMP1n, AMP2, AMP2n, gain resistor RG, feedback capacitor CF, gain resistors RA and RB.

[0026] Functionally, amplifier circuit AMP0 is a so-called unity-gain buffer, and its role is to supply the desired reference voltage VREF to the source potential of the qubit array section QBA. Amplifier circuits AMP1 and AMP1n constitute a so-called transimpedance amplifier by connecting a gain resistor RG and a feedback capacitor CF in parallel, and their role is to convert the output current from the charge sensor SET into a voltage V0 using the gain resistor RG (V / A). Amplifier circuits AMP2 and AMP2n are so-called operational amplifiers using gain resistors RA and RB, and their role is to convert the voltage V0 into a voltage Vos. Each amplifier circuit AMP receives an activation signal VEN, which brings the amplifier circuit into an operational standby state.

[0027] By interconnecting these amplification circuits as shown in the embodiment in Figure 1, the output impedance of the charge sensor SET can be converted. Specifically, the output impedance of the charge sensor SET, in other words, the quantum resistance of the charge sensor SET as a single electronic element, is approximately 26 kohm(h / e 2 (where h is Planck's constant and e is the elementary charge), or an integer multiple thereof (N*h / e 2 The impedance value of the op-amp is converted to an output impedance of, for example, about 1 kohm. Alternatively, although not shown in the diagram, it is also possible to convert the output impedance to 50 ohms by connecting a so-called common-drain circuit (source follower circuit) after the op-amp (Vos node).

[0028] By converting the output impedance of the charge sensor SET, specifically by converting it to an impedance lower than the output impedance value of the charge sensor SET alone, it becomes possible to reduce the passive circuit constants of the resonant LCM. For example, if the output impedance is converted to approximately 1 kohm, the inductor LM can be reduced to the order of nH.

[0029] The resonant section LCM is configured such that the parasitic capacitance CBB within the resonant section LCM is connected in parallel with the output impedance R of the conversion circuit CONV, and this parallel connection of output impedance R and parasitic capacitance CBB is further connected in series with an inductor LM. Therefore, if we solve the analytical equation to make the total impedance in this network 50 ohms, we find that lowering the output impedance R allows us to set a lower value for the inductor LM. Furthermore, if the parasitic capacitance CBB can be set to a value of less than pF, the constant of the inductor LM can be lowered even further.

[0030] If the constants of the inductor LM are on the order of nH and the constants of the parasitic capacitance CBB can be less than pF, then the constants of the resonant LCM can be formed using a so-called semiconductor LSI process. If it can be formed with a semiconductor LSI, shape errors can be suppressed on the order of nm, so the tolerances of the component can be kept to a minimum. In other words, even if the number of resonant LCMs increases, i.e., the number of qubits increases, it can be manufactured with the finished values ​​according to the design constants, so the material tolerances become smaller and the spin state of the qubit can be read with high precision.

[0031] A variable capacitance Cvar may be added to the resonant LCM. This variable capacitance can be formed using a semiconductor element such as a diode, and its capacitance value can be controlled by controlling the depletion layer width by applying a reverse bias. Even when inductors LM and parasitic capacitances CBB are formed using semiconductor manufacturing processes, errors cannot be eliminated. Therefore, it is advisable to add a variable capacitance for fine-tuning the constants of the resonant LCM. It is preferable to connect the variable capacitance to the conversion circuit CONV side rather than the inductor LM, as this makes it easier to control the resonant frequency in the circuit connection.

[0032] In this embodiment, the qubit array section QBA, the conversion circuit section CONV, and the resonant section LCM described above are collectively referred to as the reflector section. By using the conversion circuit section CONV to convert the output impedance to a value lower than the impedance of the charge sensor SET section alone, as in this embodiment, the resonant section LCM can be manufactured using the same semiconductor process as the qubit array section QBA and the conversion circuit section CONV, thereby improving the accuracy of the finished dimensions of the entire reflector section and, as a result, improving the readout accuracy of the reflector section.

[0033] Next, the transmit / receive circuit TXRXCKT will be explained. In the example shown in Figure 1, the transmit / receive circuit TXRXCKT consists of digital-to-analog conversion circuits DAC0, DACn, DAC1, DAC2, analog-to-digital conversion circuits ADC0, ADCn, low-pass filters LPF1, LPF2, LPFn, LPFm, mixer MIX, output driver DRIVER, low-noise amplifier LNA, and balun BALUN.

[0034] The transmit / receive circuit TXRXCKT has multiple transmit / receive element circuits for channels CH0 and CHn. Each transmit / receive element circuit receives a continuous wave of a desired frequency from, for example, a numerically controlled oscillator into input section in0, converts it to an analog value using the digital-to-analog conversion circuit DAC0 in channel CH0, removes high-frequency noise using the low-pass filter LPF1, and converts it to a continuous wave of a desired power using the output driver DRIVER.

[0035] A variable gain amplifier or the like may be configured within the output driver circuit. Furthermore, a differential circuit configuration is generally used to reduce noise in the continuous wave transmission. Since the wiring from channel CH0 to the reflector has an external conductor at ground potential and forms a 50Ω transmission line, in the example shown in Figure 1, it is preferable to use a balun (e.g., a transformer circuit) to suppress propagation noise from the balanced differential circuit to the unbalanced single-ended circuit (wiring) and transmit the signal.

[0036] For example, a continuous wave output from channel CH0 propagates through the coaxial cable CX, passes through the directional coupler CIRC0 and bias tee capacitor CBT, and is input to the reflector as an input wave. The input wave is terminated, totally reflected, or somewhere in between depending on the impedance value of the reflector.

[0037] In the embodiment shown in Figure 1, for example, when reading out a down-spin qubit with the charge sensor SET, the circuit constants of the resonant LCM and the gain of the conversion circuit CONV are set so that the entire reflection section (qubit array section QBA, conversion circuit section CONV, and resonant LCM) has an impedance of 50Ω. Needless to say, if an impedance of 50Ω can be achieved by simply configuring the qubit array section QBA and the conversion circuit section CONV, the resonant LCM is unnecessary. Here, we will explain an example in which the reflection section is configured using the resonant LCM as well.

[0038] If the qubit being read out is down-spinned, meaning the entire reflector has an impedance of 50Ω, the input wave is terminated across the entire reflector, so almost no input wave is reflected. In reality, however, due to deviations from the 50Ω transmission line, such as wiring connectors, a small amount of signal is reflected back as a continuous wave via the directional coupler CIRC to the receiver RX of channel CH0 in the transmit / receive circuit.

[0039] On the other hand, in the case of an up-spin quantum state, the output impedance of the charge sensor SET differs from that of a down-spin state, causing the overall impedance of the reflector to deviate from 50Ω. If the circuit constants of the entire reflector are set so that the impedance deviates by about 10%, the reflection coefficient will be about 0.05, and 5% of the input power waveform will be reflected. The greater the signal strength (dB) of the reflected continuous wave, the easier it is for the transmitting and receiving circuits to detect it, enabling high-precision readout. Thus, the conversion circuit CONV performs the function of amplifying the impedance difference of the charge sensor SET based on the state of the qubit.

[0040] If this embodiment is applied, the amount of the reflected signal can be appropriately set, enabling high-precision reading. To increase the amount of the reflected signal, the amount of the input signal may be increased. However, generally, when the amount of the input signal is increased, the loss power at the end may propagate to the qubit section, potentially destabilizing the spin state of the qubit. As will be described later, in this embodiment, since the conversion circuit section CONV absorbs the loss at power-on, by adopting a mounting form in which the conversion circuit section CONV and the qubit array section QBA are thermally isolated, the allowable input power amount (the amount of the input signal to the reflection section) can be increased, and the amount of the reflected signal can be relatively increased to achieve high-precision reading.

[0041] After the receiver RX receives the reflected continuous wave, it is transmitted to the differential circuit side by the balun BALUN in the same manner as on the transceiver TX side, the reflected wave is amplified by the low-noise amplifier, down-converted by the mixer, the high-frequency noise component is removed by the low-pass filter, and the amplitude value of the reflected wave is digitized by the digital-analog conversion circuit ADC to determine whether the waveform is terminated or reflected by about several percent as described above. The above is the explanation of the basic reading method.

[0042] Although the description is omitted, the channel CHn may perform the same reading operation as the channel CH0. Since the number of charge sensors (n), the number of sets of amplification circuits in the conversion circuit section CONV (n) (set 1: amplification circuits AMP1, AMP2; set n: amplification circuits AMP1n, AMP2n), and the number of channels (n) in the transceiver circuit are configured to be the same number, their operations may also be the same. The bias potential applied to the electrodes of the variable capacitor Cvar in the resonance section LCM, the reference voltage VREF of the amplification circuit, the potential difference VDS (1 mV) across the charge sensor, and the digital-analog conversion circuit DAC and its output driver may be used to create and supply them.

[0043] Although detailed explanations are omitted here, PAD refers to signal pads within a semiconductor chip, Wire refers to, for example, wire bonding, and RLPF and CLPF refer to resistors and capacitors for low-pass filters. Also, in the design constants of the reflection section, when the frequency of the continuous wave is on the order of GHz, the element constants of the balun BALUN can be reduced. Therefore, it is advisable to fabricate the balun BALUN using the same LSI process as that of the digital-to-analog conversion circuit and the output driver circuit. Since the transceiver circuit TXRXCKT can be configured with a single semiconductor chip, there is also an advantage in that the chip area is reduced and the manufacturing cost can be suppressed.

[0044] Figure 2 is a transistor-level circuit diagram of the amplifier circuit AMP1. This circuit is a two-stage amplifier consisting of an amplification stage composed of transistors T1, T2, T3, T4, T5 and an output stage composed of transistors T6, T7.

[0045] Cfi is a phase compensation capacitor, and Rc is a phase compensation resistor. In this embodiment, T1, T2, T7 are NMOS transistors, and T3, T4, T5, T6 are PMOS transistors. The operating voltages are the supply voltage VDD (for example, around 1V), the ground potential VSSA, the ground potential or negative potential VSSD, the reference voltage VREF (the source potential of the charge sensor), and the reference potential VREF+VD of the amplifier circuit AMP1.

[0046] By applying a predetermined voltage to the activation signal VEN, feedback control is performed so that the drain DRAIN node becomes the reference potential VREF+VD (virtual ground). For example, if the reference voltage VREF is 0.2V and the drain voltage VD is 1mV, the drain DRAIN node is controlled to be virtually grounded at 0.201V. If the gain resistor RG is 1M (V / A), the output current ISET of the charge sensor is converted into a voltage of Vo = ISET*RG and further voltage-amplified by the subsequent amplifier circuits AMP2 and AMP2n. As a result, the output impedance of the charge sensor SET is converted by the conversion circuit section CONV.

[0047] Furthermore, the transistor circuit configurations of the amplifier circuits AMP2 and AMP2n shown in Figure 1 can be configured in the same way as the circuit of AMP1 shown in the dashed triangle in Figure 2 to form a so-called operational amplifier. Also, if the potential VDS across the charge sensor is 1mV and the reference voltage VREF is set to a low voltage of 0.2V, the transistors constituting the amplifier circuit in Figure 2 may not be able to operate in the saturation region. In such cases, setting the VSSD potential to a negative potential of, for example, -0.2V makes it easier for each transistor element to operate in the saturation region, contributing to the stable operation of the amplifier circuit.

[0048] Figure 3 shows another example of the transistor-level circuit diagram of the amplifier circuit AMP1. It is a so-called cascode amplifier, in which NMOS transistors T6, T7 and PMOS transistors T8, T9 are connected in series with transistors T1, T2, T3, T4, and T5 that constitute the amplification stage in Figure 2. To put this amplifier into operating standby mode, the desired potentials should be applied to the activation signals VEN1, VEN2, and VEN3. Note that symbols in Figure 3 that are the same as those in Figure 2 have the same function as those in Figure 2, and therefore their explanation is omitted.

[0049] Cascode amplifiers have the advantage of being able to secure a large gain (DC gain). Because a large gain can be secured, in principle, sufficient gain can be obtained even if the bandwidth of the amplifier itself is extended to the high-frequency side. For this reason, even when the output current of the charge sensor is a small current value of nA, the difference in qubit states can be reliably detected using the configuration of this embodiment. Note that the configuration in Figure 3 can be modified in various ways. It goes without saying that it can also be made into a so-called supercascode amplifier by adding an auxiliary amplifier, or into an aliased differential cascode amplifier.

[0050] Figure 4 shows another embodiment of the readout circuit. The differences from Figure 1 are the addition of a selection circuit MUX and selection signal SEL, and an amplification circuit AMP3, and the reduction of the number of resonant section LCM and transceiver circuit sets to one. Some of the symbols used to describe the circuit configuration are the same as those used in Figure 1, but since the same symbols have equivalent functions, we will focus on the differences here in our explanation.

[0051] In the embodiment shown in Figure 4, the conversion circuit CONV includes amplification circuits AMP1 and AMP1n which constitute multiple current-voltage conversion units that convert the output current of the charge sensor into voltage, amplification circuits AMP2 and AMP3 which constitute a voltage amplification unit, and a selection circuit MUX which reduces multiple voltage signals to 1 / n and is positioned between the multiple current-voltage conversion units and the voltage amplification unit.

[0052] The current-voltage conversion section and the selection circuit SEL operate at n times faster cycle speeds than the voltage amplification section, where n is the denominator of the coefficient that reduces the voltage signal to 1 / n.

[0053] The role of the selection circuit MUX and the selection signal SEL is to convert the readout signal between parallel and serial. For example, in the case of 10 amplifier circuits AMP01 to AMP10, each amplifier circuit AMP01 to AMP10 operates at a 10MHz cycle. The selection circuit MUX consists of 10 selection switches, and each selection switch is selected at 10MHz intervals by the selection signal SEL. In the first cycle, the readout signal is transmitted through the paths of amplifier circuits AMP01, AMP2, and AMP3. In the next cycle, the readout signal is transmitted through the paths of amplifier circuits AMP02, AMP2, and AMP3. This series of operations is repeated for all 10 amplifier circuits, completing the readout operation in a 1MHz cycle of 10MHz / 10 circuits.

[0054] The conversion circuit section CONV in Figure 4 has a parallel-serial conversion function, so the amplifier circuits AMP2 and AMP3, and the resonant section LCM, which are placed in the stages after the selection circuit MUX, can each be configured with only one unit. Because the circuit size can be reduced, the variation in characteristics within the LSI circuit is reduced, enabling high-precision readout processing. Also in Figure 4, an amplifier circuit AMP3 is added to the final stage of the conversion circuit section CONV. The output voltage of the amplifier circuit AMP2 is further amplified using the reference voltage VREF1.

[0055] In other words, by converting the output impedance of the charge sensor to an even lower impedance, the reflection coefficient, including the resonant LCM, can be increased. This means that a larger readout signal difference can be transferred to the transmit / receive circuit, improving the signal-to-noise ratio of the readout signal path, and thus reducing circuit operations such as integration processing within the transmit / receive circuit. Therefore, in addition to high-precision readout due to the reduction in the number of circuit points, high-speed readout operation is also possible due to the reduction in integration processing.

[0056] Figure 5 shows an example of the timing chart for the readout circuit in Figure 4. Assuming that the down spin is held in the qubit storage element of interest, and that the down bit has moved to the reference up spin side by the Pauli spin blockade operation, the first readout operation is when the state in which both up-spin and down-spin bits are stored is read out as an output current (output node potential Vos is large) using the charge sensor SET. Conversely, the second readout operation is when the up spin is held in the qubit storage element of interest (resulting in a small output node potential Vos).

[0057] The combination of conditions such as the up / down movement of the qubit, the magnitude of the output current of the charge sensor, and the termination and reflection of the input continuous wave can be changed according to the design. As shown in Figure 5, when the activation command ACT is input to the transmit / receive circuit TXRXCKT, the transmit / receive circuit outputs a continuous wave to the TX port for input to the reflector. At the same time, the desired potential is applied to the activation signal of the amplifier circuit implemented in Figures 1 to 4.

[0058] Each amplifier circuit enters an operational standby state, and its output nodes Vo and Vos transition to standby potential. A desired potential is applied to the drain nodes DRAIN and nDRAIN of the charge sensor by virtual ground control; for example, the potential VDS across the charge sensor is controlled to approximately 1mV. Next, when the activation command MACT for the selection circuit MUX is input to the transmit / receive circuit TXRXCKT, a predetermined address signal, such as number zero, is transmitted to the selection signal SEL, and the corresponding number zero of the multiple selector circuits inside the selection circuit MUX is selected. At the same time, the selection element gates LB and RB of charge sensor number zero, which are connected to the group of qubits to be read out, are selected, and the desired gate potential is applied.

[0059] Next, when the read command READ is input to the transmit / receive circuit, the desired gate potential is applied to the gate potential of the corresponding charge sensor SET, and a read current corresponding to the state of the qubit is output to the drain DRAIN node. This charge sensor output current is converted to the output node potential Vo by the current-voltage conversion circuit, and further amplified to the output node potential Vos by the subsequent voltage-voltage conversion circuit. After impedance conversion by this conversion circuit section CONV, the total impedance is set to 50Ω using the resonant section LCM. As shown in RX in Figure 5, the reflected continuous wave has a peak amplitude VRFPP1 relative to the incident continuous wave TX and is terminated, and hardly returns to the transmit / receive circuit.

[0060] When no readout current is output from the charge sensor, if the peak amplitude of the reflected continuous wave is VRPP, then the relationship VRPP > VREFPP1 makes it possible to detect the qubit state on the transmitting / receiving circuit side. On the other hand, when the qubit storage element of interest holds an up-spin, the second readout operation is controlled in the same way as the first readout operation so that the corresponding charge sensor (SETn) is selected. In the case of the second operation, the readout current from the charge sensor SETn is small, and the output current is converted to only a small voltage. As a result, the input continuous wave from the transmitting / receiving circuit is not terminated and returns to the transmitting / receiving circuit as a reflected continuous wave. In this example, the peak amplitude of the reflected wave is VRFPP2, and since the relationship VRPP < VRFP2 holds, it is possible to detect the qubit state on the transmitting / receiving circuit.

[0061] In the example shown in Figure 5, the quantum bit state is detected by comparing the amplitude values ​​of the reflected continuous wave. However, it goes without saying that the phase shift of the reflected continuous wave could also be detected, or the quantum bit state could be determined by comparing and detecting both amplitude and phase information.

[0062] Figure 6 is a cross-sectional view of a substrate mounting of a control chip QBG, which integrates all or part of the qubit array section QBA, the conversion circuit CONV, the resonant section LCM, and the circuits for operating the qubit gates, as described in the embodiments of Figures 1 to 5, as a single LSI chip. In order for the conversion circuit section CONV to absorb power loss when power is applied, the conversion circuit section CONV and the qubit array section QBA are configured as separate LSI chips and mounted in a way that thermally separates them.

[0063] The qubit array section QBA and the control chip QBG, formed as semiconductor chips, are mounted on a cooling plate FGNDPLT. The cooling plate FGNDPLT is thermally connected to a metal plate MXC via two cooling rods C1 and C3. The printed circuit board QFRP on the cooling plate FGNDPLT is fixed to the cooling plate FGNDPLT using, for example, non-magnetic screws SCR1 and SCR3.

[0064] The QFRP printed circuit board is electrically connected to connectors (not shown) for connecting coaxial wiring (CXEO) and twisted wires using solder or similar materials. The electrical signals input to multiple pins in the connector of the coaxial wiring (CXEO) are routed through multiple metal wiring patterns (Cu patterns), such as copper (Cu), formed within the multilayer substrate of the QFRP printed circuit board, to the die bond area near the chip of the qubit array (QBA) and the control chip (QBG). Multiple pins in each connector are connected to multiple metal wiring patterns, respectively.

[0065] The chips of the qubit array (QBA) and control chip (QBG) are bonded to a die bond area inside the QFRP printed circuit board using a reflow soldering machine after applying solder material or silver paste to the back surface of the chip. The metal pads (also called aluminum pads) that are electrodes on the chips of the qubit array (QBA) and control chip (QBG) and the Cu patterns on the QFRP printed circuit board are electrically and thermally connected using metal lead frames (hereinafter referred to as metal leads) LDs created on the QFRP printed circuit board side.

[0066] The cooling pad FGND, which is an electrode on the qubit array section QBA and the control chip QBG, and the cooling plate QBAPLT, which is made of metal (mainly oxygen-free copper), are electrically and thermally connected using a metal lead LD. A ground potential is applied to the cooling pad FGND. This metal lead LD is electrically and thermally connected to the aluminum pad PAD formed on the qubit array section QBA and the control chip QBG by applying a predetermined torque to the non-magnetic screws SCRW1 and SCRW3.

[0067] Furthermore, the printed circuit board QFRP on the back surface of the qubit array section QBA and the control chip QBG forms multiple through-holes (through-vias). In this way, the ground potential on the back surface of the qubit array section QBA and the control chip QBG is electrically and thermally connected to the cooling plate (second cooling plate) QBAPLT via the through-vias.

[0068] When the metal plate MXC (shown in Figures 1 and 9) is exposed to an extremely low temperature atmosphere, the resin layers of the metal plates, such as the cooling plate (first cooling plate) FGNDPLT and the cooling plate QBAPLT, and the printed circuit board QFRP shrink at a certain rate. Because the temperature dependence of the shrinkage rate differs depending on the material, in some cases the metal lead LD and the aluminum pads PAD of the qubit array QBA and control chip QBG may physically separate, potentially leading to a loss of electrical and thermal connection. To prevent this situation, in this embodiment, a metal pin SPR with a spring structure is placed between the cooling plate QBAPLT and the cooling plate FGNDPLT. In addition, an alignment plate ALIPLT is provided to adjust the positions of the cooling plate QBAPLT and the cooling plate FGNDPLT, so as to cover the outer circumference of the cooling plate QBAPLT.

[0069] With this structure, when the metal plate MXC is cooled from room temperature to cryogenic temperatures, if the distance between the cooling plate QBAPLT and the cooling plate FGNDPLT increases, the metal pin SPR extends, reducing the distance so that contact between the metal lead LD and the aluminum pad PAD is not lost. This configuration makes it possible to efficiently cool the qubit array QBA and the control chip QBG from the chip surface.

[0070] Although the explanation is omitted, the qubit array (QBA) and control chip (QBG) are formed using silicon semiconductors. Silicon is known to have a much lower thermal conductivity than metals at extremely low temperatures. Therefore, it may be difficult to dissipate heat from the back surface (Si sub) of the qubit array (QBA) and control chip (QBG). Even in such cases, the structure of this embodiment allows for heat dissipation paths from both the front and back surfaces of the qubit array (QBA) chip, thus maintaining the extremely low temperature necessary for quantum operation.

[0071] Figure 7 is a cross-sectional view of a substrate mounting of another embodiment of the control chip QBG, which integrates the qubit array section QBA and the reflection section (excluding the qubit array section QBA) described in Figures 1 to 5 into a single LSI chip.

[0072] The difference from Figure 6 is that the qubit array section QBA and the control chip QBG, which are configured as quantum semiconductor chips, are mounted three-dimensionally. In this embodiment, the control chip QBG is thermally connected to the cooling plate QBGPLT via through-vias, and the control chip QBG and the qubit array section QBA are electrically connected by direct bonding DBD (for example, connecting the chips with Cu wiring).

[0073] Furthermore, direct bonding DBDs are electrically connected with a resistance value that does not reduce the electrical signal transfer speed between chips, but they are not thermally connected, and it is preferable to have a configuration with high thermal resistance. For example, superconducting materials may be used in the sense of thermal separation. The qubit array (QBA) is thermally connected to the cooling plate (QBAPLT). The cooling plate (QBAPLT) is thermally connected to the cooling plate (FGNDPLT) via non-magnetic screw (SCRW).

[0074] With the above configuration, even if heat is generated due to the operation of transistor elements within the control chip QBG, including the resonant LCM (reflector) and the conversion circuit CONV (conversion circuit), the heat within the control chip QBG propagates through the through-vias (Via), cooling plate QBGPLT, metal pins SPR, and cooling plate FGNDPLT, making it difficult for the heat to propagate to the qubit array QBA (QBA). Therefore, the spin states held in the qubit storage elements within the qubit array QBA can continue stable quantum operations without being affected by thermal disturbance noise. In other words, by applying the readout method and implementation method of this embodiment together, high-precision and stable quantum computation and its readout operation become possible.

[0075] Figure 8 shows the connection relationships between the quantum bit array unit QBA configured as a quantum semiconductor in the embodiment, the control chip QBG for controlling the quantum bit array unit QBA, the analog chip CAC which inputs control signals to control the quantum bit array unit QBA and the control chip QBG, and the digital processing unit CDU which inputs control signals to control the analog chip CAC.

[0076] The analog chip CAC, which includes the transmit / receive circuit TXRXCKT, the qubit array section QBA, and the control chip QBG are kept at low temperatures within a dilution refrigerator. In particular, it is desirable to place the qubit array section QBA and the control chip QBG close to the lowest temperature environment (~1K) within the dilution refrigerator.

[0077] By logically and electrically connecting these components, a quantum computer is constructed as a whole system. It is preferable to construct the analog chip CAC using a classical computer, i.e., an integrated LSI using the so-called CMOS process.

[0078] The transmit / receive circuit TXRXCKT shown in Figures 1 and 4 is best configured as the analog chip CAC. Similarly, the digital processing unit CDU is preferably a processing unit utilizing a semiconductor chip with a CMOS process, just like the analog chip CAC. Simply put, the digital processing unit CDU can be a general-purpose personal computer (PC). It is also possible to use a PC with a software module that generates the desired control signals.

[0079] Figure 9 shows an implementation method using a quantum bit array unit QBA, a control chip QBG, an analog chip CAC including a transmit / receive circuit TXRXCKT, a digital processing unit CDU, and a dilution refrigerator 10 according to an embodiment.

[0080] The dilution refrigerator 10 is separated from the ambient air outside the refrigerator 10 by a housing frame and a room temperature plate RT-PL to separate the vacuum atmosphere inside the refrigerator 10. The vacuum level inside the housing frame of the dilution refrigerator 10 is controlled by using a pump device installed outside the refrigerator 10 to expel air through a vacuum tube VC. Temperature control inside the dilution refrigerator 10 is achieved by circulating diluted liquid helium through a pulse tube shown in Figure 9. Figure 9 shows an example where two pulse tubes are connected. Diluted liquid helium refers to two isotopes of helium. 3 He and 4 He was liquefied, 3 He 4 This is the result of pouring it into the He phase and diluting it.

[0081] In the example of the dilution refrigerator 10 shown in Figure 9, multiple metal (mainly oxygen-free copper) plates (50K-PL (set to -223°C), 4KP (set to -269°C), PLA, PLB, MXC (set to approximately -273°C)) are installed and housed inside the housing frame of the dilution refrigerator 10. The metal plates PLA and PLB are controlled to temperatures between 4K (-269°C) and mK (approximately -273°C). The temperature control is configured to control and maintain thermal equilibrium using temperature control heaters (not shown) mounted on each plate (50K-PL, 4KP, PLA, PLB, MXC) and a temperature controller (not shown) installed outside the dilution refrigerator 10 that controls the amount of power supplied to the temperature control heaters.

[0082] In the example shown in Figure 9, diluted liquid helium is circulated from the pulse tube to the heatsink. As a result, the metal plates 4KP and MXC, to which the heatsink is connected, are brought to an extremely low temperature via the circulating diluted liquid helium in the heatsink. Therefore, the metal plates 4KP and MXC can be brought to an extremely low temperature atmosphere of 10mK to 100mK.

[0083] The heatsink can be considered the first cooling tube, and the pulse tube the second cooling tube. Similarly, the metal plate MXC can be considered the first metal plate, and the metal plate 4KP the second metal plate. The qubit array section QBA and the control chip QBG are mounted below the metal plate MXC, on top of the first cooling plate FGNDPLT. The cooling plate FGNDPLT is thermally connected to the metal plate MXC via cooling rods C0 to C3 (even-numbered cooling rods C0 and C2 are not shown). In other words, the heatsink is a cooling tube that cools the metal cooling plate FGNDPLT using diluted liquid helium. The metal cooling plate FGNDPLT is thermally connected to the metal plate MXC via cooling rods C0 to C3.

[0084] In this embodiment, the reason why the qubit array unit QBA and the control chip QBG are not directly mounted on the metal plate MXC but are placed below the metal plate MXC is to allow quantum operation to be performed while a static magnetic field is applied to the qubit array unit QBA. Due to space constraints for placing the magnet MAGNET for generating the static magnetic field at the bottom layer of the dilution refrigerator 10, the qubit array unit QBA and the control chip QBG are arranged as shown in Figure 9 in the configuration example of the dilution refrigerator 10 in this embodiment.

[0085] Furthermore, the electrical signals necessary to perform quantum operation on the qubit array section QBA, which is configured as a quantum semiconductor, are output from a control device (not shown) installed outside the dilution refrigerator 10. The control signals are electrically connected to the qubit array section QBA and the control chip QBG via coaxial wiring CXE and CXO, while the power supply voltage and power supply current are electrically connected via DC twisted wiring. By implementing the above configuration, quantum operations and quantum computers as described in Figures 1 to 8 can be realized.

[0086] The readout method using reflected waves disclosed in Patent Document 1 can achieve a faster readout speed compared to a method that transfers the output current of a charge sensor to a measuring instrument outside the dilution refrigerator using a current-voltage conversion circuit placed in a cryogenic atmosphere. This is because, in the above method, the physical distance from the cryogenic atmosphere to the room temperature atmosphere inside the refrigerator is large, and for example, the parasitic capacitance (100 pF / m) of the coaxial wiring inside the refrigerator becomes large, slowing down the data transfer speed.

[0087] On the other hand, in readout methods that utilize reflected waves, the same number of resonant circuits as the SET used for reading out the qubits are required, and if the tolerances between the circuits are large, the readout accuracy will decrease. In this embodiment, by impedance conversion of the output current of the SET using a conversion circuit, the constant of the inductor LM of the resonant circuit can be reduced to the order of nH, and the constant of the parasitic capacitance CBB can be reduced to less than pF. Therefore, the resonant section LCM can be formed with high processing accuracy using a normal semiconductor process, and the tolerances can be reduced to improve readout accuracy.

[0088] Although the present invention has been specifically described above based on embodiments, it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from its essence.

[0089] The embodiments described above are explained in detail for the purpose of clearly illustrating the present invention, and are not necessarily limited to those comprising all the configurations described. Furthermore, it is possible to add, delete, or replace some of the configurations in the embodiments with other configurations.

[0090] Furthermore, although the above embodiment described an example using a silicon quantum semiconductor, the present invention is not limited to this and can also be applied to superconducting quantum semiconductors and the like.

[0091] According to the above embodiment, a quantum computer using semiconductor elements can be realized, resulting in lower energy consumption, reduced carbon emissions, prevention of global warming, and contribution to the realization of a sustainable society.

[0092] Quantum bit array section QBA, conversion circuit section CONV, resonant section LCM, transmit / receive circuit section TXRXCKT

Claims

1. A quantum semiconductor circuit for reading the state of a qubit, comprising: a transmission circuit that outputs a transmission wave having a predetermined frequency and power to a reflector; a transistor that constitutes a part of the reflector and determines the state of the qubit; a conversion circuit that converts the impedance of the reflector based on the state of the qubit; and a receiving circuit that receives a reflected wave from the reflector where the transmission wave has been reflected, wherein the state of the qubit is read based on the reflected wave.

2. The quantum semiconductor circuit according to claim 1, characterized in that the conversion circuit amplifies the impedance difference of the charge sensor based on the state of the qubit.

3. The conversion circuit according to claim 2 is a quantum semiconductor circuit having a plurality of current-voltage conversion units that convert the output current of the charge sensor into a voltage, a voltage amplification unit, and a selection circuit that reduces a plurality of voltage signals arranged between the plurality of current-voltage conversion units and the voltage amplification unit to 1 / N.

4. The quantum semiconductor circuit according to claim 2, wherein the conversion circuit is mounted on a control chip, and the qubit and the charge sensor are mounted on a quantum chip independent of the control chip.

5. The quantum semiconductor circuit in claim 4, wherein the control chip and the quantum chip are mounted in different locations on the same substrate.

6. The quantum semiconductor circuit in claim 4, wherein the control chip and the quantum chip are stacked and mounted at predetermined locations on the same substrate.

7. The quantum semiconductor circuit according to claim 3, wherein the voltage amplification section is composed of a differential amplification stage and an output stage, the current-voltage conversion section has a capacitive resistor section in which the voltage amplification section, a gain resistor and a feedback capacitor are connected in parallel, and the voltage amplification section and the capacitive resistor section are connected in series.

8. The quantum semiconductor circuit according to claim 3, wherein the operating cycle speed of the current-voltage conversion unit and the selection circuit is N times faster than the operating cycle speed of the voltage amplification unit, and N is the denominator of the coefficient that reduces the voltage signal to 1 / N.

9. The quantum semiconductor circuit according to claim 4, having an inductor L and a capacitor C for impedance matching, wherein the transmitted wave is terminated by the conversion circuit, the inductor and the capacitor.

10. The quantum semiconductor circuit according to claim 8, wherein the control chip has a variable capacitance Cvar separate from the capacitor C, and the capacitance value of the variable capacitance Cvar is adjusted by changing the voltage across the variable capacitance Cvar.

11. The variable capacitance Cvar in claim 10 is a quantum semiconductor circuit disposed between the inductor L and the conversion circuit.

12. A method for reading out the spin state of a charged particle stored in a qubit array configured as a semiconductor integrated circuit, comprising: a reading step of detecting the difference in spin state as a difference in charge using a charge sensor and generating a readout output signal; a conversion step of converting the output impedance of the charge sensor using a conversion circuit; and a detection step of transmitting a predetermined signal in the direction of the charge sensor, receiving a reflected wave reflected from the direction of the charge sensor, and detecting the difference in spin state based on the reflected wave.

13. The method for reading out a qubit according to claim 12, wherein the conversion step converts the output impedance to an impedance lower than the output impedance of the charge sensor alone.

14. A method for reading out a qubit, using the conversion circuit configured as a semiconductor integrated circuit according to claim 13.

15. A method for reading out a qubit according to claim 14, wherein the charge sensor and the conversion circuit are further configured with a resonant circuit configured as a semiconductor integrated circuit, and the conversion step reduces the passive circuit constant of the resonant circuit by converting the output impedance to an impedance lower than the output impedance of the charge sensor alone.

Images