Printed wiring board

Abstract

This printed wiring board comprises a first conductor layer, a second conductor layer, a plurality of dielectric layers, and at least one third conductor layer. The plurality of dielectric layers are disposed between the first conductor layer and the second conductor layer. Each third conductor layer is disposed between two adjacent layers of the plurality of dielectric layers. The first conductor layer has a first signal pattern. The second conductor layer has a second signal pattern. Each third conductor layer has a third signal pattern. The first signal pattern, the second signal pattern, and the third signal pattern all extend along a first direction. The first signal pattern, the second signal pattern, and the third signal pattern of each of the at least one third conductor layer are electrically connected to each other to form one signal line. In a second direction perpendicular to the first direction, the width of the first signal pattern and the width of the second signal pattern are larger than the width of the third signal pattern.

Description

Printed wiring board

[0001] The present disclosure relates to a printed wiring board.

[0002] The printed wiring board described in Japanese Patent Application Laid-Open No. 2000-216603 (Patent Document 1) has a dielectric layer and a first signal pattern. The first dielectric layer has a first main surface and a second main surface that is opposite to the first main surface. The signal pattern is disposed on the first main surface. A high-frequency signal flows through the signal pattern.

[0003] Japanese Patent Application Laid-Open No. 2000-216603

[0004] The printed wiring board of the present disclosure includes a first conductor layer, a second conductor layer, a plurality of dielectric layers, and at least one third conductor layer. The plurality of dielectric layers are disposed between the first conductor layer and the second conductor layer. Each of the at least one third conductor layer is disposed between two adjacent layers among the plurality of dielectric layers. The first conductor layer has a first signal pattern. The first signal pattern extends along a first direction in a plan view. The second conductor layer has a second signal pattern. The second signal pattern extends along the first direction. Each of the at least one third conductor layer has a third signal pattern. The third signal pattern extends along the first direction. The first signal pattern, the second signal pattern, and the third signal pattern of each of the at least one third conductor layer are electrically connected to each other to form one signal line. In a second direction perpendicular to the first direction, the widths of the first signal pattern and the second signal pattern are larger than the width of the third signal pattern.

[0005] Figure 1 is a first plan view of the printed circuit board 100. Figure 2 is a bottom view of the printed circuit board 100. Figure 3 is a second plan view of the printed circuit board 100. Figure 4 is a cross-sectional view taken along line IV-IV in Figure 1. Figure 5 is a manufacturing process diagram of the printed circuit board 100. Figure 6 is a cross-sectional view illustrating the preparation process S1. Figure 7 is a cross-sectional view illustrating the patterning process S2. Figure 8 is a cross-sectional view illustrating the connection conductor layer formation process S3. Figure 9 is a cross-sectional view illustrating the dielectric layer attachment process S4. Figure 10 is a cross-sectional view illustrating the patterning process S5. Figure 11 is a cross-sectional view illustrating the connection conductor layer formation process S6. Figure 12 is a cross-sectional view illustrating the dielectric layer attachment process S7. Figure 13 is a cross-sectional view illustrating the patterning process S8. Figure 14 is a first plan view of the printed circuit board 200. Figure 15 is a bottom view of the printed circuit board 200. Figure 16 is a second plan view of the printed circuit board 200. Figure 17 shows the simulation results illustrating the relationship between the frequency of a high-frequency signal flowing through a signal line and the reflection loss. Figure 18 is a cross-sectional view of a modified printed circuit board 100.

[0006] [Problems this disclosure aims to solve] When attempting to create a multilayer printed circuit board, it is necessary to form through-holes that penetrate each of the multiple dielectric layers and to form connecting conductive layers within these through-holes to connect the signal patterns. In this case, the connection points between signal patterns can become reflection points for high-frequency signals, which can degrade the transmission characteristics of the signal lines. This disclosure provides a printed circuit board that can suppress the reflection of high-frequency signals at the connection points between signal patterns.

[0007] [Effects of this disclosure] According to the printed circuit board of this disclosure, reflection of high-frequency signals at connection points between signal patterns can be suppressed.

[0008] [Summary of Embodiments] First, embodiments of the present disclosure are listed below.

[0009] (1) The printed circuit board according to the embodiment comprises a first conductor layer, a second conductor layer, a plurality of dielectric layers, and at least one third conductor layer. The plurality of dielectric layers are arranged between the first conductor layer and the second conductor layer. Each of the at least one third conductor layer is arranged between two adjacent layers of the plurality of dielectric layers. The first conductor layer has a first signal pattern. The first signal pattern extends along a first direction in a plan view. The second conductor layer has a second signal pattern. The second signal pattern extends along a first direction. Each of the at least one third conductor layer has a third signal pattern. The third signal pattern extends along a first direction. The first signal pattern, the second signal pattern, and the third signal pattern of each of the at least one third conductor layer are electrically connected to each other to form a single signal line. In a second direction perpendicular to the first direction, the widths of the first signal pattern and the second signal pattern are greater than the width of the third signal pattern. According to the printed circuit board described in (1) above, reflection of high-frequency signals at connection points between signal patterns can be suppressed.

[0010] (2) In the printed circuit board described in (1) above, the at least one third conductor layer may be multiple third conductor layers.

[0011] (3) In the printed circuit board described in (2) above, the first conductor layer may further have a first land connected to the end of the first signal pattern in the first direction. The second conductor layer may further have a second land connected to the end of the second signal pattern in the first direction. Each of the plurality of third conductor layers may further have a third land connected to one end of the third signal pattern in the first direction and a fourth land connected to the other end of the third signal pattern in the first direction. The first land and the second land may overlap with the third land of the lowest layer and the fourth land of the uppermost layer of the plurality of third conductor layers, respectively, in a plan view. The fourth land of one of two adjacent layers of the plurality of third conductor layers may overlap with the third land of the other of two adjacent layers of the plurality of third conductor layers, in a plan view.

[0012] (4) In the printed circuit boards described in (1) to (3) above, the value obtained by subtracting the width of the third signal pattern from the width of the first signal pattern in the second direction may be 25 μm or more.

[0013] [Details of Embodiments] Next, the details of embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and redundant descriptions will not be repeated. The printed circuit board according to the embodiment will be referred to as printed circuit board 100.

[0014] Figure 1 is a first plan view of the printed circuit board 100. Figure 2 is a bottom view of the printed circuit board 100. In Figure 2, the dielectric layer 60 and the conductor layer 70 are omitted from the illustration. Figure 3 is a second plan view of the printed circuit board 100. In Figure 3, the conductor layer 20 and the dielectric layer 30C are omitted from the illustration. Figure 4 is a cross-sectional view taken along IV-IV in Figure 1. As shown in Figures 1 to 4, the printed circuit board 100 has a conductor layer 10, a conductor layer 20, a plurality of dielectric layers 30, and a plurality of conductor layers 40. In the example shown in Figures 1 to 4, the number of dielectric layers 30 is 3, and the number of conductor layers 40 is 2.

[0015] Multiple dielectric layers 30 are arranged between the conductor layer 10 and the conductor layer 20. Multiple conductor layers 40 are arranged between two adjacent layers of the multiple dielectric layers 30. In the example shown in Figures 1 to 4, the bottommost layer of the multiple dielectric layers 30 is defined as dielectric layer 30A. The topmost layer of the multiple dielectric layers 30 is defined as dielectric layer 30C. The layer located between dielectric layer 30A and dielectric layer 30C is defined as dielectric layer 30B. In the example shown in Figures 1 to 4, the bottommost layer of the multiple conductor layers 40 is defined as conductor layer 40A. The topmost layer of the multiple conductor layers 40 is defined as conductor layer 40B.

[0016] Each of the multiple dielectric layers 30 has a main surface 30a and a main surface 30b. The main surface 30b is the opposite surface to the main surface 30a. The main surfaces 30a and 30b form the end faces of the dielectric layer 30 in the thickness direction. A conductor layer 10 is arranged on the main surface 30b of dielectric layer 30A. A conductor layer 40A is arranged on the main surface 30a of dielectric layer 30B.

[0017] Each dielectric layer 30B and dielectric layer 30C has a first layer 31 and a second layer 32. The first layer 31 is formed of an adhesive. The second layer 32 is disposed on the first layer 31. The second layer 32 forms the main surface 30a, and the first layer 31 forms the main surface 30b. The second layer 32 is formed of, for example, a fluororesin. The first layer 31 of dielectric layer 30B is disposed on the main surface 30a of dielectric layer 30A so as to cover the conductor layer 40A. The conductor layer 40B is disposed on the main surface 30a of dielectric layer 30B. The first layer 31 of dielectric layer 30C is disposed on the main surface 30a of dielectric layer 30B so as to cover the conductor layer 40B. The conductor layer 20 is disposed on the main surface 30a of dielectric layer 30C.

[0018] Each of the conductive layer 10, conductive layer 20, and the plurality of conductive layers 40 is formed of, for example, copper or a copper alloy.

[0019] The conductor layer 10 has a signal pattern 11, lands 12, and a ground pattern 13. In a plan view, the signal pattern 11 extends along a first direction DR1. The lands 12 are connected to the ends of the signal pattern 11 in the first direction DR1. In a plan view, the ground pattern 13 surrounds the signal pattern 11 and the lands 12. There is a gap between the ground pattern 13 and the signal pattern 11 and the lands 12.

[0020] The conductor layer 20 has a signal pattern 21, lands 22, and a ground pattern 23. In a plan view, the signal pattern 21 extends along a first direction DR1. The lands 22 are connected to the ends of the signal pattern 21 in the first direction DR1. In a plan view, the ground pattern 23 surrounds the signal pattern 21 and the lands 22. There is a gap between the ground pattern 23 and the signal pattern 21 and the lands 22.

[0021] Each of the multiple conductor layers 40 has a signal pattern 41, lands 42 and lands 43, and a ground pattern 44. The signal pattern 41 extends along a first direction DR1 in a plan view. Land 42 is connected to one end of the signal pattern 41 in the first direction DR1, and land 43 is connected to the other end of the signal pattern 41 in the first direction DR1. The ground pattern 44 surrounds the signal pattern 41, lands 42 and lands 43 in a plan view. There is a gap between the ground pattern 44 and the signal pattern 41, lands 42 and lands 43.

[0022] Land 12 overlaps with land 42 of the lowest layer among the multiple conductor layers 40 in a plan view. Land 22 overlaps with land 43 of the uppermost layer among the multiple conductor layers 40 in a plan view. Land 43 of one of two adjacent layers among the multiple conductor layers 40 overlaps with land 42 of the other of those two layers. More specifically, land 12 overlaps with land 42 of conductor layer 40A in a plan view, and land 22 overlaps with land 43 of conductor layer 40B in a plan view. Also, land 43 of conductor layer 40A overlaps with land 42 of conductor layer 40B in a plan view.

[0023] Through-holes 50 are formed in the dielectric layer 30 and land 12 located between the conductor layer 10 and the bottommost layer among the multiple conductor layers 40. Through-holes 51 are formed in the dielectric layer 30 and land 22 located between the conductor layer 20 and the topmost layer among the multiple conductor layers 40. Through-holes 52 are formed in the dielectric layer 30 and land 42 located between two adjacent layers among the multiple conductor layers 40. More specifically, through-holes 50 are formed in dielectric layer 30A and land 12, through-holes 51 are formed in dielectric layer 30C and land 22, and through-holes 52 are formed in dielectric layer 30B and land 42.

[0024] The printed circuit board 100 has a plurality of connecting conductor layers 53. The connecting conductor layers 53 are arranged in through holes 50, through holes 51, and through holes 52. The connecting conductor layers 53 are also arranged on lands 12 located around through holes 50, on lands 22 located around through holes 51, and on lands 42 located around through holes 52. The connecting conductor layers 53 are made of, for example, copper or a copper alloy. The land 12 is electrically connected to the land 42 of the lowest layer of the plurality of conductor layers 40, the land 22 is electrically connected to the land 43 of the uppermost layer of the plurality of conductor layers 40, and the land 43 of one of two adjacent layers of the plurality of conductor layers 40 is electrically connected to the other land 42 of those two layers. As a result, the signal pattern 11, the signal pattern 21, and each signal pattern 41 of the plurality of conductor layers 40 are electrically connected to each other and form a single signal line. This signal line may be a single signal line or one of a pair of differential signal lines.

[0025] The printed circuit board 100 may further include a dielectric layer 60 and a conductor layer 70. The dielectric layer 60 has a main surface 60a and a main surface 60b. The main surface 60b is the opposite surface of the main surface 60a. The main surfaces 60a and 60b form the end faces in the thickness direction of the dielectric layer 60. The dielectric layer 60 has a first layer 61 and a second layer 62. The second layer 62 is disposed on the first layer 61. The first layer 61 forms the main surface 60b, and the second layer 62 forms the main surface 60a. The first layer 61 is formed of an adhesive. The second layer 62 is formed of, for example, a fluororesin.

[0026] The conductor layer 70 is arranged on the main surface 60a. The conductor layer 70 is made of, for example, copper or a copper alloy. The conductor layer 70 has a ground pattern 71. The ground pattern 71 includes a plurality of parts. At least one of the plurality of parts included in the ground pattern 71 is arranged so as not to overlap in plan view with at least one of the connecting conductor layers 53 that connect land 12 and land 42, the connecting conductor layer 53 that electrically connects land 22 and land 43, and the connecting conductor layer 53 that electrically connects land 42 and land 43. Figure 4 shows a first part 71a and a second part 71b as the plurality of parts included in the ground pattern 71. The first part 71a is arranged so as not to overlap with any of the connecting conductor layers 53 in plan view. The second portion 71b overlaps with the connecting conductor layer 53 that electrically connects land 22 and land 43 in a plan view, and with the connecting conductor layer 53 that electrically connects land 42 and land 43, but is positioned so as not to overlap with the connecting conductor layer 53 that electrically connects land 12 and land 42 in a plan view.

[0027] To put this from another perspective, the ground pattern 71 has an opening 72, and in plan view, the opening 72 overlaps with at least one of the connecting conductor layers 53 that connect land 12 and land 42, the connecting conductor layer 53 that electrically connects land 22 and land 43, and the connecting conductor layer 53 that electrically connects land 42 and land 43. In plan view, the opening 72 may have the same shape as the connecting conductor layer 53 or a different shape. Also, the dimensions of the opening 72 in plan view should be greater than or equal to the dimensions of the connecting conductor layer 53 in plan view.

[0028] In a plan view, the direction perpendicular to the first direction DR1 is defined as the second direction DR2. The width of the signal pattern 11 in the second direction DR2 is defined as width W1. The width of the signal pattern 21 in the second direction DR2 is defined as width W2, and the width of the signal pattern 41 in the second direction DR2 is defined as width W3. Widths W1 and W2 are greater than width W3. To put this in other terms, width W3 is smaller than widths W1 and W2. The value obtained by subtracting width W3 from width W1 (or subtracting width W3 from width W2) is, for example, 25 μm or more. The value obtained by subtracting width W3 from width W1 (or subtracting width W3 from width W2) may be 50 μm or more, 75 μm or more, or 100 μm or more. The value obtained by subtracting width W3 from width W1 (or width W3 from width W2) is, for example, 125 μm or more.

[0029] (Method for manufacturing the printed circuit board 100) The method for manufacturing the printed circuit board 100 will be described below.

[0030] Figure 5 is a diagram illustrating the manufacturing process of the printed circuit board 100. As shown in Figure 5, the manufacturing method of the printed circuit board 100 includes a preparation step S1, a patterning step S2, a connecting conductor layer formation step S3, a dielectric layer attachment step S4, a patterning step S5, a connecting conductor layer formation step S6, a dielectric layer attachment step S7, a patterning step S8, and a connecting conductor layer formation step S9.

[0031] Figure 6 is a cross-sectional view illustrating the preparation step S1. In the preparation step S1, the dielectric layer 30A is prepared as shown in Figure 6. At this stage, the dielectric layer 30A has a conductive layer 10 on the main surface 30b and a conductive layer 40A on the main surface 30a. After the preparation step S1, the patterning step S2 is performed.

[0032] Figure 7 is a cross-sectional view illustrating the patterning process S2. In the patterning process S2, as shown in Figure 7, the conductor layer 10 is patterned to form a signal pattern 11, a land 12, and a ground pattern 13. In the patterning process S2, firstly, a resist pattern having openings is formed on the conductor layer 10. The resist pattern is formed by exposing and developing a dry film resist attached to the conductor layer 10. Secondly, etching is performed on the conductor layer 10 through the openings in the resist pattern. In the patterning process S2, the dielectric layer 30A is patterned in a similar manner to form a signal pattern 41, a land 42, a land 43, and a ground pattern 44. After the patterning process S2, the connecting conductor layer formation process S3 is performed.

[0033] Figure 8 is a cross-sectional view illustrating the connecting conductor layer formation process S3. In the connecting conductor layer formation process S3, a connecting conductor layer 53 is formed as shown in Figure 8. In the connecting conductor layer formation process S3, firstly, through holes 50 are formed. The through holes 50 are formed, for example, by laser processing. Secondly, the connecting conductor layer 53 is formed on the lands 12 located inside and around the through holes 50 by, for example, electroless plating. After the connecting conductor layer formation process S3, a dielectric layer attachment process S4 is performed.

[0034] Figure 9 is a cross-sectional view illustrating the dielectric layer attachment process S4. In the dielectric layer attachment process S4, as shown in Figure 9, the dielectric layer 30B is attached to the main surface 30a of the dielectric layer 30A so as to cover the conductive layer 40A, and the dielectric layer 60 is attached to the main surface 30b of the dielectric layer 30B so as to cover the conductive layer 10. In the dielectric layer attachment process S4, firstly, the dielectric layer 30B and the dielectric layer 60 are prepared. At this stage, the dielectric layer 30B has the conductive layer 40B on its main surface 30a, and the dielectric layer 60 has the conductive layer 70 on its main surface 60a. At this stage, the first layer 31 of the dielectric layer 30B and the first layer 61 of the dielectric layer 60 are uncured.

[0035] Secondly, a dielectric layer 30B is placed on the main surface 30a of the dielectric layer 30A such that the first layer 31 covers the conductor layer 40A, and a dielectric layer 60 is placed on the main surface 30b of the dielectric layer 30A such that the first layer 61 covers the conductor layer 10. Thirdly, the dielectric layer 30B and the dielectric layer 60 are hot-pressed onto the dielectric layer 30A. This hardens the first layer 31 and the first layer 61, and the dielectric layer 30B and the dielectric layer 60 are attached to the dielectric layer 30A. After the dielectric layer attachment process S4, a patterning process S5 is performed.

[0036] Figure 10 is a cross-sectional view illustrating the patterning process S5. In the patterning process S5, as shown in Figure 10, the conductor layer 40B is patterned to form the signal pattern 41, lands 42, lands 43, and ground pattern 44, and the conductor layer 70 is patterned to form the opening 72. The patterning of the conductor layer 40B and the conductor layer 70 is performed in the same manner as in the patterning process S2. After the patterning process S5, the connecting conductor layer formation process S6 is performed.

[0037] Figure 11 is a cross-sectional view illustrating the connecting conductor layer formation process S6. In the connecting conductor layer formation process S6, as shown in Figure 11, through holes 52 are formed in the same manner as in the connecting conductor layer formation process S3, and a connecting conductor layer 53 is formed inside the through holes 52 and on the lands 43 located around the through holes 52. After the connecting conductor layer formation process S6, the dielectric layer attachment process S7 is performed. Figure 12 is a cross-sectional view illustrating the dielectric layer attachment process S7. In the dielectric layer attachment process S7, as shown in Figure 12, the dielectric layer 30C is attached to the dielectric layer 30B in the same manner as in the dielectric layer attachment process S4. After the dielectric layer attachment process S7, the patterning process S8 is performed.

[0038] Figure 13 is a cross-sectional view illustrating the patterning process S8. In the patterning process S8, as shown in Figure 13, the conductor layer 20 is patterned to form the signal pattern 21, land 22, and ground pattern 23. The patterning of the conductor layer 20 is performed in the same manner as in the patterning process S2. After the patterning process S8, the connecting conductor layer formation process S9 is performed.

[0039] In the connecting conductor layer formation step S9, through holes 51 are formed in the same manner as in the connecting conductor layer formation step S3, and connecting conductor layers 53 are formed inside the through holes 51 and on the lands 22 located around the through holes 51. This completes the formation of the printed circuit board 100 shown in Figures 1 to 4.

[0040] (Effects of Printed Wiring Board 100) The effects of printed wiring board 100 will be explained below in comparison with the printed wiring board of the comparative example. The printed wiring board of the comparative example will be referred to as printed wiring board 200.

[0041] Figure 14 is a first plan view of the printed circuit board 200. Figure 15 is a bottom view of the printed circuit board 200. Note that the dielectric layer 60 and the conductor layer 70 are not shown in Figure 15. Figure 16 is a second plan view of the printed circuit board 200. Note that the conductor layer 20 and the dielectric layer 30C are not shown in Figure 16. As shown in Figures 14 to 16, in the printed circuit board 200, the width W3 is equal to the widths W1 and W2. In other respects, the configuration of the printed circuit board 200 is the same as that of the printed circuit board 100.

[0042] In the printed circuit board 100, the signal line, composed of signal pattern 11, signal pattern 21, signal pattern 41 of conductor layer 40A, and signal pattern 41 of conductor layer 40B, suffers from impedance mismatch at the connection points between signal pattern 11 and signal pattern 41 of conductor layer 40A, between signal pattern 41 of conductor layer 40A and signal pattern 41 of conductor layer 40B, and between signal pattern 41 of conductor layer 40B and signal pattern 21. As a result, these connection points become reflection points for high-frequency signals, degrading the transmission characteristics. On the other hand, in the printed circuit board 100, the width W3 is smaller than the widths W1 and W2. Therefore, the impedance mismatch described above is mitigated. As a result, the transmission characteristics of the signal line are improved in the printed circuit board 100.

[0043] Figure 17 shows the simulation results illustrating the relationship between the frequency of a high-frequency signal flowing through a signal line and the reflection loss. In samples 1 through 4, the width W3 is smaller than the widths W1 and W2. In sample 5, the width W3 is equal to the widths W1 and W2. That is, samples 1 through 4 correspond to printed circuit board 100, and sample 5 corresponds to printed circuit board 200. As shown in Figure 17, the reflection loss of samples 1 through 4 is smaller than the reflection loss of sample 5. From this, it can be seen that by making the width W3 smaller than the widths W1 and W2, the reflection loss at the connection points between each signal pattern is reduced, and the transmission characteristics of the signal line are improved.

[0044] Also, in Sample 1, Sample 2, Sample 3, and Sample 4, the value obtained by subtracting Width W3 from Width W1 (the value obtained by subtracting Width W3 from Width W2) is 25 μm, 50 μm, 75 μm, and 100 μm, respectively. From this, it can be seen that the larger the value obtained by subtracting Width W3 from Width W1 (the value obtained by subtracting Width W3 from Width W2), the smaller the reflection loss. Note that if the value obtained by subtracting Width W3 from Width W1 (the value obtained by subtracting Width W3 from Width W2) is too large, that is, if Width W3 is too small, the leakage of the signal flowing through the signal pattern 41, which is the inner layer signal pattern, increases, and the transmission characteristics deteriorate. Therefore, the value obtained by subtracting Width W3 from Width W1 (the value obtained by subtracting Width W3 from Width W2) should be 125 μm or less.

[0045] When the ground pattern 71 overlaps all the connection conductor layers 53 in a plan view, the impedance mismatch increases, and the above-described effect of improving the reflection characteristics becomes small. Therefore, at least one of the plurality of portions of the ground pattern 71 is arranged so as not to overlap with at least any one of the connection conductor layers 53 connecting the land 12 and the land 42, the connection conductor layer 53 electrically connecting the land 22 and the land...

[0046] (Modified Example) FIG. 18 is a cross-sectional view of a printed wiring board 100 according to a modified example. As shown in FIG. 18, in the example shown in FIG. 18, the number of the plurality of dielectric layers 30 is 2. Further, in the example shown in FIG. 18, the printed wiring board 100 has one conductor layer 40. That is, in the printed wiring board 100, it is sufficient to have at least one conductor layer 40 between the conductor layer 10 and the conductor layer 20. In this case, the land 12 and the land 42 of the one conductor layer 40 overlap each other in a plan view and are electrically connected by the connection conductor layer 53, and the land 22 and the land 43 of the one conductor layer 40 overlap each other in a plan view and are electrically connected by the connection conductor layer 53.

[0047] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of the present invention is indicated by the claims rather than by the embodiments described above, and all modifications within the meaning and scope of equivalents of the claims are intended to be included.

[0048] 100 Printed circuit board, 10 Conductor layer, 11 Signal pattern, 12 Land, 13 Ground pattern, 20 Conductor layer, 21 Signal pattern, 22 Land, 23 Ground pattern, 30, 30A, 30B, 30C Dielectric layer, 30a, 30b Main surface, 31 First layer, 32 Second layer, 40, 40A, 40B Conductor layer, 41 Signal pattern, 42, 43 Land, 44 Ground pattern, 50, 51, 52 Through hole, 53 Connecting conductor layer, 60 Dielectric layer, 60a, 60b Main surface, 61 First layer, 62 Second layer, 70 Conductor layer, 71 Ground pattern, 71a First part, 71b Second part, 72 Opening, 200 Printed circuit board, DR1 First direction, DR2 Second direction, S1 Preparation process, S2 Patterning process, S3 S4 Connection conductor layer formation step, S5 Dielectric layer attachment step, S6 Connection conductor layer formation step, S7 Dielectric layer attachment step, S8 Patterning step, S9 Connection conductor layer formation step, W1, W2, W3 Width.

Claims

1. A printed circuit board comprising: a first conductor layer; a second conductor layer; a plurality of dielectric layers; and at least one third conductor layer, wherein the plurality of dielectric layers are arranged between the first conductor layer and the second conductor layer; each of the at least one third conductor layer is arranged between two adjacent layers of the plurality of dielectric layers; the first conductor layer has a first signal pattern, the first signal pattern extends along a first direction in a plan view; the second conductor layer has a second signal pattern, the second signal pattern extends along the first direction; each of the at least one third conductor layer has a third signal pattern, the third signal pattern extends along the first direction; the first signal pattern, the second signal pattern and the third signal pattern of each of the at least one third conductor layer are electrically connected to each other to form a single signal line; and in a second direction perpendicular to the first direction, the width of the first signal pattern and the width of the second signal pattern are greater than the width of the third signal pattern.

2. The printed circuit board according to claim 1, wherein the at least one third conductor layer is a plurality of third conductor layers.

3. The printed circuit board according to claim 2, wherein the first conductor layer further has a first land connected to the end of the first signal pattern in the first direction, the second conductor layer further has a second land connected to the end of the second signal pattern in the first direction, each of the plurality of third conductor layers further has a third land connected to one end of the third signal pattern in the first direction and a fourth land connected to the other end of the third signal pattern in the first direction, the first land and the second land overlap, in a plan view, the third land of the lowest of the plurality of third conductor layers and the fourth land of the uppermost of the plurality of third conductor layers, respectively, and the fourth land of one of two adjacent layers of the plurality of third conductor layers overlaps, in a plan view, the third land of the other of two adjacent layers of the plurality of third conductor layers.

4. The printed circuit board according to any one of claims 1 to 3, wherein in the second direction, the value obtained by subtracting the width of the third signal pattern from the width of the first signal pattern is 25 μm or more.

5. The printed circuit board according to claim 3, further comprising a fourth conductor layer different from any of the first conductor layer, the second conductor layer and the plurality of third conductor layers, wherein the fourth conductor layer has a ground pattern comprising a plurality of parts, and at least one of the plurality of parts is arranged in a plan view such that it does not overlap with at least one of the following: a first connecting conductor layer electrically connecting the first land to the lowest third land of the plurality of third conductor layers; a second connecting conductor layer electrically connecting the second land to the uppermost fourth land of the plurality of third conductor layers; and the fourth land of one of two adjacent third conductor layers and the third land of the other two adjacent third conductor layers.

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