Solid-state imaging element
The solid-state image sensor addresses the challenge of reducing memory area and improving sensitivity by sharing memory selection lines among pixel-unit memory areas, ensuring robust signal storage and interpolation, thereby enhancing image quality and yield.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- TOHOKU UNIV
- Filing Date
- 2025-10-15
- Publication Date
- 2026-07-23
AI Technical Summary
Conventional solid-state image sensors face challenges in reducing the memory area without thinning memory selection lines, which can lead to short circuits and slower signal transfer speeds, affecting image quality and sensitivity.
The sensor design includes a group memory area where multiple pixel-unit memory areas share memory selection lines, reducing their number and area, while using a specific arrangement of memory cells to ensure robust signal storage and interpolation in case of defects.
This design effectively reduces the memory area without thinning memory selection lines, improving image quality and sensitivity by minimizing the risk of short circuits and enabling efficient signal transfer and interpolation, thus enhancing yield and reducing manufacturing costs.
Smart Images
Figure JP2025036352_23072026_PF_FP_ABST
Abstract
Description
Solid-state image sensor
[0001] This invention relates to a solid-state image sensor.
[0002] Solid-state image sensors, which are high-speed imaging devices, are used to continuously capture phenomena that occur rapidly in a short period of time. A solid-state image sensor has N pixels (where N is an integer greater than or equal to 2) and M memory elements (where M is an integer greater than or equal to 2) associated with each of the N pixels. In conventional solid-state image sensors, the N pixels are arranged in a pixel area (light-receiving surface), and the N*M memory elements are arranged in a memory area separated from the pixel area. However, in an arrangement where the pixel area and the memory area are separated, the wiring (pixel signal output line) that outputs the pixel signal from each pixel from the pixel area to the memory area becomes long, and the transfer of the pixel signal takes time.
[0003] Patent Document 1 describes a configuration in which, on a light-receiving surface, a memory area is placed adjacent to each of multiple pixels, and 80 memory elements are placed adjacent to each other within these memory areas, thereby shortening the wiring (pixel signal output lines) from the pixels to the memory elements. In each memory area, memory cells containing memory elements are arranged in a grid pattern of 4 in the horizontal (row) direction and 20 in the vertical (column) direction. In addition, 80 memory selection lines (the same number as the memory elements) are provided to transmit selection signals to select a memory cell containing a memory element that holds the pixel signal output from the pixel.
[0004] International Publication No. 2020 / 039531, International Publication No. 2017 / 006411
[0005] In the solid-state image sensor with the above configuration, both pixels and memory areas are provided on the light-receiving surface. Therefore, in order to improve image quality or sensitivity without changing the size of the light-receiving surface, it is necessary to increase the proportion of pixels on the light-receiving surface, that is, to minimize the area of the memory area. One way to reduce the area of the memory area is to thin the memory selection lines, which are provided in the same number as the memory cells. However, thinning the memory selection lines can cause short circuits between adjacent memory selection lines, resulting in poor yield and slower signal transfer speeds. Therefore, there is a need to reduce the area of the memory area without thinning the memory selection lines.
[0006] The problem that this invention aims to solve is to reduce the area of the memory region in a solid-state image sensor that stores pixel signals output from each of multiple pixels in multiple memory cells, without making the wiring thinner.
[0007] To solve the above problems, the present invention provides a solid-state image sensor comprising: N (N = N1 * N2) pixels arranged two-dimensionally with N1 pixels (N1 is an integer of 2 or more) in a first direction and N2 pixels (N2 is an integer of 2 or more) in a second direction; a memory area provided for each of the N pixels, wherein each memory area comprises a pixel-unit memory area having M (M = M1 * M2) memory cells arranged two-dimensionally with M1 memory cells (M1 is an integer of 2 or more) in the first direction and M2 memory cells (M2 is an integer of 1 or more) in the second direction; a group memory area provided for N3 pixels (2 ≤ N3 ≤ N1) arranged in the first direction, with the N3 pixel-unit memory areas arranged in the second direction; and a pixel signal output line that outputs the pixel signal of each of the N pixels to the pixel-unit memory area corresponding to that pixel. A memory selection line for selecting a memory cell to hold the pixel signal output from the pixel signal output line, the memory selection line being provided individually for the M2 memory cells arranged in the second direction in each of the pixel unit memory areas, and being provided in common between the pixel unit memory areas arranged in the second direction.
[0008] In the solid-state image sensor according to the present invention, M memory cells are provided for each of the N pixels. In conventional solid-state image sensors, an independent pixel-unit memory area is provided for each pixel, and a memory selection line is provided for each of the M memory cells within the pixel-unit memory area. On the other hand, in the solid-state image sensor according to the present invention, a group memory area is provided in which the N3 pixel-unit memory areas provided for N3 pixels arranged in a first direction are arranged in a second direction, and the memory selection lines are shared among the pixel-unit memory areas arranged in the second direction. Therefore, the number of memory selection lines can be reduced compared to conventional solid-state image sensors in which memory selection lines are provided individually for each memory cell arranged in the second direction, thereby reducing the area of the memory area.
[0009] A schematic diagram of one embodiment of the solid-state image sensor according to the present invention. A diagram illustrating the configuration of the pixel circuit section constituting each pixel of the solid-state image sensor of this embodiment. A diagram illustrating the configuration of the memory area in the solid-state image sensor of this embodiment. A schematic diagram of the light-receiving surface of a conventional solid-state image sensor. A diagram illustrating the configuration of the memory area in a conventional solid-state image sensor. A diagram illustrating the number of memory cells in the group memory area of this embodiment. A diagram illustrating a circuit in this embodiment that outputs a control signal to sequentially hold pixel signals in multiple memory cells located at a distance from each other. A diagram illustrating another circuit in this embodiment that outputs a control signal to sequentially hold pixel signals in multiple memory cells located at a distance from each other. A diagram illustrating yet another circuit in this embodiment that outputs a control signal to sequentially hold pixel signals in multiple memory cells located at a distance from each other.
[0010] One embodiment of the solid-state image sensor according to the present invention will be described below with reference to the drawings.
[0011] Figure 1 is a schematic diagram of the solid-state image sensor 1 of this embodiment. The solid-state image sensor 1 comprises a main body 10 and a control / processing unit 4. Figure 1 is a plan view of the main body 10 and shows the arrangement of pixels and memory areas on the light-receiving surface.
[0012] N pixels P are arranged two-dimensionally on the light-receiving surface of the main body 10. The N pixels P are arranged in a first direction (vertical direction in Figure 1) with N1 pixels and in a second direction (horizontal direction in Figure 1) with N2 pixels (N = N1 * N2). In addition, for every 3 pixels (corresponding to N3 pixels in this invention) arranged in the first direction, a group storage area GM is arranged adjacent to those 3 pixels in the second direction. N1 / 3 group storage areas GM are provided in the first direction and N2 in the second direction. Although not shown in Figure 1, each group storage area GM is provided with a light-shielding portion to prevent light from entering the group storage area GM.
[0013] The control and processing unit 4 has the function of generating control signals that control operations related to reading out pixel signals generated in pixels P provided in the main unit 10, operations to hold said pixel signals in memory elements in the pixel unit memory area UM, and operations to read out the pixel signals held in said memory elements, as well as outputting the read-out pixel signals to external devices such as personal computers.
[0014] Figure 2 shows an example of a pixel circuit section 100 that constitutes each pixel P. Each pixel P's pixel circuit section 100 includes a light sensor pixel circuit 101a and an in-pixel correlated double sampling circuit (In-pixel CDS) 101b. In this embodiment, the pixel circuit section 100 is capable of performing correlated double sampling, but a pixel circuit section that does not perform correlated double sampling may also be used.
[0015] The light sensor pixel circuit 101a includes a light receiving element (PD) 102 and a floating diffusion (C) ＦＤ The device includes a 103, a reset transistor (R) 104, a first source follower transistor (SF1) 105, a first selection transistor (X1) 106, a first current source transistor (CS1) 107, a pixel-interphase double sampling selection switch (CDS) 108, and a pixel-interphase double sampling bypass switch (CDSb) 109. In Figure 2, a photodiode (PD) is shown as one preferred example of the light-receiving element (PD) 102, but other elements such as a phototransistor may also be used.
[0016] The interphase dual sampling circuit 101b within the pixel has an inter-pixel correlated dual sampling coupling capacitance (C Ｃ ) 110, Intrapixel Correlation Double Sampling Sample-Hold Capacitance (C ＳＨ The pixel-interphase dual sampling circuit 101b is equipped with a pixel-interphase dual sampling reset transistor (NS) 112, a second source follower transistor (SF2) 113, a second selection transistor (X2) 114, a second selection transistor (X2') 115, and a second current source transistor (CS2) 116. A pixel signal output line (PIXEL_OUT) 117 for outputting a pixel signal to the pixel unit memory area UM corresponding to the pixel P is wired to the pixel-interphase dual sampling circuit 101b.
[0017] Further, in the pixel circuit section 100, in order to apply a control signal for operating the photosensor, a terminal 118 for pixel reset voltage (VR_FD), terminals 119a and 119b for power supply voltage (AVDD), a terminal 120 for pixel in-phase double sampling circuit reset voltage (VR_CDS), a terminal 121 for first current source bias voltage (VB1), a terminal 122 for second current source bias voltage (VB2), a terminal 123 for pixel reset pulse (ΦR), a terminal 124 for pixel selection first pulse (ΦX1), a terminal 125 for pixel in-phase double sampling circuit selection pulse (ΦCDS), a terminal 126 for pixel in-phase double sampling circuit bypass pulse (ΦCDSb), a terminal 127 for pixel selection second pulse (ΦX2), a terminal 127a for pixel selection second A pulse (ΦX2'), and a terminal 128 for pixel in-phase double sampling reset pulse (ΦNS) are provided.
[0018] Note that the configuration of the pixel circuit section 100 in the solid-state imaging device 1 of the present embodiment is the same as that described in Patent Document 1. Since the operation of the pixel circuit section 100 is also the same as that described in Patent Document 1, detailed descriptions of the signals applied to each terminal and the operation of the pixel circuit section 100 are omitted here.
[0019] Next, the configuration of the group memory area GM of the solid-state imaging device 1 of the present embodiment will be described with reference to FIG. 3. In FIG. 3, the description of the reference numerals for the same elements in the circuit is partially omitted.
[0020] FIG. 3 shows the configuration of the group memory area GM located in a part of the light-receiving surface shown in FIG. 1 (the part indicated by the broken line in FIG. 1). In the group memory area GM, pixel unit memory areas UM (UM １，１ ~UM ３，１ ), corresponding to each of the three adjacent pixels P (P １，１ ~UM ３，１ ), are arranged side by side in the second direction. However, for the convenience of the drawing, in FIG. 3, only two pixel unit memory areas UM １，１ 、UM ３，１ located at both ends among the three pixel unit memory areas UM are shown, and the pixel unit memory area UM located in the center２，１ The diagram is omitted. The group storage area GM is provided with a storage cell column selection switch array 201 for each pixel-unit storage area UM.
[0021] Each pixel-unit memory area UM contains 120 memory cells 202. The 120 memory cells 202 are arranged in a grid of 60 in the first direction (vertical direction in Figure 3) and 2 in the second direction (horizontal direction in Figure 3) for each pixel-unit memory area UM. Each memory cell 202 is connected to a memory selection switch (SW) 203 and a memory capacitor (C ＡＭ ) has 204. Note that in Figure 3, only 4 of the 60 memory cells 202 arranged in the first direction are shown.
[0022] The memory cell column selection switch array 201 has memory column selection switches (WS1, WS2) 206. The 60 memory cells arranged in the first direction in the pixel-unit memory area UM share one of the two pixel signal transfer lines 205. Each of the two pixel signal transfer lines 205 in the pixel-unit memory area UM is connected to a memory column selection line 207, and by turning on either of the two memory column selection switches (WS1, WS2) 206 via the memory column selection line 207, one of the pixel signal transfer lines 205 is selected.
[0023] Each of the two memory selection switches (SW) 203, which are aligned in the second direction within the pixel-unit memory area UM, is connected to a memory selection line 208. These memory selection lines 208 are shared between the pixel-unit memory areas UM aligned in the second direction. The memory selection lines 208 are arranged in pairs, and 60 pairs (the same number as the memory cells 202 aligned in the first direction within the pixel-unit memory area UM) are provided in the second direction.
[0024] The pixel signal output from each pixel P is sent to the pixel-unit memory area UM via the pixel signal output line 117. In the pixel-unit memory area UM, one memory cell 202 is selected by turning on one of the memory column selection switches (WS1, WS2) 206 and one of the memory selection switches (SW1, SW2) 203, and the memory capacitor (C) within that memory cell 202 is selected. ＡＭ The pixel signal is held in 204. Control signals for selecting these switches are transmitted from the control / processing unit 4.
[0025] Here, for comparison with the solid-state image sensor 1 of this embodiment, we will now describe the configuration of a conventional solid-state image sensor 300 (for example, Patent Document 1) in which the same N pixels P as in this embodiment are arranged, and 120 memory cells are arranged for each pixel P, with reference to Figures 4 and 5. Note that in Figure 5, due to space limitations, only the structure of the memory area SM provided corresponding to one pixel P is shown, but similarly, memory areas SM are provided adjacent to each pixel P for the other pixels as well.
[0026] The solid-state image sensor 300 comprises a main body 310 and a control / processing unit (not shown). Figure 4 is a plan view of the main body 310, showing the arrangement of pixels and memory areas on the light-receiving surface.
[0027] As shown in Figure 4, N pixels P are arranged two-dimensionally on the light-receiving surface of the solid-state image sensor 300. Similar to the solid-state image sensor 1 of this embodiment, N1 pixels P are arranged in the first direction (vertical direction in Figure 4) and N2 pixels P are arranged in the second direction (horizontal direction in Figure 4) (N = N1 * N2). In addition, a storage area SM for storing the pixel signal from each pixel P is arranged adjacent to each pixel P. The N storage areas SM are also arranged in the same way as the pixels P, with N1 in the first direction (vertical direction in Figure 4) and N2 in the second direction (horizontal direction in Figure 4) (N = N1 * N2).
[0028] Each memory area SM, corresponding to each pixel P, contains 120 memory cells 302. Each memory cell 302 is connected to a memory selection switch (SW) 303 and a memory capacitor (C ＡＭ) has 304. The 120 memory cells 303 are arranged 20 in the first direction (only 2 memory cells 302 are shown in Figure 5, and the other memory cells 302 are not shown) and 6 in the second direction. As a result, the arrangement of memory cells 302 in the 3-pixel memory area SM is the same as the arrangement of memory cells 202 in the group memory area GM (3 pixel-unit memory areas UM) in the above embodiment (size with 60 memory cells in the first direction and 6 memory cells in the second direction arranged in two dimensions). The memory area SM is provided with a memory cell column selection switch array 301.
[0029] The memory cell column selection switch array 301 has six memory column selection switches (WS1 to WS6) 306. Twenty memory cells arranged in the first direction in the memory area SM share one of the six pixel signal transfer lines 305. Each of the six pixel signal transfer lines 305 for pixel signal transfer within the memory area SM is connected to one of the memory column selection switches (WS1 to WS6) 306. Each of the memory column selection switches (WS1 to WS6) 306 within the memory area SM is connected to one of the memory column selection lines 307, and by turning on any of the six memory column selection switches (WS1 to WS6) 306 through the memory column selection line 307, one of the pixel signal transfer lines 305 is selected.
[0030] Each of the six memory selection switches (SW1 to SW6) 303 arranged in the second direction within the memory area SM is connected to a memory selection line 308. The memory selection lines 308 are arranged in sets of six, and 20 sets (the same number as the memory cells 302 arranged in the first direction within the memory area SM) are provided in the first direction.
[0031] The pixel signal output from each pixel P is sent to the memory area SM via the pixel signal output line 117. In the memory area SM, one memory cell 302 is selected by turning on one of the memory row selection switches (WS1 to WS6) 306 and one of the memory selection switches (SW1 to SW6) 303, and the pixel signal is held in the memory capacitor (CAM) 304 within that memory cell 302.
[0032] Compare the configuration of the memory region in the solid-state imaging device 1 of the present embodiment (FIG. 3) with the configuration of the memory region in the conventional solid-state imaging device 300 (FIG. 5). As described above, in the solid-state imaging device 1 of the present embodiment, three pixel unit memory regions UM are provided in the group memory region GM adjacent to the three pixels P, and for each pixel unit memory region UM, 60 memory cells 202 are arranged in the first direction and 2 memory cells 202 are arranged in the second direction. That is, when viewed from the group memory region GM, 60 memory cells 202 are arranged in the first direction and 6 memory cells 202 are arranged in the second direction.
[0033] In the conventional solid-state imaging device 300, 20 memory cells 302 are arranged in the first direction and 6 memory cells 302 are arranged in the second direction for each memory region SM adjacent to each pixel P. Therefore, the arrangement of the memory cells 202 in the group memory region GM (three pixel unit memory regions UM) in the present embodiment (the size in which 60 memory cells 202 are arranged in the first direction and 6 memory cells 202 are arranged in the second direction in a two-dimensional arrangement) and the arrangement of the memory cells 302 in the memory region SM for three pixels of the conventional solid-state imaging device 300 are almost the same.
[0034] As shown in FIG. 5, in the conventional solid-state imaging device 300, a memory selection line 308 is provided for each memory cell 302 (memory selection switches (SW1 to SW6) 303). Therefore, 120 (= 20 * 6) memory selection lines 308 are provided in the memory region SM of each pixel, and 360 (= 〖120〗* 3) memory selection lines 308 are provided in the memory region SM for three pixels.
[0035] On the other hand, in the solid-state imaging device 1 of the present embodiment, a memory selection line 208 is provided for each memory cell 202 (memory selection switches (SW1, SW2) 203) within the pixel unit memory region UM, while the memory selection lines 208 are shared among the three adjacent pixel unit memory regions UM within the group memory region GM. Therefore, only 120 (= 60 * 2) memory selection lines 208 need to be provided in the group memory region GM corresponding to the memory region SM for three pixels of the conventional solid-state imaging device, and the number of memory selection lines 208 can be reduced to 1 / 3 compared to the conventional case.
[0036] In a solid-state imaging device where both pixels and a memory area are provided on the light-receiving surface, in order to improve the image quality or increase the sensitivity without changing the size of the light-receiving surface, it is necessary to increase the ratio of pixels occupying the light-receiving surface, that is, to make the area of the memory area as small as possible. In order to reduce the area of the memory area, it is conceivable to make the memory selection lines provided in the same number as the memory cells thinner. However, when the memory selection lines are made thinner, a short circuit may occur between adjacent memory selection lines, resulting in a poor yield or a slow signal transfer speed. Therefore, it is required to reduce the area of the memory area without thinning the memory selection lines. By using the solid-state imaging device 1 of the present embodiment, the number of memory selection lines can be reduced to 1 / 3 compared to the conventional solid-state imaging device 300, thereby reducing the area of the memory area.
[0037] Next, the order of designating the memory cells 202 for holding the pixel signals output from the pixels P in the solid-state imaging device 1 of the present embodiment will be described.
[0038] FIG. 6 is a table for explaining the numbers for specifying the memory cells 202 in the group memory area GM described in FIG. 3. In a conventional solid-state imaging device, the memory cells for holding the pixel signals output from the pixels P are designated in order from the first memory cell (that is, in the order of 1, 2, 3,...).
[0039] In a solid-state imaging device, in the manufacturing process, defects may occur in circuit elements in the memory cell, etc., and some of the memory cells may not operate. Conventionally, in such a case, an interpolation process is performed to estimate the value of the pixel signal that should have been held in the malfunctioning memory cell from the values of the pixel signals output from the same pixel at timings before and after in time (for example, Patent Document 2). Specifically, for example, the value of the pixel signal at time t when a pixel signal loss occurs due to a malfunction of the memory cell is obtained by averaging (completing with a linear expression) the values of the pixel signals obtained at times t-1 and t+1 adjacent to that time, or the value of the pixel signal at time t is obtained by polynomially approximating the values of the pixel signals obtained at a plurality of times before and after time t.
[0040] However, in the manufacturing process of solid-state image sensors, malfunctions can occur not only in the circuit elements but also in the wiring. For example, as in the solid-state image sensor 1 of this embodiment, when multiple memory selection lines 208 are arranged adjacent to each other, these adjacent memory selection lines 208 may short-circuit. As a result, the memory selection switches (SW) 203 connected to those memory selection lines 208 will not function, and consequently, the memory capacitor (C) in the adjacent memory cell 202 will not function. ＡＭ ) This makes it impossible to store the pixel signal in cell 204. In this case, if the memory cells 202 that store the pixel signal are specified sequentially from the first memory cell (i.e., in the order of 1, 2, 3, ...) as in the conventional method, multiple pixel signals that are out of order in time will be lost, and it will not be possible to perform the signal interpolation process described above.
[0041] Therefore, in this embodiment, the memory cells 202 that hold the pixel signal output from the pixel P are specified with at least one cell in between. This makes it possible to perform the pixel signal interpolation processing described above without being affected even if, for example, two adjacent memory selection lines 208 are short-circuited and it becomes impossible to hold the pixel signal in the two adjacent memory cells 202 connected to those memory selection lines 208.
[0042] In this embodiment, an example of specifying a storage cell 202 that holds pixel signals will be described.
[0043] In this example, the number K(i) of the memory cell 202 that holds the pixel signal output from pixel P in the i-th position in time is determined by the formula K(i) = L*i + i / (M / L) - MmodL*i / M (where L is an integer of 2 or more, M is the number of memory cells provided for each pixel, and the decimal part of i / M is truncated). "MmodL" is the remainder when M is divided by L. If K(i) > M, the subtraction K(i) - M is repeated until K(i) ≤ M. By setting L to an appropriate integer of 2 or more in this formula, the memory capacitor (C) in the memory cell 202 located L spaces away (or M-L spaces away if (K(i) + L) > M) holds the pixel signals of adjacent pixels in time. ＡＭ) can be stored in 204. Here, by setting the value of L to be equal to or greater than the number of memory cells 202 (the number of adjacent memory selection lines 208) that are aligned in the second direction in the pixel unit memory area UM, pixel signals that are in a temporal order can be stored in memory cells 202 that are separated in the first direction.
[0044] In the above formula, L can be expressed as L = M / A (where A is an integer between 2 and M / 2, with decimal places truncated) or L = M 1 / 2 Values such as (rounded down to the nearest whole number) can be suitably used. When L = M / A, the time-continuous pixel signals are transmitted to the memory capacitor (C) in the memory cell 202 that is L spaces away. ＡＭ ) is held in 204 (skipping L-1 memory selection lines). Therefore, even if there are defects in the adjacent memory selection lines 208 of L lines or less, only one pixel signal is lost as a result, preventing the loss of pixel signals continuously over time. Robustness to such defects increases as the value of L increases.
[0045] Furthermore, the values of the missing pixel signals can be interpolated using a polynomial that uses the values of A-1 pixel signals that are sequentially preceding or following each other in time. Specifically, by using an A-2 polynomial and determining the coefficients of each term based on A-1 polynomials, a formula can be obtained to interpolate the values of the missing pixel signals. In this case, the accuracy of the values interpolated by the formula increases as the value of A increases. Therefore, L = M 1 / 2 By setting L = A (which is synonymous with A), a configuration that combines robustness and high interpolation accuracy can be achieved.
[0046] In the solid-state image sensor 1 of this embodiment, as described above, the pixel signals output from the pixel P at different time points are stored in a memory capacitor (C) within a non-adjacent memory cell 202. ＡＭ ) In order to hold it in 204, even if an adjacent memory cell 202 malfunctions due to a short circuit between adjacent memory selection lines 208 in the memory area, the memory capacitor (C) of the memory cell 202 will not be held. ＡＭThis process allows interpolation of the pixel signal values that should be held in 204 from pixel signal values that are earlier or later in time, improving the yield in the manufacturing process. And the improvement in the yield in the manufacturing process leads to a reduction in the cost of the solid-state image sensor 1.
[0047] As a circuit that outputs a control signal to sequentially store the pixel signal from pixel P in multiple memory cells located at a distance from each other, as described above, the circuit shown in Figures 7 to 9 can be used, for example.
[0048] Figure 7 shows the simplest configuration of the circuit. In this circuit, control signals output sequentially (from left to right in this case) from the output terminal of the shift register 401 are output to memory selection lines 208 connected to memory selection switches (SW) of memory cells 202 located L spaces apart. The circuit in Figure 7 can be easily constructed by simply adding the connections shown by dashed lines in the figure to a control signal output circuit similar to those used conventionally. Note that in Figure 7, a 6-bit shift register is used and a configuration is shown in which memory cells 202 are selected every two spaces for ease of understanding, but the number of bits and the configuration of the connections can be appropriately changed depending on the number of memory selection lines 208.
[0049] Furthermore, as shown in Figures 8 and 9, by combining the shift register 401 and the selection bit, it is also possible to configure the system to output a control signal to the memory selection line 208 connected to the memory selection switch (SW) of a memory cell 202 located L spaces apart. In Figures 8 and 9, a 3-bit shift register 401 and one selection bit are used to select one of the memory selection lines 208. In Figure 8, the memory selection line 208 connected to the memory selection switch (SW) of a memory cell 202 located at a distance is selected by sequentially shifting the shift register 401, and in Figure 9, by sequentially switching the selection bit. In Figures 8 and 9, the case where there are 6 memory selection lines 208 is illustrated for ease of understanding, but the number of bits in the shift register 401 and the number of selection bits can be appropriately changed according to the number of memory selection lines 208.
[0050] The above embodiments are examples and can be modified as appropriate in accordance with the spirit of the present invention.
[0051] In the above embodiment, a group storage area GM is formed by arranging pixel-unit storage areas UM corresponding to three pixels P in a second direction. However, this number (a value corresponding to N3 in the present invention) can be changed as appropriate. However, it is preferable that N3 be between 2 and 6. Depending on the number of storage cells 202 associated with each pixel P (a value corresponding to M in the present invention), if N3 becomes too large, the number of storage cells 202 arranged in a first direction within one pixel-unit storage area UM increases. If the number of storage cells 202 arranged in the first direction increases, the pixel signal transfer line 205 shared by these storage cells 202 becomes longer, which can cause delays in the transfer of pixel signals. Alternatively, if the number of storage cells 202 arranged in the first direction is reduced, the number of pixel-unit storage areas UM arranged in the second direction increases, and the pixels P arranged in the second direction become spatially separated. Therefore, as described above, it is preferable that N3 be between 2 and 6.
[0052] In the above embodiment, for the sake of simplicity, the number of pixels N1 arranged in the first direction was set to a multiple of 3 (a multiple of N3 when generalized to the present invention), but this is not essential in the present invention. If N1 is not a multiple of N3, the remaining number of pixel-unit storage areas UM for each pixel P can be arranged in the second direction to form a group storage area GM. To give a simple example, if N1 is 103 and N3 is 5, then 20 group storage areas GM, each consisting of a pixel-unit storage area UM corresponding to 5 pixels P arranged in the second direction, can be arranged in the first direction, and for the remaining 3 pixels P, a group storage area GM can be provided, each consisting of a pixel-unit storage area UM corresponding to 3 pixels P arranged in the second direction.
[0053] In the above embodiment, 60 memory cells (corresponding to M1 in the present invention) were arranged in the first direction and 2 memory cells (corresponding to M2 in the present invention) were arranged in the second direction in the pixel-unit memory area UM. In other words, in the above embodiment, the arrangement was such that M = M1 * M2, but M1 and M2 do not have to be divisors of M. In that case, first set M2 to an appropriate number and arrange M / M2 (rounded down to the nearest whole number) memory cells in the first direction, and then arrange the remaining number of memory cells in the second direction at positions adjacent to them in the first direction.
[0054] In the above embodiment, a configuration in which the first and second directions are orthogonal was described, but this is not essential in the present invention, and the first and second directions may be configured to be non-orthogonal. Specifically, for example, a set of N3 pixels and group storage area GM can be arranged in a honeycomb pattern.
[0055] [Embodiments] It will be apparent to those skilled in the art that the exemplary embodiments described above are specific examples of the following embodiments.
[0056] (Section 1) A solid-state image sensor according to one aspect of the present invention comprises: N (N = N1 * N2) pixels arranged two-dimensionally with N1 pixels (N1 being an integer of 2 or more) in a first direction and N2 pixels (N2 being an integer of 2 or more) in a second direction; a memory area provided for each of the N pixels, wherein each memory area comprises a pixel-unit memory area having M (M = M1 * M2) memory cells arranged two-dimensionally with M1 memory cells (M1 being an integer of 2 or more) in the first direction and M2 memory cells (M2 being an integer of 1 or more) in the second direction; a group memory area provided for N3 pixels (2 ≤ N3 ≤ N1) arranged in the first direction, the N3 pixel-unit memory areas arranged in the second direction; and a pixel signal output line that outputs the pixel signal of each of the N pixels to the pixel-unit memory area corresponding to that pixel. A memory selection line for selecting a memory cell to hold the pixel signal output from the pixel signal output line, the memory selection line being provided individually for the M2 memory cells arranged in the second direction in each of the pixel unit memory areas, and being provided in common between the pixel unit memory areas arranged in the second direction.
[0057] In the solid-state image sensor according to paragraph 1, M memory cells are provided for each of the N pixels. In conventional solid-state image sensors, an independent pixel-unit memory area is provided for each pixel, and a memory selection line is provided for each of the M memory cells within the pixel-unit memory area. On the other hand, in the solid-state image sensor according to paragraph 1, a group memory area is provided in which the N3 pixel-unit memory areas provided for N3 pixels arranged in a first direction are arranged in a second direction, and the memory selection lines are shared among the pixel-unit memory areas arranged in the second direction. Therefore, the number of memory selection lines can be reduced compared to conventional imaging devices in which memory selection lines are provided individually for memory cells arranged in the second direction, thereby reducing the area of the memory area.
[0058] (Clause 2) The solid-state image sensor according to Clause 2 is a solid-state image sensor according to Clause 1, further comprising a pixel signal transfer line for transferring the pixel signal output from the pixel output line to the memory cells arranged in the first direction, wherein N3 is an integer between 2 and 6.
[0059] In the solid-state image sensor according to paragraph 2, it is possible to avoid situations where the number of memory cells aligned in the first direction increases, causing delays due to the time required for transferring pixel signals, or where the number of pixel-unit memory areas aligned in the second direction increases, causing pixels P aligned in the second direction to be spatially separated and resulting in poor spatial resolution.
[0060] (Paragraph 3) The solid-state image sensor relating to Paragraph 3 is a solid-state image sensor relating to either Paragraph 1 or Paragraph 2, wherein the solid-state image sensor is of the CMOS type.
[0061] The solid-state image sensor described in paragraph 1 can also be applied to CCD-type solid-state image sensors, but it is particularly suitable for use as a CMOS-type solid-state image sensor as described in paragraph 3.
[0062] (Clause 4) The solid-state image sensor according to Clause 4 is a solid-state image sensor according to any of Clauses 1 to 3, wherein the pixel signals output from the pixels in a temporal order are held in the storage cells located separately in the pixel unit storage area.
[0063] In the solid-state image sensor described in paragraph 4, pixel signals output from pixels in a temporally preceding or succeeding order are stored in memory cells located at separated positions. Therefore, even if a problem such as a short circuit between adjacent memory selection lines in the pixel-unit memory area prevents the storage of pixel signals in adjacent memory cells, the possibility of loss of consecutive pixel signals is reduced, and the value of the lost pixel signal can be compensated for from pixel signals that are in a temporally preceding or succeeding order.
[0064] (Clause 5) The solid-state image sensor according to Clause 5 is a solid-state image sensor according to Clause 4, in which, with respect to the M storage cells arranged in the pixel unit storage area, the storage cell is identified as the k-th cell according to the arrangement of the M storage cells, and the storage cell K(i) that holds the pixel signal output from the i-th pixel is calculated by L*i + i / (M / N) - MmodL*i / M (L is an integer of 2 or more. The decimal part of "i / M" is truncated. "MmodL" is the remainder when M is divided by L), and if K(i) > M, the subtraction K(i) - M is repeated until K(i) ≤ M to determine the storage cell K(i) > M.
[0065] (Paragraph 6) The solid-state image sensor relating to Paragraph 6 is the solid-state image sensor relating to Paragraph 5, where L is M / A (A is an integer between 2 and M, with decimal places truncated).
[0066] (Clause 7) The solid-state image sensor relating to paragraph 7 is a solid-state image sensor relating to any of paragraphs 1 to 5 in which L is M 1 / 2 (The decimal part is truncated.)
[0067] In the solid-state image sensor described in paragraph 5, pixel signals that are in a temporal order can be stored in memory cells located L spaces apart. Therefore, even if there are defects in L or fewer adjacent memory selection lines 208, only one pixel signal will be lost as a result, preventing the loss of consecutive pixel signals in time. Furthermore, the number L can be M / A as described in paragraph 6 (A is an integer between 2 and M, with decimal places truncated) or M as described in paragraph 7. 1 / 2Values such as (with decimal places truncated) can be suitably used. This makes it possible to interpolate the values of missing pixel signals with high precision using an A-2 polynomial.
[0068] 1,300...Solid-state image sensor 10,310...Main unit 100...Pixel circuit section 101a...Optical sensor pixel circuit 101b...Interphase double sampling circuit within pixel 102...Photodetector (PD) 103...Floating diffusion (C) ＦＤ ) 117...Pixel signal output line (PIXEL_OUT) 201, 301...Memory cell column selection switch array 202, 302...Memory cell 205, 305...Pixel signal transfer line 207, 307...Memory column selection line 208, 308...Memory selection line 4...Control / processing unit 401...Shift register P...Pixel GM...Group memory area UM...Pixel unit memory area
Claims
1. N pixels (N = N1 * N2) arranged two-dimensionally with N1 pixels (N1 is an integer of 2 or more) in a first direction and N2 pixels (N2 is an integer of 2 or more) in a second direction; a memory area provided for each of the N pixels, wherein each memory area is a pixel-unit memory area having M (M = M1 * M2) memory cells arranged two-dimensionally with M1 memory cells (M1 is an integer of 2 or more) in the first direction and M2 memory cells (M2 is an integer of 1 or more) in the second direction; a group memory area provided for N3 pixels (2 ≤ N3 ≤ N1) arranged in the first direction, with the N3 pixel-unit memory areas arranged in the second direction; a pixel signal output line that outputs the pixel signal of each of the N pixels to the pixel-unit memory area corresponding to that pixel; A solid-state image sensor comprising a memory selection line for selecting a memory cell to hold a pixel signal output from the pixel signal output line, the memory selection line being individually provided for the M2 memory cells arranged in the second direction in each of the pixel unit memory areas, and being commonly provided between the pixel unit memory areas arranged in the second direction.
2. The solid-state image sensor according to claim 1, further comprising a pixel signal transfer line for transferring the pixel signal output from the pixel output line to the memory cells arranged in the first direction, wherein N3 is an integer between 2 and 6.
3. The solid-state image sensor according to claim 1, wherein the solid-state image sensor is of the CMOS type.
4. The solid-state image sensor according to claim 1, wherein the pixel signals output from the pixels in a time order are held in the storage cells located separately in the pixel unit storage area.
5. With respect to the M storage cells arranged in the pixel-unit storage area, the storage cell is identified as the k-th cell according to the arrangement of the M storage cells, and the storage cell K(i) that holds the i-th pixel signal output from the pixel is calculated by L*i + i / (M / L) - MmodL*i / M (where L is an integer of 2 or more; the decimal part of "i / M" is truncated; "MmodN" is the remainder when M is divided by N), and if K(i) > M, the subtraction K(i) - M is repeated until K(i) ≤ M to determine the storage cell K(i) as described in claim 4.
6. The solid-state image sensor according to claim 1, wherein L is M / A (where A is an integer between 2 and M, with decimal places truncated).
7. The aforementioned L is M 1 / 2 The solid-state image sensor according to claim 1, wherein the decimal part is truncated.